Circuit comprising a transistor, and method of operating the same

Abstract

Circuits and methods of operating circuits are disclosed, said circuits comprising a transistor having a source, a drain, a first gate, and a first energy barrier at the source. The method comprises switching the transistor to an on state to permit a flow of current between the source and the drain, switching the transistor to an off state, and applying a first potential to the source and a second potential to the drain at a first point in time while the transistor is in the off state. The first potential is different to the second potential, and the first energy barrier inhibits a first leakage current through the transistor in the off state. In some embodiments, the method comprises controlling the circuit to operate the transistor such that an amount of charge carriers that are injected from the source is greater than a threshold, while transistor is in the on state, such that the source exhibits Ohmic or quasi-Ohmic behaviour.

Description

[0001] Circuit comprising a transistor, and method of operating the same

[0002] Technical Field

[0003] The present invention relates to circuits comprising transistors, and to methods of operating such circuits.

[0004] Background

[0005] Transistors, such as Thin-Film Transistors (TFTs), are widely used in many types of circuits. For example, transistors are commonly used as solid-state electrical switches, to turn a flow of current in a certain part of the circuit on or off as required. It is often desirable for the transistor to be capable of conducting a high current in the on state. However, designing the transistor to have a high transconductance in the on state can compromise the device's performance in the off state, resulting in higher leakage currents through the transistor in the off state during circuit operation. The need to balance these two conflicting technical requirements often leads to compromises and trade-offs when designing circuits. In large area electronics (LAE), which comprise TFTs and TFT-based circuits, this often results in increased device fabrication steps or circuit complexity.

[0006] For example, a flat panel display comprises an array of pixels containing light emitting elements, such as Light Emitting Diodes (LEDs). The LEDs are controlled by various electronic components, including: TFTs for driving the light emitting element (drivers); TFTs which act as switches for the various signals and electrical quantities that control the drivers (switches); and capacitors that retain the value of set signals for a duration dictated by the time required to display the image.

[0007] A trade-off occurs in designing such electronic circuits for pixels, due to the conflicting requirements of pixel density (image resolution), energy efficiency, image brightness, and image refresh rate. For example, when the display is operating at a high refresh rate, the switches should have a high current capability in their on state to allow the capacitors to be rapidly programmed (i.e. charged / discharged to the required voltages). Conversely, a low refresh rate is desirable when displaying a static image, to reduce the energy consumed by the display. In this scenario, the switches responsible for programming the capacitors spend longer periods in their off state, and hence the leakage current through each switch should be low to allow the capacitors to retain their charge for a longer time. The display may be required to switch between high and low refresh rates depending on the circumstances. For example, a mobile phone screen may need to refresh rapidly when displaying a video, but should revert to a low refresh rate when displaying a static image. This functionality must be achieved by the same hardware, leading to the conflicting technical requirement that the same switches should support both a high on current and a low off current. Conventionally, switches are implemented with TFTs which comprise Ohmic source and drain contacts. Various doping strategies at the drain (e.g. low drain doping (LDD), gate-overlapped low drain doping (GOLDD)), as well as drain-side auxiliary gates, are implemented to mitigate unwanted charge carrier generation at the drain, particularly during the off state.

[0008] Summary of the Invention

[0009] According to a first aspect of the present invention, there is provided a method of operating a circuit comprising a transistor, the transistor comprising a source, a drain, a first gate, and a first energy barrier at the source, the method comprising: switching the transistor to an on state by applying a first switching potential having a magnitude greater than a switching threshold potential to the first gate, so as to permit a flow of current between the source and the drain; switching the transistor to an off state by applying a second switching potential having a magnitude lower than the switching threshold potential to the first gate; and controlling the circuit to apply a first potential to the source and a second potential to the drain at a first point in time while the transistor is in the off state, wherein the first potential is different to the second potential, and wherein the first energy barrier inhibits a first leakage current through the transistor in the off state.

[0010] In some embodiments according to the first aspect, the method comprises: while the transistor is in the on state, controlling the circuit to operate the transistor such that an amount of charge carriers that are injected from the source is greater than a threshold, such that the source exhibits Ohmic or quasi-Ohmic behaviour.

[0011] In some embodiments according to the first aspect, said threshold corresponds to a point at which said amount of charge carriers injected is too high for an electric field of the drain to fully pinch-off the source.

[0012] In some embodiments according to the first aspect, the transistor is a phototransistor, and controlling the circuit to operate the transistor such that the amount of charge carriers that are injected from the source is greater than the threshold comprises exposing the phototransistor to light of sufficient intensity to cause said amount of charge carriers to be generated.

[0013] In some embodiments according to the first aspect, the circuit comprises a capacitor connected to the drain, and controlling the circuit to apply the second potential to the drain comprises charging the capacitor to the second potential.

[0014] In some embodiments according to the first aspect, the capacitor is charged to the second potential by the flow of current through the transistor in the on state.

[0015] In some embodiments according to the first aspect, the source is connected to an input configured to receive a control signal, such that the capacitor is charged to the second potential in dependence on a level of said control signal.

[0016] In some embodiments according to the first aspect, the circuit comprises a pixel circuit.

[0017] In some embodiments according to the first aspect, the pixel circuit comprises a driving circuit comprising said capacitor and said transistor, wherein said transistor operates as a switching transistor in the driving circuit.

[0018] In some embodiments according to the first aspect, the source and drain of the transistor are biased in a first direction when the first potential is applied to the source and the second potential is applied to the drain, wherein the transistor comprises a second energy barrier at the drain, the method further comprising: controlling the circuit to apply a third potential to the source and a fourth potential to the drain at a second point in time while the transistor is in the off state, wherein the third potential is different to the fourth potential such that the source and drain of the transistor are biased in a second direction opposite to the first direction when the third potential is applied to the source and the fourth potential is applied to the drain, and wherein the second energy barrier inhibits a second leakage current through the transistor in the off state.

[0019] In some embodiments according to the first aspect, the transistor is a multiple-gate transistor comprising a current control gate for controlling a magnitude of current flowing between the source and the drain through the semiconductor region in dependence on a potential applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region.

[0020] According to a second aspect of the present invention, there is provided a circuit comprising: a transistor comprising a source, a drain, a first gate, and a first energy barrier at the source, wherein the circuit is configured to switch the transistor to an on state by applying a first switching potential having a magnitude greater than a switching threshold potential to the first gate, so as to permit a flow of current between the source and the drain, wherein the circuit is configured to switch the transistor to an off state by applying a second switching potential having a magnitude lower than the switching threshold potential to the first gate, and wherein the circuit is configured to apply a first potential to the source and a second potential to the drain at a first point in time while the transistor is in the off state, wherein the first potential is different to the second potential, and wherein the first energy barrier is configured to inhibit a first leakage current through the transistor in the off state.

[0021] In some embodiments according to the second aspect, in use, while the transistor is in the on state, the circuit is configured to operate the transistor such that an amount of charge carriers that are injected from the source is greater than a threshold, such that the source exhibits Ohmic or quasi-Ohmic behaviour.

[0022] In some embodiments according to the second aspect, said threshold corresponds to a point at which said amount of charge carriers injected is too high for an electric field of the drain to fully pinch-off the source.

[0023] In some embodiments according to the second aspect, the circuit comprises a capacitor connected to the drain, wherein the circuit is configured to apply the second potential to the drain by charging the capacitor to the second potential.

[0024] In some embodiments according to the second aspect, the circuit is configured to charge the capacitor to the second potential by the flow of current through the transistor in the on state.

[0025] In some embodiments according to the second aspect, the source is connected to an input configured to receive a control signal, such that in use, the circuit is configured to charge the capacitor to the second potential in dependence on a level of said control signal. In some embodiments according to the second aspect, the circuit comprises a pixel circuit.

[0026] In some embodiments according to the second aspect, the pixel circuit comprises a driving circuit comprising said capacitor and said transistor, wherein in use, said transistor operates as a switching transistor in the driving circuit.

[0027] In some embodiments according to the second aspect, the circuit is configured to bias the source and drain of the transistor in a first direction when the first potential is applied to the source and the second potential is applied to the drain, wherein the transistor comprises a second energy barrier at the drain, and wherein the circuit is configured, in use, to apply a third potential to the source and a fourth potential to the drain at a second point in time while the transistor is in the off state, wherein the third potential is different to the fourth potential such that the source and drain of the transistor are biased in a second direction opposite to the first direction when the third potential is applied to the source and the fourth potential is applied to the drain, and wherein the second energy barrier is configured to inhibit a second leakage current through the transistor in the off state.

[0028] Brief Description of the Drawings

[0029] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0030] Figure 1 illustrates a pixel circuit comprising a plurality of contact-controlled transistors (CCTs), in the form of multimodal transistors (MMTs);

[0031] Figure 2 illustrates a multiple-gate transistor;

[0032] Figure 3 illustrates the orientation of a second switching transistor in the pixel circuit of Fig. 1;

[0033] Figure 4 is a graph comparing a variation in driver drain current over a 1-second time period in the circuit of Fig. 1 versus a comparative thin-film transistor (TFT)-based circuit;

[0034] Figure 5 illustrates a pixel driving circuit comprising a plurality of source-gated transistors (SGTs) as switches and an MMT as driver;

[0035] Figure 6 illustrates an SGT showing the location of the source-side depletion envelope; Figure 7 illustrates graphs showing transfer characteristics on logarithmic and linear scales for a Schottky contact SGT comprising an Ohmic drain contact, in which the solid line represents the Schottky source grounded for SGT operation, and the dashed line represents the same device but with the Ohmic contact grounded for field-effect transistor (FET) operation; Figure 8 illustrates a source-gated transistor comprising a field plate structure (depletion envelope illustrated);

[0036] Figure 9 illustrates a source-gated transistor comprising a field plate and a barrier modification implant;

[0037] Figure 10 illustrates a source-gated transistor having a split source comprising two materials with different work functions;

[0038] Figure 11 illustrates a source-gated transistor having a source comprising two materials with different work functions in contact with each other;

[0039] Figure 12 is a flowchart showing a method of operating a circuit comprising a transistor;

[0040] Figure 13 illustrates a multimodal transistor comprising an offset doping region in a semiconductor region over the source;

[0041] Figure 14 illustrates graphs comparing the performance of a low temperature polysilicon (LTPS) Ohmic-contact TFT, an LTPS MMT with a high energy barrier without offset doping, and an LTPS MMT with an offset doped contact;

[0042] Figure 15 illustrates transfer characteristics for single gate organic transistors with Cu and Ag contacts (left-hand graph) compared to a dual gate MMT device with Ag contacts (right-hand graph); and

[0043] Figure 16 illustrates output characteristics of an LTPS TFT with Ohmic contacts, an MMT with 0.3 eV barrier, and an MMT with offset doped contacts with 0.4 eV barrier.

[0044] Detailed Description

[0045] In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realise, the described embodiments may be modified in various different ways, all without departing from the scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.

[0046] Referring now to Figs. 1 and 2, a pixel circuit comprising a plurality of multiple-gate transistors is illustrated, according to an embodiment of the present invention. It should be understood that in this context, the term "pixel circuit" refers to the circuit that controls the emission of each physical pixel in a display comprising an array of such pixels (e.g. red, green or blue pixels in an RGB display). When considering the image that is formed by the display, the term "pixel" can also be used to describe the light components from which the image is formed. In practice, each image pixel is formed by light emitted from a number of physical pixels in the display (e.g. a pixel group comprising one red, one green and one blue light emitting component, each of which has an associated pixel circuit to control the emission of that component). Hence, the physical pixels (and pixel circuits) may sometimes be referred to as "subpixels".

[0047] As shown in Fig. 1, the circuit 100 comprises a transistor Ml configured to control the emission of light by a light emitting component DI, for example a Light Emitting Diode (LED) or Organic LED (OLED). The transistor Ml may be referred to as a driving transistor, in the sense that the first transistor Ml "drives" the light emitting component DI to emit light. In the present embodiment the light emitting component DI is connected to the drain of the driving transistor Ml, but in another embodiment the light emitting component DI may be connected to the source of the driving transistor Ml.

[0048] The driving transistor Ml is a multiple-gate transistor comprising two gate electrodes CGI, CG2 that can be used to independently control the magnitude of drain current separately from controlling on / off channel switching. The multiple-gate transistor Ml may also be referred to as a multimodal transistor (MMT). The principle of operation of the MMT will now be briefly described with reference to Fig. 2, to aid understanding of the present inventive concept. As described below, the MMT is an example of a type of transistor that includes an energy barrier at the source, resulting in a rectifying source contact.

[0049] The MMT is an example of a contact-controlled transistor (CCT). Other examples of CCTs include Schottky barrier transistors (SBTs) and source-gated transistors (SGTs). Here, the term "contact-controlled transistor" refers to a transistor that comprises an energy barrier at the source contact, as described in more detail below. The principles disclosed herein may also be applied to other types of CCT than the particular example shown in Fig. 2. For example, in some embodiments the MMT may be embodied using a different device architecture, including but not limited to vertical TFTs (VTFTs), Corbino / circular devices, and gate all around (GAA) devices.

[0050] Whilst an MMT is used as the driving transistor Ml in the present embodiment, in other embodiments the driving transistor Ml may comprise another type of CCT (e.g. an SGT), or may comprise a non-CCT device (e.g. a TFT with Ohmic contacts). In some embodiments, a pixel circuit similar to the one shown in Fig. 1 may comprise one or more other transistors in series with the MMT, for example, one or more Ohmic contact TFTs (or one or more contact-controlled transistors) in series with the MMT. Combining other transistors in series with the MMT can further reduce the leakage current.

[0051] As shown in Fig. 2, the MMT 200 comprises a source 201, a drain 202, a first gate 203 and a second gate 204. The source 201 and drain 202 are spaced apart from each other and separated by a semiconductor region 205. The first gate 203 is disposed over at least part of the source 201, and is separated from the source 201 by the semiconductor region 205 and by an electrical insulator 206 disposed over the semiconductor region 205. The electrical insulator 206 may be referred to as an "insulating region". The region of semiconductor material 205 above the source 201 which is overlapped by the first gate 203 may be referred to as the "source region" of the semiconductor 205. When a potential difference greater than a first threshold is applied to the first gate 203, an accumulation layer 205b is formed in the source region at the interface between the semiconductor 205 and the insulator 206.

[0052] Similarly, the second gate 204 is disposed over a gap 207 between the source 201 and the drain 202, and is separated from the source 201 and the drain 202 by the semiconductor region 205 and by the electrical insulator 206. When a potential difference greater than a second threshold is applied to the second gate 204, an accumulation layer 205b is formed in the gap 207 between the source 201 and drain 202 (also referred to as the "source-drain gap" 207), at the interface between the semiconductor 205 and the insulator 206. Depending on the device geometry and the materials used, the second threshold may be the same as the first threshold, or may be different.

[0053] Therefore, the first gate 203 and the second gate 204 can together create a conductive layer at the interface between the semiconductor region 205 and the insulator 206, providing a path for current to flow between the source 201 and the drain 202 in the semiconductor region 205. In the present embodiment the conductive layer is an accumulation layer, but in other embodiments an inversion layer may be formed as the conductive layer. In this way, when appropriate voltages are applied respectively to the first and second gates 203, 204, the MMT 200 chargeinjection principles and contact-controlled operation functions in a similar manner to a conventional source-gated transistor (SGT), whereby application of a potential to the drain 202 contact reverse biases an energy barrier at the source 201, which depletes the semiconductor 205 from free charge carriers under the source edge. When the depletion region 205a reaches the interface between the semiconductor 205 and the gate insulator 206, source-side pinch-off is produced. The charge injection of the MMT 200 can be understood with reference to Mode I and Mode II currents, as shown in Fig. 2. The diagram in Fig. 2 illustrates an example of the MMT 200 when operating in a similar mode to an SGT (e.g. when the same potential is applied to CGI and CG2), which may be referred to as an "SGT-like" mode. In the SGT-like operating mode, two distinct modes of current exist due to the source pinch-off effect. When a potential difference greater than a certain threshold is applied across the source 201 and drain 202, a depletion layer 205a is formed in the semiconductor region 205 adjacent to the source 201, at the edge of the source 201 closest to the drain 202. The Mode I current, Ii, is determined by thermionic-field emission in the electric field in the depletion region 205a at the edge of the source 201 nearest the drain 202.

[0054] The Mode II current, h, is injected along the remaining length of the source 201, i.e. away from the source-drain gap, and encounters resistance in the horizontal accumulation layer 205b as it travels through the semiconductor 205 along the length of the gate-insulator interface in the region of overlap between the source 201 and the first gate 203, which may be referred to as the source-gate overlap region. The Mode II current also encounters resistance vertically as it is injected from the source contact 201 and traverses the semiconductor 205. The total current flowing into the drain 202, ID, is equal to the sum of the Mode I and Mode II currents, i.e. ID = (Ii + I2). Here, it should be appreciated that the arrows in Fig. 2 illustrate the direction of travel of electrons, in the scenario where a higher potential is applied to the drain 202 compared to the potential at the source 201. Therefore, the direction of the conventional current in this scenario will be in the opposite direction to that shown by the arrows in Fig. 2.

[0055] The first gate 203 can be used to control the charge injection from the source electrode 201, and hence control the magnitude of the Mode I and Mode II currents. The second gate 104 can be used to control the conductive channel between the source 201 and the drain 202 without influencing charge injection. Consequently, the first gate 203 is hereinafter referred to as a "current control gate", and the second gate 204 is hereinafter referred to as a "switching gate". Therefore, the conduction state of the device (on / off) can be controlled by varying the voltage that is applied to the switching gate 204, whilst the magnitude of the current can be controlled by varying the voltage that is applied to the current control gate 203. In practice, if the potential applied to the current control gate 203 is low enough that no current is produced, then the MMT 200 will remain in the off state regardless of whether the potential applied to the switching gate 204 is above a switching threshold.

[0056] Terms such as "low enough", "lower", "high enough", "higher" etc. in the context of potentials that are applied to terminals of a transistor should be understood as referring to the magnitude of the potential relative to a corresponding threshold. The sign of the potential, i.e. whether a potential is positive or negative, may depend on the type of material used in the transistor (e.g. n-type or p-type). For example, when a CCT such as an MMT or SGT is formed from a p-type semiconductor, negative voltage(s) with magnitude(s) greater than corresponding threshold(s) should be applied to the gate(s) to cause the transistor to switch on. Accordingly, references to a potential applied to a gate as being "low enough", "lower", "high enough", "higher" etc., should be interpreted accordingly throughout this disclosure.

[0057] In the pixel circuit 100 of Fig. 1, since the first transistor Ml is an MMT, the current flowing through the light emitting component is controlled by the current control gate of the driving transistor Ml, and is blocked or permitted to flow through the light emitting component under the control of the switching gate of the driving transistor Ml. As such, the pixel circuit 100 comprises a driving circuit 110 configured to independently control the voltages that are applied to the current control gate CGI and the switching gate CG2 of the driving transistor Ml, so as to independently control a magnitude of said current and a time at which said current flows through the light emitting component DI.

[0058] The driving circuit 110 comprises a first capacitor Cl and a second capacitor C2 for independently controlling the voltages applied to the current control gate CGI and the switching gate CG2 of the driving transistor Ml. The first capacitor Cl is connected to the current control gate CGI such that, in use, a voltage on the first capacitor Cl can be applied to the current control gate CGI as the first voltage. The second capacitor C2 is connected to the switching gate CG2 such that, in use, a voltage on the second capacitor C2 can be applied to the switching gate CG2 as the second voltage. In the present embodiment, the first capacitor Cl is connected between the current control gate CGI and ground (GND), and the second capacitor C2 is connected between the switching control gate CG2 and GND.

[0059] By providing a separate capacitor Cl, C2 for each of the current control gate CGI and the switching gate CG2, the driving circuit 110 is capable of independently controlling the voltage that is applied to the respective gates CGI, CG2 during an emission phase, by charging each capacitor Cl, C2 to an appropriate level before the start of the emission phase.

[0060] The driving circuit 110 further comprises a first switching transistor T1 and a second switching transistor T2, which can be controlled to charge / discharge the first and second capacitors Cl, C2 as required. The respective gates of the first and second switching transistors Tl, T2 are configured to receive different control signals, here labelled as SEL n-l and SEL n respectively. Accordingly, the first and second switching transistors Tl, T2 can be switched independently of one another.

[0061] The first switching transistor Tl is connected between the current control gate CGI and the switching gate CG2 of the driving transistor Ml. Therefore, the first switching transistor Tl is configured to block or permit the flow of current between the current control gate CGI and the switching gate CG2, depending on whether the first switching transistor Tl is in an ON state or an OFF state (referred to simply as the transistor being "on" or "off"). Here, the term "ON state" refers to the state in which a transistor is able to conduct and produce current between its source and drain, whereas the "OFF state" refers to the state in which substantially no current is able to flow between the source and drain. A transistor may be switched between its ON and OFF states by applying an appropriate voltage to its gate electrode(s).

[0062] The second switching transistor T2 is connected between the second capacitor C2 and a data input (DATA). In other words, the second switching transistor T2 is configured to block or permit the flow of current between the second capacitor C2 and the first reference voltage node, depending on whether the second switching transistor T2 is on or off. The second switching transistor T2 is further connected to the switching gate CG2 of the driving transistor Ml, such that the second capacitor C2, the first switching transistor Tl, the second switching transistor T2 and the switching control gate CG2 are all connected to a common node, as shown in Fig. 1. Hence, when the first and second switching transistors Tl, T2 are both on simultaneously, the DATA voltage is provided to both the first and second capacitors Cl, C2.

[0063] During a programming phase of operation of the pixel circuit 100, the second switching transistor T2 can therefore be switched ON to reset a voltage on the second capacitor C2 to a voltage (DATA) at the data input, or to an intermediate voltage between ground and the DATA voltage (i.e. by switching off the second switching transistor T2 before the voltage on the second capacitor C2 reaches the DATA voltage). The first capacitor Cl can also be charged or discharged to the desired voltage (e.g. the DATA voltage, or an intermediate voltage between DATA and GND) by switching the first switching transistor T1 on while the second switching transistor T2 is on.

[0064] When controlling the first switching transistor T1 and / or the second switching transistor T2 to charge the first and / or second capacitors Cl, C2 to the DATA voltage, the gate voltages that are applied to the first switching transistor T1 and / or the second switching transistor T2 may be such that the first or second switching transistor Tl, T2 (each of which is a contact-controlled transistor, e.g. MMT) is operating in the linear or triode regime of its output characteristics. Specifically, the selection voltage (SEL n or SEL n-l) that is applied to the gates of the first or second switching transistor Tl, T2 may be substantially greater in absolute terms than the DATA node voltage, meaning that the transient charging (discharging) of the first or second capacitor Cl, C2 may begin with the switch operating in the linear region rather than in saturation.

[0065] When the first or second switching transistor Tl, T2 is operating in the linear region, the current flowing through the switching transistor Tl, T2 is much lower than the maximum attainable current by that device for that gate potential. This in turn means that the penalty of using a contact-controlled device for the first or second switching transistor Tl, T2 is significantly smaller, because the linear portions of the characteristics of contact-controlled and channel-controlled devices can be fairly close in terms of attainable current magnitude, which may not always be the case for the saturation region. This is demonstrated by the graph in Fig. 16, which compares the output characteristics of a TFT with Ohmic contacts, an MMT with 0.3 eV barrier (curve labelled MMT WF = 4.47 eV), and an MMT with offset doped contacts (solid and dashed curves labelled MMT WF = 4.57 eV). The dots along the curves in Fig. 16 illustrate potentials that may be used to charge a capacitor to a DATA potential, which generally correspond to the linear / triode regime and not saturation.

[0066] During the programming phase, if it is desired to charge both the first and second capacitors Cl, C2 to the same voltage, the first and second switching transistors Tl, T2 can both be switched on for a sufficient time for both capacitors Cl, C2 to charge to the desired voltage (e.g. the DATA voltage). If on the other hand it is desired to charge the first capacitor Cl to a lower voltage than the second capacitor C2, the first switching transistor Tl may be switched off before the first capacitor Cl reaches the DATA voltage. Then, the second capacitor C2 can continue charging up to the DATA voltage (or to a higher intermediate voltage) while the first switching transistor remains off.

[0067] As another alternative, if it is desired to charge the first capacitor Cl to a higher voltage than the second capacitor C2, then the first switching transistor T1 may be switched off once the first capacitor Cl reaches the desired higher voltage. Then, the signal at the data input (DATA) may be reduced to a lower voltage level to allow the second capacitor to charge / discharge to the desired lower voltage. The second switching transistor T2 may then be switched off once the second capacitor reaches the desired lower voltage.

[0068] Once the first and second capacitors Cl, C2 have been charged to the desired voltages, the first and second switching transistors Tl, T2 are then switched off in the retention (or "hold") phase. In the retention phase, the current control gate CGI and the switching gate CG2 of the MMT driving transistor Ml are isolated from each other. Consequently, the length of time for which the first and second capacitors Cl, C2 can retain their respective voltages is dependent on the leakage current through the first and second switching transistors Tl, T2.

[0069] It will be appreciated that the driving circuit 110 illustrated in Fig. 1 is just one example of a driving circuit for independently controlling the voltages applied to the current control gate CGI and switching gate CG2 of an MMT driving transistor Ml. In other embodiments of the present invention different configurations of driving circuits may be used. For example, instead of the first switching transistor Tl being connected to the first capacitor Cl and between the current control gate CGI and switching gate CG2, in another embodiment the first switching transistor Tl may be connected to the first capacitor Cl and may be connected between the current control gate CGI and a second data signal input. This arrangement can allow both capacitors Cl, C2 to be simultaneously charged to different voltages, by setting the second data signal to a different level to the data signal that is provided to the second capacitor C2 via the second switching transistor T2.

[0070] Typically, MMTs require higher gate voltages compared to an equivalent TFT to achieve the same drain current. Therefore, since the driving transistor Ml is an MMT, during the programming phase the first and second capacitors Cl, C2 may have to be charged to higher voltages compared to capacitors in an equivalent TFT-based pixel circuit. Without taking mitigating action, the use of higher gate voltages therefore has the potential to exacerbate an existing problem in TFT-based pixel circuits, namely, discharge of the capacitors during the retention phase (e.g. via leakage path through the switching transistors in the driving circuit). In conventional pixel circuits which use TFTs as the switching transistors, such leakage currents can prove problematic during the retention phase. For example, when the first switching transistor T1 is implemented as a TFT, the increased voltage seen across the source and drain of T1 during the retention phase can lead to a significant leakage current through the first switching transistor Tl. Similarly, the second switching transistor T2 may also suffer from a significant leakage current during the retention phase for the same reasons, when the second switching transistor T2 is implemented as a TFT. It should also be appreciated that a similar problem exists in pixel circuits that use conventional Ohmic TFTs as the driving transistor (i.e. in terms of the leakage current through switching transistors), albeit to a lesser extent due to the lower gate voltages for the driving transistor.

[0071] To mitigate this problem, in the present embodiment the first and second switching transistors Tl, T2 are both implemented as CCTs rather than TFTs, utilising the rectifying behaviour of the source contact in CCTs to reduce the leakage current in the off state. In the present embodiment MMTs are used as the first and second switching transistors Tl, T2, but in other embodiments another type of CCT may be used for the first and / or second switching transistors Tl, T2, e.g. an SGT. As explained below, the choice of MMTs rather than TFTs for the first and second switching transistors Tl, T2 can reduce the leakage currents through both switching transistors Tl, T2, enabling the pixel circuit to operate at a lower refresh rate when required. Typically, CCTs such as SBTs, SGTs and MMTs have been considered as unsuitable for switch applications due to their low transconductance (gm), as a consequence of the energy barrier at the source that provides the necessary contact-control behaviour. To mitigate this, embodiments of the present invention employ strategies to increase gmin CCTs which can allow them to be used in higher-speed applications as switch transistors. By using CCTs as switches, the performance of the circuit can be improved due to the lower off- state leakage of CCTs compared to conventional transistors and TFTs with Ohmic contacts.

[0072] As a type of contact-controlled transistor (CCT), such as the SGT, in an MMT the contact between the source 201 and the semiconductor 205, which may be referred to as the "source contact", comprises a potential barrier. The potential barrier may also be referred to as an "energy barrier". As a consequence, this potential barrier at the source contact in a CCT, such as an SGT or MMT, acts as a rectifying contact, inhibiting the flow of current in one direction. For example, a potential barrier between the source 201 and the semiconductor 205 may be provided by selecting suitable materials for the source 201 and the semiconductor region 205, by doping the material of the source 201 and / or the semiconductor region 205, or by forming a heterojunction contact between two or more semiconductor materials. In the same manner as SGTs, in some embodiments, the MMT 200 can comprise an interfacial layer between the source 201 and the semiconductor region 205 for controlling the properties of the potential barrier. For example, an interfacial layer may be formed by depositing a different material over the source 201 before depositing the semiconductor region 205, by doping a surface region of the source 201, or by processing the source material (e.g. by oxidising a surface of the source 201) before depositing the semiconductor region 205.

[0073] Although in the present embodiment two capacitors Cl, C2 are provided, so that different voltages can be applied to the current control gate CGI and the switching gate CG2, in other embodiments the circuit may be configured to apply the same voltage to both the current control gate CGI and the switching gate CG2. In such embodiments, one of the first and second capacitors Cl, C2 may be omitted, with the remaining capacitor (i.e. the first capacitor Cl or the second capacitor C2) being connected to both the current control gate CGI and the switching gate CG2. In such embodiments, depending on which of the first and second capacitors Cl, C2 is omitted, the respective one of the first and second switching transistors Tl, T2 may also be omitted.

[0074] Continuing with reference to the embodiment illustrated in Fig. 1, the first switching transistor Tl and the second switching transistor T2 are each arranged such that in the retention and / or emission phases, a lower potential is applied to the source 201 of the switching transistor compared to the potential that is applied to the drain 202 as a consequence of the charge stored on the respective one of the first and second capacitors Cl, C2. Hence, the drain 202 of the second switching transistor T2 is connected to the second capacitor C2 and the source 201 of the second switching transistor T2 is connected to the data signal input (DATA). The orientation of the second switching transistor T2 is illustrated in more detail in Fig. 3, showing the connections between the data signal input and the source 201, and between the drain 202 and the second capacitor C2.

[0075] In this way, once the second capacitor C2 has been charged during the programming phase, the potential at the drain 202 of the second switching transistor T2 is higher than the potential at the source 201 of the second switching transistor T2 (assuming that DATA is switched to a lower level compared to the charge on the second capacitor C2). Under this biasing condition, in effect the source terminal 201 of the device becomes the electrical drain, whilst the drain terminal 202 becomes the electrical source. While the second switching transistor T2 is in the off state, the magnitude of any leakage current of the second switching transistor T2 in its off state is significantly reduced due to the presence of the potential barrier at the source terminal 201, compared to a hypothetical similar circuit in which an Ohmic TFT is used as the second switching transistor.

[0076] In the present embodiment, during the programming phase the DATA signal will typically be set to a value that is higher compared to the potential that is expected to exist at the terminal of the second capacitor C2 connected to the second switching transistor T2 (i.e. the potential due to any remaining charge stored on the second capacitor C2 after the preceding emission and hold phases have been completed). In this way, during the programming phase it is expected that current will typically flow from the DATA signal input to the second capacitor C2, in other words, the second capacitor C2 will be charged during the programming phase.

[0077] In other embodiments, depending on the implementation it is possible that during the programming phase the DATA signal will typically be set to a value that is lower compared to the potential that is expected to exist at the terminal of the second capacitor C2 connected to the second switching transistor T2. In such embodiments, during the programming phase it is expected that current will typically flow from the second capacitor C2 to the DATA signal input, in other words, the second capacitor C2 will be discharged during the programming phase. In such embodiments, when fabricating the circuit the second switching transistor T2 may be connected in the reverse orientation to that shown in Fig. 3 (i.e. with the source 201 connected to the second capacitor C2, and the drain 202 connected to the DATA signal input).

[0078] In more detail, with reference to Fig. 3, the second switching transistor T2 is used as a switch to change (program) the potential on the second switching capacitor C2. The desired voltage value is presented at the data signal input DATA, and the second switching transistor T2 is turned on by application of a suitable voltage on the gate terminals via the control signal SEL n. The second capacitor C2 charges until the voltage at the drain 202 is practically identical to that at the source 201, or to an intermediate value dictated by the timing of the signal applied to the gates of the second switching transistor T2. The second switching transistor T2 is arranged to permit a high 'on' current to flow from the source 201 to the drain 202 during the programming phase. This can be achieved either by ensuring that the contact at the drain 202 (hereinafter referred to as the "drain contact") comprises an Ohmic or quasi-Ohmic contact. This arrangement ensures fast charging of the second capacitor C2 during the programming phase. Here, the term "quasi-Ohmic" may be understood as referring to a contact with a weakly rectifying energy barrier (i.e. an energy barrier with a height below a certain threshold), or to a contact where the energy barrier is too low to fully pinch-off the source edge but sufficiently high to be capable of reducing the off-state current (i.e. in comparison to the off-state current in an equivalent Ohmic TFT).

[0079] Subsequently, when transitioning from the programming phase to the retention phase, the potential on the gates of the second switching transistor T2 is changed suitably so that the transistor is turned off, by changing the value of the control signal SEL n. In this state, the second switching transistor T2 has a low off-current by virtue of the rectifying source contact (i.e. the potential barrier at the source 201). Given the differing biasing condition, the electrical source of the second switching transistor T2 may now be at the drain 202 during the retention phase. In this example, the charge in the second capacitor C2, and thus the potential at the drain 202 of the second switching transistor Tl, can be retained for a long period, as the leakage of the contact-controlled transistor (CCT) is low relative to a comparable switch TFT with Ohmic contacts.

[0080] The advantage of using CCTs, such as the MMT by way of example, as the switching transistors in the pixel circuit 100 of Fig. 1 is illustrated in Fig. 4, which compares the variation in driver drain current over a 1-second time period in the MMT-based circuit of Fig. 1 versus a comparative Ohmic contact TFT-based circuit. The results shown in Fig. 4 were obtained based on simulations of comparable MMT-based and TFT-based circuits similar to the one shown in Fig. 1, using capacitors totalling approximately 500 femtofarads (fF). The results show that the retention of charge on the first and second capacitors Cl, C2 is significantly improved in the MMT-based circuit (~2% variation in drain current over a 1-second time period). For reference, a 2% variation is deemed acceptable for human users in terms of flicker effect, indicating that the MMT-based circuit in Fig. 1 is capable of providing acceptable flicker-free performance at a 1 Hz refresh rate. By comparison, the TFT-based equivalent circuit shows a degradation in drain current of >40% during the same Is time period, meaning that the equivalent TFT-based circuit would not be capable of acceptable performance at such low refresh rates. It will be appreciated that a refresh rate of 1 Hz is used here purely as an illustrative example, and in other embodiments a pixel circuit may be operated at any other refresh rate.

[0081] Therefore, using CCTs, such as SGTs and MMTs, as switching transistors in a pixel circuit can offer a number of advantages over conventional TFT-based pixel circuits, including reduced flicker and increased energy efficiency (i.e. by virtue of being able to operate at lower refresh rates).

[0082] Furthermore, such advantages are not restricted solely to MMT-based pixel circuits, but may also apply to other pixel circuits in which transistors with at least one rectifying contact are used as the switching transistors (e.g. the first and second switching transistors Tl, T2 in Fig. 1). Another example of a transistor comprising a rectifying source contact is a Source-Gated Transistor, SGT.

[0083] Figure 5 illustrates an example of a pixel driving circuit 500 similar to the one shown in Fig. 1, but in which the driving circuit 510 uses SGTs as the first and second switching transistors Tl, T2. As with the embodiment of Fig. 1, in some embodiments a circuit similar to the one shown in Fig. 5 may include another type of OCT or a non- CCT device (e.g. TFT) as the driving transistor Ml. Since the SGT-based first and second switching transistors Tl, T2 in the embodiment of Fig. 5 have rectifying source contacts, similar to the MMT-based first and second switching transistors Tl, T2 in the embodiment of Fig. 1, the SGT-based pixel circuit 500 will offer similar advantages to the MMT-based pixel circuit 100 compared to conventional TFT-based pixel circuits, such as reduced flicker and increased energy efficiency. As described above, MMTs and SGTs are both examples of CCTs, where the term "CCT" refers to a transistor that comprises an energy barrier at the source contact. By extension, it will be appreciated that such advantages may exist in any pixel circuit that uses a type of CCT as the switching transistors.

[0084] An embodiment of an SGT 600 is illustrated in Fig. 6. For example, the first and second switching transistors Tl, T2 in the pixel circuit 500 of Fig. 5 may comprise SGTs 600 with structures similar to that shown in Fig. 6. Like the MMT 200 of Fig. 2, the SGT 600 comprises a source 601, a drain 602, and a gate 603. The source 601 and drain 602 are spaced apart from each other and separated by a semiconductor region 605. The gate 603 is disposed over at least part of the source 601, and is separated from the source 601 by the semiconductor region 605 and by an electrical insulator 606 disposed over the semiconductor region 605. The SGT 600 differs from the MMT 200 in that the gate 603 in the SGT 600 also extends across the source-drain gap, for example, up to or beyond the edge of the drain 602 that is closest to the source 601, as opposed to there being a separate gate over the source-drain gap.

[0085] When a potential difference greater than a first threshold is applied to the gate 603, an accumulation layer 605b is formed at the interface between the semiconductor 605 and the insulator 606. Also, like the MMT 200, when a potential is applied to the drain 602, the potential barrier at the source 601 of the SGT 600 becomes reverse biased by the drain electric field and results in formation of a depletion region 605a in the semiconductor region 605 adjacent to the source 601, at the edge of the source 601 closest to the drain 602.

[0086] An example of transfer characteristics for an SGT 600 comprising a Schottky source 601 and an Ohmic drain 602 is illustrated in Fig. 7. In Fig. 7, solid lines show the transfer characteristics with the Schottky source 601 grounded, whilst dashed lines show the transfer characteristics with the Ohmic drain 602 grounded. The left-hand graph in Fig. 7 plots the drain current against a logarithmic axis, whilst the right-hand graph plots the drain current against a linear axis. Grounding the Schottky source 601 leads to SGT-like behaviour, as shown by the solid lines, whereas grounding the Ohmic drain 602 leads to behaviour similar to a conventional Ohmic TFT, as shown by the dashed lines. Grounding the drain has the effect of running the SGT 600 in reverse, compared to the normal mode of operation of an SGT 600.

[0087] In both MMTs and SGTs, the source contact comprises a potential barrier, leading to rectifying behaviour when the source barrier is reverse biased by the drain electric field during operation. The drain contact of an MMT or SGT may either be designed to be Ohmic or Schottky (i.e. rectifying), depending on the embodiment. For example, in circuits where the source and drain of an MMT or SGT are biased in one direction in the off state at one point in time, and are biased in the opposite direction in the off state at another point in time, it may be advantageous to include a potential barrier at the drain contact as well as at the source contact, such that the MMT or SGT exhibits SGT-like behaviour under both biasing conditions. Since the device is rectifying in both directions, the leakage current in the off state can be reduced under both biasing conditions, compared to a conventional TFT with Ohmic source and drain contacts.

[0088] In any given embodiment, the relative positioning (i.e. alignment) of the gate with respect to the drain may be adapted depending on whether the drain contact is Ohmic or Schottky. For example, in embodiments where the drain contact is Ohmic, the edge of the gate (in the case of an SGT) or the switching gate (in the case of an MMT) closest to the drain may be aligned with the edge of the drain closest to the sourcedrain gap, such that there is no overlap (or as little overlap as is practically achievable, within manufacturing tolerances) between the drain and the gate. On the other hand, in embodiments where the drain contact comprises an energy barrier (i.e. a Schottky contact), the gate may at least partially overlap the drain, similar to the manner in which the current control gate 203 overlaps the source 201 in an MMT 200.

[0089] Transistors that include at least one Schottky contact, such as MMTs and SGTs, may therefore be advantageously employed in circuits that are configured to bias the source 201, 601 and drain 202, 602 of the transistor 200, 600 in one direction while the transistor 200, 600 is in the on state, and in the opposite direction while the transistor 200, 600 is in the off state. In this case, the leakage current through the transistor in the off state can be significantly reduced compared to a conventional Ohmic TFT, by virtue of the rectifying behaviour (e.g. the Schottky source 201, 601 in an MMT 200 or an SGT 600).

[0090] Depending on the circuit configuration, in some circumstances the transistor 200, 600 may be biased in such a way in the on state that the presence of the potential barrier (i.e. the Schottky contact) would tend to inhibit a flow of current through the transistor 200, 600 in the on state, compared to a conventional Ohmic TFT.

[0091] Purely by way of an illustrative example, depending on factors such as the image being displayed, refresh rate, brightness level and so on, it is possible that in one emission phase it may be necessary to apply a higher potential to the current control gate CGI of the driving transistor Ml compared to the potential applied to the switching gate CG2, whereas in another emission phase it may be necessary to apply a lower potential to the current control gate CGI compared to the potential applied to the switching gate CG2. In such circumstances, at one point in time (e.g. during a first retention or emission phase) the circuit may be configured such that a voltage stored on the first capacitor Cl is higher than a voltage stored on the second capacitor C2, whilst at another point in time (e.g. during a second retention or emission phase) the circuit may be configured such that a voltage stored on the first capacitor Cl is lower than a voltage stored on the second capacitor C2.

[0092] For example, if the source 201, 601 of the first switching transistor T1 is connected to the first capacitor Cl and the drain 202, 602 is connected to the second capacitor C2, at the first point in time the potential at the source 201, 601 will be higher than the potential at the drain 201, 601. Conversely, at the second point in time the potential at the source 201, 601 will be lower than the potential at the drain 201, 601. Hence, in this example the source 201, 601 and 202, 602 drain of the first switching transistor T1 will be biased in a first direction at the first point in time, and will be biased in a second direction opposite to the first direction at the second point in time.

[0093] In this example, the first switching transistor T1 may be configured such that energy barriers are present at both the source and drain contacts, so that the leakage current in the off state can be reduced under both biasing conditions. In embodiments in which a transistor comprises a Schottky drain contact, the transistor may further comprise a drain gate to enable the transistor to be switched on when the potential at the source 201, 601 is higher than the potential at the drain 202, 602 (e.g. if the first capacitor Cl needs to be discharged to a lower DATA level during the programming phase).

[0094] However, the presence of Schottky contacts at both the source 201, 601 and drain 202, 602 would lead to a reduced on current in both directions during the programming phase. To mitigate this potential drawback, in some embodiments of the present invention the circuit may be configured such that while the first switching transistor T1 is in the on state (e.g. during the programming phase), the first switching transistor T1 is operated in such a way that the amount of charge carriers that are injected from the source 201, 601 is greater than a certain threshold. In particular, the threshold corresponds to a point at which the amount of charge carriers injected is too high for the drain electric field to fully pinch-off the source. This results in Ohmic or quasi-Ohmic behaviour at the source contact, resulting in an on current that is comparable to that of a conventional Ohmic TFT in an equivalent circuit.

[0095] For example, in some embodiments an additional OCT (e.g. an MMT 200 or SGT 600) may be connected in parallel with one of the first and second capacitors Cl, C2, to rapidly discharge the capacitor when needed (e.g. during a reset timing phase). In such embodiments, it would be desirable for the additional CCT to maintain a low leakage current in the hold / emission phase (i.e. while in the off state), but to exhibit high transconductance (i.e. a high on-current) during the reset phase. This can be achieved by operating the CCT during the reset phase such that the amount of charge carriers that are injected from the source 201, 601 is too high for the drain electric field to fully pinch-off the accumulation layer 205b, 605b at the source 201, 601. Examples of mechanisms by which this effect can be achieved will now be described. In some embodiments, a transistor comprising a Schottky contact (e.g. a Schottky source 201, 601, as in an MMT 200 or an SGT 600) may have a sufficiently high potential difference applied across the source 201, 601 and drain 202, 602 that the lateral electric field of the drain 202, 602 lowers the height of the energy barrier in addition to the gate-source bias, and the amount of charge injection becomes too great for the Schottky source energy barrier to fully pinch off the device under the source edge.

[0096] In some embodiments, a CCT such as an MMT or SGT may comprise a field plate extending across the source-drain gap, the field plate comprising an insulator. An example of an SGT 800 comprising a field plate is illustrated in Fig. 8. Like the SGT 600 of Fig. 6, the SGT 800 of the present embodiment comprises a source 801, drain 802, gate 803, semiconductor region 805, and insulator region 806.

[0097] As with the SGT 600 of Fig. 6, when a potential difference greater than a first threshold is applied to the gate 803, an accumulation layer 805b is formed at the interface between the semiconductor 805 and the insulator 806. Also, like the MMT 200, when a potential is applied to the drain 802, the potential barrier at the source 801 of the SGT 800 becomes reverse biased by the drain electric field and results in formation of a depletion region 805a in the semiconductor region 805 adjacent to the source 801, at the edge of the source 801 closest to the drain 802.

[0098] The field plate insulator 807 thickness may be configured (e.g. selected) to ensure that the SGT 800 can be made to saturate as expected for an SGT. For example, in some devices a field plate may allow tunnelling of charge carriers if the field plate is too thin. In such devices, with increasing thickness of the field plate insulator 807, the Schottky source barrier is able to fully deplete the semiconductor 805 and show SGT saturation. However, in other devices (e.g. polysilicon SGTs) the field plate insulator thickness may need to be reduced to achieve SGT behaviour. Other dimensions of the field plate may also be modified to achieve the desired performance.

[0099] In embodiments in which a CCT comprises a field plate, a suitable voltage (e.g. a voltage above a certain threshold voltage) may be applied to the gate 803 (or to the switching gate CG2, in an MMT embodiment) to generate a sufficient amount of charge carriers in the semiconductor region at the edge of the field plate closest to the drain, to achieve the required increase in drain current. However, in general the voltage that is required to generate a sufficient amount of charge carriers to prevent the drain electric field from fully pinching-off the accumulation layer 205b, 605b at the source 201, 601 can be reduced by omitting the field plate 807 entirely. Hence, in some embodiments a CCT (e.g. MMT 200 or SGT 600) without a field plate may be used as a switching transistor, so that the switching transistor can be more easily made to exhibit Ohmic behaviour when required (e.g. to rapidly charge or discharge a capacitor during a programming phase in a pixel circuit).

[0100] The MMTs and SGTs described above with reference to Figs. 2, 6 and 8 are examples of asymmetric devices comprising a gated source and channel, and an Ohmic drain. In some embodiments of the present invention, a switching transistor may comprise a symmetric device having an energy barrier at the source. Furthermore, in both cases (i.e. for symmetric and asymmetric CCTs) in some embodiments the drain may also comprise an energy barrier, such that both the source and drain contacts are rectifying. In such embodiments, depending on the configuration of the CCT (e.g. the materials used and the device geometry) the rectifying source and drain contacts may have identical properties or may have different properties. When a CCT comprises a rectifying drain contact (i.e. an energy barrier at the drain), the drain may also be gated (i.e. in addition to the source and the channel being gated).

[0101] Referring now to Fig. 9, an SGT comprising a field plate and a barrier modification implant is illustrated, according to an embodiment of the present invention. The SGT 900 illustrated in Fig. 9 is an example of a symmetric device, in contrast to the asymmetric devices of Figs. 2, 6 and 8. The SGT 900 may be circular or rectangular in plan view, depending on the embodiment. In circular embodiments (e.g. a Corbino SGT), the two drains 902 illustrated in the cross-section in Fig. 9 may in fact be part of a single annular drain 902.

[0102] Like the SGT 800 of Fig. 8, the SGT 900 of the present embodiment comprises a source 901, drain 902, gate 903, semiconductor region 905, and insulator region 906. The SGT 900 further comprises a barrier modification implant 901a disposed on the source 901, between the source 901 and the gate 903. The field plate in the present embodiment comprises part 901b of the source 901 that overhangs the semiconductor 905, so as to shield the injecting region where the source 901 is in contact with the semiconductor 905. In the present embodiment, the semiconductor region 905 comprises low-temperature polycrystalline Si (LTPS).

[0103] In LTPS devices, the properties of a barrier modification implant 901a (e.g. composition and / or dimensions) may be selected to provide a source energy barrier with the desired height. For example, using a P-type material for the barrier modification implant can provide a lower barrier height and thus higher current, relative to a comparable BF2 implant device. For example, output characteristics of an SGT 900 comprising a IxlO13cm-3P implant 901a show that flat saturation and low voltage saturation are traded-off compared to a IxlO13cm’3BF2 implant, but the characteristics are still superior to conventional LTPS TFTs which have short channel effects and the kink effect from hot-carrier generation at the drain. Thus, an SGT 900 with a deliberate energy barrier (i.e. in the form of a barrier modification implant) is capable of providing sufficient on-current while maintaining desirable off-current behaviour.

[0104] Barrier modification implants 901a such as the one described above with reference to Fig. 9 can also be employed in other OCT devices. The properties of the implant 901a, such as its composition and dimensions, can be selected to achieve the desired barrier height. In some embodiments a barrier modification implant 901a may only extend along part of the length of the source 901, as opposed to extending across the full length of the source 901 as in the embodiment of Fig. 9.

[0105] Referring now to Fig. 10, an SGT is illustrated having a split source comprising two materials with different work functions. Like the SGTs 600, 800 of Figs. 6 and 8, the SGT 1000 of the present embodiment comprises a source, drain 1002, gate 1003, semiconductor region 1005, and insulator region 1006. The source comprises a first part 1001a and a second part 1001b, the first and second parts 1001a, 1001b respectively comprising materials with different work functions (e.g. different metals). The first and second parts 1001a, 1001b are separated by a source gap 1001c, wherein the second part 1001b is disposed between the first part 1001a and the drain 1002.

[0106] The first part 1001a comprises a first material having a first work function and the second part 1001b comprises a second material having a second work function, the second work function resulting in an energy barrier being higher than the energy barrier that results from the first work function. For example, in n-type semiconductors the work function should be higher to form a higher energy barrier, whereas in p-type semiconductors the work function should be lower to form a higher energy barrier. Purely by way of an illustrative example, the first material may have a work function of 0.3 electron volts (eV), whilst the second material may have a work function of 0.45 eV. The higher work function material of the second part 1001b provides the pinch-off capability and is responsible for the low off-state current, while the lower work function material of the first part 1001a facilitates higher charge injection and thus higher drain current. Also, it should be recognised that in some embodiments a different combination of work functions may be required to provide the desired energy barrier. For instance, interfacial properties such as fermi-level pinning may result in different behaviour to that which would otherwise be expected. For example, in InGaZnO an Ohmic contact is often formed even when the source is formed from a material with a higher work function.

[0107] This approach, i.e. employing materials with different work functions, may be used in material systems where barrier modification implants or surface modification treatments are not possible. Conversely, in material systems where suitable work functions are not available, a barrier modification implant may be included at either / both of the first and second parts 1001a, 1001b so as to create the desired higher energy barrier at the source edge (i.e. at the first part 1001a), and a lower energy barrier away from the source edge (i.e. at the second part 1001b).

[0108] By selecting materials with appropriate work functions, the height of the potential barrier can be controlled so as to ensure that the barrier is low enough to be capable of being overwhelmed by the amount of charge carriers that are generated when the SGT 1000 is operating in the on state. In this way, the SGT 1000 can exhibit Ohmic behaviour in the on state, providing a comparable on-current to conventional TFT devices. At the same time, the SGT 1000 can exhibit rectifying behaviour in the off state, due to the energy barrier at the source, providing a significantly lower off- current compared to conventional TFT devices.

[0109] Figure 11 illustrates an SGT 1100 having a source comprising two materials with different work functions in contact with each other. The SGT 1100 of the present embodiment is similar in many respects to the SGT 1000 of Fig. 10, comprising a source, drain 1102, gate 1103, semiconductor region 1105, and insulator region 1106. Also like the SGT 1000 of Fig. 10, the SGT 1100 of the present embodiment comprises a source comprising a first part 1101a and a second part 1101b, wherein the first part 1101a comprises a first material having a first work function and the second part 1101b comprises a second material having a second work function, the second work function being higher than the first work function. As described above with reference to Fig. 10, in embodiments similar to the one in Fig. 11 but where suitable work functions are not available, a barrier modification implant may be included at either / both of the first and second parts 1101a, 1101b so as to create the desired higher energy barrier at the source edge (i.e. at the first part 1101a), and a lower energy barrier away from the source edge (i.e. at the second part 1101b). The SGT 1100 of the present embodiment differs from the embodiment of Fig. 10 in that the first and second parts 1101a, 1101b of the source are disposed in contact with one another, rather than being separated by a source gap 1001c as in Fig. 10. This difference aside, the SGT 1100 of Fig. 11 can operate in a similar manner to the SGT 1000 of Fig. 10, and for the sake of brevity a detailed description will not be repeated here.

[0110] Referring now to Fig. 12, a flowchart is illustrated showing a method of operating a circuit comprising a transistor (e.g. the MMT of Fig. 2 or the SGT of Fig. 6, the transistor comprising a source, a drain, a gate for controlling a flow of current between the source and the drain, and an energy barrier at the source. In other words, the transistor is a OCT. Aspects of the method illustrated in Fig. 12 can apply to the operation of any of the circuits described above. The transistor may comprise any of the transistors described above, e.g. the transistors illustrated in Figs. 2, 6, 8, 9, 10 and 11.

[0111] First, in step S1201 the transistor is switched to an on state by applying a potential greater than a switching threshold potential to the gate, so as to permit a flow of current between the source and the drain. For example, step S1201 may correspond to switching the first and / or second transistors Tl, T2 on during the programming phase in the circuit 100 of Fig. 1, or in the circuit 500 of Fig. 5.

[0112] In step S1202, while the transistor is in the on state, the transistor is operated such that an amount of charge carriers that are injected from the source is greater than a threshold, such that the source exhibits Ohmic or quasi-Ohmic behaviour. This allows a high on-current to be achieved with the OCT transistor, despite the presence of the energy barrier at the source. In some embodiments step S1202 may be omitted.

[0113] Next, in step S1203 the transistor is switched to an off state by applying a potential lower than the switching threshold potential to the gate. Then, in step S1204 a first potential is applied to the source and a second potential is applied to the drain at a first point in time while the transistor is in the off state. The first potential is different to the second potential, such that a potential difference exists across the source and drain. In a comparable Ohmic TFT, the presence of such a potential difference could lead to a significant leakage current flowing between the source and drain while the transistor is in the off state. In contrast, since the transistor in the present embodiment is a CCT, the energy barrier at the source inhibits the leakage current through the transistor in the off state (i.e. compared to an equivalent Ohmic TFT).

[0114] In the embodiments of Figs. 11 and 12, a source is formed from materials with different work functions to provide the required energy barrier at the edge of the source, whilst enabling high current in the on-state. In some embodiments, a similar effect may be provided by providing a source comprising a single material (and therefore having the same work function over the full width of the source), but by varying a doping level in the semiconductor region across the width of the source. Specifically, higher doping may be used in part of the semiconductor region away from the edge of the source, with lower (or no) doping in part of the semiconductor region at the edge of the source. This may be referred to as "offset doping", with higher doping being used in an offset doping region that is offset from the edge of the source in a direction away from the drain. Figure 13 illustrates an example of a multimodal transistor comprising an offset doping region in a semiconductor region over the source.

[0115] The offset doping approach makes use of the fact that the energy barrier needs only to be at the edge of the source contact to block the off-current. An offset doped region (i.e. a doped region offset away from the edge of the source) allows for higher current in the on-state, similar to the dual work function contact approach described above with reference to Figs. 10 and 11, but may be simpler to fabricate compared to forming the source from two materials with different work functions.

[0116] The proximity of the doped region from the energy barrier may vary between embodiments, depending on factors such as the height of the energy barrier and the amount of doping. The embodiment illustrated in Fig. 13 represents an MMT, but the same principle of offset doping can be applied to single-gate devices. In the embodiment of Fig. 13, the drain represents a doping profile with low drain doping (LDD). Depending on the embodiment, the drain contact may be Ohmic, or may be symmetrical to the source (i.e. with the energy barrier at the source edge and offset doped region). The depletion region that forms at the energy barrier is depicted in Fig. 13. SI denotes the portion of contact between the source and semiconductor region that comprises an energy barrier, whilst S2 denotes the portion of doped region.

[0117] Figure 13 illustrates an embodiment in which n+ doping (n-type doping) is used, meaning that the device that operates with electrons as the majority charge carrier. However, in other embodiments the same principle can be applied to devices that operate with holes as the majority charge carrier (i.e. p+, or 'p-type', doping). Also, whilst Fig. 13 illustrates a staggered-electrode device structure with a gate (CGI) on an opposite side of the semiconductor region to the source and drain, in other embodiments the same principle of offset doping may be applied in coplanar device structures (i.e. devices in which all electrodes are on the same side of the semiconductor region).

[0118] Figure 14 illustrates graphs comparing the performance of an Ohmic-contact TFT, an MMT with a high energy barrier without offset doping, and an MMT with an offset doped contact as shown in Fig. 13. The MMT without offset doping has a work function (WF) of 4.57 eV, which forms a 0.4 eV high barrier in Si. The curve for the MMT with the offset doped contact shows that the low off current is maintained, whilst the on-current is higher compared to the MMT without offset doping. The two righthand graphs (labelled 'b' in Fig. 14) demonstrate how varying either the work function and / or doped portion can allow the amount and behaviour of the on-current to be tuned without affecting the off-current.

[0119] Also, as shown in Fig. 14, the off-state current is even lower when the channel gate is biased in the on-state and the source gate is biased in the off-state. This demonstrates that in an MMT, where the source comprises an energy barrier, even lower off-state currents can be achieved by biasing the channel gate in the on-state while the source gate is kept in the off-state, which at first instance may seem counterintuitive. The graphs in Fig. 14 illustrate the transfer characteristics for the current control gate (source gate, CGI) for varying channel gate voltage (VCG2S) . When the channel gate is biased at a low potential, the off-current is lower than a device with Ohmic contacts, but when the channel gate is biased at a higher potential (in other words, in an on-state) the off-current is significantly lower whilst the source gate is biased in the off-state.

[0120] The data plotted in Fig. 14 were obtained using low temperature polysilicon (LTPS) devices. However, studies by the inventors have demonstrated that this effect is not limited to LTPS devices and can also occur in other types of devices (e.g. organic MMTs). Figure 15 illustrates transfer characteristics for single gate organic transistors with Cu and Ag contacts (left-hand graph) compared to a dual gate MMT device with Ag contacts (right-hand graph). In organic TFTs (OTFTs), off-current is always low in a unipolar semiconductor (e.g. holes). In the examples illustrated in Fig. 15, the device with Ag contacts has a lower energy barrier than the device with Cu contacts, but their off-current is the same. As shown in the right-hand graph in Fig. 15, as long as the channel gate (CG2) in an organic MMT is biased in the on-state, the off-state current can be over two orders of magnitude lower. When CG2 is biased in the off- state ( VCG2S = 0 V), the off-current is lower than the single gate devices, but when CG2 is biased in the on-state ( VCG2S = -1, -2, -3, -4, -5 or -6 V), it is much lower if the source gate (CGI) is in the off-state. This demonstrates that the effect of a lower off- state current when biasing the channel gate 'on' applies even in unipolar semiconductors as long as the source gate is biased 'off'. Whilst certain embodiments of the invention have been described herein with reference to the drawings, it will be understood that many variations and modifications will be possible without departing from the scope of the invention as defined in the accompanying claims. For example, whilst embodiments of the invention have been described in relation to thin film devices, the principles disclosed herein may be readily applied to other types of devices and materials (e.g. bulk semiconductors).

Claims

1. Claims1. A method of operating a circuit comprising a transistor, the transistor comprising a source, a drain, a first gate, and a first energy barrier at the source, the method comprising: switching the transistor to an on state by applying a first switching potential having a magnitude greater than a switching threshold potential to the first gate, so as to permit a flow of current between the source and the drain; switching the transistor to an off state by applying a second switching potential having a magnitude lower than the switching threshold potential to the first gate; and controlling the circuit to apply a first potential to the source and a second potential to the drain at a first point in time while the transistor is in the off state, wherein the first potential is different to the second potential, and wherein the first energy barrier inhibits a first leakage current through the transistor in the off state.

2. The method according to claim 1, comprising: while the transistor is in the on state, controlling the circuit to operate the transistor such that an amount of charge carriers that are injected from the source is greater than a threshold, such that the source exhibits Ohmic or quasi-Ohmic behaviour.

3. The method according to claim 2, wherein said threshold corresponds to a point at which said amount of charge carriers injected is too high for an electric field of the drain to fully pinch-off the source.

4. The method according to claim 2 or 3, wherein the transistor is a phototransistor, and controlling the circuit to operate the transistor such that the amount of charge carriers that are injected from the source is greater than the threshold comprises exposing the phototransistor to light of sufficient intensity to cause said amount of charge carriers to be generated.

5. The method according to any one of claims 1 to 4, wherein the circuit comprises a capacitor connected to the drain, and controlling the circuit to apply the second potential to the drain comprises charging the capacitor to the second potential.

6. The method according to claim 5, wherein the capacitor is charged to the second potential by the flow of current through the transistor in the on state.

7. The method according to claim 5 or 6, wherein the source is connected to an input configured to receive a control signal, such that the capacitor is charged to the second potential in dependence on a level of said control signal.

8. The method according to any one of claims 5 to 7, wherein the circuit comprises a pixel circuit.

9. The method according to claim 8, wherein the pixel circuit comprises a driving circuit comprising said capacitor and said transistor, wherein said transistor operates as a switching transistor in the driving circuit.

10. The method according to any one of the preceding claims, wherein the source and drain of the transistor are biased in a first direction when the first potential is applied to the source and the second potential is applied to the drain, wherein the transistor comprises a second energy barrier at the drain, the method further comprising: controlling the circuit to apply a third potential to the source and a fourth potential to the drain at a second point in time while the transistor is in the off state, wherein the third potential is different to the fourth potential such that the source and drain of the transistor are biased in a second direction opposite to the first direction when the third potential is applied to the source and the fourth potential is applied to the drain, and wherein the second energy barrier inhibits a second leakage current through the transistor in the off state.

11. The method according to any one of the preceding claims, wherein the transistor is a multiple-gate transistor further comprising a current control gate for controlling a magnitude of current flowing between the source and the drain through the semiconductor region in dependence on a potential applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region.

12. A circuit comprising: a transistor comprising a source, a drain, a first gate, and a first energy barrier at the source, wherein the circuit is configured to switch the transistor to an on state by applying a first switching potential having a magnitude greater than a switching threshold potential to the first gate, so as to permit a flow of current between the source and the drain,wherein the circuit is configured to switch the transistor to an off state by applying a second switching potential having a magnitude lower than the switching threshold potential to the first gate, and wherein the circuit is configured to apply a first potential to the source and a second potential to the drain at a first point in time while the transistor is in the off state, wherein the first potential is different to the second potential, and wherein the first energy barrier is configured to inhibit a first leakage current through the transistor in the off state.

13. The circuit according to claim 12, wherein in use, while the transistor is in the on state, the circuit is configured to operate the transistor such that an amount of charge carriers that are injected from the source is greater than a threshold, such that the source exhibits Ohmic or quasi-Ohmic behaviour.

14. The circuit according to claim 13, wherein said threshold corresponds to a point at which said amount of charge carriers injected is too high for an electric field of the drain to fully pinch-off the source.

15. The circuit according to any one of claims 12 to 14, comprising a capacitor connected to the drain, wherein the circuit is configured to apply the second potential to the drain by charging the capacitor to the second potential.

16. The circuit according to claim 15, wherein the circuit is configured to charge the capacitor to the second potential by the flow of current through the transistor in the on state.

17. The circuit according to claim 15 or 16, wherein the source is connected to an input configured to receive a control signal, such that in use, the circuit is configured to charge the capacitor to the second potential in dependence on a level of said control signal.

18. The circuit according to any one of claims 15 to 17, wherein the circuit comprises a pixel circuit.

19. The circuit according to claim 18, wherein the pixel circuit comprises a driving circuit comprising said capacitor and said transistor, wherein in use, said transistor operates as a switching transistor in the driving circuit.

20. The circuit according to any one of claims 12 to 19, wherein the circuit is configured to bias the source and drain of the transistor in a first direction when the first potential is applied to the source and the second potential is applied to the drain, wherein the transistor comprises a second energy barrier at the drain, and wherein the circuit is configured, in use, to apply a third potential to the source and a fourth potential to the drain at a second point in time while the transistor is in the off state, wherein the third potential is different to the fourth potential such that the source and drain of the transistor are biased in a second direction opposite to the first direction when the third potential is applied to the source and the fourth potential is applied to the drain, and wherein the second energy barrier is configured to inhibit a second leakage current through the transistor in the off state.

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