Detection device

Abstract

This detection device comprises a light detection unit in which a plurality of photodiodes are two-dimensionally arranged, and a scintillator which is provided to a light-detecting surface side of the light detection unit, wherein a thin film transistor provided to the light detection unit has a top gate and a bottom gate which are opposite from each other with an oxide semiconductor of the thin film transistor sandwiched therebetween, the bottom gate being provided such that the potential thereof can be set equal to or lower than the minimum potential of the top gate.

Description

Detection device

[0001] This disclosure relates to a detection device.

[0002] A detection device that detects light and uses a scintillator to obtain visible light from X-rays is known (for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2021-102716

[0004] There is a need to adopt, as a switching element for output control of a photodiode provided in a light detection unit that detects light in a detection device, a thin-film transistor having a semiconductor layer formed of an oxide semiconductor (hereinafter referred to as an oxide semiconductor TFT). Here, the response characteristics of the oxide semiconductor TFT may change due to a load (stress) generated by a voltage applied to the gate of the thin-film transistor, the influence of X-rays irradiated on the detection device, etc. Due to the change in the response characteristics of the oxide semiconductor TFT, the detection device may operate unintentionally.

[0005] This disclosure has been made in view of the above problems, and an object thereof is to provide a detection device that can operate in a state where the influence of changes in response characteristics is suppressed even when the response characteristics of the oxide semiconductor TFT change.

[0006] A detection device according to an aspect of this disclosure is a detection device including a light detection unit in which a plurality of photodiodes are two-dimensionally arranged, and a scintillator provided on the light detection surface side of the light detection unit, wherein the thin-film transistor provided in the light detection unit has an upper gate and a lower gate, the upper gate and the lower gate face each other with the oxide semiconductor of the thin-film transistor interposed therebetween, individual potentials are applied to the upper gate and the lower gate, and the lower gate is provided so that the lowest potential of the upper gate or a potential lower than the lowest potential can be set.

[0007] Figure 1 is a schematic diagram showing the main configuration of the detection device. Figure 2 is a diagram showing the signals input to the photodetector, gate driver, and multiplexer, the signals output from the photodetector, gate driver, and multiplexer, and the connections of the wiring that transmits these signals. Figure 3 is a diagram showing the circuit configuration of the optical sensor provided in the photodetector. Figure 4 is a diagram showing the relationship between multiple optical sensors provided in the photodetector, scan lines, and signal lines. Figure 5 is a plan view of the stacked structure included in the circuit configuration shown in Figure 3. Figure 6 is a plan view of the stacked structure included in the circuit configuration shown in Figure 3. Figure 7 is a cross-sectional view of the IV-V section shown from Figure 5 to Figure 6. Figure 8 is a graph showing an example of the response characteristics of an oxide semiconductor TFT. Figure 9 is a graph showing an example of the response characteristics of an oxide semiconductor TFT before and after characteristic shift. Figure 10 is a graph showing an example of how the lower gate's potential shift control corresponds to the characteristic shift. Figure 11 shows the signal input to the photodetector, gate driver, and multiplexer, the signal output from the photodetector, gate driver, and multiplexer, and the connections to the wiring that transmits these signals in Embodiment 2. Figure 12 shows the circuit configuration of the optical sensor provided in the photodetector. Figure 13 is a plan view of the stacked structure included in the circuit configuration shown in Figure 12. Figure 14 is a plan view of the stacked structure included in the circuit configuration shown in Figure 12. Figure 15 shows the signal input to the photodetector, gate driver, and multiplexer, the signal output from the photodetector, gate driver, and multiplexer, and the connections to the wiring that transmits these signals in Embodiment 3. Figure 16 shows the circuit configuration of the optical sensor provided in the photodetector. Figure 17 is a plan view of the stacked structure included in the circuit configuration shown in Figure 16. Figure 18 is a plan view of the stacked structure included in the circuit configuration shown in Figure 16.

[0008] The embodiments of this disclosure will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and modifications that can be easily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of this disclosure. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of parts in order to clarify the explanation, but these are merely examples and do not limit the interpretation of this disclosure. In addition, in this specification and the drawings, elements similar to those described above in previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] (Embodiment 1) Figure 1 is a schematic diagram showing the main configuration of the detection device 1. The detection device 1 comprises a light detection unit 2, a gate driver 3, a multiplexer 4, a control circuit 5, a connection unit 6, and a setting circuit 7.

[0010] The light detection unit 2 includes a plurality of two-dimensionally arranged light sensors LS (see Figure 3, etc.) and a scintillator provided on the side of the light entering the plurality of light sensors LS. In this embodiment, the scintillator converts X-rays into visible light. Each of the plurality of light sensors LS detects the visible light converted from X-rays by the scintillator.

[0011] The gate driver 3 is a circuit that functions as a gate driver, supplying a drive signal Vgate to a plurality of optical sensors LS provided in the optical detection unit 2. The multiplexer 4 is a multiplexer connected to the plurality of optical sensors LS provided in the optical detection unit 2. The optical detection unit 2, the gate driver 3, and the multiplexer 4 are mounted on a substrate 10. The substrate 10 is, for example, a rigid substrate, but is not limited to this, and may be of other types.

[0012] The control circuit 5 is a Read Out Integrated Circuit (ROIC) that reads the output obtained from the multiple optical sensors LS provided in the optical detection unit 2 via the multiplexer 4. Furthermore, the control circuit 5 in this embodiment has the function of operating the multiple optical sensors LS provided in the optical detection unit 2.

[0013] The connection section 6 is a flexible printed circuit board (FPC) on which wiring is provided to connect the various components provided on the circuit board 10 with the control circuit 5.

[0014] The setting circuit 7 is a circuit for setting the gate voltage of the switching elements mounted on the circuit board 10. The setting circuit 7 has a register 8. The register 8 is a register that holds the settings related to the gate voltage of the switching elements mounted on the circuit board 10. Details of the setting circuit 7 and the register 8 will be described later.

[0015] Figure 2 shows the signals input to the photodetector 2, gate driver 3, and multiplexer 4, the signals output from the photodetector 2, gate driver 3, and multiplexer 4, and the connections of the wiring that transmits these signals. Figure 4 shows the relationship between the multiple optical sensors LS provided in the photodetector 2, the scan lines Rd1, Rd2, ..., RdV, and the signal lines Sig1, Sig2, ..., SigH. The multiple optical sensors LS provided in the photodetector 2 are connected to the gate driver 3 via the scan line Rd, as shown in Figure 2. The scan line Rd includes V wires, such as scan lines Rd1, Rd2, ..., RdV. The value of V corresponds to the number of arrangements of the second direction Dy (see Figure 3) of the multiple optical sensors LS in the photodetector 2. To give a specific example, V in this embodiment is, for example, 210, but is not limited to this and can be changed as appropriate.

[0016] As shown in Figure 2, the multiple optical sensors LS provided in the optical detection unit 2 are connected to the multiplexer 4 via signal lines Sig. The signal lines Sig include H wires, such as signal lines Sig1, Sig2, ..., SigH. The value of H corresponds to the number of arrangements of the multiple optical sensors LS in the optical detection unit 2 in the first direction Dx (see Figure 3). For example, in this embodiment, H is 162, but is not limited to this and can be changed as appropriate.

[0017] Hereinafter, the direction along which scan lines Rd1, Rd2, ..., RdV lie will be referred to as the first direction Dx. The direction along which signal lines Sig1, Sig2, ..., SigH lie will be referred to as the second direction Dy. The first direction Dx and the second direction Dy intersect (for example, are perpendicular). The term "plan view" refers to a front view of the plane (Dx-Dy plane) that lies along the first direction Dx and the second direction Dy. When "plan view" is used, it refers to the viewpoint from which the Dx-Dy plane is viewed from the front.

[0018] The scan lines Rd1, Rd2, ..., RdV included in the scan line Rd can be said to be multiple scan lines aligned along the first direction Dx and the second direction Dy. The signal lines Sig1, Sig2, ..., SigH included in the signal line Sig can be said to be multiple signal lines aligned along the second direction Dy and the first direction Dx. The scan line Rd and the signal line Sig are insulated from each other by being formed in different layers in a laminated structure described later, and are non-conductive. The scan line Rd and the signal line Sig extend into the photodetector 2. In Embodiment 1, one optical sensor LS is placed in each of the multiple subregions separated by a grid formed by the scan line Rd and the signal line Sig within the photodetector 2. That is, the optical sensors LS are arranged two-dimensionally in the photodetector 2 along the Dx-Dy plane. Furthermore, it can be said that, of the multiple optical sensors LS, all except those along the outer edge are located within the range enclosed by two of the multiple signal lines included in the signal line Sig and two of the multiple scan lines included in the scan line Rd.

[0019] Figure 3 shows the circuit configuration of the light sensor LS provided in the light detection unit 2. The light sensor LS has a photodiode 21. The photodiode 21 is a photodiode that converts irradiated light into electric charge (electrons and holes). The light sensor LS also functions as a capacitor 22. The charge output from the photodiode 21 is stored in the capacitor 22. The anode of the photodiode 21 is connected to a wiring to which the potential PVSS2 is applied. The cathode of the photodiode 21 is connected to either the source or the drain of the TFT 23. The capacitor 22 is electrically in parallel with the photodiode 21. Therefore, when shown in the circuit diagram, the capacitor 22 can be considered to be connected to the wiring and either the source or the drain of the TFT 23.

[0020] TFT23 is a thin-film transistor (TFT) having a semiconductor layer OS formed of an oxide semiconductor. TFT23 is a switching element. TFT23 is formed of an oxide semiconductor containing, for example, indium, gallium, zinc, and oxygen. Hereinafter, when referred to as an oxide semiconductor TFT, it refers to a TFT having a semiconductor layer OS formed of an oxide semiconductor, similar to TFT23. The oxide semiconductor TFT has electrode layers GL2 and GL1 sandwiching the semiconductor layer OS, as shown in the TFT portion 500 in Figure 7. Electrode layer GL2 is the upper gate, and electrode layer GL1 is the lower gate. Electrode layer GL2 faces the semiconductor layer OS with an insulating layer GI in between. Electrode layer GL1 faces the semiconductor layer OS with an insulating layer UG in between.

[0021] The source or drain of TFT23 is connected to the signal line Sig(x). The signal line Sig(x) is one of the signal lines Sig1, Sig2, ..., SigH.

[0022] The TFT 23 has two gates positioned opposite each other across the source-drain semiconductor layer. One of the two gates is designated as the upper gate 231, and the other as the lower gate 241. The upper gate 231 is connected to the scan line Rd(y) to which the drive signal Vgate is applied. The scan line Rd(y) is one of the scan lines Rd1, Rd2, ..., RdV. The lower gate 241 is connected to the potential line 24 to which the lower gate potential VGL2 is applied. Details of the lower gate potential VGL2 will be described later.

[0023] The drive signal Vgate is either the drive potential VGH or the reference potential VGL (see Figure 2). The drive potential VGH is a potential higher than the reference potential and functions as an ON signal to operate the TFT so that current flows between its source and drain. The reference potential VGL is the reference potential and functions as an OFF signal to operate the TFT so that current does not flow between its source and drain. The reference potential is, for example, 0 volts (V), but any preset potential is acceptable, and its specific potential can be changed as appropriate.

[0024] The gate driver 3 applies an ON signal to the gate of the TFT 23 to turn it ON. When the TFT 23 is ON, electrical signals are transmitted between the source and drain. Therefore, when the TFT 23 is turned ON, the charge stored in the capacitor 22 is transmitted to the signal line Sig(x). Hereafter, when referred to as signal OP1, it refers to the electrical signal applied to the signal line Sig(x).

[0025] The gate driver 3 is a shift register circuit that performs scanning by sequentially supplying ON signals to scan lines Rd1, Rd2, ..., RdV. In Figure 2, scanning is shown as scan Vscan. The gate driver 3 supplies an OFF signal to the TFT 23 during periods when no ON signal is supplied. That is, the TFT 23 is in an OFF state with an OFF signal supplied, except during periods when an ON signal is supplied. In the OFF state of the TFT 23, no electrical signal is transmitted between the source and drain.

[0026] Furthermore, the wiring connected to the gate driver 3 shown in Figure 2 is not limited to the wiring that provides the drive potential VGL, the wiring that provides the reference potential VGL, and the potential line 24 mentioned above. Specifically, the gate driver 3 is also connected to wiring for individually transmitting the input signals OE1_CK1, OE1_CK2, OE1_VST, and VOUT1, respectively. These wires are used to transmit the operation control signals of the scanning gate driver 3 from the control circuit 5 to the gate driver 3.

[0027] As shown in Figure 2, an output holding unit 11 is interposed between the photodetector 2 and the multiplexer 4. The output holding unit 11 is connected to the photodetector 2 via a signal line Sig. The output holding unit 11 is connected to the multiplexer 4 via an input line Ccds. The number of input lines Ccds is the same as the number of signal lines Sig (H). The output holding unit 11 has a configuration (such as a circuit that functions as a capacitor) for holding the signal OP1. The register of the output holding unit 11 holds the signal OP1 transmitted from the photodetector 2 via the signal line Sig and provides it to the input line Ccds. Note that the expression "input line Ccds" is intended to mean the input to the multiplexer 4.

[0028] Multiplexer 4 is a multiplexer. Multiplexer 4 sequentially outputs the signal OP1 transmitted via the input line Ccds to output lines Rx, which are fewer in number than the input line Ccds. The number of output lines Rx is 1 / R of the number of signal lines Sig and input lines Ccds. R is a natural number greater than or equal to 2, for example, 6.

[0029] In Figure 2, the wiring connected to the multiplexer 4 transmits the signals ASW and xASW from the control circuit 5 to the multiplexer 4 individually to operate the multiplexer 4. Furthermore, among the wiring connected to the output holding unit 11, the wiring to which the potential VREF is supplied provides the reset potential for the output holding unit 11, while the other wiring transmits the control signals RST1T and xRST1T to reset the output holding unit 11.

[0030] As shown in Figure 2, one end 14 of the wiring connected to the photodetector 2, gate driver 3, multiplexer 4, and output holding unit 11, beyond the dashed line 13, is connected to various signal or potential supply sources such as the control circuit 5. Furthermore, a rectifier 12 is provided in the wiring connected to the photodetector 2, gate driver 3, multiplexer 4, and output holding unit 11. The rectifier 12 is equipped with a protection diode to define the signal transmission direction in each wiring in one direction and to suppress overcurrent.

[0031] Next, a more detailed explanation of the implementation of the circuit configuration shown in Figure 3 will be given with reference to Figures 5 to 7.

[0032] Figures 5 and 6 are plan views of the stacked structure included in the circuit configuration shown in Figure 3. Figure 5 mainly shows the TFT 23 and the wiring connected to the TFT 23. Figure 6 mainly shows a part of the configuration of the optical sensor LS in Figure 3. The configuration shown in Figure 6 is located on an upper layer than the configuration shown in Figure 5.

[0033] Figure 7 is a cross-sectional view of the IV-V section shown from Figure 5 to Figure 6. Primarily, PU1 below the dashed line PU in Figure 7 represents the IV-IV' section shown in Figure 5. The IV-IV' section shown in Figure 5 is assumed to continue via a connection point Cn. Also, PU2 below the dashed line PU in Figure 7 represents the V'-V section shown in Figure 6. As indicated by the dashed arrows pointing from IV' to V' in Figures 5 and 6, IV' in Figure 5 and V' in Figure 6 are assumed to be continuous.

[0034] The circuit configuration shown in Figure 3 is implemented by a laminated structure formed on one side of the substrate 10, as shown in Figure 7. The laminated structure is provided between the substrate 10 and the scintillator 15. Hereinafter, the lamination direction of the laminated structure will be referred to as the third direction Dz. The third direction Dz intersects (for example, is orthogonal to) the first direction Dx and the second direction Dy. When one end Dz1 of a certain configuration included in the laminated structure is described, it refers to the substrate 10 side with respect to that configuration. When the other end Dz2 of a certain configuration is described, it refers to the scintillator 15 side with respect to that configuration. For example, one side of the substrate 10 is the other end Dz2 of the substrate 10. The other end Dz2 is the photodetection surface side of the photodetection unit 2, which is provided with a plurality of photosensors LS. That is, the scintillator 15 is provided on the photodetection surface side of the photodetection unit 2. The scintillator 15 is a component that can obtain visible light from X-rays. More specifically, visible light generated by X-rays irradiated onto the scintillator 15 enters the area beyond the scintillator 15 towards the Dz1 side, moving from the other end Dz2 towards the one end Dz1 side. The light sensor LS detects the visible light and generates an output (charge) corresponding to the intensity of the detected visible light.

[0035] As shown in Figure 7, on the other end Dz2 side of the substrate 10, the following layers are stacked in order from the substrate 10 side toward the scintillator 15 side: electrode layer GL1, insulating layer UC, semiconductor layer OS, insulating layer GI, electrode layer GL2, insulating layer PAS, electrode layer SL, insulating layer IL1, planarization film OC1, electrode layer LE, first semiconductor layer 281, second semiconductor layer 282, third semiconductor layer 283, electrode layer UIO, insulating layer IL2, planarization film OC2, electrode layer BIS, electrode layer PIO, insulating layer IL3, and planarization film OC3.

[0036] The electrode layer GL1 is an electrode layer formed of a conductor. The electrode layer GL1 is formed using, for example, a molybdenum alloy (MoW) containing molybdenum (Mo) and tungsten (W). The electrode layer GL1 is provided as the lower gate 241 of the TFT 23 (see Figures 3 and 5).

[0037] The insulating layer UC is an insulating layer that insulates the electrode layer GL1 from the semiconductor layer OS. The insulating layer UC has a multilayer structure in which, for example, a silicon nitride (SiN) layer is formed at one end Dz1 and a silicon oxide (SiO) layer is formed at the other end Dz2.

[0038] The semiconductor layer OS is an oxide semiconductor layer. The semiconductor layer OS is formed using, for example, IGZO containing In (indium), Ga (gallium), Zn (zinc), and O (oxygen), or IGO containing In (indium), Ga (gallium), and O (oxygen). The semiconductor layer OS is provided, for example, as an oxide semiconductor interposed between the source and drain of the TFT 23. In Figure 5, the oxide semiconductor is shown as oxide semiconductor 232.

[0039] The insulating layer GI is an insulating layer that insulates the electrode layer GL2 from the insulating layer GI. The insulating layer GI and the electrode layer GL2 are formed using, for example, silicon oxide (SiO).

[0040] The electrode layer GL2 is an electrode layer formed of a conductor. The electrode layer GL2 has a multilayer structure in which, for example, a titanium (Ti) layer is formed on one end Dz1 and a molybdenum alloy (MoW) layer is formed on the other end Dz2. The electrode layer GL2 is provided as the upper gate 231 and scan line Rd(y) of the TFT 23 (see Figures 3 and 5). The upper gate 231 is positioned opposite the electrode layer GL1 in the third direction Dz, with the semiconductor of the TFT 23, which is formed of semiconductor layer OS, in between.

[0041] The insulating layer PAS is an insulating layer that insulates the electrode layer GL2 from the electrode layer SL. The insulating layer PAS has a multilayer structure in which, for example, a silicon nitride (SiN) layer is formed at one end Dz1 and a silicon oxide (SiO) layer is formed at the other end Dz2.

[0042] The electrode layer SL is an electrode layer formed of a conductor. The electrode layer SL has a multilayer structure in which, for example, a layer of aluminum (Al) is sandwiched between layers of titanium (Ti) at one end Dz1 and the other end Dz2. The electrode layer SL is provided as a signal line Sig(x), the source and drain of the TFT 23, wiring connecting the TFT 23 and the optical sensor LS, and potential line 24 (see Figures 3 and 5). In Figure 5, the wiring connecting the TFT 23 and the optical sensor LS is shown as a connection part 235.

[0043] In the laminated structure between the substrate 10 and the scintillator 15, a contact hole 291 for connecting the source and drain of the TFT 23 and the semiconductor layer OS is provided. The contact hole 291 is a contact hole that penetrates the insulating layer GI and the insulating layer PAS in the third direction Dz.

[0044] In the laminated structure between the substrate 10 and the scintillator 15, a contact hole 292 for connecting the potential line 24 and the electrode layer GL1 is provided. The contact hole 292 is a contact hole that penetrates the insulating layer UC, the insulating layer GI, and the insulating layer PAS in the third direction Dz.

[0045] The insulating layer IL1 is an insulating layer that insulates the electrode layer SL and the planarization film OC1. The insulating layer IL1 is formed using, for example, silicon nitride (SiN).

[0046] The planarization film OC1 is an organic planarization film. The planarization film OC1 has lower moisture permeability than the planarization films OC2 and OC3. The planarization film OC1 can suppress the influence of moisture on the structure on one end Dz1 side compared to the planarization film OC1. The planarization film OC1 is formed using, for example, a low moisture permeability polyimide.

[0047] The electrode layer LE is an electrode layer formed of a conductor. The electrode layer LE is formed using, for example, a molybdenum alloy (MoW). The electrode layer LE is provided as one of the two electrodes sandwiching the photodetector 280.

[0048] As shown in FIG. 7, the electrode layer LE is connected to the connection portion 235. In the laminated structure between the substrate 10 and the scintillator 15, a contact hole 293 for connecting the electrode layer LE to the connection portion 235 is provided. The contact hole 293 is a contact hole that penetrates the insulating layer IL1 and the planarization film OC1 in the third direction Dz.

[0049] The first semiconductor layer 281, the second semiconductor layer 282, and the third semiconductor layer 283 constitute the photodetector 280. Specifically, the second semiconductor layer 282, which is formed using amorphous silicon (a-Si), is sandwiched between the first semiconductor layer 281, which is an N-type semiconductor corresponding to the second semiconductor layer 282, and the third semiconductor layer 283, which is a P-type semiconductor corresponding to the second semiconductor layer 282.

[0050] Electrode layer UIO is an electrode layer formed of a conductor. Electrode layer LE is formed using a translucent conductor such as indium tin oxide (ITO). Alternatively, it may be formed using an opaque conductor such as titanium (Ti) or molybungsten (MoW). Furthermore, an ITO electrode may be laminated on top of the MoW. Electrode layer UIO is provided as the other of two electrodes sandwiching the photodetector 280.

[0051] When light is shone on the photodetector 280, the power generated by the photovoltaic effect causes a current to be generated in the electrode layer LE. In this way, the light sensor LS functions as a photodiode 21. The electrode layer LE, the first semiconductor layer 281, the second semiconductor layer 282, the third semiconductor layer 283, and the electrode layer UIO constitute the main parts of the light sensor LS.

[0052] The insulating layer IL2 is an insulating layer that insulates the planarization film OC1 and the main portion of the optical sensor LS from the planarization film OC2. The insulating layer IL2 is formed using, for example, silicon nitride (SiN).

[0053] The planarization film OC2 is an organic planarization film. Planarization films OC2 and OC3 have higher light transmittance than planarization film OC1. The light transmittance of planarization films OC2 and OC3 allows for a higher light sensitivity of the optical sensor LS. Planarization films OC2 and OC3 are formed using, for example, acrylic, which exhibits high light transmittance.

[0054] The electrode layer BIS is an electrode layer formed of a conductor. The electrode layer BIS has a multilayer structure in which, for example, a layer of aluminum-silicon alloy (AlSi) is sandwiched between layers of molybdenum alloy (MoW) at one end Dz1 and the other end Dz2.

[0055] The electrode layer PIO is an electrode layer formed of a conductor. The electrode layer PIO is formed using a translucent conductor such as indium tin oxide (ITO). The electrode layer BIS and the electrode layer PIO constitute an additional part of the optical sensor LS.

[0056] As shown in Figure 7, electrode layer PIO connects electrode layer UIO and electrode layer BIS. The laminated structure between substrate 10 and scintillator 15 is provided with contact holes 294 in electrode layer PIO for connecting electrode layer UIO and electrode layer BIS. Contact holes 294 are contact holes that penetrate the planarization film OC1 and the insulating layer IL2 in the third direction Dz. Contact holes 294 include a large contact hole 2941 that penetrates the planarization film OC1 at one end Dz1, and a small contact hole 2942 that penetrates the insulating layer IL2 in the third direction Dz within the large contact hole 2941 (see Figure 6).

[0057] The insulating layer IL3 is an insulating layer that insulates the planarization film OC2 and the added portion of the optical sensor LS from the planarization film OC3. The insulating layer IL3 is formed using, for example, silicon nitride (SiN). The planarization film OC3 is an organic planarization film.

[0058] For the first direction Dx, the signal line Sig(x) side is designated as one end Dx1, and the potential line 24 side is designated as the other end Dx2, with the connection portion 235 in between (see Figures 5 and 6). Similarly, for the second direction Dy, the contact hole 293 side is designated as the other end Dy1, with the TFT 23 in between, and the scan line Rd(y) side is designated as the other end Dy2 (see Figures 5 and 6). With the upper gate 231 in between, the signal line Sig(x) and the connection portion 235 are aligned in the first direction Dx. In Figure 5, with the upper gate 231 in between, the signal line Sig(x) is positioned on one end Dx1, and the connection portion 235 is positioned on the other end Dx2.

[0059] As shown in Figure 5, the upper gate 231 is provided so that its longitudinal direction is aligned with the second direction Dy. The upper gate 231 extends from both ends of the oxide semiconductor 232 in the second direction Dy in a plan view. The upper gate 231 is connected to the scan line Rd(y) at the other end Dy2 side. The oxide semiconductor 232 is provided so as to overlap with a part of the upper gate 231 and a part of the lower gate 241 in a plan view. The part of the lower gate 241 that overlaps with the upper gate 231 is aligned with the second direction Dy. In addition, the other part of the lower gate 241 that is connected to the potential line 24 via the contact hole 292 is aligned with the first direction Dx. Near the position where the lower gate 241 overlaps with the other end Dy1 side of the upper gate 231 in a plan view, the part aligned with the second direction Dy and the part aligned with the first direction Dx are connected so as to be continuous.

[0060] In Embodiment 1, the width of a portion of the lower gate 241 that overlaps with the upper gate 231 in a plan view, in the first direction Dx, is greater than the width of the upper gate 231 in the first direction Dx. Specifically, the lower gate 241 has a width that is greater than the upper gate 231 by a width D0 on one end Dx1 side and the other end Dx2 side, in a plan view.

[0061] Furthermore, in Embodiment 1, the width of the scan line Rd(y) in the second direction Dy is width D1, except for the area overlapping with the signal line Sig(x) in a planar view and its vicinity. Of the scan line Rd(y), the width of the second direction Dy in the area overlapping with the signal line Sig(x) in a planar view and its vicinity is width D2. Width D2 is smaller than width D1.

[0062] Furthermore, in Embodiment 1, the width of the signal line Sig(x) and the potential line 24 in the first direction Dx is D3, except for the area that overlaps with the scan line Rd(y) in a planar view and its vicinity. Of the signal line Sig(x) and the potential line 24, the width of the first direction Dx in the area that overlaps with the scan line Rd(y) in a planar view and its vicinity is D4. Width D4 is greater than width D3.

[0063] The width D0 is, for example, 1.4 μm. The widths D1 and D4 are, for example, 4 μm. The widths D2 and D3 are, for example, 3 μm. Furthermore, the area shown as TFT23 in Figure 5 is provided to be, for example, approximately 15 μm in the first direction Dx and approximately 3 μm in the second direction Dy. Note that the positional relationship between TFT23 and the lower gate 241 in Figure 5 is only approximate and does not strictly reflect the actual dimensions of the width of TFT23 in the first direction Dx and the width of a part of the lower gate 241 in the first direction Dx. In reality, as shown in Figure 7, the electrode layer GL1 including the lower gate 241 is provided to cover a larger area than the semiconductor layer OS and the electrode layer GL2.

[0064] As shown in Figure 6, in a planar view, the electrode layer PIO, electrode layer BIS, electrode layer LE, photodetector 280, and electrode layer UIO are arranged to overlap. In a single photosensor LS configuration, of the electrode layer PIO, electrode layer BIS, electrode layer LE, photodetector 280, and electrode layer UIO, electrode layer PIO has the largest outer edge relatively.

[0065] From a planar perspective, the shapes of electrode layer PIO and electrode layer BIS are frame-like. The frame is square. Two of the four sides are parallel to the first direction Dx, and the other two sides are parallel to the second direction Dy. From a planar perspective, electrode layer BIS is bordered by electrode layer PIO, which covers a larger area.

[0066] The electrode layer LE is provided to cover a smaller area inside the electrode layer BIS than the electrode layer PIO. In a plan view, the electrode layer LE is bordered by the electrode layer BIS. In Embodiment 1, the outer edge of the electrode layer BIS is almost square in shape, following the inner edge of the electrode layer BIS, but strictly speaking, it is an octagon with the corners of the four vertices of the square slightly cut off. A portion of the outer edge of the electrode layer LE overlaps with a portion of the inner edge of the electrode layer PIO in a plan view.

[0067] The photodetector 280 is provided to cover a smaller area than the electrode layer LE, within the range that overlaps with the translucent electrode layer LE. The electrode layer UIO is provided to cover a smaller area than the electrode layer LE and the photodetector 280, within the range that overlaps with the translucent electrode layer LE. As shown in Figure 7, the photodetector 280 and the electrode layer UIO are provided on the other end Dz2 side of the electrode layer LE, so that they can receive external X-ray irradiation converted to visible light by the scintillator 15.

[0068] Furthermore, the insulating layer IL3, as described with reference to Figure 7, is provided with drainage holes 271 and 272 as shown in Figure 6. Drainage hole 271 is positioned in a location that does not overlap with electrode layer PIO and electrode layer BIS in a plan view. Also, drainage hole 271 is positioned in the area where electrode layer LE is provided in a plan view. Specifically, drainage hole 271 is positioned, for example, near one of the four vertices of the square frame of electrode layer BIS. Contact hole 294 is positioned in the area where electrode layer LE is provided in a plan view, near one of the other four vertices of the square frame of electrode layer BIS. Here, one of the four vertices of electrode layer BIS closer to drainage hole 271 and one of the four vertices of electrode layer BIS closer to contact hole 294 are positioned opposite each other in directions that intersect the first direction Dx and the second direction Dy. The drainage holes 271 and 272 have a rectangular shape in a plan view, for example, with a side length of about 5 μm, but are not limited to this, and their specific shape and dimensions can be changed as appropriate.

[0069] The contact hole 293 is located in the area where the electrode layer LE is provided from a plan view, near one of the four vertices of the square frame of the electrode layer BIS and near the drain hole 271. However, the contact hole 293 is located in a position that does not overlap with the drain hole 271 and is relatively far from one of the four vertices.

[0070] In Embodiment 1, the photodetector 280 and electrode layer UIO are shaped so as not to overlap with the drainage holes 271 and contact holes 293 in a planar view. Specifically, as shown in Figure 7, the photodetector 280 and electrode layer UIO are formed to cover an area that is cut out from the square-shaped area formed by the inner edge of the electrode layer PIO, specifically the area where the drainage holes 271 and contact holes 293 are formed. More precisely, the area covered by the photodetector 280 is shaped like the corners of the remaining triangle in the aforementioned square-shaped area slightly cut off.

[0071] More specifically, the photodetector 280 and the contact hole 293 are separated by a width D5 in the first direction Dx and a width D6 in the second direction Dy. The outer edge of electrode layer UIO traces a position approximately D7 away from the outer edge of photodetector 280. The outer edge of photodetector 280 also traces a position approximately D8 away from the inner edge of electrode layer BIS.

[0072] The drain holes 272 are positioned so as not to overlap with the electrode layer LE in a planar view. In Embodiment 1, the drain holes 272 and the electrode layer LE are separated by a width D9. The drain holes 271 are positioned in a range that overlaps with the electrode layer BIS. Specifically, the drain holes 271 are positioned, for example, near the four vertices of the square frame of the electrode layer BIS.

[0073] Widths D5 and D6 are, for example, 4 μm. Width D7 is, for example, 2.75 μm. Width D8 is, for example, 3.25 μm. Width D9 is, for example, 3.8 μm.

[0074] Contact holes such as contact hole 293 are holes formed in the insulating layer, which widen from one end Dz1 to the other end Dz2, and the inside is filled with a layer laminated on the other end Dz2 of the insulating layer. Specifically, the smallest part of contact hole 2932 on the one end Dz1 side is 4 μm in the first direction Dx and 4 μm in the second direction Dy when viewed from a plan view. The largest part of contact hole 2931 on the other end Dz2 side is 8 μm in the first direction Dx and 8 μm in the second direction Dy when viewed from a plan view.

[0075] The largest portion of the contact hole 294 on the other end Dz2 side of the large contact hole 2941 is 14 μm in the first direction Dx and 14 μm in the second direction Dy when viewed from a plan view. The largest portion of the contact hole 294 on the other end Dz2 side of the small contact hole 2942 is 6.5 μm in the first direction Dx and 6.5 μm in the second direction Dy when viewed from a plan view.

[0076] Contact holes other than contact holes 293 and 294 (contact holes 291, 292, etc.) are generally about 2.5 μm in the first direction Dx and about 2.5 μm in the second direction Dy. Although contact holes other than contact holes 293 and 294 are strictly speaking flared holes, there is not much of a remarkable difference in dimensions between the upper and lower ends.

[0077] The configurations shown in Figures 5 and 6 represent the configuration of one of the multiple optical sensors LS arranged in a matrix in the optical detection unit 2. Therefore, the optical detection unit 2 has multiple stacked structures in which the configuration shown in Figure 5 and the configuration shown in Figure 6 overlap in a planar view, arranged in a matrix along the first direction Dx and the second direction Dy. The mounting area units for the configuration of one optical sensor LS are, for example, 100 μm in the first direction Dx and 100 μm in the second direction Dy, but are not limited to these and can be changed as appropriate. In other words, the sizes of widths D1 to D9, the mounting area of ​​the oxide semiconductor TFT, the dimensions of various contact holes, etc., described above are examples based on the mounting area units and are not limited to the above values.

[0078] Next, we will explain the response characteristics of oxide semiconductor TFTs, such as TFT23, with reference to Figures 8 and 9.

[0079] Figure 8 is a graph showing an example of the response characteristics of an oxide semiconductor TFT. In the graphs of Figure 8 and Figure 9 (described later), the horizontal axis represents the potential applied to the upper gate. In the graphs of Figure 8 and Figure 9 (described later), the vertical axis represents the magnitude of the signal current passing through the source-drain of the oxide semiconductor TFT, as in TFT 23. In the explanation referring to Figure 8, it is assumed that the potential of the lower gate 241 is 0 volts (V).

[0080] As shown in Graph 901 of Figure 8, oxide semiconductor TFTs generally do not conduct current between the source and drain when the potential applied to the upper gate is the reference potential VGL, i.e., 0 volts (V). In other words, an oxide semiconductor TFT in the off state does not conduct current between the source and drain. On the other hand, when the potential applied to the upper gate exceeds 0 volts, the oxide semiconductor TFT begins to conduct current between the source and drain. In other words, an oxide semiconductor TFT in the on state does not conduct current between the source and drain.

[0081] Furthermore, in an oxide semiconductor TFT, the higher the potential applied to the upper gate, the greater the current that can flow between the source and drain. Figure 8 shows an example where the potential applied to the upper gate to turn on the oxide semiconductor TFT corresponds to the drive potential VGH, resulting in a dynamic range of DR1. Here, dynamic range refers to the difference in the magnitude of the current that can flow between the source and drain when the potential applied to the upper gate of the oxide semiconductor TFT is the reference potential VGL and when it is the drive potential VGH.

[0082] Incidentally, oxide semiconductor TFTs like TFT23 can change their response characteristics due to degradation. Specifically, for oxide semiconductor TFTs, the gate potential required to prevent current flow between the source and drain may shift from 0 volts to a negative potential due to certain causes. These certain causes include, for example, the load (stress) on the gate voltage due to repeated switching between the on and off states of the oxide semiconductor TFT, and the irradiation of the detection device 1 with light. Hereinafter, when "characteristic shift" is mentioned, it refers to the shift from 0 volts to a negative potential at the gate potential required to prevent current flow between the source and drain.

[0083] Figure 9 is a graph showing an example of the response characteristics of an oxide semiconductor TFT before and after a characteristic shift. In Figure 9, the graph showing the response characteristics before the characteristic shift is shown as graph 901, similar to Figure 8. Also in Figure 9, the graph showing the response characteristics after the characteristic shift is shown as graph 902. After the characteristic shift, the oxide semiconductor TFT is in a state where current (current SHA) can flow between the source and drain even when the potential applied to the upper gate is the reference potential VGL, i.e., 0 volts (V). Furthermore, the dynamic range of the oxide semiconductor TFT after the shift becomes dynamic range DR2. Dynamic range DR2 is significantly smaller than dynamic range DR1. Therefore, the characteristic shift significantly changes the behavior of the oxide semiconductor TFT in response to changes in the potential of the upper gate. If no response is taken to such a characteristic shift, the detection device 1 may not operate normally in response to the potential control of the upper gate.

[0084] Therefore, in Embodiment 1, a mechanism is applied to make the oxide semiconductor TFT operate substantially the same as before the characteristic shift even if a characteristic shift occurs. Specifically, the detection device 1 is equipped with a function that can shift the potential of the lower gate to a negative value.

[0085] Figure 10 is a graph showing an example of how the lower gate potential shift control addresses characteristic shifts. In Embodiment 1, when a characteristic shift occurs, a lower gate potential shift SHT can be performed to shift the potential of the lower gate from 0 volts (V) to a negative potential MV. The negative potential MV is a negative potential lower than 0 volts (V). This makes it possible to substantially prevent current from flowing between the source and drain when the potential applied to the upper gate is the reference potential VGL, i.e., 0 volts (V). Furthermore, by performing the lower gate potential shift SHT, the dynamic range can be set to dynamic range DR3 even after a characteristic shift. Dynamic range DR3 is significantly closer to dynamic range DR1 than dynamic range DR2. Thus, in Embodiment 1, even after a characteristic shift, the response characteristics of the oxide semiconductor TFT can be substantially the same as before the characteristic shift. Therefore, according to Embodiment 1, even if a characteristic shift occurs, abnormal operation of the detection device 1 can be suppressed.

[0086] The application of the lower gate potential shift SHT by setting a negative potential MV is performed by the setting circuit 7, as explained with reference to Figure 1. Specifically, when a value corresponding to the negative potential MV is set in the register 8 of the setting circuit 7, the setting circuit 7 applies a potential corresponding to the value set in the register 8 as the lower gate potential VGL2 to the potential line 24. This makes it possible to set the potential applied to the lower gate of an oxide semiconductor TFT, such as the lower gate 241 in TFT 23, to a negative potential MV.

[0087] In Embodiment 1, the maximum potential of the lower gate potential VGL2 that can be achieved by setting a value for the register 8 of the setting circuit 7 is the same potential as the reference potential VGL. In other words, the lower gate potential VGL2 is a potential less than or equal to the reference potential VGL. Unless a characteristic shift occurs, the lower gate potential VGL2 may be the same as the reference potential VGL. If a characteristic shift occurs, the degree of the negative potential MV is determined according to the degree of the shift, and a value corresponding to the determined degree is set in the register 8. As a result, the lower gate potential VGL2 becomes a potential less than the reference potential VGL.

[0088] The administrator of detection device 1 can adjust the operation of detection device 1 after a characteristic shift occurs by setting a value for register 8. Specifically, by adjusting the value set for register 8 until the administrator of detection device 1 operates substantially the same as before the characteristic shift, detection device 1 will operate normally even after a characteristic shift occurs. The value for register 8 can be set by, for example, an external setting device connected to the setting circuit 7, but is not limited to this. As another example, an adjustment interface (volume) for changing the value set for register 8 may be provided as part of the configuration of the setting circuit 7 or detection device 1 connected to the setting circuit 7.

[0089] It should be noted that TFTs mounted on the substrate 10, not limited to TFT 23, are oxide semiconductor TFTs similar to TFT 23 and have a TFT portion 500 (see Figure 7). Examples of "TFTs mounted on the substrate 10" include the TFTs that constitute the shift register of the gate driver 3, and the TFTs interposed between the signal line Sig(x) and the wiring Ccds(x) in the output holding unit 11. Therefore, characteristic shifts may occur in these TFTs as well as in TFT 23. Accordingly, in Embodiment 1, as shown in Figure 2, wiring for transmitting the lower gate potential VGL2 is connected not only to the photodetector 2 but also to the gate driver 3 and the output holding unit 11. These wires, similar to the TFT 23 of the photodetector 2, are for supplying the lower gate potential VGL2 to the lower gates of the TFTs of the gate driver 3 and the TFTs of the output holding unit 11. In other words, just as the potential applied to the lower gate 241 of the TFT 23 corresponds to the value set for the register 8, the potential applied to the lower gates of the TFTs of the gate driver 3 and the TFTs of the output holding unit 11 also corresponds to the value set for the register 8.

[0090] Note that, not limited to TFT 23, oxide semiconductor TFTs, as shown in Figure 7, consist of a semiconductor composed of a semiconductor layer OS, an upper gate and a lower gate arranged opposite each other in the third direction Dz with the semiconductor in between, and a source and drain of the semiconductor. The upper gate of the oxide semiconductor TFT is composed of an electrode layer GL2. The lower gate of the oxide semiconductor TFT is composed of an electrode layer GL1. The source and drain of the oxide semiconductor TFT are composed of an electrode layer SL. The connection between the semiconductor and the source and the connection between the semiconductor and the drain of the oxide semiconductor TFT is via a contact hole that penetrates the insulating layer PAS in the third direction Dz, similar to the contact hole 291.

[0091] Thus, the detection device according to this disclosure (for example, detection device 1) comprises a photodetection unit (for example, photodetection unit 2) in which a plurality of photodiodes (photosensors LS) are arranged two-dimensionally, and a scintillator (scintillator 15) provided on the photodetection surface side of the photodetection unit. The thin-film transistor provided in the photodetection unit has an upper gate (for example, an upper gate 231 composed of an electrode layer GL2) and a lower gate (for example, a lower gate 241 composed of an electrode layer GL2). The upper gate and the lower gate face each other across the oxide semiconductor of the thin-film transistor (for example, an oxide semiconductor 232 composed of a semiconductor layer OS). The upper gate and the lower gate are each given separate potentials. The lower gate is provided so that it can be set to "the lowest potential of the upper gate or a potential lower than the lowest potential" (for example, the lower gate potential VGL2).

[0092] As described above, according to Embodiment 1, the potential applied to the lower gate of the oxide semiconductor TFT can be set to "the lowest potential of the upper gate or a potential lower than the lowest potential" (for example, the lower gate potential VGL2). Therefore, even if the characteristic shift described above occurs, by setting the potential of the lower gate to a potential lower than the lowest potential of the upper gate, the response characteristics of the oxide semiconductor TFT after the characteristic shift can be made substantially the same as the response characteristics of the oxide semiconductor TFT before the characteristic shift. Therefore, even after a change in the response characteristics of the oxide semiconductor TFT, the detection device 1 can be operated in the same manner as before the change in response characteristics.

[0093] Furthermore, the upper gate (e.g., upper gate 231) of the thin-film transistor (e.g., TFT 23) is connected to a scan line (e.g., scan line Rd(y)) to which a drive signal (e.g., drive signal Vgate) is applied. The lower gate (e.g., lower gate 241) of the thin-film transistor is connected to a potential line 24 to which the lowest potential of the upper gate or a potential lower than the lowest potential is applied. One of the source or drain of the thin-film transistor is connected to the cathode of a photodiode (e.g., light sensor LS), and the other is connected to a signal line (e.g., signal line Sig(x)) to which a signal corresponding to the intensity of light detected by the photodiode is output. As a result, even if a change in the response characteristics occurs in the oxide semiconductor TFT provided in the photodetector (e.g., photodetector 2) of the passive photosensor (PPS), the detection device 1 can be operated in the same manner as before the change in response characteristics.

[0094] (Embodiment 2) Hereinafter, Embodiment 2, which differs in some configurations from Embodiment 1, will be described with reference to Figures 11 to 14. In the description of Embodiment 2, the same reference numerals will be used for components similar to those in Embodiment 1, and their descriptions may be omitted.

[0095] Figure 11 shows the signals input to the photodetector 2A, gate driver 3A, and multiplexer 4, the signals output from the photodetector 2A, gate driver 3A, and multiplexer 4, and the connections of the wiring that transmits these signals in Embodiment 2. As shown in Figure 11, in Embodiment 2, the gate driver 3 of Embodiment 1 is replaced by gate driver 3A. The gate driver 3A has a first circuit 301 and a second circuit 302. The first circuit 301 has the same configuration as the gate driver 3 in Embodiment 1. Note that in Figure 11 and Figure 15 described later, the scan line Rd is shown as a single line, but the scan line Rd in Embodiment 2 also includes V wires, such as scan lines Rd1, Rd2, ..., RdV, similar to Embodiment 1. Multiple optical sensors LS (see Figure 3) provided in the photodetector 2A of Embodiment 2 are connected to the first circuit 301 via scan lines Rd, similar to Embodiment 1.

[0096] The second circuit 302 is a shift register circuit that outputs a reset signal RST for resetting the capacitance 22 of the optical sensor LS of Embodiment 2. The multiple optical sensors LS (see Figure 12) provided in the optical detection unit 2A of Embodiment 2 are connected to the second circuit 302 via reset lines Rs, as shown in Figure 11. The reset lines Rs include V wires, such as reset lines Rs1, Rs2, ..., RsV.

[0097] In Embodiment 1, the strength of the output of the optical sensor LS is directly reflected in the output of output OP1. In contrast, in Embodiment 2, the strength of the output of the optical sensor LS is reflected in the output of output OP1 through TFT 603, with the potential reduced by the gate-source voltage (Vth) of TFT 602. At this time, current is supplied to the output from the output power supply potential PVDD. Also in Embodiment 2, first, a signal OP1 corresponding to the strength of the output of the optical sensor LS is applied to the signal line Sig(x), and then a reset signal RST is applied to TFT 601, resetting the optical sensor LS and the signal line Sig(x) to the reset potential VREF. As a result, an output fluctuation occurs in the signal line Sig(x) from signal OP1 to the reset potential VREF-Vth. In Embodiment 2, the intensity of light detected by the optical sensor LS is determined based on the degree of output fluctuation.

[0098] Figure 12 is a diagram showing the circuit configuration of the photodetector LS provided in the photodetector 2A. As shown in Figure 11, in Embodiment 2, the photodetector 2 of Embodiment 1 is replaced by the photodetector 2A. The photodetector LS provided in the photodetector 2A has a photodiode 21 and a capacitor 22, similar to the photodetector LS of Embodiment 1. The anode of the photodiode 21 in Embodiment 2 is connected to the wiring to which the potential PVSS2 is supplied, similar to Embodiment 1. On the other hand, the cathode of the photodiode 21 in Embodiment 2 is connected to either the source or drain of the TFT 601 and to the upper gate 236 of the TFT 602. The capacitor 22 in Embodiment 2 is electrically in parallel with the photodiode 21, similar to Embodiment 1. Therefore, when shown in the circuit diagram, the capacitor 22 can be considered to be connected to the wiring, either the source or drain of the TFT 601 and the upper gate 236 of the TFT 602.

[0099] TFTs 601 and 602 are oxide semiconductor TFTs. The source or drain of TFT 601 is connected to wiring 25 to which a reset potential VREF is applied. The upper gate 237 of TFT 601 is connected to reset line Rs(y). Reset line Rs(y) is one of the reset lines Rs1, Rs2, ..., RsV. When a reset signal RST is applied to the upper gate 237 of TFT 601 from the second circuit 302, the reset potential VREF is applied to capacitor 22 and capacitor 22 is reset.

[0100] The drain of TFT 602 is connected to wiring 26 to which the output power supply potential PVDD is supplied. The source of TFT 602 is connected to either the source or the drain of TFT 23. In Embodiment 2, the source potential of TFT 602 changes according to the charge stored in capacitor 22. That is, in Embodiment 2, TFT 602 operates as a source follower transistor. Here, in Embodiment 1, a current corresponding to the charge stored in capacitor 22 flows to either the source or the drain of TFT 23. On the other hand, in Embodiment 2, the charge stored in capacitor 22 does not move to the signal line sig(x), and a potential corresponding to the charge stored in capacitor 22 is supplied to the signal line sig(x). That is, a potential lower than the gate-source voltage (Vth) of TFT 23 is supplied to the signal line sig(x).

[0101] TFT601 and TFT602 are oxide semiconductor TFTs, similar to TFT23. The lower gates 242 of TFT601 and 243 of TFT602 are connected to the potential line 24, similar to the lower gate 241 of TFT23, and the lower gate potential VGL2 is applied.

[0102] In Embodiment 2, as shown in Figure 11, the output holding unit 11 of Embodiment 1 is replaced by the output holding unit 11A. In addition to the wiring connected to the output holding unit 11, the output holding unit 11A has additional wiring to individually supply the signals IREF1, CDS_VREF, HOLD, xHOLD, and ASWBIAS, respectively, as wiring for inputting control signals. The output holding unit 11A has a register that holds the signal OP1, and its general function is the same as that of the output holding unit 11 in that it holds the signal OP1 transmitted from the photodetector 2 via the signal line Sig and supplies it to the input line Ccds.

[0103] Figures 13 and 14 are plan views of the laminated structure included in the circuit configuration shown in Figure 12. The reset line Rs(y) shown in Figure 13 is composed of the electrode layer GL2, similar to the scan line Rd(y). The upper gate 236 of the TFT 602 is also composed of the electrode layer GL2. In the configuration shown in Figure 13, the connection portion 235, which was described with reference to Figures 5 and 7, is replaced by the connection portion 2351. The connection portion 2351 is the same as the connection portion 235, except that the connection targets are either the source or drain of the TFT 601 and the upper gate 236 of the TFT 602. The connection portion 2351 and the upper gate 236 are connected via a contact hole 2901. The contact hole 2901 is a contact hole that penetrates the insulating layer PAS in the third direction Dz.

[0104] Furthermore, wiring 25 and wiring 26 are composed of electrode layer SL, similar to the signal line Sig(x). Also, lower gates 242 and 243 are composed of electrode layer GL1, similar to lower gate 241. In addition, the connection part 2401, which connects wiring 25 to the other source or drain of TFT 601 across wiring 26, is composed of electrode layer GL1. The connection part 2401 is connected to the other source or drain of TFT 601 and wiring 25 via contact hole 2920. Contact hole 2920 is a contact hole provided to connect electrode layer GL1 and electrode layer SL, similar to contact hole 292. Also, lower gate 242 is connected to potential line 24 via contact hole 2920. Furthermore, in both TFT 601 and TFT 602, the semiconductor connecting the source and drain is composed of a semiconductor layer OS, similar to the oxide semiconductor 232 of TFT 23, and is connected to the respective source and drain via contact holes similar to the contact hole 291.

[0105] The reset line Rs(y) is located on the other end Dy1 side of the connection part 2351 and is a wiring that runs along the first direction Dx. In Embodiment 2, the width of the reset line Rs(y) in the second direction Dy is D21, except for the area that overlaps with the signal line Sig(x) in a plan view and its vicinity. Of the reset line Rs(y), the width of the second direction Dy in the area that overlaps with the signal line Sig(x) in a plan view and its vicinity is D22. Width D22 is smaller than width D21. The upper gate 237 of the TFT 601 extends from the reset line Rs(y) along the second direction Dy. The signal line Sig(x), connection part 2351, wiring 26, wiring 25, and potential line 24 are arranged in that order from one end Dx1 to the other end Dx2. The TFT 601 is located between the connection part 2351 and the wiring 26.

[0106] Wirings 25 and 26 are wires that align with the second direction Dy. The width of wiring 25 in the first direction Dx is width D23. The width of wiring 25 in the first direction Dx is width D24. Widths D23 and D24 are greater than width D21. The connection part 261 that connects wiring 26 to the drain of TFT 602 aligns with the first direction Dx. The width of the connection part 261 in the second direction Dy is width D25. Width D25 is less than width D24.

[0107] TFT 602 is positioned on the other end Dy2 side of the connection portion 2351 and on the other end Dx2 side of TFT 23. In Embodiment 2, TFT 602 has a configuration in which two semiconductor layers are arranged side by side in the second direction Dy, and is substantially composed of oxide semiconductor TFTs equivalent to two TFTs 23. The upper gate 236 is provided along the second direction Dy so as to cover the semiconductors of the two oxide semiconductor TFTs. The source of TFT 602 on the other end Dy2 side overlaps with either the source or drain of TFT 23 in a planar view. That is, the source of TFT 602 on the other end Dy2 side and either the source or drain of TFT 23 are shared.

[0108] The lower gate 241 of Embodiment 2 differs from the lower gate 241 of Embodiment 1 in that, near the point where it overlaps with the other end Dy2 side of the upper gate 231 in a plan view, a portion along the second direction Dy and a portion along the first direction Dx are connected in a continuous manner. The lower gate 243 is arranged so as to overlap with the upper gate 236 and the semiconductor layer of the TFT 602 in a plan view. The lower gate 243 is aligned with the second direction Dy. The lower gate 243 is continuous with a portion of the lower gate 241 along the first direction Dx on the other end Dy2 side.

[0109] In Embodiment 2, the width of the lower gate 243 that overlaps with the upper gate 236 in a plan view is greater than the width of the upper gate 236 in a first direction Dx. Specifically, the lower gate 243 has a width that is greater than that of the upper gate 236 by a width D201 on one end Dx1 side and the other end Dx2 side in a plan view.

[0110] The lower gate 242 is positioned so as to overlap with a portion of the upper gate 237 and the semiconductor of the TFT 601 in a planar view. The portion of the lower gate 242 that overlaps with the upper gate 237 is aligned with the second direction Dy. The other portion of the lower gate 242 that is connected to the potential line 24 via the contact hole 2920 is aligned with the first direction Dx. Near the position where the lower gate 242 overlaps with the other end Dy2 side of the upper gate 236 in a planar view, the portion aligned with the second direction Dy and the portion aligned with the first direction Dx are connected in a continuous manner.

[0111] In Embodiment 2, the width of a portion of the lower gate 242 that overlaps with the upper gate 237 in a plan view is greater than the width of the upper gate 237 in a first direction Dx. Specifically, the lower gate 242 has a width that is D202 greater than the upper gate 237 on one end Dx1 side and the other end Dx2 side in a plan view.

[0112] Width D201 is, for example, 1.4 μm. Width D202 is, for example, 2 μm. Widths D21 and D25 are, for example, 4 μm. Width D22 is, for example, 3 μm. Widths D23 and D24 are, for example, 9 μm.

[0113] Furthermore, in Embodiment 2, the width of the first direction Dx of the signal line Sig(x) and potential line 24 is D4, not only in the range and vicinity of the overlap with the scan line Rd(y) in a planar view, but also in the range and vicinity of the overlap with the reset line Rs(y).

[0114] It should be noted that, not limited to TFT 23, the TFTs mounted on the substrate 10 in Embodiment 2 are oxide semiconductor TFTs similar to TFT 23 and have a TFT portion 500 (see Figure 7). Therefore, characteristic shifts may occur in these TFTs as well as in TFT 23. Examples of "TFTs mounted on the substrate 10 in Embodiment 2" include TFT 601, TFT 602, TFTs constituting the shift register of the gate driver 3A, and TFTs interposed between the signal line Sig(x) and the wiring Ccds(x) in the output holding unit 11A. In Embodiment 2, as shown in Figure 2, wiring for transmitting the lower gate potential VGL2 is connected not only to the photodetector 2A but also to the gate driver 3A and the output holding unit 11A. These wires, like the TFTs 23, 601, and 602 of the photodetector unit 2A, are for supplying the lower gate potential VGL2 to the lower gates of the TFTs of the gate driver 3 and the TFTs of the output holding unit 11. In other words, the potential supplied to the lower gates of the TFTs mounted on the substrate 10 in Embodiment 2 also corresponds to the value set for the register 8.

[0115] TFT 601 is provided with a width of approximately 3 μm in the first direction Dx and approximately 3 μm in the second direction Dy. TFT 602 has a configuration in which two oxide semiconductor TFTs are aligned in the second direction Dy, and each is provided with a width of approximately 15 μm in the first direction Dx and approximately 3 μm in the second direction Dy. In addition, the distance between the two oxide semiconductor TFTs in TFT 602 in the second direction Dy is approximately 4 μm.

[0116] In Embodiment 2, TFTs 601 and 602 are oxide semiconductor TFTs similar to TFT 23, and have a TFT portion 500 (see Figure 7). Therefore, characteristic shifts may occur in these TFTs as well as in TFT 23. Accordingly, in Embodiment 2, as explained with reference to Figures 12 and 13, a lower gate potential VGL2 is also applied to the lower gates of TFTs 601 and 602. This makes it possible to make the response characteristics of the oxide semiconductor TFTs after characteristic shifts substantially the same as the response characteristics of the oxide semiconductor TFTs before characteristic shifts in Embodiment 2, as in Embodiment 1. Except for the matters specifically noted above, Embodiment 2 is the same as Embodiment 1.

[0117] As described above, according to Embodiment 2, the photodetector (for example, the photodetector 2A) is provided with a first transistor (for example, TFT 601), a second transistor (for example, TFT 602), and a third transistor (for example, TFT 23), all of which are oxide semiconductor TFTs. The upper gate of the first transistor is connected to a wiring to which a reset signal is supplied (for example, the reset line Rs(y)). One of the source or drain of the first transistor is connected to a wiring to which the reset potential (for example, the reset potential VREF) of the photodiode (for example, the light sensor LS) is supplied, and the other is connected to the cathode of the photodiode. The upper gate of the second transistor is connected to the cathode of the photodiode. The drain of the second transistor is connected to a wiring to which a reference potential (for example, the output power supply potential PVDD) is supplied, and the source is connected to one of the source or drain of the third transistor. The upper gate of the third transistor is connected to a scan line (for example, the scan line Rd(x)) to which a drive signal (for example, the drive signal Vgate) is supplied. The source or drain of the third transistor is connected to a signal line (e.g., signal line Sig(x)) that outputs a signal corresponding to the intensity of light detected by the photodiode. The lower gates of the first, second, and third transistors are connected to a potential line 24 that is supplied with "the lowest potential of the upper gate or a potential lower than the lowest potential" (e.g., lower gate potential VGL2). This allows the detection device to operate while suppressing the effects of changes in response characteristics, even if a change occurs in the response characteristics of the oxide semiconductor TFT provided in the photodetector, which functions as an active photosensor (APS).

[0118] (Embodiment 3) Hereinafter, Embodiment 3, which differs in some configuration from Embodiment 2, will be described with reference to Figures 15 to 18. In the description of Embodiment 3, the same reference numerals will be used for components similar to those in Embodiment 2, and their descriptions may be omitted.

[0119] Figure 15 shows the signals input to the photodetector 2B, gate driver 3B, and multiplexer 4, the signals output from the photodetector 2B, gate driver 3B, and multiplexer 4, and the connections of the wiring that transmits these signals in Embodiment 3. In Embodiment 3, the gate driver 3A of Embodiment 2 is replaced by the gate driver 3B. The gate driver 3B has a first circuit 301, a second circuit 302, and a third circuit 303. The first circuit 301 has the same configuration as the first circuit 301 in Embodiment 2. The second circuit 302 has the same configuration as the second circuit 302 in Embodiment 2. In Figure 15, the reset line Rs is shown as a single line, but the reset line Rs in Embodiment 3 also includes V wires, such as reset lines Rs1, Rs2, ..., RsV, similar to Embodiment 2. The multiple light sensors LS (see Figure 16) provided in the light detection unit 2B of Embodiment 3 are connected to the second circuit 302 via a reset line Rs, similar to Embodiment 2.

[0120] The third circuit 303 is a shift register circuit that outputs an output command signal PD for controlling the on / off state of the TFT 603 (see Figure 16) connected to the optical sensor LS of Embodiment 3. The multiple optical sensors LS provided in the optical detection unit 2B of Embodiment 3 are connected to the third circuit 303 via the output command signal line Rp, as shown in Figure 15. The output command signal line Rp includes V wires, such as output command signal lines Rp1, Rp2, ..., RpV.

[0121] In Embodiment 3, the strength of the output of the optical sensor LS is reflected in the source output of the TFT 602, which is used as a source follower transistor. The drain of the TFT 602 is connected to the output power supply potential PVDD. These points are the same as in Embodiment 2. However, the order in which the signals that cause output fluctuations are applied to the signal line Sig(x) differs between Embodiment 3 and Embodiment 2. Specifically, in Embodiment 3, first, the reset signal RST is applied to the TFT 601, resetting the optical sensor LS and the signal line Sig(x) to the reset potential VREF. Then, the output command signal PD is applied to the TFT 603, applying the signal OP1 corresponding to the strength of the output of the optical sensor LS to the signal line Sig(x). This causes an output fluctuation from the reset potential VREF to the signal OP1 in the signal line Sig(x). In Embodiment 3, the intensity of the light detected by the optical sensor LS is determined based on the degree of output fluctuation.

[0122] Figure 16 is a diagram showing the circuit configuration of the photodetector LS provided in the photodetector 2B. As shown in Figure 15, in Embodiment 3, the photodetector 2A of Embodiment 2 is replaced by the photodetector 2B. The photodetector LS provided in the photodetector 2B has a photodiode 21 and a capacitor 22, similar to the photodetector LS of Embodiments 1 and 2. The anode of the photodiode 21 in Embodiment 3 is connected to the wiring to which the potential PVSS2 is supplied, similar to Embodiments 1 and 2. On the other hand, the cathode of the photodiode 21 in Embodiment 3 is connected to either the source or the drain of the TFT 603. The capacitor 22 in Embodiment 3 is electrically in parallel with the photodiode 21, similar to Embodiments 1 and 2. Therefore, when shown in the circuit diagram, the capacitor 22 can be considered to be connected to the wiring and either the source or the drain of the TFT 603.

[0123] TFT 603, like TFT 23, is an oxide semiconductor TFT. The lower gate 244 of TFT 603, like the lower gate 241 of TFT 23, is connected to the potential line 24, and the lower gate potential VGL2 is applied. The other end of the source or drain of TFT 603 is connected to one end of the source or drain of TFT 601, the upper gate 236 of TFT 602, and the conductor portion 802. Based on the "connection relationship between the optical sensor LS and TFT 601 and TFT 602" in Embodiment 2, TFT 603 is provided so as to be interposed between the optical sensor LS and TFT 601 and TFT 602 in Embodiment 2.

[0124] Furthermore, as shown in Figure 16, the photodetector 2B of Embodiment 3 is provided with a capacitor 800. The capacitor 800 functions as a charge-storing capacitor. As shown in Figure 16, the capacitor 800 is connected to the wiring via a conductor portion 801. The capacitor 800 is also connected via a conductor portion 802 to the other source or drain of the TFT 603, one source or drain of the TFT 601, and the upper gate 236 of the TFT 602. Therefore, when the TFT 603 is turned on, the charge from the current flowing from the source or drain of the photosensor LS is stored in the capacitor 800 via the conductor portion 802. A voltage corresponding to the charge stored in the capacitor 800 is applied to the upper gate 236 of the TFT 602. Thus, Embodiment 3 is similar to Embodiment 2 in that the potential corresponding to the charge stored in the capacitance 22 is used to determine the source potential of the TFT 602, but it differs from Embodiment 2 in that a charge-storing capacitor 800 is provided. Furthermore, Embodiment 3 differs from Embodiment 2 in that it includes the TFT 603.

[0125] Figures 17 and 18 are plan views of the laminated structure included in the circuit configuration shown in Figure 16. The capacitor 800 is configured to store charge by stacking a conductor portion 801 and a conductor portion 802 facing each other in the third direction Dz. The conductor portion 801 is composed of an electrode layer GL2. The conductor portion 802 is composed of an electrode layer SL. The capacitor 800 is positioned on the other end Dy1 side of the TFT 23. A connection portion 8010 extends from the conductor portion 801 along the first direction Dx to the other end Dx2 side and is connected to the wiring 26 via a contact hole 2909. The contact hole 2909 is a contact hole that penetrates the insulating layer PAS in the third direction Dz. The connection portion 8010 is composed of an electrode layer GL2, similar to the conductor portion 801. From the conductor portion 802, a connection portion 8020 extends toward the other end Dy2 along the second direction Dy and is connected to the upper gate 236 of the TFT 602 via the contact hole 2905.

[0126] In Embodiment 3, the upper gate 236 of the TFT 602 is divided into a first gate 2361 and a second gate 2362, forming a so-called double gate structure. The first gate 2361 is positioned relatively on the other end Dy1 side, and the second gate 2362 is positioned relatively on the other end Dy2 side. The first gate 2361 is aligned in the first direction Dx. The second gate 2362 has a portion that overlaps with the semiconductor of the TFT 602 and is aligned in the first direction Dx, and another portion that is aligned in the second direction Dy and is continuous with the first portion at one end on the other end Dy2 side. One end of the first gate 2361 on the Dx1 side and the other portion of the second gate 2362 on the other end Dy1 side are continuous. The contact hole 2905 is provided at a position that overlaps with the one end of the first gate 2361 on the Dx1 side and the other portion of the second gate 2362 on the other end Dy1 side. The contact hole 2905 is connected via a contact hole that penetrates the insulating layer PAS in the third direction Dz.

[0127] Furthermore, in Embodiment 3, a connecting portion 2391 extending from the semiconductor layer of the TFT 602 along the first direction Dx toward the other end Dx2 is connected to the wiring 26 via a contact hole 2960. The contact hole 2960, like the contact hole 291, is a contact hole provided to connect the semiconductor layer OS and the electrode layer SL.

[0128] Furthermore, in Embodiment 3, the connection portion 2352, where the contact hole 293 is provided, is located on the other end Dx2 side of the capacitor 800. A TFT 603 is placed between the capacitor 800 and the connection portion 2352. One of the source or drain of the TFT 603 is connected to the optical sensor LS by being connected to the connection portion 2352. The other of the source or drain of the TFT 603 is continuous with the conductor portion 802. In the area where the conductor portion 802 is located in a plan view, there is no conductor portion 801 in a portion that overlaps with the contact hole in the plan view for the connection of the TFT 603 to the semiconductor. Also, as shown in Figure 17, the conductor portion 802 is continuous with one of the source or drain of the TFT 601.

[0129] The lower gate 244 of the TFT 603 is continuous with another portion of the lower gate 242 along the first direction Dx. The upper gate 234 of the TFT 603 is connected to the output command signal line Rp(y). The output command signal line Rp(y) is one of the output command signal lines Rp1, Rp2, ..., RpV. The output command signal line Rp(y) is composed of electrode layer GL1. On the other hand, the upper gate 234 is composed of electrode layer GL2. The connection between the output command signal line Rp(y) and the upper gate 234 is made via a connection structure 703. The connection structure 703 includes a connection portion 2943, a contact hole 2953, and a contact hole 2904. The connection portion 2943 is composed of electrode layer SL. The contact hole 2953 is the contact hole through which the connection between the connection portion 2943 and the output command signal line Rp(y) is made. The contact hole 2904 is a contact hole through which the connection portion 2943 and the upper gate 234 are connected.

[0130] The output command signal line Rp(y) is located between capacitor 800 and TFT 602 in the second direction Dy. The output command signal line Rp(y) is aligned with the first direction Dx. The width of the output command signal line Rpy in the second direction Dy is D31, except for the area overlapping with signal line Sig(x) in a planar view and its vicinity. The width of the output command signal line Rp(y) in the area overlapping with signal line Sig(x) in a planar view and its vicinity in the second direction Dy is D32. Width D32 is smaller than width D31.

[0131] Furthermore, the width of the lower gate 244, which overlaps with the upper gate 234 in a plan view, in the first direction Dx is greater than the width of the upper gate 234 in the first direction Dx. Specifically, the relationship between the upper gate 234 and the lower gate 244 with respect to the width of the first direction Dx is the same as the relationship between the upper gate 237 and the lower gate 242 with respect to the width of the first direction Dx. That is, the lower gate 244 has a width that is greater than the upper gate 234 by a width D202 (see Figure 13) on one end Dx1 side and the other end Dx2 side in a plan view.

[0132] Furthermore, the reset wire Rs(y) in Embodiment 3 is composed of the electrode layer GL1. Therefore, in Embodiment 3, a connection structure 701 is provided for connecting the reset wire Rs(y) and the upper gate 237. The connection structure 701 includes a connection portion 2946, a contact hole 2951, and a contact hole 2902. The connection portion 2946 is composed of the electrode layer SL. The contact hole 2951 is a contact hole through which the connection portion 2946 and the reset wire Rs(y) are connected. The contact hole 2902 is a contact hole through which the connection portion 2946 and the upper gate 237 are connected.

[0133] Furthermore, the scan line Rd(y) in Embodiment 3 is composed of the electrode layer GL1. For this reason, Embodiment 3 is provided with a connection structure 702 for connecting the scan line Rd(y) and the upper gate 231. The connection structure 702 includes a connection portion 2947, a contact hole 2952, and a contact hole 2903. The connection portion 2947 is composed of the electrode layer SL. The contact hole 2952 is a contact hole through which the connection portion 2947 and the scan line Rd(y) are connected. The contact hole 2903 is a contact hole through which the connection portion 2947 and the upper gate 231 are connected.

[0134] Furthermore, in this embodiment, due to the provision of the capacitor 800, the position of the contact hole 293 is shifted towards the other end Dx2 side compared to embodiments 1 and 2, as shown in Figures 17 and 18. Consequently, the shape of the photodetector 280 and electrode layer UIO in a planar view is slightly different in embodiment 3 compared to embodiments 1 and 2. Specifically, in embodiment 3, the photodetector 280 and electrode layer UIO extend to the area where they were not provided diagonally opposite the contact hole 294 in embodiments 1 and 2. Also, in embodiment 3, the arrangement of the drainage holes 271 is the same as in embodiments 1 and 2. However, because the area in which the photodetector 280 and electrode layer UIO are provided is wider than in embodiments 1 and 2, the drainage holes 271 are located within the area in which the photodetector 280 and electrode layer UIO are provided.

[0135] In Embodiment 2, the width of the first direction Dx of the signal line Sig(x) and potential line 24 is D4, not only in the range and vicinity of the range that overlaps with either the scan line Rd(y) or the reset line Rs(y) in a planar view, but also in the range and vicinity of the range that overlaps with the output command signal line Rp(y).

[0136] The width D31 is, for example, 4 μm. The width D32 is, for example, 3 μm. The TFT603 is provided such that it is approximately 3 μm in the first direction Dx and approximately 3 μm in the second direction Dy.

[0137] In Embodiment 3, TFT 603 is an oxide semiconductor TFT similar to TFT 23 and has a TFT portion 500 (see Figure 7). Therefore, characteristic shifts may occur in TFT 603 as well as in TFT 23. Accordingly, in Embodiment 3, as explained with reference to Figures 16 and 17, a lower gate potential VGL2 is also applied to the lower gate 244 of TFT 603. This makes it possible to make the response characteristics of the oxide semiconductor TFT after the characteristic shift substantially the same as the response characteristics of the oxide semiconductor TFT before the characteristic shift in Embodiment 3, as in Embodiments 1 and 2. Except for the matters specifically noted above, Embodiment 3 is the same as Embodiment 2.

[0138] As described above, according to Embodiment 3, the photodetector (for example, the photodetector 2B) is provided with a first transistor (for example, TFT 601), a second transistor (for example, TFT 602), a third transistor (for example, TFT 23), and a fourth transistor (for example, TFT 603), all of which are oxide semiconductor TFTs. The upper gate of the first transistor is connected to a wiring to which a reset signal is supplied (for example, the reset line Rs(y)). One of the source or drain of the first transistor is connected to a wiring to which the reset potential (for example, the reset potential VREF) of the photodiode (for example, the light sensor LS) is supplied, and the other is connected to the upper gate of the second transistor. The drain of the second transistor is connected to a wiring to which a reference potential (output power supply potential PVDD) is supplied, and its source is connected to one of the source or drain of the third transistor. The upper gate of the third transistor is connected to a first scan line (for example, the scan line Rd(y)) to which a first drive signal (for example, the drive signal Vgate) is supplied. The source or drain of the third transistor is connected to a signal line (e.g., signal line Sig(x)) to which a signal is output. The upper gate of the fourth transistor is connected to a second scan line (e.g., output command signal line Rp(y)) to which a second drive signal (e.g., output command signal PD) is applied. One of the source or drain of the fourth transistor is connected to the upper gate of the second transistor, and the other is connected to the cathode of the photodiode. The lower gates of the first, second, third, and fourth transistors are connected to a potential line 24 to which a potential lower than the lowest potential of the upper gate (e.g., lower gate potential VGL2) is applied. This allows the detection device to operate while suppressing the effects of changes in response characteristics, even if a change occurs in the response characteristics of the oxide semiconductor TFT provided in the photodetector unit that functions as an active photosensor (APS).

[0139] The numerical values ​​exemplified above as the widths for the first direction Dx and the second direction Dy are merely examples and are not limited to these values; they can be changed as appropriate.

[0140] Furthermore, any other effects and advantages brought about by the embodiments described herein that are obvious from this specification or that can be appropriately conceived by those skilled in the art are naturally provided by this disclosure.

[0141] 1 Detection device 7 Setting circuit 8 Registers 23, 601, 602, 603 TFTs 231, 234, 236, 237 Upper gate 232 Oxide semiconductor 241, 242, 243, 244 Lower gate GL1 First electrode layer GL2 Second electrode layer OS Oxide semiconductor layer SL Third electrode layer

Claims

1. A detection device comprising: a photodetector unit in which a plurality of photodiodes are arranged two-dimensionally; and a scintillator provided on the photodetector side of the photodetector unit, wherein a thin-film transistor provided in the photodetector unit has an upper gate and a lower gate, the upper gate and the lower gate face each other with an oxide semiconductor of the thin-film transistor in between, and the lower gate is provided so as to be able to set a potential lower than or equal to the lowest potential of the upper gate.

2. The detection device according to claim 1, wherein the upper gate is connected to a scan line to which a drive signal is supplied, the lower gate is connected to a potential line to which the lowest potential of the upper gate or a potential lower than the lowest potential is supplied, and one of the source or drain of the thin-film transistor is connected to the cathode of the photodiode, and the other is connected to a signal line to which a signal corresponding to the intensity of light detected by the photodiode is output.

3. The light detection unit is provided with a first transistor, a second transistor, and a third transistor, each of the first, second, and third transistors being a thin-film transistor, the upper gate of the first transistor is connected to a wiring to which a reset signal is supplied, one of the source or drain of the first transistor is connected to a wiring to which a reset potential of the photodiode is supplied, and the other is connected to the cathode of the photodiode, the upper gate of the second transistor is connected to the cathode of the photodiode, the drain of the second transistor is connected to a wiring to which a reference potential of a signal corresponding to the intensity of light detected by the photodiode is supplied, and the source is connected to one of the source or drain of the third transistor, the upper gate of the third transistor is connected to a scanning line to which a drive signal is supplied, the other of the source or drain of the third transistor is connected to a signal line to which a signal corresponding to the intensity of light detected by the photodiode is output, and the lower gates of the first, second, and third transistors are connected to a potential line to which the lowest potential of the upper gate or a potential lower than the lowest potential is supplied, the detection device according to claim 1.

4. The light detection unit is provided with a first transistor, a second transistor, a third transistor, and a fourth transistor, each of which is a thin-film transistor, the upper gate of the first transistor is connected to a wiring to which a reset signal is supplied, one drain of the first transistor is connected to a wiring to which the reset potential of the photodiode is supplied, and the other drain is connected to the upper gate of the second transistor, the drain of the second transistor is connected to a wiring to which a reference potential of a signal corresponding to the intensity of light detected by the photodiode is supplied, and its source is connected to either the source or the drain of the third transistor, the upper gate of the third transistor is connected to a first scan line to which a first drive signal is supplied, the other drain of the third transistor is connected to a signal line to which the signal is output, the upper gate of the fourth transistor is connected to a second scan line to which a second drive signal is supplied, one source or the drain of the fourth transistor is connected to the upper gate of the second transistor, and the other drain is connected to the cathode of the photodiode, The detection device according to claim 1, wherein the lower gates of the first transistor, the second transistor, the third transistor, and the fourth transistor are connected to a potential line to which the lowest potential of the upper gate or a potential lower than the lowest potential is supplied.

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