Detection device

Abstract

A detection device according to the present invention comprises: a light detection unit provided with a photodiode; and a scintillator provided on a light detection surface side of the light detection unit. A thin film transistor provided in the light detection unit has an upper gate and a lower gate facing each other with an oxide semiconductor interposed therebetween, and is composed of a laminate including, in order from a structure far from the scintillator to a structure close to the scintillator: a first conductive film constituting the lower gate; a first inorganic film; a semiconductor layer constituting the oxide semiconductor; a second inorganic film; a second conductive film constituting the upper gate; a third inorganic film; a third conductive film constituting a source and a drain connected to the oxide semiconductor; a fourth inorganic film; a first organic film; a multilayer structure constituting the photodiode; a second organic film; a fifth inorganic film; and a third organic film. The source or drain is connected to the oxide semiconductor and a first electrode of the photodiode, the fourth inorganic film covers the first electrode and a portion of a second electrode, and a translucent fourth conductive film to which a non-translucent electrode is connected is formed in an opening where the second electrode is not covered with the fourth inorganic film.

Description

Detection device

[0001] The present disclosure relates to a detection device.

[0002] A detection device that detects light and uses a scintillator to obtain visible light from X-rays is known (for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2021-102716

[0004] There is a need to reduce the power consumption of the detection device.

[0005] The present disclosure is a detection device using a scintillator, and an object thereof is to provide a detection device with reduced power consumption.

[0006] The detection device according to one aspect of the present disclosure is a detection device including a light detection unit provided with a photodiode and a scintillator provided on the light detection surface side of the light detection unit. The thin film transistor provided in the light detection unit has an upper gate and a lower gate, and the upper gate and the lower gate face each other with the oxide semiconductor of the thin film transistor interposed therebetween. In order from a configuration relatively far from the scintillator to a configuration relatively close to the scintillator, a first conductive film constituting the lower gate, a first inorganic film, a semiconductor layer constituting the oxide semiconductor, a second inorganic film, a second conductive film constituting the upper gate, a third inorganic film, a third conductive film constituting a source and a drain connected to the oxide semiconductor, a fourth inorganic film, a first organic film, a multilayer structure constituting a photodiode, a second organic film, a fifth inorganic film, and a third organic film are laminated in this order. One of the source or the drain is connected to the oxide semiconductor through a first through hole penetrating the second inorganic film and the third inorganic film, and is connected to a first electrode of the photodiode through a second through hole penetrating the fourth inorganic film and the first organic film. The fourth inorganic film covers a part of the first electrode and the second electrode of the photodiode, and a light-transmissive fourth conductive film is formed in an opening of the second electrode not covered by the fourth inorganic film, and a non-light-transmissive electrode is connected to the fourth conductive film.

[0007] Figure 1 is a schematic diagram showing the main configuration of the detection device. Figure 2 is a diagram showing the signals input to the photodetector, gate driver, and multiplexer, the signals output from the photodetector, gate driver, and multiplexer, and the connections of the wiring that transmits these signals. Figure 3 is a diagram showing the circuit configuration of the optical sensor provided in the photodetector. Figure 4 is a diagram showing the relationship between the multiple optical sensors provided in the photodetector, the scan lines, and the signal lines. Figure 5 is a plan view of the stacked structure included in the circuit configuration shown in Figure 3. Figure 6 is a plan view of the stacked structure included in the circuit configuration shown in Figure 3. Figure 7 is a cross-sectional view taken along the IV-V section from Figure 5 to Figure 6. Figure 8 is a schematic diagram showing a legendary aspect of an oxide semiconductor TFT from a planar viewpoint. Figure 9 is a schematic diagram showing an example of the configuration of multiple wiring sections and pads provided in the pad section. Figure 10 is a view with the focus range of Figure 9 enlarged. Figure 11 is a cross-sectional view taken along the XI-XI line in Figure 9. Figure 12 is a diagram showing the circuit configuration of the optical sensor in a modified example of Embodiment 1. Figure 13 is a diagram showing an example of the connection configuration between the lower gate and the upper gate formed in a modified example of Embodiment 1. Figure 14 is a diagram showing the connection targets of the signal input to the photodetector, gate driver, and multiplexer, the signal output from the photodetector, gate driver, and multiplexer, and the wiring that transmits these signals in Embodiment 2. Figure 15 is a diagram showing the circuit configuration of the optical sensor provided in the photodetector. Figure 16 is a plan view of the stacked structure included in the circuit configuration shown in Figure 15. Figure 17 is a plan view of the stacked structure included in the circuit configuration shown in Figure 15. Figure 18 is a diagram showing the circuit configuration of the optical sensor in a modified example of Embodiment 2. Figure 19 is a diagram showing an example of the connection configuration between the lower gate and other configurations connected to the lower gate formed in a modified example of Embodiment 2. Figure 20 is a diagram showing the connection targets of the signal input to the photodetector, gate driver, and multiplexer, the signal output from the photodetector, gate driver, and multiplexer, and the wiring that transmits these signals in Embodiment 3. Figure 21 is a diagram showing the circuit configuration of the optical sensor provided in the photodetector. Figure 22 is a plan view of the stacked structure included in the circuit configuration shown in Figure 21. Figure 23 is a plan view of the laminated structure included in the circuit configuration shown in Figure 21. Figure 24 is a cross-sectional view taken along the line XXIV-XXIV in Figure 22.Figure 25 shows the circuit configuration of the optical sensor in a modified example of Embodiment 3. Figure 26 shows an example of the connection configuration between the lower gate formed in the modified example of Embodiment 3 and other components connected to the lower gate.

[0008] The embodiments of this disclosure will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and modifications that can be easily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of this disclosure. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of parts in order to clarify the explanation, but these are merely examples and do not limit the interpretation of this disclosure. In addition, in this specification and the drawings, elements similar to those described above in previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] (Embodiment 1) Figure 1 is a schematic diagram showing the main configuration of the detection device 1. The detection device 1 comprises a photodetector 2, a gate driver 3, a multiplexer 4, a control circuit 5, and a connection unit 6.

[0010] The light detection unit 2 includes a plurality of two-dimensionally arranged light sensors LS (see Figure 3, etc.) and a scintillator provided on the side of the light entering the plurality of light sensors LS. In this embodiment, the scintillator converts X-rays into visible light. Each of the plurality of light sensors LS detects the visible light converted from X-rays by the scintillator.

[0011] The gate driver 3 is a circuit that functions as a gate driver, supplying a drive signal Vgate to a plurality of optical sensors LS provided in the optical detection unit 2. The multiplexer 4 is a multiplexer connected to the plurality of optical sensors LS provided in the optical detection unit 2. The optical detection unit 2, the gate driver 3, and the multiplexer 4 are mounted on a substrate 10. The substrate 10 is, for example, a rigid substrate, but is not limited to this, and may be of other types.

[0012] The control circuit 5 is a Read Out Integrated Circuit (ROIC) that reads the output obtained from the multiple optical sensors LS provided in the optical detection unit 2 via the multiplexer 4. Furthermore, the control circuit 5 in this embodiment has the function of operating the multiple optical sensors LS provided in the optical detection unit 2.

[0013] The connection section 6 is a flexible printed circuit board (FPC) on which wiring is provided to connect various components on the circuit board 10 with the control circuit 5. The connection section 6 is connected to the pad section 9 provided on the circuit board 10.

[0014] Figure 2 shows the signals input to the photodetector 2, gate driver 3, and multiplexer 4, the signals output from the photodetector 2, gate driver 3, and multiplexer 4, and the connections of the wiring that transmits these signals. Figure 4 shows the relationship between the multiple optical sensors LS provided in the photodetector 2, the scan lines Rd1, Rd2, ..., RdV, and the signal lines Sig1, Sig2, ..., SigH. The multiple optical sensors LS provided in the photodetector 2 are connected to the gate driver 3 via the scan line Rd, as shown in Figure 2. The scan line Rd includes V wires, such as scan lines Rd1, Rd2, ..., RdV. The value of V corresponds to the number of arrangements of the second direction Dy (see Figure 3) of the multiple optical sensors LS in the photodetector 2. To give a specific example, V in this embodiment is, for example, 210, but is not limited to this and can be changed as appropriate.

[0015] As shown in Figure 2, the multiple optical sensors LS provided in the optical detection unit 2 are connected to the multiplexer 4 via signal lines Sig. The signal lines Sig include H wires, such as signal lines Sig1, Sig2, ..., SigH. The value of H corresponds to the number of arrangements of the multiple optical sensors LS in the optical detection unit 2 in the first direction Dx (see Figure 3). For example, in this embodiment, H is 162, but is not limited to this and can be changed as appropriate.

[0016] Hereinafter, the direction along which scan lines Rd1, Rd2, ..., RdV lie will be referred to as the first direction Dx. The direction along which signal lines Sig1, Sig2, ..., SigH lie will be referred to as the second direction Dy. The first direction Dx and the second direction Dy intersect (for example, are perpendicular). The term "plan view" refers to a front view of the plane (Dx-Dy plane) that lies along the first direction Dx and the second direction Dy. When "plan view" is used, it refers to the viewpoint from which the Dx-Dy plane is viewed from the front.

[0017] The scan lines Rd1, Rd2, ..., RdV included in the scan line Rd can be said to be multiple scan lines aligned along the first direction Dx and the second direction Dy. The signal lines Sig1, Sig2, ..., SigH included in the signal line Sig can be said to be multiple signal lines aligned along the second direction Dy and the first direction Dx. The scan line Rd and the signal line Sig are insulated from each other by being formed in different layers in a laminated structure described later, and are non-conductive. The scan line Rd and the signal line Sig extend into the photodetector 2. In Embodiment 1, one optical sensor LS is placed in each of the multiple subregions separated by a grid formed by the scan line Rd and the signal line Sig within the photodetector 2. That is, the optical sensors LS are arranged two-dimensionally in the photodetector 2 along the Dx-Dy plane. Furthermore, it can be said that, of the multiple optical sensors LS, all except those along the outer edge are located within the range enclosed by two of the multiple signal lines included in the signal line Sig and two of the multiple scan lines included in the scan line Rd.

[0018] Figure 3 shows the circuit configuration of the light sensor LS provided in the light detection unit 2. The light sensor LS has a photodiode 21. The photodiode 21 is a photodiode that converts irradiated light into electric charge (electrons and holes). The light sensor LS also functions as a capacitor 22. The charge output from the photodiode 21 is stored in the capacitor 22. The anode of the photodiode 21 is connected to a wiring to which the potential PVSS2 is applied. The cathode of the photodiode 21 is connected to either the source or the drain of the TFT 23. The capacitor 22 is electrically in parallel with the photodiode 21. Therefore, when shown in the circuit diagram, the capacitor 22 can be considered to be connected to the wiring and either the source or the drain of the TFT 23.

[0019] TFT23 is a thin-film transistor (TFT) having a semiconductor layer OS formed of an oxide semiconductor. TFT23 is a switching element. TFT23 is formed of an oxide semiconductor containing, for example, indium, gallium, zinc, and oxygen. Hereinafter, when referred to as an oxide semiconductor TFT, it refers to a TFT having a semiconductor layer OS formed of an oxide semiconductor, similar to TFT23. The oxide semiconductor TFT has electrode layers GL2 and GL1 sandwiching the semiconductor layer OS, as shown in the TFT portion 500 in Figure 7. Electrode layer GL2 is the upper gate, and electrode layer GL1 is the lower gate. Electrode layer GL2 faces the semiconductor layer OS with an insulating layer GI in between. Electrode layer GL1 faces the semiconductor layer OS with an insulating layer UG in between. Oxide semiconductor TFTs have advantages such as lower power consumption compared to TFTs that use amorphous silicon or low-temperature polysilicon (LTPS: Low Temperature Polycrystalline Silicon) as semiconductor layers.

[0020] The source or drain of TFT23 is connected to the signal line Sig(x). The signal line Sig(x) is one of the signal lines Sig1, Sig2, ..., SigH.

[0021] The TFT 23 has two gates positioned opposite each other across the source-drain semiconductor layer. One of the two gates is designated as the upper gate 231, and the other as the lower gate 241. The upper gate 231 is connected to the scan line Rd(y) to which the drive signal Vgate is applied. The scan line Rd(y) is one of the scan lines Rd1, Rd2, ..., RdV. The lower gate 241 is connected to the potential line 24 to which the lower gate potential VGL2 is applied. The lower gate potential VGL2 is a predetermined potential that is below the reference potential, which will be described later.

[0022] The drive signal Vgate is either the drive potential VGH or the reference potential VGL (see Figure 2). The drive potential VGH is a potential higher than the reference potential and functions as an ON signal to operate the TFT so that current flows between its source and drain. The reference potential VGL is the reference potential and functions as an OFF signal to operate the TFT so that current does not flow between its source and drain. The reference potential is, for example, 0 volts (V), but any preset potential is acceptable, and its specific potential can be changed as appropriate.

[0023] The gate driver 3 applies an ON signal to the gate of the TFT 23 to turn it ON. When the TFT 23 is ON, electrical signals are transmitted between the source and drain. Therefore, when the TFT 23 is turned ON, the charge stored in the capacitor 22 is transmitted to the signal line Sig(x). Hereafter, when referred to as signal OP1, it refers to the electrical signal applied to the signal line Sig(x).

[0024] The gate driver 3 is a shift register circuit that performs scanning by sequentially supplying ON signals to scan lines Rd1, Rd2, ..., RdV. In Figure 2, scanning is shown as scan Vscan. The gate driver 3 supplies an OFF signal to the TFT 23 during periods when no ON signal is supplied. That is, the TFT 23 is in an OFF state with an OFF signal supplied, except during periods when an ON signal is supplied. In the OFF state of the TFT 23, no electrical signal is transmitted between the source and drain.

[0025] Furthermore, the wiring connected to the gate driver 3 shown in Figure 2 is not limited to the wiring that provides the drive potential VGL, the wiring that provides the reference potential VGL, and the potential line 24 mentioned above. Specifically, the gate driver 3 is also connected to wiring for individually transmitting the input signals OE1_CK1, OE1_CK2, OE1_VST, and VOUT1, respectively. These wires are used to transmit the operation control signals of the scanning gate driver 3 from the control circuit 5 to the gate driver 3.

[0026] As shown in Figure 2, an output holding unit 11 is interposed between the photodetector 2 and the multiplexer 4. The output holding unit 11 is connected to the photodetector 2 via a signal line Sig. The output holding unit 11 is connected to the multiplexer 4 via an input line Ccds. The number of input lines Ccds is the same as the number of signal lines Sig (H). The output holding unit 11 has a configuration (such as a circuit that functions as a capacitor) for holding the signal OP1. The register of the output holding unit 11 holds the signal OP1 transmitted from the photodetector 2 via the signal line Sig and provides it to the input line Ccds. Note that the expression "input line Ccds" is intended to mean the input to the multiplexer 4.

[0027] Multiplexer 4 is a multiplexer. Multiplexer 4 sequentially outputs the signal OP1 transmitted via the input line Ccds to output lines Rx, which are fewer in number than the input line Ccds. The number of output lines Rx is 1 / R of the number of signal lines Sig and input lines Ccds. R is a natural number greater than or equal to 2, for example, 6.

[0028] In Figure 2, the wiring connected to the multiplexer 4 transmits the signals ASW and xASW from the control circuit 5 to the multiplexer 4 individually to operate the multiplexer 4. Furthermore, among the wiring connected to the output holding unit 11, the wiring to which the potential VREF is supplied provides the reset potential for the output holding unit 11, while the other wiring transmits the control signals RST1T and xRST1T to reset the output holding unit 11.

[0029] As shown in Figure 2, one end 14 of the wiring connected to the photodetector 2, gate driver 3, multiplexer 4, and output holding unit 11, beyond the dashed line 13, is connected to various signal or potential supply sources such as the control circuit 5. Furthermore, a rectifier 12 is provided in the wiring connected to the photodetector 2, gate driver 3, multiplexer 4, and output holding unit 11. The rectifier 12 is equipped with a protection diode to define the signal transmission direction in each wiring in one direction and to suppress overcurrent.

[0030] Next, a more detailed explanation of the implementation of the circuit configuration shown in Figure 3 will be given with reference to Figures 5 to 7.

[0031] Figures 5 and 6 are plan views of the stacked structure included in the circuit configuration shown in Figure 3. Figure 5 mainly shows the TFT 23 and the wiring connected to the TFT 23. Figure 6 mainly shows a part of the configuration of the optical sensor LS in Figure 3. The configuration shown in Figure 6 is located on an upper layer than the configuration shown in Figure 5.

[0032] Figure 7 is a cross-sectional view of the IV-V section shown from Figure 5 to Figure 6. Primarily, PU1 below the dashed line PU in Figure 7 represents the IV-IV' section shown in Figure 5. The IV-IV' section shown in Figure 5 is assumed to continue via a connection point Cn. Also, PU2 below the dashed line PU in Figure 7 represents the V'-V section shown in Figure 6. As indicated by the dashed arrows pointing from IV' to V' in Figures 5 and 6, IV' in Figure 5 and V' in Figure 6 are assumed to be continuous.

[0033] The circuit configuration shown in Figure 3 is implemented by a laminated structure formed on one side of the substrate 10, as shown in Figure 7. The laminated structure is provided between the substrate 10 and the scintillator 15. Hereinafter, the lamination direction of the laminated structure will be referred to as the third direction Dz. The third direction Dz intersects (for example, is orthogonal to) the first direction Dx and the second direction Dy. When one end Dz1 of a certain configuration included in the laminated structure is described, it refers to the substrate 10 side with respect to that configuration. When the other end Dz2 of a certain configuration is described, it refers to the scintillator 15 side with respect to that configuration. For example, one side of the substrate 10 is the other end Dz2 of the substrate 10. The other end Dz2 is the photodetection surface side of the photodetection unit 2, which is provided with a plurality of photosensors LS. That is, the scintillator 15 is provided on the photodetection surface side of the photodetection unit 2. The scintillator 15 is a component that can obtain visible light from X-rays. More specifically, visible light generated by X-rays irradiated onto the scintillator 15 enters the area beyond the scintillator 15 towards the Dz1 side, moving from the other end Dz2 towards the one end Dz1 side. The light sensor LS detects the visible light and generates an output (charge) corresponding to the intensity of the detected visible light.

[0034] As shown in Figure 7, on the other end Dz2 side of the substrate 10, the following layers are stacked in order from the substrate 10 side toward the scintillator 15 side: electrode layer GL1, insulating layer UC, semiconductor layer OS, insulating layer GI, electrode layer GL2, insulating layer PAS, electrode layer SL, insulating layer IL1, planarization film OC1, electrode layer LE, first semiconductor layer 281, second semiconductor layer 282, third semiconductor layer 283, electrode layer UIO, insulating layer IL2, planarization film OC2, electrode layer BIS, electrode layer PIO, insulating layer IL3, and planarization film OC3. Of these, insulating layers UC, GI, PAS, IL1, IL2, and IL3 are film-like structures made of inorganic materials. Also, electrode layers GL1, GL2, SL, LE, and PIO are film-like structures (conductive films) made of conductors. Furthermore, the planarized films OC1, OC2, and OC3 are membrane-like structures made of organic matter.

[0035] The electrode layer GL1 is an electrode layer formed of a conductor. The electrode layer GL1 is formed using, for example, a molybdenum alloy (MoW) containing molybdenum (Mo) and tungsten (W). The electrode layer GL1 is provided as the lower gate 241 of the TFT 23 (see Figures 3 and 5).

[0036] The insulating layer UC is an insulating layer that insulates the electrode layer GL1 from the semiconductor layer OS. The insulating layer UC has a multilayer structure in which, for example, a silicon nitride (SiN) layer is formed at one end Dz1 and a silicon oxide (SiO) layer is formed at the other end Dz2.

[0037] The semiconductor layer OS is an oxide semiconductor layer. The semiconductor layer OS is formed using, for example, IGZO containing In (indium), Ga (gallium), Zn (zinc), and O (oxygen), or IGO containing In (indium), Ga (gallium), and O (oxygen). The semiconductor layer OS is provided, for example, as an oxide semiconductor interposed between the source and drain of the TFT 23. In Figure 5, the oxide semiconductor is shown as oxide semiconductor 232.

[0038] The insulating layer GI is an insulating layer that insulates the electrode layer GL2 from the insulating layer GI. The insulating layer GI and the electrode layer GL2 are formed using, for example, silicon oxide (SiO).

[0039] The electrode layer GL2 is an electrode layer formed of a conductor. The electrode layer GL2 has a multilayer structure in which, for example, a titanium (Ti) layer is formed on one end Dz1 and a molybdenum alloy (MoW) layer is formed on the other end Dz2. The electrode layer GL2 is provided as the upper gate 231 and scan line Rd(y) of the TFT 23 (see Figures 3 and 5). The upper gate 231 is positioned opposite the electrode layer GL1 in the third direction Dz, with the semiconductor of the TFT 23, which is formed of semiconductor layer OS, in between.

[0040] The insulating layer PAS is an insulating layer that insulates the electrode layer GL2 from the electrode layer SL. The insulating layer PAS has a multilayer structure in which, for example, a silicon nitride (SiN) layer is formed at one end Dz1 and a silicon oxide (SiO) layer is formed at the other end Dz2.

[0041] The electrode layer SL is an electrode layer formed of a conductor. The electrode layer SL has a multilayer structure in which, for example, a layer of titanium (Ti) is formed on one end Dz1 side and the other end Dz2 side with a layer of aluminum (Al) sandwiched therebetween. The electrode layer SL is provided as a signal line Sig(x), the source and drain of the TFT23, a wiring connecting the TFT23 and the optical sensor LS, and a potential line 24 (see FIGS. 3 and 5). In FIG. 5, the wiring connecting the TFT23 and the optical sensor LS is shown as a connection portion 235.

[0042] In the laminated structure between the substrate 10 and the scintillator 15, a contact hole 291 for connecting the source and drain of the TFT23 and the semiconductor layer OS is provided. The contact hole 291 is a contact hole that penetrates the insulating layer GI and the insulating layer PAS in the third direction Dz.

[0043] Also, in the laminated structure between the substrate 10 and the scintillator 15, a contact hole 292 for connecting the potential line 24 and the electrode layer GL1 is provided. The contact hole 292 is a contact hole that penetrates the insulating layer UC, the insulating layer GI, and the insulating layer PAS in the third direction Dz.

[0044] The insulating layer IL1 is an insulating layer that insulates the electrode layer SL and the planarization film OC1. The insulating layer IL1 is formed using, for example, silicon nitride (SiN).

[0045] The planarization film OC1 is an organic planarization film. The planarization film OC1 has lower moisture permeability than the planarization film OC2 and the planarization film OC3. By the planarization film OC1, the influence of moisture on the structure on the one end Dz1 side with respect to the planarization film OC1 can be suppressed. The planarization film OC1 is formed using, for example, a low moisture permeability polyimide.

[0046] The electrode layer LE is an electrode layer formed of a conductor. The electrode layer LE is formed using, for example, a molybdenum alloy (MoW). The electrode layer LE is provided as one of two electrodes sandwiching the photodetector 280.

[0047] As shown in FIG. 7, the electrode layer LE is connected to the connection portion 235. In the laminated structure between the substrate 10 and the scintillator 15, a contact hole 293 for connecting the electrode layer LE to the connection portion 235 is provided. The contact hole 293 is a contact hole that penetrates the insulating layer IL1 and the planarization film OC1 in the third direction Dz.

[0048] The first semiconductor layer 281, the second semiconductor layer 282, and the third semiconductor layer 283 constitute the photodetector 280. Specifically, sandwiching the second semiconductor layer 282 formed using amorphous silicon (a-Si), a first semiconductor layer 281 as an N-type semiconductor corresponding to the second semiconductor layer 282 and a third semiconductor layer 283 as a P-type semiconductor corresponding to the second semiconductor layer 282 are provided.

[0049] The electrode layer UIO is an electrode layer formed of a conductor. The electrode layer LE is formed using a light-transmissive conductor such as indium tin oxide (ITO: Indium Tin Oxide). Also, it may be formed using an opaque conductor such as titanium (Ti) or molybdenum tungsten (MoW). Further, an ITO electrode may be laminated on MoW. The electrode layer UIO is provided as the other of the two electrodes sandwiching the photodetector 280.

[0050] When the photodetector 280 is irradiated with light, the power generated by the photovoltaic effect causes a current in the electrode layer LE. Thus, the optical sensor LS functions as a photodiode 21. The electrode layer LE, the first semiconductor layer 281, the second semiconductor layer 282, the third semiconductor layer 283, and the electrode layer UIO constitute the main part of the optical sensor LS.

[0051] The insulating layer IL2 is an insulating layer that insulates the planarization film OC1 and the main part of the optical sensor LS from the planarization film OC2. The insulating layer IL2 is formed using, for example, silicon nitride (SiN).

[0052] The planarization film OC2 is an organic planarization film. Planarization films OC2 and OC3 have higher light transmittance than planarization film OC1. The light transmittance of planarization films OC2 and OC3 allows for a higher light sensitivity of the optical sensor LS. Planarization films OC2 and OC3 are formed using, for example, acrylic, which exhibits high light transmittance.

[0053] The electrode layer BIS is an electrode layer formed of a conductor. The electrode layer BIS has a multilayer structure in which, for example, a layer of aluminum-silicon alloy (AlSi) is sandwiched between layers of molybdenum alloy (MoW) at one end Dz1 and the other end Dz2.

[0054] The electrode layer PIO is an electrode layer formed of a conductor. The electrode layer PIO is formed using a translucent conductor such as indium tin oxide (ITO). The electrode layer BIS and the electrode layer PIO constitute an additional part of the optical sensor LS.

[0055] As shown in Figure 7, electrode layer PIO connects electrode layer UIO and electrode layer BIS. The laminated structure between substrate 10 and scintillator 15 is provided with contact holes 294 in electrode layer PIO for connecting electrode layer UIO and electrode layer BIS. Contact holes 294 are contact holes that penetrate the planarization film OC1 and the insulating layer IL2 in the third direction Dz. Contact holes 294 include a large contact hole 2941 that penetrates the planarization film OC1 at one end Dz1, and a small contact hole 2942 that penetrates the insulating layer IL2 in the third direction Dz within the large contact hole 2941 (see Figure 6).

[0056] The insulating layer IL3 is an insulating layer that insulates the planarization film OC2 and the added portion of the optical sensor LS from the planarization film OC3. The insulating layer IL3 is formed using, for example, silicon nitride (SiN). The planarization film OC3 is an organic planarization film.

[0057] For the first direction Dx, the signal line Sig(x) side is designated as one end Dx1, and the potential line 24 side is designated as the other end Dx2, with the connection portion 235 in between (see Figures 5 and 6). Similarly, for the second direction Dy, the contact hole 293 side is designated as one end Dy1, with the scan line Rd(y) side being designated as the other end Dy2, with the TFT 23 in between (see Figures 5 and 6). With the upper gate 231 in between, the signal line Sig(x) and the connection portion 235 are aligned in the first direction Dx. In Figure 5, with the upper gate 231 in between, the signal line Sig(x) is positioned on one end Dx1, and the connection portion 235 is positioned on the other end Dx2.

[0058] As shown in Figure 5, the upper gate 231 is provided so that its longitudinal direction is aligned with the second direction Dy. The upper gate 231 extends from both ends of the oxide semiconductor 232 in the second direction Dy in a plan view. The upper gate 231 is connected to the scan line Rd(y) at the other end Dy2 side. The oxide semiconductor 232 is provided so as to overlap with a part of the upper gate 231 and a part of the lower gate 241 in a plan view. The part of the lower gate 241 that overlaps with the upper gate 231 is aligned with the second direction Dy. In addition, the other part of the lower gate 241 that is connected to the potential line 24 via the contact hole 292 is aligned with the first direction Dx. Near the position where the lower gate 241 overlaps with one end Dy1 side of the upper gate 231 in a plan view, the part aligned with the second direction Dy and the part aligned with the first direction Dx are connected so as to be continuous.

[0059] In Embodiment 1, the width of a portion of the lower gate 241 that overlaps with the upper gate 231 in a plan view, in the first direction Dx, is greater than the width of the upper gate 231 in the first direction Dx. Specifically, the lower gate 241 has a width that is D0 greater than the upper gate 231 on one end Dx1 side and the other end Dx2 side, in a plan view.

[0060] Furthermore, in Embodiment 1, the width of the scan line Rd(y) in the second direction Dy is width D1, except for the area overlapping with the signal line Sig(x) in a planar view and its vicinity. Of the scan line Rd(y), the width of the second direction Dy in the area overlapping with the signal line Sig(x) in a planar view and its vicinity is width D2. Width D2 is smaller than width D1.

[0061] Furthermore, in Embodiment 1, the width of the signal line Sig(x) and the potential line 24 in the first direction Dx is D3, except for the area that overlaps with the scan line Rd(y) in a planar view and its vicinity. Of the signal line Sig(x) and the potential line 24, the width of the first direction Dx in the area that overlaps with the scan line Rd(y) in a planar view and its vicinity is D4. Width D4 is greater than width D3.

[0062] The width D0 is, for example, 1.4 μm. The widths D1 and D4 are, for example, 4 μm. The widths D2 and D3 are, for example, 3 μm. Furthermore, the area shown as TFT23 in Figure 5 is provided to be, for example, approximately 15 μm in the first direction Dx and approximately 3 μm in the second direction Dy. Note that the positional relationship between TFT23 and the lower gate 241 in Figure 5 is only approximate and does not strictly reflect the actual dimensions of the width of TFT23 in the first direction Dx and the width of a part of the lower gate 241 in the first direction Dx. In reality, as shown in Figure 7, the electrode layer GL1 including the lower gate 241 is provided to cover a larger area than the semiconductor layer OS and the electrode layer GL2.

[0063] As shown in Figure 6, in a planar view, the electrode layer PIO, electrode layer BIS, electrode layer LE, photodetector 280, and electrode layer UIO are arranged to overlap. In a single photosensor LS configuration, of the electrode layer PIO, electrode layer BIS, electrode layer LE, photodetector 280, and electrode layer UIO, electrode layer PIO has the largest outer edge relatively.

[0064] From a planar perspective, the shapes of electrode layer PIO and electrode layer BIS are frame-like. The frame is square. Two of the four sides are parallel to the first direction Dx, and the other two sides are parallel to the second direction Dy. From a planar perspective, electrode layer BIS is bordered by electrode layer PIO, which covers a larger area.

[0065] The electrode layer LE is provided to cover a smaller area inside the electrode layer BIS than the electrode layer PIO. In a plan view, the electrode layer LE is bordered by the electrode layer BIS. In Embodiment 1, the outer edge of the electrode layer BIS is almost square in shape, following the inner edge of the electrode layer BIS, but strictly speaking, it is an octagon with the corners of the four vertices of the square slightly cut off. A portion of the outer edge of the electrode layer LE overlaps with a portion of the inner edge of the electrode layer PIO in a plan view.

[0066] The photodetector 280 is provided to cover a smaller area than the electrode layer LE, within the range that overlaps with the translucent electrode layer LE. The electrode layer UIO is provided to cover a smaller area than the electrode layer LE and the photodetector 280, within the range that overlaps with the translucent electrode layer LE. As shown in Figure 7, the photodetector 280 and the electrode layer UIO are provided on the other end Dz2 side of the electrode layer LE, so that they can receive external X-ray irradiation converted to visible light by the scintillator 15.

[0067] Furthermore, the insulating layer IL3, as described with reference to Figure 7, is provided with drainage holes 271 and 272 as shown in Figure 6. Drainage hole 271 is positioned in a location that does not overlap with electrode layer PIO and electrode layer BIS in a plan view. Also, drainage hole 271 is positioned in the area where electrode layer LE is provided in a plan view. Specifically, drainage hole 271 is positioned, for example, near one of the four vertices of the square frame of electrode layer BIS. Contact hole 294 is positioned in the area where electrode layer LE is provided in a plan view, near one of the other four vertices of the square frame of electrode layer BIS. Here, one of the four vertices of electrode layer BIS closer to drainage hole 271 and one of the four vertices of electrode layer BIS closer to contact hole 294 are positioned opposite each other in directions that intersect the first direction Dx and the second direction Dy. The drainage holes 271 and 272 have a rectangular shape in a plan view, for example, with a side length of about 5 μm, but are not limited to this, and their specific shape and dimensions can be changed as appropriate.

[0068] The contact hole 293 is located in the area where the electrode layer LE is provided from a plan view, near one of the four vertices of the square frame of the electrode layer BIS and near the drain hole 271. However, the contact hole 293 is located in a position that does not overlap with the drain hole 271 and is relatively far from one of the four vertices.

[0069] In Embodiment 1, the photodetector 280 and electrode layer UIO are shaped so as not to overlap with the drainage holes 271 and contact holes 293 in a planar view. Specifically, as shown in Figure 7, the photodetector 280 and electrode layer UIO are formed to cover an area that is cut out from the square-shaped area formed by the inner edge of the electrode layer PIO, specifically the area where the drainage holes 271 and contact holes 293 are formed. More precisely, the area covered by the photodetector 280 is shaped like the corners of the remaining triangle in the aforementioned square-shaped area slightly cut off.

[0070] More specifically, the photodetector 280 and the contact hole 293 are separated by a width D5 in the first direction Dx and a width D6 in the second direction Dy. The outer edge of electrode layer UIO traces a position approximately D7 away from the outer edge of photodetector 280. The outer edge of photodetector 280 also traces a position approximately D8 away from the inner edge of electrode layer BIS.

[0071] The drain holes 272 are positioned so as not to overlap with the electrode layer LE in a planar view. In Embodiment 1, the drain holes 272 and the electrode layer LE are separated by a width D9. The drain holes 271 are positioned in a range that overlaps with the electrode layer BIS. Specifically, the drain holes 271 are positioned, for example, near the four vertices of the square frame of the electrode layer BIS.

[0072] Widths D5 and D6 are, for example, 4 μm. Width D7 is, for example, 2.75 μm. Width D8 is, for example, 3.25 μm. Width D9 is, for example, 3.8 μm.

[0073] Contact holes such as contact hole 293 are holes formed in the insulating layer, which widen from one end Dz1 to the other end Dz2, and the inside is filled with a layer laminated on the other end Dz2 of the insulating layer. Specifically, the smallest part of contact hole 2932 on the one end Dz1 side is 4 μm in the first direction Dx and 4 μm in the second direction Dy when viewed from a plan view. The largest part of contact hole 2931 on the other end Dz2 side is 8 μm in the first direction Dx and 8 μm in the second direction Dy when viewed from a plan view.

[0074] The largest portion of the contact hole 294 on the other end Dz2 side of the large contact hole 2941 is 14 μm in the first direction Dx and 14 μm in the second direction Dy when viewed from a plan view. The largest portion of the contact hole 294 on the other end Dz2 side of the small contact hole 2942 is 6.5 μm in the first direction Dx and 6.5 μm in the second direction Dy when viewed from a plan view.

[0075] Contact holes other than contact holes 293 and 294 (contact holes 291, 292, etc.) are generally about 2.5 μm in the first direction Dx and about 2.5 μm in the second direction Dy. Although contact holes other than contact holes 293 and 294 are strictly speaking flared holes, there is not much of a remarkable difference in dimensions between the upper and lower ends.

[0076] The configurations shown in Figures 5 and 6 represent the configuration of one of the multiple optical sensors LS arranged in a matrix in the optical detection unit 2. Therefore, the optical detection unit 2 has multiple stacked structures in which the configuration shown in Figure 5 and the configuration shown in Figure 6 overlap in a planar view, arranged in a matrix along the first direction Dx and the second direction Dy. The mounting area units for the configuration of one optical sensor LS are, for example, 100 μm in the first direction Dx and 100 μm in the second direction Dy, but are not limited to these and can be changed as appropriate. In other words, the sizes of widths D1 to D9, the mounting area of ​​the oxide semiconductor TFT, the dimensions of various contact holes, etc., described above are examples based on the mounting area units and are not limited to the above values.

[0077] Although Figures 4 to 7 show a configuration in which TFT 23 is provided as an oxide semiconductor TFT, the planar view of the oxide semiconductor TFT is not limited to that of TFT 23. Not limited to TFT 23, any TFT mounted on the substrate 10 is an oxide semiconductor TFT similar to TFT 23 and has a TFT portion 500 (see Figure 7). Hereinafter, a general overview of the planar view of the oxide semiconductor TFT provided on the substrate 10 will be described with reference to Figures 7 and 8.

[0078] Figure 8 is a schematic diagram showing a typical configuration of an oxide semiconductor TFT from a planar viewpoint. In a planar view, the oxide semiconductor TFT has an upper gate 431, an oxide semiconductor 432, and a lower gate 441 that overlap. The upper gate 431 is composed of the electrode layer GL2 of the TFT portion 500 shown in Figure 7. The oxide semiconductor 432 is composed of the semiconductor layer OS of the TFT portion 500 shown in Figure 7. The lower gate 441 is composed of the electrode layer GL1 of the TFT portion 500 shown in Figure 7. The upper gate 431 is the upper gate of the oxide semiconductor TFT. The oxide semiconductor 432 is the oxide semiconductor of the oxide semiconductor TFT. The lower gate 441 is the lower gate of the oxide semiconductor TFT.

[0079] The longitudinal direction of the upper gate 431 and the longitudinal direction of the oxide semiconductor 432 intersect. The oxide semiconductor 432 extends to a position where it does not overlap with the upper gate 431 and the lower gate 441 in a planar view. At a position where it does not overlap with the upper gate 431 and the lower gate 441 in a planar view, the oxide semiconductor 432 has one end 4321 and the other end 4322 which are connected to the source and drain of the oxide semiconductor TFT. In Figure 8, one end 4321 is connected to electrode 451, which is either the source or the drain. Also in Figure 8, the other end 4322 is connected to electrode 452, which is the other source or drain. Electrodes 451 and 452 are composed of the electrode layer SL shown in Figure 7.

[0080] The connection between one end 4321 and electrode 451, and the connection between the other end 4322 and electrode 452, are made via a contact hole such as contact hole 461. Like contact hole 291, contact hole 461 is a contact hole that penetrates the insulating layer GI and insulating layer PAS in the third direction Dz.

[0081] One end 4321, the other end 4322, and electrodes 451 and 452 are formed with a margin relative to the contact hole 461 in a plan view, so that a contact hole like the contact hole 461 can be sufficiently formed. Here, we assume that the contact hole 461 is rectangular in shape with a width D51 in the width direction and a height D52 in the height direction. One end 4321 and the other end 4322 have a margin of width D54 on the upper gate 431 side of the contact hole 461, and a margin of width D53 on the opposite side of the upper gate 431, with the contact hole 461 in between. That is, the size of one end 4321 and the other end 4322 in the width direction is the sum of widths D51, D53, and D54. In Figure 8, width D53 is larger than width D54, but this is not limited to this and can be changed as appropriate. Furthermore, one end 4321 and the other end 4322 have a margin of height D56 on both sides in the height direction, centered on the contact hole 461. That is, the size of one end 4321 and the other end 4322 in the height direction is the sum of the height D52 and twice the height D56.

[0082] Electrodes 451 and 452 have a margin of width D54 on the upper gate 431 side of the contact hole 461, and a margin of width D55 on the opposite side of the upper gate 431, across the contact hole 461. That is, the width of electrodes 451 and 452 is the sum of widths D51, D54, and D55. In Figure 8, width D55 is smaller than width D54, but this is not limited to this and can be changed as appropriate. Also, electrodes 451 and 452 have a margin of height D57 on both sides in the height direction with the contact hole 461 as the center. That is, one end 4321 and the other end 4322 have a height that is the sum of height D52 and twice height D57. Here, height D57 is smaller than height D56. Therefore, in a plan view, one end 4321 and the other end 4322 appear to protrude from electrodes 451 and 452 by an amount corresponding to the difference between height D56 and height D57 in the height direction. Also, in a plan view, one end 4321 and the other end 4322 appear to protrude from electrodes 451 and 452 by an amount corresponding to the difference between width D53 and width D55 in the width direction.

[0083] Although not shown in Figure 8, in reality, wiring sections for connecting the oxide semiconductor TFT to other components are provided extending from electrodes 451 and 452, respectively.

[0084] Furthermore, from a plan view, the lower gate 441 is larger in the width direction than the upper gate 431. Specifically, the width of the upper gate 431 is width D41. In contrast, the lower gate 441 extends from the upper gate 431 on both sides in the width direction by width D43. That is, the width of the lower gate 441 is the sum of width D41 and twice width D43.

[0085] Furthermore, the upper gate 431 and the lower gate 441 are larger in the height direction than the oxide semiconductor 432. Specifically, the width of the oxide semiconductor 432 is its height D42. In contrast, the lower gate 441 extends from the oxide semiconductor 432 on both sides in the height direction by a height D44. That is, the height of the oxide semiconductor 432 is the sum of its height D42 and twice its height D44. Moreover, the height end of the upper gate 431 extends from the lower gate 441 on one side in the height direction by a height D45.

[0086] Furthermore, when the upper gate 431 is connected to an electrode layer different from electrode layer GL1 (for example, electrode layer GL1), an extension portion 4310 is provided at the end of the extension portion 4310 that extends to the other side in the height direction relative to the lower gate 441. The extension portion 4310 is connected via a connecting portion 450. The connecting portion 450 is made of electrode layer SL. In a plan view, the lower gate 441 and the connecting portion 450 are separated by a distance D46.

[0087] The extension portion 4310 and the connecting portion 450 are connected via a contact hole 462. The connecting portion 450 is connected to an electrode layer different from electrode layer GL1 (for example, electrode layer GL1) via a contact hole 463. The contact hole 462 is a contact hole that penetrates the insulating layer PAS in the third direction Dz. The contact hole 463, like the contact hole 291, is a contact hole that penetrates the insulating layer UC, insulating layer GI, and insulating layer PAS in the third direction Dz.

[0088] The extension portion 4310 and the connecting portion 450 are formed with a margin relative to the contact holes 462 and 463 in a plan view, so that the contact holes 462 and 463 can be sufficiently formed. Here, assume that the contact hole 462 is rectangular in shape with a size D61 in the width direction. The extension portion 4310 has a margin of width D62 on both sides of the contact hole 462 in the width direction. That is, the size of the extension portion 4310 in the width direction is the sum of the size D61 and twice the width D62. Also, the extension portion 4310 has a margin of height D63 on both sides of the contact hole 462 in the height direction. That is, the size of the extension portion 4310 in the height direction is the sum of the size D61 and twice the height D63.

[0089] Furthermore, the contact hole 463 is rectangular in shape with a width D71 in the width direction. The contact holes 462 and 463 are spaced apart in the width direction at an interval equal to the sum of widths D62 and D72. The connecting portion 450 has a margin of width D64 on one side in the width direction relative to the contact hole 462. The connecting portion 450 also has a margin of width D73 on the other side in the width direction relative to the contact hole 463. In other words, the size of the connecting portion 450 in the width direction is the sum of width D64, size D61, width D62, width D72, width D71, and width D73.

[0090] Furthermore, the connecting portion 450 has a height margin D65 on both sides in the height direction relative to the width of the contact hole 462 in the height direction (for example, size D61) of the contact hole 462. That is, the size of the connecting portion 450 in the height direction is the sum of the width of the contact hole 462 in the height direction and the height D65. The height D65 is smaller than the height D63. Therefore, in a plan view, a portion of the extension portion 4310 appears to protrude from the connecting portion 450.

[0091] Next, the pad section 9 (see Figure 1) will be described with reference to Figures 9 to 11. Figure 9 is a schematic diagram showing an example of the configuration of multiple wiring sections 91 and pads 92 provided in the pad section 9. Figure 10 is an enlarged view of the focus range 900 in Figure 9. Figure 11 is a cross-sectional view taken along line XI-XI in Figure 9.

[0092] As shown in Figure 9, the pad portion 9 is provided with a wiring portion 91, a pad 92, and a covering portion 93. The wiring portion 91 is one of the wires connected to the configuration provided on the substrate 10. The pad 92 is an exposed terminal formed at the end of the wiring portion 91. The pad 92 is rectangular in shape, for example, with a width D89 in the second direction Dy being larger than a width D88 in the first direction Dx, but is not limited to this, and the specific shape in a planar view can be changed as appropriate. The covering portion 93 is an insulator that covers the portion of the pad portion 9 other than the pad 92. In Figure 9, the wiring portion 91 is shown for the purpose of indicating the direction of extension of the wiring portion 91, but in reality it is covered by the covering portion 93.

[0093] One end of the wiring of the connection part 6 shown in Figure 1 is joined to the pad 92. This connects the control circuit 5 to the components provided on the substrate 10 via the connection part 6. The components provided on the substrate 10 include, for example, the photodetector 2, gate driver 3, multiplexer 4, output holding unit 11, rectifier unit 12, etc., as explained with reference to Figure 2.

[0094] As shown in Figures 10 and 11, the pad 92 is made up of multiple electrode layers stacked together. Specifically, as shown in Figure 11, with electrode layer GL2 as the starting point at one end Dz1, these electrode layers are stacked in the order of electrode layer GL2, electrode layer SL, electrode layer LE, electrode layer BIS, and electrode layer PIO, without any insulating layers in between, moving from one end Dz1 to the other end Dz2. Here, electrode layer GL2 is the same layer as the upper gate 231. Electrode layer SL is the same layer as the source and drain connected to the TFT 23. Electrode layer LE is the same layer as the electrode (first electrode) at one end Dz1 of the optical sensor LS. Electrode layer BIS is the same layer as the electrode layer PIO provided at one end Dz1 of the additional portion of the optical sensor LS. Electrode layer PIO is the same layer as the electrode layer BIS provided at the other end Dz2 of the additional portion of the optical sensor LS. Thus, the pad 92 has layers in the same layer as the upper gate of the oxide semiconductor TFT, the drain or source electrode connected to the oxide semiconductor TFT, the first electrode, the electrode layer BIS, and the electrode layer PIO. Therefore, the pad (pad 92) of the substrate (substrate 10) on which the photodetector (photodetector 2) is formed has a second conductive film (e.g., electrode layer GL2), a third conductive film (e.g., electrode layer SL), a conductive film in the same layer as the first electrode (e.g., electrode layer LE), a non-transparent electrode and a conductive film in the same layer (e.g., electrode layer BIS), and a fourth conductive film (e.g., electrode layer PIO).

[0095] Furthermore, as shown in Figures 10 and 11, the pad 92 tends to be larger in a planar view when stacked on the other end Dz2 side compared to when stacked on the one end Dz1 side. Specifically, the third intermediate portion 286 is formed with a width and height that extends by a margin D91 at both ends of the first direction Dx and both ends of the second direction Dy compared to the width of the electrode layer GL2 in the first direction Dx and the height of the second direction Dy in a planar view. Note that the magnified focus range 900 in Figure 10 shows the vicinity of one of the four vertices of the rectangular pad 92, but a similar stacking relationship is established for the remaining three of the four vertices. Also, the second intermediate portion 285 is formed with a width and height that extends by a margin D91 at both ends of the first direction Dx and both ends of the second direction Dy compared to the width of the third intermediate portion 286 in the first direction Dx and the height of the second direction Dy in a planar view. Furthermore, compared to the width Dx and height Dy of the second intermediate portion 285 in a plan view, the first intermediate portion 284 is formed with a width and height that extends by a margin D91 at both ends in the first direction Dx and at both ends in the second direction Dy. Also, compared to the width Dx and height Dy of the first intermediate portion 284 in a plan view, the electrode layer PIO is formed with a width and height that extends by a margin D91 at both ends in the first direction Dx and at both ends in the second direction Dy.

[0096] The first intermediate section 284 shown in Figure 10 indicates the formation range of electrode layer LE and electrode layer BIS from a planar viewpoint. The second intermediate section 285 shown in Figure 10 indicates the formation range of electrode layer SL from a planar viewpoint and the formation range of the opening in insulating layer IL3. The third intermediate section 286 shown in Figure 10 indicates the formation range of the opening in insulating layer IL1.

[0097] The fourth intermediate portion 287 shown in Figure 10 is an opening formed in the insulating layer PAS shown in Figure 11, and indicates the formation range of the opening that exposes the other end Dz2 side of the electrode layer GL2. In other words, the fourth intermediate portion 287 can be said to represent the contact area between the electrode layer GL2 and the electrode layer SL. The fifth intermediate portion 288 shown in Figure 10 is an opening formed in the insulating layer IL2 shown in Figure 11, and indicates the formation range of the opening that exposes the other end Dz2 side of the electrode layer LE. In other words, the fifth intermediate portion 288 can be said to represent the contact area between the electrode layer LE and the electrode layer BIS.

[0098] Furthermore, as shown in Figure 11, an insulating layer 2892 is formed between the electrode layer GL2 of the pad 92 and the substrate 10. The insulating layer 2892 is an insulating layer that includes an insulating layer GI and an insulating layer UC.

[0099] Furthermore, as shown in Figure 11, a portion of the electrode layer PIO of the pad 92 is covered on the other end Dz2 side with an insulating layer IL3. This insulating layer IL3 is the configuration on the other end Dz2 side of the covering portion 93 shown in Figure 9. Note that the width D88, which is the width in the first direction Dx of the electrode layer PIO exposed on one pad 92, is larger than the width D93, which is the width in the first direction Dx of the insulating layer IL3 formed between two adjacent pads 92 in the first direction Dx. Also, the width D93 is larger than the width D94, which is the distance in the first direction Dx between the respective electrode layers PIO of two adjacent pads 92 in the first direction Dx.

[0100] Note that, not limited to TFT 23, oxide semiconductor TFTs, as shown in Figure 7, consist of a semiconductor composed of a semiconductor layer OS, an upper gate and a lower gate arranged opposite each other in the third direction Dz with the semiconductor in between, and a source and drain of the semiconductor. The upper gate of the oxide semiconductor TFT is composed of an electrode layer GL2. The lower gate of the oxide semiconductor TFT is composed of an electrode layer GL1. The source and drain of the oxide semiconductor TFT are composed of an electrode layer SL. The connection between the semiconductor and the source, and the connection between the semiconductor and the drain of the oxide semiconductor TFT, is via a contact hole that penetrates the insulating layer GI and the insulating layer PAS in the third direction Dz, similar to the contact hole 291.

[0101] Here, the insulating layers GI, PAS, IL1, LI2, and IL3 are film-like structures made of inorganic materials. The planarization layers OC1, OC2, and OC3 are film-like structures made of organic materials. Therefore, insulating layer GI can be considered the first inorganic film. Insulating layer PAS can be considered the second inorganic film. Insulating layer IL1 can be considered the third inorganic film. Insulating layer LI2 can be considered the fourth inorganic film. Insulating layer IL3 can be considered the fifth inorganic film. Electrode layers GL1, GL2, SL, and PIO are conductive films. Therefore, electrode layer GL1 can be considered the first conductive film. Electrode layer GL2 can be considered the second conductive film. Electrode layer SL can be considered the third conductive film. Electrode layer PIO can be considered the fourth conductive film. Furthermore, the electrode layer LE, the first semiconductor layer 281, the second semiconductor layer 282, the third semiconductor layer 283, and the electrode layer UIO constitute a multilayer structure that forms the optical sensor LS. Accordingly, the detection device according to this disclosure (for example, detection device 1) has a configuration that is relatively far from the scintillator 15, in order from the configuration that is relatively close to the scintillator 15, consisting of a first conductive film (for example, electrode layer GL1) that constitutes the lower gate of the oxide semiconductor TFT, a first inorganic film (for example, insulating layer GI), a semiconductor layer that constitutes the oxide semiconductor (for example, semiconductor layer OS), a second inorganic film (for example, insulating layer PAS), a second conductive film (for example, electrode layer GL2) that constitutes the upper gate of the oxide semiconductor TFT, and a third inorganic film (for example, insulating layer IL1). It can be said that the photodiode is constructed by stacking the following layers in order: a third conductive film (e.g., electrode layer SL) constituting the source and drain connected to the oxide semiconductor, a fourth inorganic film (e.g., insulating layer IL2), a first organic film (e.g., planarization film OC1), a multilayer structure constituting the photodiode (e.g., electrode layer LE, first semiconductor layer 281, second semiconductor layer 282, third semiconductor layer 283, electrode layer UIO), a second organic film (e.g., planarization film OC2), a fifth inorganic film (e.g., insulating layer IL3), and a third organic film (e.g., planarization film OC3).

[0102] Furthermore, the contact hole 291 can be considered as a first through-hole penetrating the second inorganic film (e.g., insulating layer PAS) and the third inorganic film (e.g., insulating layer IL1). Therefore, it can be said that one of the source or drain of the oxide semiconductor TFT (e.g., TFT 23) is connected to the oxide semiconductor (e.g., the oxide semiconductor 232 of the semiconductor layer OS) via the first through-hole.

[0103] Furthermore, the portion of the optical sensor LS made up of the electrode layer LE can be considered as the first electrode of the optical sensor LS. Also, the portion of the optical sensor LS made up of the electrode layer UIO can be considered as the second electrode of the optical sensor LS. In addition, the contact hole 293 can be considered as a through-hole (second through-hole) that penetrates the fourth inorganic film (e.g., the insulating layer IL2) and the first organic film (e.g., the planarization film OC1). Therefore, it can be said that the first electrode of the photodiode (e.g., optical sensor LS) (e.g., the portion made up of the electrode layer LE) is connected to either the source or the drain of the oxide semiconductor TFT (e.g., TFT 23) via the second through-hole. Here, the source or drain connected to the oxide semiconductor via the first through-hole and the source or drain connected to the first electrode via the second through-hole have the same configuration.

[0104] Furthermore, the contact hole 294 for connecting electrode layer UIO and electrode layer BIS in electrode layer PIO can be considered as an opening in the second electrode of the photodiode (for example, the portion made of electrode layer UIO) that is not covered by the fourth inorganic film (for example, insulating layer IL2). In other words, the fourth inorganic film (for example, insulating layer IL2) covers the first electrode of the photodiode (for example, the photosensor LS) (for example, the portion made of electrode layer LE) and a portion of the second electrode of the photodiode (for example, the portion made of electrode layer UIO), excluding the opening.

[0105] Furthermore, the electrode layer PIO is translucent. Therefore, it can be said that a translucent fourth conductive film (e.g., electrode layer PIO) is formed on the second electrode of the photodiode (e.g., the light sensor LS) (e.g., the portion made of electrode layer UIO). Furthermore, it can be said that a non-translucent electrode (electrode layer BIS) is connected to this fourth conductive film.

[0106] As described above, Embodiment 1 provides a detection device using a scintillator that obtains visible light from X-rays, and which has reduced power consumption.

[0107] Furthermore, the first organic film (e.g., planarization film OC1) has lower moisture permeability compared to the second organic film (e.g., planarization film OC2) and the third organic film (e.g., planarization film OC3). This suppresses the degradation of oxide semiconductor TFTs due to humidity.

[0108] Furthermore, the second organic film (e.g., planarization film OC2) and the third organic film (e.g., planarization film OC3) have higher light transmittance than the first organic film (e.g., planarization film OC1). This makes it easier to improve the accuracy of light detection for the photodiode (e.g., light sensor LS).

[0109] Furthermore, the pad (pad 92) of the substrate (substrate 10) on which the photodetector (photodetector 2) is formed has a second conductive film (e.g., electrode layer GL2), a third conductive film (e.g., electrode layer SL), a conductive film in the same layer as the first electrode (e.g., electrode layer LE), a conductive film in the same layer as the non-transparent electrode (e.g., electrode layer BIS), and a fourth conductive film (e.g., electrode layer PIO). This makes it possible to increase the physical strength of the pad compared to when the pad is formed of a single layer of conductive film. Consequently, it becomes easier to ensure a more reliable connection through the pad.

[0110] (Modifications of Embodiment 1) Next, modifications of Embodiment 1 will be described with reference to Figures 12 and 13. Figure 12 is a diagram showing the circuit configuration of the optical sensor LS in a modification of Embodiment 1. Figure 13 is a diagram showing an example of the connection configuration between the lower gate 241 and the upper gate 231 formed in the modification of Embodiment 1.

[0111] As shown in Figures 12 and 13, in the modified embodiment of Embodiment 1, the potential line 24 that was provided in Embodiment 1 is not provided. That is, in the modified embodiment of Embodiment 1, there is no configuration for transmitting the lower gate potential VGL2 to the lower gate 241. In the modified embodiment of Embodiment 1, the lower gate 241 is given the same potential as the upper gate 231. That is, in the modified embodiment of Embodiment 1, the drive signal Vgate is given to the lower gate 241.

[0112] Specifically, a connection structure 750 is provided for connecting the lower gate 241 and the upper gate 231. The connection structure 750 includes a connection portion 751, a contact hole 752, and a contact hole 753. The connection portion 751 is made of the electrode layer SL. The contact hole 752 is a contact hole through which the connection portion 751 is connected to the base of the upper gate 231 near the scan line Rd(y). The contact hole 752 is a contact hole that penetrates the insulating layer PAS. The contact hole 753 is a contact hole through which the connection portion 751 is connected to the lower gate 241. Similar to the contact hole 292, the contact hole 753 is a contact hole provided to connect the electrode layer GL1 and the electrode layer SL. The connecting portion 751 overlaps with the upper gate 231 near the base of the upper gate 231 on the scan line Rd(y) side, with another portion extending from that portion toward the other end Dx2 side. In the modified example of Embodiment 1, the lower gate 241 has an L-shape that extends to the base of the upper gate 231 on the scan line Rd(y) side and overlaps with the connecting portion 751 in a plan view. Note that the modified example of Embodiment 1 does not have a potential line 24. Accordingly, the portion of the lower gate 241 in the second direction Dy that was connected to the potential line 24 in Embodiment 1 (another part of the lower gate 241) is omitted in the modified example of Embodiment 1. For this reason, in the modified example of Embodiment 1, the end of the upper gate 231 on the Dy1 side extends from the lower gate 241 in a plan view. Except for the matters specifically noted above, the modified example of Embodiment 1 is the same as Embodiment 1. The modified example of Embodiment 1 can achieve the same effects as Embodiment 1.

[0113] (Embodiment 2) Hereinafter, Embodiment 2, which differs in some configuration from Embodiment 1, will be described with reference to Figures 14 to 17. In the description of Embodiment 2, the same reference numerals will be used for components similar to those in Embodiment 1, and their descriptions may be omitted.

[0114] Figure 14 shows the signals input to the photodetector 2A, gate driver 3A, and multiplexer 4, the signals output from the photodetector 2A, gate driver 3A, and multiplexer 4, and the connections of the wiring that transmits these signals in Embodiment 2. As shown in Figure 14, in Embodiment 2, the gate driver 3 of Embodiment 1 is replaced by gate driver 3A. The gate driver 3A has a first circuit 301 and a second circuit 302. The first circuit 301 has the same configuration as the gate driver 3 in Embodiment 1. Note that in Figure 14 and Figure 20 described later, the scan line Rd is shown as a single line, but the scan line Rd in Embodiment 2 also includes V wires, such as scan lines Rd1, Rd2, ..., RdV, similar to Embodiment 1. Multiple optical sensors LS (see Figure 3) provided in the photodetector 2A of Embodiment 2 are connected to the first circuit 301 via scan lines Rd, similar to Embodiment 1.

[0115] The second circuit 302 is a shift register circuit that outputs a reset signal RST for resetting the capacitance 22 of the optical sensor LS of Embodiment 2. The multiple optical sensors LS (see Figure 15) provided in the optical detection unit 2A of Embodiment 2 are connected to the second circuit 302 via reset lines Rs, as shown in Figure 14. The reset lines Rs include V wires, such as reset lines Rs1, Rs2, ..., RsV.

[0116] In Embodiment 1, the strength of the output of the optical sensor LS is directly reflected in the output of output OP1. In contrast, in Embodiment 2, the strength of the output of the optical sensor LS is reduced by the gate-source voltage (Vth) of TFT 602 and reflected in the output of output OP1 through TFT 603. At this time, current is supplied to the output from the output power supply potential PVDD. Also in Embodiment 2, first, a signal OP1 corresponding to the strength of the output of the optical sensor LS is applied to the signal line Sig(x), and then a reset signal RST is applied to TFT 601, resetting the optical sensor LS and the signal line Sig(x) to the reset potential VREF. As a result, an output fluctuation from signal OP1 to the reset potential VREF occurs in the signal line Sig(x). In Embodiment 2, the intensity of light detected by the optical sensor LS is determined based on the degree of output fluctuation. In other words, the light detection unit 2 of Embodiment 1 functions as a passive photosensor (PPS). In contrast, the light detection unit 2A of Embodiment 2 functions as an active photosensor (APS).

[0117] Figure 15 is a diagram showing the circuit configuration of the photodetector LS provided in the photodetector 2A. As shown in Figure 14, in Embodiment 2, the photodetector 2 of Embodiment 1 is replaced by the photodetector 2A. The photodetector LS provided in the photodetector 2A has a photodiode 21 and a capacitor 22, similar to the photodetector LS of Embodiment 1. The anode of the photodiode 21 in Embodiment 2 is connected to the wiring to which the potential PVSS2 is supplied, similar to Embodiment 1. On the other hand, the cathode of the photodiode 21 in Embodiment 2 is connected to either the source or drain of the TFT 601 and the upper gate 236 of the TFT 602. The capacitor 22 in Embodiment 2 is electrically parallel with the photodiode 21, similar to Embodiment 1. Therefore, when shown in the circuit diagram, the capacitor 22 can be considered to be connected to the wiring, either the source or drain of the TFT 601 and the upper gate 236 of the TFT 602.

[0118] TFTs 601 and 602 are oxide semiconductor TFTs. The source or drain of TFT 601 is connected to wiring 25 to which a reset potential VREF is applied. The upper gate 237 of TFT 601 is connected to reset line Rs(y). Reset line Rs(y) is one of the reset lines Rs1, Rs2, ..., RsV. When a reset signal RST is applied to the upper gate 237 of TFT 601 from the second circuit 302, the reset potential VREF is applied to capacitor 22 and capacitor 22 is reset.

[0119] The drain of TFT 602 is connected to wiring 26 to which the output power supply potential PVDD is supplied. The source of TFT 602 is connected to either the source or the drain of TFT 23. In Embodiment 2, the source potential of TFT 602 changes according to the charge stored in capacitor 22. That is, in Embodiment 2, TFT 602 operates as a source follower transistor. Here, in Embodiment 1, a current corresponding to the charge stored in capacitor 22 flows to either the source or the drain of TFT 23. On the other hand, in Embodiment 2, the charge stored in capacitor 22 does not move to the signal line sig(x), and a potential corresponding to the charge stored in capacitor 22 is supplied to the signal line sig(x). That is, a potential lower than the gate-source voltage (Vth) of TFT 23 is supplied to the signal line sig(x).

[0120] TFT601 and TFT602 are oxide semiconductor TFTs, similar to TFT23. The lower gates 242 of TFT601 and 243 of TFT602 are connected to the potential line 24, similar to the lower gate 241 of TFT23, and the lower gate potential VGL2 is applied.

[0121] In Embodiment 2, as shown in Figure 14, the output holding unit 11 of Embodiment 1 is replaced by the output holding unit 11A. In addition to the wiring connected to the output holding unit 11, the output holding unit 11A has additional wiring for individually supplying the signals IREF1, CDS_VREF, HOLD, xHOLD, and ASWBIAS, respectively, as wiring for inputting control signals. The output holding unit 11A has a register that holds the signal OP1, and its general function is the same as that of the output holding unit 11 in that it holds the signal OP1 transmitted from the photodetector 2 via the signal line Sig and supplies it to the input line Ccds.

[0122] Figures 16 and 17 are plan views of the laminated structure included in the circuit configuration shown in Figure 15. The reset line Rs(y) shown in Figure 16 is composed of the electrode layer GL2, similar to the scan line Rd(y). The upper gate 236 of the TFT 602 is also composed of the electrode layer GL2. In the configuration shown in Figure 16, the connection portion 235, which was described with reference to Figures 5 and 7, is replaced by the connection portion 2351. The connection portion 2351 is the same as the connection portion 235, except that the connection targets are either the source or drain of the TFT 601 and the upper gate 236 of the TFT 602. The connection portion 2351 and the upper gate 236 are connected via a contact hole 2901. The contact hole 2901 is a contact hole that penetrates the insulating layer PAS in the third direction Dz.

[0123] Furthermore, wiring 25 and wiring 26 are composed of electrode layer SL, similar to the signal line Sig(x). Also, lower gates 242 and 243 are composed of electrode layer GL1, similar to lower gate 241. In addition, the connection part 2401, which connects wiring 25 to the other source or drain of TFT 601 across wiring 26, is composed of electrode layer GL1. The connection part 2401 is connected to the other source or drain of TFT 601 and wiring 25 via contact hole 2920. Contact hole 2920 is a contact hole provided to connect electrode layer GL1 and electrode layer SL, similar to contact hole 292. Also, lower gate 242 is connected to potential line 24 via contact hole 2920. Furthermore, the semiconductors connecting the source and drain in TFT 601 and TFT 602 are composed of a semiconductor layer OS, similar to the oxide semiconductor 232 of TFT 23, and are connected to the respective source and drain via contact holes similar to the contact hole 291.

[0124] The reset line Rs(y) is positioned on one end Dy1 side of the connection part 2351 and is a wiring that runs along the first direction Dx. In Embodiment 2, the width of the reset line Rs(y) in the second direction Dy is D21, except for the area that overlaps with the signal line Sig(x) in a plan view and its vicinity. Of the reset line Rs(y), the width of the second direction Dy in the area that overlaps with the signal line Sig(x) in a plan view and its vicinity is D22. Width D22 is smaller than width D21. The upper gate 237 of the TFT 601 extends from the reset line Rs(y) along the second direction Dy. The signal line Sig(x), connection part 2351, wiring 26, wiring 25, and potential line 24 are arranged in that order from one end Dx1 side to the other end Dx2 side. The TFT 601 is located between the connection part 2351 and the wiring 26.

[0125] Wirings 25 and 26 are wires that align with the second direction Dy. The width of wiring 25 in the first direction Dx is width D23. The width of wiring 25 in the first direction Dx is width D24. Widths D23 and D24 are greater than width D21. The connection part 261 that connects wiring 26 to the drain of TFT 602 aligns with the first direction Dx. The width of the connection part 261 in the second direction Dy is width D25. Width D25 is less than width D24.

[0126] TFT 602 is positioned on the other end Dy2 side of the connection portion 2351 and on the other end Dx2 side of TFT 23. In Embodiment 2, TFT 602 has a configuration in which two semiconductor layers are arranged side by side in the second direction Dy, and is substantially composed of oxide semiconductor TFTs equivalent to two TFTs 23. The upper gate 236 is provided along the second direction Dy so as to cover the semiconductors of the two oxide semiconductor TFTs. The source of TFT 602 on the other end Dy2 side overlaps with either the source or drain of TFT 23 in a planar view. That is, the source of TFT 602 on the other end Dy2 side and either the source or drain of TFT 23 are shared.

[0127] The lower gate 241 of Embodiment 2 differs from the lower gate 241 of Embodiment 1 in that, near the point where it overlaps with the other end Dy2 side of the upper gate 231 in a plan view, a portion along the second direction Dy and a portion along the first direction Dx are connected in a continuous manner. The lower gate 243 is arranged so as to overlap with the upper gate 236 and the semiconductor layer of the TFT 602 in a plan view. The lower gate 243 is aligned with the second direction Dy. The lower gate 243 is continuous with a portion of the lower gate 241 along the first direction Dx on the other end Dy2 side.

[0128] In Embodiment 2, the width of the lower gate 243 that overlaps with the upper gate 236 in a plan view is greater than the width of the upper gate 236 in a plan view in a first direction Dx. Specifically, the lower gate 243 has a width that is greater than the upper gate 236 by a width D201 on one end Dx1 side and the other end Dx2 side in a plan view.

[0129] The lower gate 242 is positioned so as to overlap with a portion of the upper gate 237 and the semiconductor of the TFT 601 in a planar view. The portion of the lower gate 242 that overlaps with the upper gate 237 is aligned with the second direction Dy. The other portion of the lower gate 242 that is connected to the potential line 24 via the contact hole 2920 is aligned with the first direction Dx. Near the position where the lower gate 242 overlaps with the other end Dy2 side of the upper gate 236 in a planar view, the portion aligned with the second direction Dy and the portion aligned with the first direction Dx are connected in a continuous manner.

[0130] In Embodiment 2, the width of a portion of the lower gate 242 that overlaps with the upper gate 237 in a plan view is greater than the width of the upper gate 237 in a first direction Dx. Specifically, the lower gate 242 has a width that is D202 greater than the upper gate 237 on one end Dx1 side and the other end Dx2 side in a plan view.

[0131] Width D201 is, for example, 1.4 μm. Width D202 is, for example, 2 μm. Widths D21 and D25 are, for example, 4 μm. Width D22 is, for example, 3 μm. Widths D23 and D24 are, for example, 9 μm.

[0132] Furthermore, in Embodiment 2, the width of the first direction Dx of the signal line Sig(x) and potential line 24 is D4, not only in the range and vicinity of the overlap with the scan line Rd(y) in a planar view, but also in the range and vicinity of the overlap with the reset line Rs(y).

[0133] Furthermore, not limited to TFT23, the TFT mounted on the substrate 10 in Embodiment 2 is an oxide semiconductor TFT similar to TFT23 and has a TFT portion 500 (see Figure 7).

[0134] TFT 601 is provided with a width of approximately 3 μm in the first direction Dx and approximately 3 μm in the second direction Dy. TFT 602 has a configuration in which two oxide semiconductor TFTs are aligned in the second direction Dy, and each TFT is provided with a width of approximately 15 μm in the first direction Dx and approximately 3 μm in the second direction Dy. In addition, the distance between the two oxide semiconductor TFTs in TFT 602 in the second direction Dy is approximately 4 μm.

[0135] In Embodiment 2, TFT 601 and TFT 602 are oxide semiconductor TFTs similar to TFT 23, and have a TFT portion 500 (see Figure 7). Except for the features noted above, Embodiment 2 is the same as Embodiment 1. Embodiment 2 can achieve the same effects as Embodiment 1.

[0136] (Modification of Embodiment 2) Next, a modification of Embodiment 1 will be described with reference to Figures 18 and 19. Figure 18 is a diagram showing the circuit configuration of the optical sensor LS in a modification of Embodiment 2. Figure 19 is a diagram showing an example of the connection configuration between the lower gates 241, 242, and 243 formed in the modification of Embodiment 2 and other configurations connected to each of these configurations.

[0137] As shown in Figures 18 and 19, in the modified embodiment of Embodiment 2, the potential line 24 that was provided in Embodiment 2 is not provided. That is, in the modified embodiment of Embodiment 2, there is no configuration for transmitting the lower gate potential VGL2 to the lower gates 241, 242, and 243. In the modified embodiment of Embodiment 2, the same potential as the upper gate 231 is applied to the lower gate 241. That is, in the modified embodiment of Embodiment 1, the drive signal Vgate is applied to the lower gate 241.

[0138] Furthermore, in the modified embodiment of the second embodiment, the lower gate 242 is given the same potential as the upper gate 237. That is, in the modified embodiment of the second embodiment, a reset signal RS is given to the lower gate 242.

[0139] Furthermore, in the modified embodiment of the second embodiment, the lower gate 243 is given the same potential as the upper gate 236. That is, in the modified embodiment of the second embodiment, the charge stored in the capacitor 22 is given to the lower gate 243.

[0140] Specifically, in the modified embodiment of Embodiment 2, a connecting structure 750 for connecting the lower gate 241 and the upper gate 231 is provided, similar to the modified embodiment of Embodiment 1. In addition, in the modified embodiment of Embodiment 2, a connecting structure 760 for connecting the lower gate 242 and the upper gate 237 is provided.

[0141] The connection structure 760 includes a connection portion 761, a contact hole 762, and a contact hole 763. The connection portion 761 is made of the electrode layer SL. The contact hole 762 is a contact hole through which the connection portion 761 is connected to the base of the upper gate 237 near the reset line Rs(y). The contact hole 762 is a contact hole that penetrates the insulating layer PAS. The contact hole 763 is a contact hole through which the connection portion 761 is connected to the lower gate 241. Similar to the contact hole 292, the contact hole 763 is a contact hole provided to connect the electrode layer GL1 and the electrode layer SL. The connection portion 761 overlaps with the upper gate 237 near the base of the upper gate 237 near the reset line Rs(y), and another portion extends from this overlapping portion toward the other end Dx2. In the modified embodiment of Embodiment 2, the lower gate 242 extends to the base of the upper gate 237 near the reset line Rs(y) and has an inverted L-shape that overlaps with the connection portion 761 in a plan view. Note that the potential line 24 is absent in the modified embodiment of Embodiment 2. Accordingly, the extension portion of the lower gate 242 in the second direction Dy that was connected to the potential line 24 in Embodiment 2 (another part of the lower gate 242) is omitted in the modified embodiment of Embodiment 2. For this reason, in the modified embodiment of Embodiment 2, the other end of the upper gate 237 on the Dy2 side extends from the lower gate 242 in a plan view.

[0142] Furthermore, in the modified embodiment of Embodiment 2, a contact hole 770 is provided for connecting the lower gate 243 and the connecting portion 2351. The contact hole 770, like the contact hole 292, is a contact hole provided to connect the electrode layer GL1 and the electrode layer SL. In the modified embodiment of Embodiment 2, the lower gate 243 extends in the second direction Dy to a position that overlaps with the contact hole 770 in a plan view. Note that the potential line 24 is absent in the modified embodiment of Embodiment 2. Accordingly, a portion of the lower gate 243 near where it was connected to the lower gate 241 in Embodiment 2 is omitted in the modified embodiment of Embodiment 2. For this reason, in the modified embodiment of Embodiment 2, the other end Dy2 side of the upper gate 236 extends from the lower gate 243 in a plan view. Except for the matters specifically noted above, the modified embodiment of Embodiment 2 is the same as Embodiment 2. The modified embodiment of Embodiment 2 can achieve the same effects as Embodiment 2.

[0143] (Embodiment 3) Hereinafter, Embodiment 3, which differs in some configuration from Embodiment 2, will be described with reference to Figures 20 to 23. In the description of Embodiment 3, the same reference numerals will be used for components similar to those in Embodiment 2, and their descriptions may be omitted.

[0144] Figure 20 shows the signals input to the photodetector 2B, gate driver 3B, and multiplexer 4, the signals output from the photodetector 2B, gate driver 3B, and multiplexer 4, and the connections of the wiring that transmits these signals in Embodiment 3. In Embodiment 3, the gate driver 3A of Embodiment 2 is replaced by the gate driver 3B. The gate driver 3B has a first circuit 301, a second circuit 302, and a third circuit 303. The first circuit 301 has the same configuration as the first circuit 301 in Embodiment 2. The second circuit 302 has the same configuration as the second circuit 302 in Embodiment 2. In Figure 20, the reset line Rs is shown as a single line, but the reset line Rs in Embodiment 3 also includes V wires, such as reset lines Rs1, Rs2, ..., RsV, similar to Embodiment 2. The multiple light sensors LS (see Figure 21) provided in the light detection unit 2B of Embodiment 3 are connected to the second circuit 302 via a reset line Rs, similar to Embodiment 2.

[0145] The third circuit 303 is a shift register circuit that outputs an output command signal PD for controlling the on / off state of the TFT 603 (see Figure 21) connected to the optical sensor LS of Embodiment 3. The multiple optical sensors LS provided in the optical detection unit 2B of Embodiment 3 are connected to the third circuit 303 via the output command signal line Rp, as shown in Figure 20. The output command signal line Rp includes V wires, such as output command signal lines Rp1, Rp2, ..., RpV.

[0146] In Embodiment 3, the strength of the output of the optical sensor LS is reflected in the output of the output OP1, which is lowered by the gate-source voltage (Vth) of the TFT 602. At this time, the current is supplied to the output from the output power supply potential PVDD. In these respects, it is the same as Embodiment 2. That is, the optical detection unit 2B in Embodiment 3 functions as an APS, similar to the optical detection unit 2A in Embodiment 2. However, the order in which the signal that causes the output fluctuation is given to the signal line Sig(x) differs between Embodiment 3 and Embodiment 2. Specifically, in Embodiment 3, first, the reset signal RST is given to the TFT 601, which resets the optical sensor LS and the signal line Sig(x) to the reset potential VREF. Then, the output command signal PD is given to the TFT 603, which gives the signal OP1 corresponding to the strength of the output of the optical sensor LS to the signal line Sig(x). As a result, an output fluctuation from the reset potential VREF to the signal OP1 occurs in the signal line Sig(x). In Embodiment 3, the intensity of light detected by the optical sensor LS is determined based on the degree of output fluctuation.

[0147] Figure 21 is a diagram showing the circuit configuration of the photodetector LS provided in the photodetector 2B. As shown in Figure 20, in Embodiment 3, the photodetector 2A of Embodiment 2 is replaced by the photodetector 2B. The photodetector LS provided in the photodetector 2B has a photodiode 21 and a capacitor 22, similar to the photodetector LS of Embodiments 1 and 2. The anode of the photodiode 21 in Embodiment 3 is connected to the wiring to which the potential PVSS2 is supplied, similar to Embodiments 1 and 2. On the other hand, the cathode of the photodiode 21 in Embodiment 3 is connected to either the source or the drain of the TFT 603. The capacitor 22 in Embodiment 3 is electrically in parallel with the photodiode 21, similar to Embodiments 1 and 2. Therefore, when shown in the circuit diagram, the capacitor 22 can be considered to be connected to the wiring and either the source or the drain of the TFT 603.

[0148] TFT 603, like TFT 23, is an oxide semiconductor TFT. The lower gate 244 of TFT 603, like the lower gate 241 of TFT 23, is connected to the potential line 24, and the lower gate potential VGL2 is applied. The other end of the source or drain of TFT 603 is connected to one end of the source or drain of TFT 601, the upper gate 236 of TFT 602, and the conductor portion 802. Based on the "connection relationship between the optical sensor LS and TFT 601 and TFT 602" in Embodiment 2, TFT 603 is provided so as to be interposed between the optical sensor LS and TFT 601 and TFT 602 in Embodiment 2.

[0149] Furthermore, as shown in Figure 21, the photodetector 2B of Embodiment 3 is provided with a capacitor 800. The capacitor 800 functions as a charge-storing capacitor. As shown in Figure 21, the capacitor 800 is connected to the wiring via a conductor portion 801. The capacitor 800 is also connected via a conductor portion 802 to the other source or drain of the TFT 603, one source or drain of the TFT 601, and the upper gate 236 of the TFT 602. Therefore, when the TFT 603 is turned on, the charge from the current flowing from the source or drain of the photosensor LS is stored in the capacitor 800 via the conductor portion 802. A voltage corresponding to the charge stored in the capacitor 800 is applied to the upper gate 236 of the TFT 602. Thus, Embodiment 3 is similar to Embodiment 2 in that the potential corresponding to the charge stored in the capacitance 22 is used to determine the source potential of the TFT 602, but it differs from Embodiment 2 in that a charge-storing capacitor 800 is provided. Furthermore, Embodiment 3 differs from Embodiment 2 in that it includes the TFT 603.

[0150] Figures 22 and 23 are plan views of the laminated structure included in the circuit configuration shown in Figure 21. The capacitor 800 is configured to store charge by stacking a conductor portion 801 and a conductor portion 802 facing each other in the third direction Dz. The conductor portion 801 is composed of an electrode layer GL2. The conductor portion 802 is composed of an electrode layer SL. The capacitor 800 is positioned on one end Dy1 side of the TFT 23. A connection portion 8010 extends from the conductor portion 801 along the first direction Dx to the other end Dx2 side and is connected to the wiring 26 via a contact hole 2909. The contact hole 2909 is a contact hole that penetrates the insulating layer PAS in the third direction Dz. The connection portion 8010 is composed of an electrode layer GL2, similar to the conductor portion 801. From the conductor portion 802, a connection portion 8020 extends toward the other end Dy2 along the second direction Dy and is connected to the upper gate 236 of the TFT 602 via the contact hole 2905.

[0151] In Embodiment 3, the upper gate 236 of the TFT 602 is divided into a first gate 2361 and a second gate 2362, forming a so-called double gate structure. The first gate 2361 is positioned relatively on one end Dy1 side, and the second gate 2362 is positioned relatively on the other end Dy2 side. The first gate 2361 is aligned in the first direction Dx. The second gate 2362 has a portion that overlaps with the semiconductor of the TFT 602 and is aligned in the first direction Dx, and another portion that is aligned in the second direction Dy and is continuous with the first portion at one end on the other end Dy2 side. One end of the first gate 2361 on the Dx1 side and the end of the other portion of the second gate 2362 on the Dy1 side are continuous. The contact hole 2905 is provided at a position that overlaps with one end of the first gate 2361 on the Dx1 side and the end of the other portion of the second gate 2362 on the Dy1 side. The contact hole 2905 is connected via a contact hole that penetrates the insulating layer PAS in the third direction Dz.

[0152] Furthermore, in Embodiment 3, a connecting portion 2391 extending from the semiconductor layer of the TFT 602 along the first direction Dx toward the other end Dx2 is connected to the wiring 26 via a contact hole 2960. The contact hole 2960, like the contact hole 291, is a contact hole provided to connect the semiconductor layer OS and the electrode layer SL.

[0153] Furthermore, in Embodiment 3, the connection portion 2352, where the contact hole 293 is provided, is located on the other end Dx2 side of the capacitor 800. A TFT 603 is placed between the capacitor 800 and the connection portion 2352. One of the sources or drains of the TFT 603 is connected to the optical sensor LS by being connected to the connection portion 2352. The other of the sources or drains of the TFT 603 is continuous with the conductor portion 802. In the area where the conductor portion 802 is located in a plan view, there is no conductor portion 801 in a portion that overlaps with the contact hole in the plan view for the connection of the TFT 603 to the semiconductor. Also, as shown in Figure 22, the conductor portion 802 is continuous with one of the sources or drains of the TFT 601.

[0154] The lower gate 244 of the TFT 603 is continuous with another portion of the lower gate 242 along the first direction Dx. The upper gate 234 of the TFT 603 is connected to the output command signal line Rp(y). The output command signal line Rp(y) is one of the output command signal lines Rp1, Rp2, ..., RpV. The output command signal line Rp(y) is composed of electrode layer GL1. On the other hand, the upper gate 234 is composed of electrode layer GL2. The connection between the output command signal line Rp(y) and the upper gate 234 is made via a connection structure 703. The connection structure 703 includes a connection portion 2943, a contact hole 2953, and a contact hole 2904. The connection portion 2943 is composed of electrode layer SL. The contact hole 2953 is the contact hole through which the connection between the connection portion 2943 and the output command signal line Rp(y) is made. The contact hole 2904 is a contact hole through which the connection portion 2943 and the upper gate 234 are connected.

[0155] The output command signal line Rp(y) is located between capacitor 800 and TFT 602 in the second direction Dy. The output command signal line Rp(y) is aligned with the first direction Dx. The width of the output command signal line Rpy in the second direction Dy is D31, except for the area overlapping with signal line Sig(x) in a planar view and its vicinity. The width of the output command signal line Rp(y) in the area overlapping with signal line Sig(x) in a planar view and its vicinity in the second direction Dy is D32. Width D32 is smaller than width D31.

[0156] Furthermore, the width of the lower gate 244, which overlaps with the upper gate 234 in a plan view, in the first direction Dx is greater than the width of the upper gate 234 in the first direction Dx. Specifically, the relationship between the upper gate 234 and the lower gate 244 with respect to the width of the first direction Dx is the same as the relationship between the upper gate 237 and the lower gate 242 with respect to the width of the first direction Dx. That is, the lower gate 244 has a width that is greater than the upper gate 234 by a width D202 (see Figure 16) on one end Dx1 side and the other end Dx2 side in a plan view.

[0157] Furthermore, the reset wire Rs(y) in Embodiment 3 is composed of the electrode layer GL1. Therefore, in Embodiment 3, a connection structure 701 is provided for connecting the reset wire Rs(y) and the upper gate 237. The connection structure 701 includes a connection portion 2946, a contact hole 2951, and a contact hole 2902. The connection portion 2946 is composed of the electrode layer SL. The contact hole 2951 is a contact hole through which the connection portion 2946 and the reset wire Rs(y) are connected. The contact hole 2902 is a contact hole through which the connection portion 2946 and the upper gate 237 are connected.

[0158] Furthermore, the scan line Rd(y) in Embodiment 3 is composed of the electrode layer GL1. For this reason, Embodiment 3 is provided with a connection structure 702 for connecting the scan line Rd(y) and the upper gate 231. The connection structure 702 includes a connection portion 2947, a contact hole 2952, and a contact hole 2903. The connection portion 2947 is composed of the electrode layer SL. The contact hole 2952 is a contact hole through which the connection portion 2947 and the scan line Rd(y) are connected. The contact hole 2903 is a contact hole through which the connection portion 2947 and the upper gate 231 are connected.

[0159] Furthermore, in this embodiment, due to the provision of the capacitor 800, the position of the contact hole 293 is shifted towards the other end Dx2 side compared to embodiments 1 and 2, as shown in Figures 22 and 23. Consequently, the shape of the photodetector 280 and electrode layer UIO in a planar view is slightly different in embodiment 3 compared to embodiments 1 and 2. Specifically, in embodiment 3, the photodetector 280 and electrode layer UIO extend to the area where they were not provided diagonally opposite the contact hole 294 in embodiments 1 and 2. Also, in embodiment 3, the arrangement of the drainage holes 271 is the same as in embodiments 1 and 2. However, because the area in which the photodetector 280 and electrode layer UIO are provided is wider than in embodiments 1 and 2, the drainage holes 271 are located within the area in which the photodetector 280 and electrode layer UIO are provided.

[0160] In Embodiment 2, the width of the first direction Dx of the signal line Sig(x) and potential line 24 is D4, not only in the range and vicinity of the range that overlaps with either the scan line Rd(y) or the reset line Rs(y) in a planar view, but also in the range and vicinity of the range that overlaps with the output command signal line Rp(y).

[0161] The width D31 is, for example, 4 μm. The width D32 is, for example, 3 μm. The TFT603 is provided such that it is approximately 3 μm in the first direction Dx and approximately 3 μm in the second direction Dy.

[0162] In Embodiment 3, TFT 603 is an oxide semiconductor TFT similar to TFT 23, and has a TFT portion 500 (see Figure 7). Except for the features noted above, Embodiment 3 is the same as Embodiment 2.

[0163] Figure 24 is a cross-sectional view taken along line XXII-XXII of Figure 22. As shown in Figure 24, the capacitor 800 has an electrode layer GL2, an electrode layer SL, and an electrode layer LE overlapping. The electrode layer GL2 shown in Figure 24 is the conductor portion 801 described with reference to Figure 22. The electrode layer SL shown in Figure 24 is the conductor portion 802 described with reference to Figure 22. In other words, the capacitor 800 not only forms capacitance between the electrode layer GL2, which is the conductor portion 801, and the electrode layer SL, which is the conductor portion 802, but also forms capacitance between the electrode layer SL and the electrode layer LE.

[0164] Furthermore, electrode layer GL2 is formed between insulating layer GI and insulating layer PAS. Also, electrode layer SL is formed between insulating layer PAS and insulating layer IL1. Therefore, in embodiment 3, capacitance is formed by the electrode between insulating layer GI and insulating layer PAS (electrode layer GL2) and the electrode between insulating layer PAS and insulating layer IL1 (electrode layer SL).

[0165] According to Embodiment 3, the same effects as in Embodiment 1 can be achieved. Furthermore, a capacitance (e.g., capacitor 800) for the charge obtained from the photodiode (e.g., light sensor LS) is formed by an electrode (e.g., conductor portion 801) made of a second conductive film (e.g., electrode layer GL2) and an electrode (e.g., conductor portion 802) made of a third conductive film (e.g., electrode layer SL). This allows for more flexible output control of the photodiode (e.g., light sensor LS).

[0166] (Modification of Embodiment 3) Next, a modification of Embodiment 1 will be described with reference to Figures 25 and 26. Figure 25 is a diagram showing the circuit configuration of the optical sensor LS in the modification of Embodiment 3. Figure 26 is a diagram showing an example of the connection configuration between the lower gates 241, 242, 2431, 2432, and 244 formed in the modification of Embodiment 3 and other configurations connected to each of these configurations.

[0167] As shown in Figures 25 and 26, in the modified embodiment of Embodiment 3, the potential line 24 that was provided in Embodiment 3 is not provided. That is, in the modified embodiment of Embodiment 3, there is no configuration for transmitting the lower gate potential VGL2 to the lower gates 241, 242, 2431, 2432, and 244. In the modified embodiment of Embodiment 3, the same potential as the upper gate 231 is applied to the lower gate 241. That is, in the modified embodiment of Embodiment 1, the drive signal Vgate is applied to the lower gate 241.

[0168] Furthermore, in the modified embodiment of Embodiment 3, the lower gate 242 is given the same potential as the upper gate 237. That is, in the modified embodiment of Embodiment 3, a reset signal RS is given to the lower gate 242.

[0169] Furthermore, in the modified embodiment of Embodiment 3, the lower gates 2431 and 2432 are given the same potential as the first gate 2361 and the second gate 2362. That is, in the modified embodiment of Embodiment 3, the charge stored in the capacitor 22 is given to the lower gate 243.

[0170] Furthermore, in the modified embodiment of Embodiment 3, the lower gate 244 is supplied with the same potential as the upper gate 234. That is, in the modified embodiment of Embodiment 3, the output command signal PD is supplied to the lower gate 244.

[0171] Specifically, in the modified embodiment of Embodiment 3, the lower gate 241 is continuous with the scan line Rd(y). Therefore, as shown in Figure 26, the lower gate 241 in the modified embodiment of Embodiment 3 extends further toward the other end Dy2 in a plan view compared to Embodiment 3. Also, in the modified embodiment of Embodiment 3, the lower gate 242 is continuous with the reset line Rs(y). Therefore, as shown in Figure 26, the lower gate 242 in the modified embodiment of Embodiment 3 extends further toward the one end Dy1 in a plan view compared to Embodiment 3.

[0172] Furthermore, in a modified example of Embodiment 3, the first gate 2361 extends toward one end Dx1 to a position where it overlaps with the connection portion 8010 in a plan view. Also, the first gate 2361 and the second gate 2362 are continuous at a position where they overlap with the connection portion 8010 in a plan view. In addition, in a modified example of Embodiment 3, the contact hole 2905 in Embodiment 3 is replaced by a contact hole 2915. The contact hole 2915 is a contact hole for connecting the electrode layer SL, the electrode layer GL2, and the electrode layer GL1, and includes a first contact hole and a second contact hole. More specifically, the electrode layer GL2 and the electrode layer GL1 are connected by forming a first contact hole that penetrates the insulating layer UC and the insulating layer GI before the formation of the electrode layer GL2. Furthermore, the electrode layer SL and the electrode layer GL2 are connected by forming a second contact hole that penetrates the insulating layer PAS which is laminated after the formation of the electrode layer GL2.

[0173] Furthermore, in the modified embodiment of Embodiment 3, the lower gate 244 is continuous with the output command signal line Rp(y). Therefore, as shown in Figure 26, the lower gate 244 in the modified embodiment of Embodiment 3 extends further toward the other end Dy2 in a plan view compared to Embodiment 3. Note that the modified embodiment of Embodiment 3 does not have a potential line 24. Accordingly, a portion of the lower gates 241, 242, 2431, 2432, and 244 in Embodiment 2 that extended toward the potential line 24 along the first direction Dx is omitted in the modified embodiment of Embodiment 3. Also, in the modified embodiment of Embodiment 3, the ends of the upper gates 231, 234, and 237 extend from the lower gate in a plan view. Except for the points mentioned above, the modified embodiment of Embodiment 3 is the same as Embodiment 3. The modified embodiment of Embodiment 3 can achieve the same effects as Embodiment 3.

[0174] The numerical values ​​exemplified above as the widths for the first direction Dx and the second direction Dy are merely examples and are not limited to these values; they can be changed as appropriate.

[0175] Furthermore, any other effects and advantages brought about by the embodiments described herein that are obvious from this specification or that can be appropriately conceived by those skilled in the art are naturally provided by this disclosure.

[0176] 1. Detection device 92 Pads 23, 601, 602, 603 TFTs 231, 234, 236, 237 Upper gate 232 Oxide semiconductor 241, 242, 243, 244 Lower gate BIS, GL1, GL2, LE, SL, PIO, UIO Electrode layer GI, IL1, IL2, IL3, PAS Insulating layer OC1, OC2, OC3 Planarization film OS Semiconductor layer

Claims

1. A detection device comprising a photodetector provided with a photodiode, and a scintillator provided on the photodetector side of the photodetector, wherein the thin-film transistor provided in the photodetector has an upper gate and a lower gate, the upper gate and the lower gate face each other across the oxide semiconductor of the thin-film transistor, and the layers are stacked in the following order from a configuration relatively farther from the scintillator to a configuration relatively closer to the scintillator: a first conductive film constituting the lower gate, a first inorganic film, a semiconductor layer constituting the oxide semiconductor, a second inorganic film, a second conductive film constituting the upper gate, a third inorganic film, a third conductive film constituting the source and drain connected to the oxide semiconductor, a fourth inorganic film, a first organic film, a multilayer structure constituting the photodiode, a second organic film, a fifth inorganic film, and a third organic film, in that order, and either the source or the drain is connected to the oxide semiconductor via a first through-hole penetrating the second inorganic film and the third inorganic film, and is connected to the first electrode of the photodiode via a second through-hole penetrating the fourth inorganic film and the first organic film. A detection device in which the fourth inorganic film covers the first electrode and a portion of the second electrode of the photodiode, a translucent fourth conductive film is formed in the opening of the second electrode that is not covered by the fourth inorganic film, and a non-translucent electrode is connected to the fourth conductive film.

2. The detection device according to claim 1, wherein the first organic membrane has lower moisture permeability than the second organic membrane and the third organic membrane.

3. The detection device according to claim 1 or 2, wherein the second organic film and the third organic film have higher light transmittance than the first organic film.

4. The detection device according to claim 1 or 2, wherein the capacitance of the charge obtained from the photodiode is formed by an electrode composed of the second conductive film and an electrode composed of the third conductive film.

5. The detection device according to claim 1 or 2, wherein the pad of the substrate on which the light detection unit is formed has the second conductive film, the third conductive film, a conductive film in the same layer as the first electrode, a conductive film in the same layer as the non-transparent electrode, and the fourth conductive film.

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