Advanced back-end wire automated process control system for smart chip factory

Abstract

The present disclosure relates to the technical field of chips. Provided is an advanced back-end wire automated process control system for a smart chip factory. The system comprises: an insulating layer deposition component, an insulating layer chemical mechanical polishing component, an anti-reflection coating and photoresist applying component, a lithography component, an etching component, a barrier layer deposition component, an electroplating component, an electroplated layer chemical mechanical polishing component, and a cobalt cap layer atomic layer deposition component. Parameters of each component are predicted by means of virtual metrology, thereby assisting in process control.

Description

Advanced Back-End Automated Manufacturing Control System for Smart Chip Factories

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese patent application No. 202411791023.9, filed on December 5, 2024, entitled "Automatic Process Control System for Advanced Back-End Wires in Intelligent Chip Factory", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of chip technology, and in particular to an advanced back-end wire automated process control system for intelligent chip factories. Background Technology

[0004] The automatic process control in related technologies does not use advanced virtual measurement systems, resulting in excessively erroneous prediction data and causing inaccurate automatic process control. Some calculations are based solely on SPC (Statistical Process Control) data and lack real-time data, leading to deviations due to insufficient sampling measurement data.

[0005] Public content

[0006] This disclosure aims to at least partially address one of the technical problems in the related art. To this end, the first objective of this disclosure is to propose an automated back-end wiring process control system for an intelligent chip factory. The system includes: an insulating layer deposition unit for depositing an insulating layer on a wafer based on insulating layer deposition parameters determined by virtual measurement; an insulating layer chemical mechanical polishing (CMP) unit for performing CMP polishing on the wafer after deposition based on the insulating layer deposition thickness determined by virtual measurement, the insulating layer deposition thickness before polishing, and the CMP polishing parameters determined by virtual measurement; an anti-reflective coating and photoresist coating unit for applying an anti-reflective coating and photoresist to the wafer after CMP polishing based on the insulating layer deposition thickness after polishing and the anti-reflective coating and photoresist coating parameters determined by virtual measurement; a photolithography unit for performing photolithography on the wafer after anti-reflective coating and photoresist coating; and an etching unit. The system comprises the following components: a etcher for etching the photolithographically etched wafer based on the thicknesses of the anti-reflective coating and photoresist after virtual measurement, the thickness of the insulating layer after grinding determined by virtual measurement, and the etching parameters determined by virtual measurement; a barrier layer deposition component for depositing a barrier layer on the etched wafer based on the barrier layer deposition parameters determined by virtual measurement; an electroplating component for electroplating the wafer after barrier layer deposition based on the electroplating parameters determined by virtual measurement; an electroplating layer chemical mechanical polishing component for performing electroplating layer chemical mechanical polishing on the electroplated wafer based on the electroplating layer thickness, the electroplating layer grinding thickness determined by virtual measurement, and the critical dimensions after etching determined by virtual measurement; and a cobalt cap layer atomic layer deposition component for depositing a cobalt cap layer atomic layer on the wafer after electroplating layer chemical mechanical polishing to obtain the corresponding chip.

[0007] To achieve the above objectives, the first aspect of this disclosure proposes an automated process control system for advanced back-end wiring in an intelligent chip factory. The system includes: an insulating layer deposition unit for depositing an insulating layer on a wafer based on insulating layer deposition parameters determined by virtual measurement; an insulating layer chemical mechanical polishing (CMP) unit for performing CMP polishing on the deposited wafer based on the insulating layer deposition thickness determined by virtual measurement, the insulating layer deposition thickness before polishing, and the CMP polishing parameters determined by virtual measurement; an anti-reflective coating and photoresist coating unit for applying an anti-reflective coating and photoresist to the CMP-polished wafer based on the polished insulating layer deposition thickness and the anti-reflective coating and photoresist coating parameters determined by virtual measurement; and a photolithography unit for performing photolithography on the wafer after anti-reflective coating and photoresist coating. The wafer is etched using virtual measurements of the thickness of the anti-reflective coating and photoresist after coating, the thickness of the insulating layer after grinding after grinding, and the etching parameters determined by virtual measurements. A barrier layer deposition component deposits a barrier layer on the etched wafer using the deposition parameters determined by virtual measurements. An electroplating component electroplats the wafer after barrier layer deposition using the electroplating parameters determined by virtual measurements. An electroplating layer chemical mechanical polishing (CMP) component performs CMP polishing on the electroplated wafer using the electroplating layer thickness, the electroplating layer grinding thickness, and the critical dimensions after etching determined by virtual measurements. A cobalt cap layer atomic layer deposition component deposits a cobalt cap layer atomic layer on the electroplated wafer after CMP polishing to obtain the corresponding chip.

[0008] According to one embodiment of this disclosure, a deposition correspondence is determined based on the operating parameters of the insulating layer deposition component and a preset virtual measurement AI model. Insulating layer deposition parameters are determined based on the target insulating layer deposition thickness and the insulating layer deposition correspondence. The insulating layer deposition parameters include insulating layer deposition time and insulating layer deposition rate. The insulating layer deposition correspondence is used to characterize the correspondence between insulating layer deposition time, insulating layer deposition rate, and insulating layer deposition thickness. The insulating layer deposition thickness is determined based on the insulating layer deposition time and insulating layer deposition rate.

[0009] According to one embodiment of this disclosure, the chemical mechanical polishing (CMP) correspondence of the insulating layer is determined based on the operating parameters of the insulating layer CMP component and a preset virtual measurement AI model. The CMP parameters of the insulating layer are determined based on the target CMP thickness and the CMP correspondence. The CMP parameters include the CMP time and CMP rate. The CMP correspondence is used to characterize the relationship between the CMP time, CMP rate, and CMP thickness. The thickness of the insulating layer deposited after polishing is determined based on the CMP time and CMP rate.

[0010] According to one embodiment of this disclosure, a coating correspondence is determined based on the operating parameters of the anti-reflective coating and photoresist coating components and a preset virtual measurement AI model. The coating parameters of the anti-reflective coating and photoresist are determined based on the target coating thickness and the coating correspondence. The coating parameters of the anti-reflective coating and photoresist include coating time and coating rate. The coating correspondence is used to characterize the correspondence between coating time, coating rate and coating thickness. The coating thickness is determined based on the coating time and coating rate.

[0011] According to one embodiment of this disclosure, the etching correspondence is determined based on the operating parameters of the etching component and a preset virtual measurement AI model, and the etching parameters are determined based on the target etching critical dimension and the etching correspondence. The etching parameters include etching time and etching rate, and the etching correspondence is used to characterize the correspondence between etching time, etching rate and the critical dimension after etching. The critical dimension after etching is determined based on the etching time and etching rate.

[0012] According to one embodiment of this disclosure, the barrier layer deposition correspondence is determined based on the operating parameters of the barrier layer deposition component and a preset virtual measurement AI model. The barrier layer deposition parameters are determined based on the target barrier layer deposition thickness and the barrier layer deposition correspondence. The barrier layer deposition parameters include barrier layer deposition time and barrier layer deposition rate. The barrier layer deposition correspondence is used to characterize the correspondence between barrier layer deposition time, barrier layer deposition rate, and barrier layer deposition thickness. The barrier layer deposition thickness is determined based on the barrier layer deposition time and barrier layer deposition rate.

[0013] According to one embodiment of this disclosure, an electroplating correspondence is determined based on the operating parameters of the electroplated component and a preset virtual measurement AI model. Electroplating parameters are determined based on the target electroplating layer thickness and the electroplating correspondence. The electroplating parameters include electroplating time and electroplating rate. The electroplating correspondence is used to characterize the correspondence between electroplating time, electroplating rate, and electroplating layer thickness. The electroplating layer thickness is determined based on the electroplating time and electroplating rate.

[0014] According to one embodiment of this disclosure, the electroplating layer chemical mechanical polishing (CMP) correspondence is determined based on the operating parameters of the electroplating layer chemical mechanical polishing (CMP) component and a preset virtual measurement AI model. Electroplating layer CMP parameters are determined based on the target electroplating layer CMP thickness and the CMP correspondence. These parameters include electroplating layer CMP time and electroplating layer CMP rate. The CMP correspondence is used to characterize the relationship between electroplating layer CMP time, electroplating layer CMP rate, and electroplating layer CMP thickness. The electroplating layer CMP thickness is determined based on the electroplating layer CMP time and electroplating layer CMP rate.

[0015] According to one embodiment of this disclosure, an integrated layout and / or mask design is performed based on the critical dimensions after etching.

[0016] According to one embodiment of this disclosure, the insulation layer deposition parameters of the insulation layer deposition component are adjusted based on the insulation layer deposition thickness after grinding determined by virtual measurement and the insulation layer grinding thickness determined by virtual measurement.

[0017] According to an embodiment of the intelligent chip factory advanced back-end automated process control system, the system includes: an insulating layer deposition unit for depositing an insulating layer on a wafer based on insulating layer deposition parameters determined by virtual measurement; an insulating layer chemical mechanical polishing (CMP) unit for performing CMP polishing on the wafer after deposition based on the insulating layer deposition thickness determined by virtual measurement, the insulating layer deposition thickness before polishing, and the CMP polishing parameters determined by virtual measurement; an anti-reflective coating and photoresist coating unit for applying an anti-reflective coating and photoresist to the wafer after CMP polishing based on the insulating layer deposition thickness after polishing determined by virtual measurement and the anti-reflective coating and photoresist coating parameters determined by virtual measurement; a photolithography unit for performing photolithography on the wafer after anti-reflective coating and photoresist coating; and an etching unit for etching... Based on the thicknesses of the anti-reflective coating and photoresist after virtual measurement, the thickness of the insulating layer after polishing after virtual measurement, and the etching parameters determined by virtual measurement, the wafer after photolithography is etched; a barrier layer deposition component is used to deposit a barrier layer on the etched wafer according to the barrier layer deposition parameters determined by virtual measurement; an electroplating component is used to electroplat the wafer after barrier layer deposition according to the electroplating parameters determined by virtual measurement; an electroplating layer chemical mechanical polishing component is used to perform electroplating layer chemical mechanical polishing on the electroplated wafer according to the electroplating layer thickness, electroplating layer polishing thickness, and key dimensions after etching determined by virtual measurement; a cobalt cap layer atomic layer deposition component is used to deposit a cobalt cap layer atomic layer on the wafer after electroplating layer chemical mechanical polishing to obtain the corresponding chip. Attached Figure Description

[0018] Figure 1 is a schematic diagram of the structure of an automated process control system for advanced back-end wiring in a smart chip factory according to some embodiments of the present disclosure. Detailed Implementation

[0019] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0020] The following describes in detail, with reference to the accompanying drawings, an embodiment of the intelligent chip factory advanced back-end wire automated process control system of the present disclosure.

[0021] In some embodiments, monitoring data and online monitoring data are acquired and stored in an SPC database according to preset corresponding locations. Offline and online monitoring data in the SPC database are offset and calibrated according to the performance change trend of the measurement tool to obtain first calibration data. Then, the first calibration data is filtered to obtain SPC data. Process tool sensor data and measurement tool sensor data are acquired and stored in an FDC database according to preset corresponding locations. Process tool sensor data and measurement tool sensor data are offset and calibrated according to the performance change trends of the process tool sensors and measurement tool sensors, respectively, to obtain second calibration data. Then, the second calibration data is filtered to obtain FDC data. The preset virtual measurement AI (Artificial Intelligence) model is trained using SPC data and FDC data. During use, the process tool running parameters can be input into the preset virtual measurement AI model to predict virtual measurement auxiliary data. Uncorrected and unfiltered offline monitoring data and online monitoring data can be used as virtual measurement auxiliary data. Both virtual measurement auxiliary data and virtual measurement auxiliary data are stored in the SPC database. APC (Auto Process Control) and RMS (Recipe Management System) will control the process tools based on the virtual measurement auxiliary data and virtual measurement auxiliary data in the SPC database, thereby controlling the smart chip factory.

[0022] In chip manufacturing processes, such as insulating layer deposition, insulating layer chemical mechanical polishing, anti-reflective coating and photoresist coating, photolithography, etching, barrier layer deposition, electroplating, electroplating layer chemical mechanical polishing, and cobalt cap layer atomic layer deposition, the above-mentioned preset virtual measurement AI model is used to predict the process parameters, that is, an advanced virtual measurement system is used to assist process control and improve the accuracy of automatic process control.

[0023] Referring to Figure 1, the advanced back-end automated process control system 1 of the intelligent chip factory includes: an insulating layer deposition unit 11, used to deposit an insulating layer on the wafer according to the insulating layer deposition parameters determined by virtual measurement; an insulating layer chemical mechanical polishing unit 12, used to perform insulating layer chemical mechanical polishing on the wafer after deposition according to the insulating layer deposition thickness determined by virtual measurement, the insulating layer deposition thickness before polishing, and the insulating layer chemical mechanical polishing parameters determined by virtual measurement; an anti-reflective coating and photoresist coating unit 13, used to apply an anti-reflective coating and photoresist to the wafer after insulating layer chemical mechanical polishing according to the insulating layer deposition thickness after polishing and the anti-reflective coating and photoresist coating parameters determined by virtual measurement; a photolithography unit 14, used to perform photolithography on the wafer after anti-reflective coating and photoresist coating; and an etching unit 15, used to perform etching according to the virtual measurement parameters. The wafer after photolithography is etched using the anti-reflective coating and photoresist thicknesses determined by virtual measurement, the insulating layer deposition thickness after polishing determined by virtual measurement, and the etching parameters determined by virtual measurement. A barrier layer deposition component 16 is used to deposit a barrier layer on the etched wafer according to the barrier layer deposition parameters determined by virtual measurement. An electroplating component 17 is used to electroplat the wafer after barrier layer deposition according to the electroplating parameters determined by virtual measurement. An electroplating layer chemical mechanical polishing component 18 is used to perform electroplating layer chemical mechanical polishing on the electroplated wafer according to the electroplating layer thickness, electroplating layer polishing thickness, and critical dimensions after etching determined by virtual measurement. A cobalt cap layer atomic layer deposition component 19 is used to deposit a cobalt cap layer atomic layer on the wafer after electroplating layer chemical mechanical polishing to obtain the corresponding chip.

[0024] Specifically, before the insulating layer deposition component 11 performs the insulating layer deposition operation on each product wafer, it is necessary to use virtual measurement to predict the insulating layer deposition parameters, that is, to predict the insulating layer deposition time and insulating layer deposition rate when the insulating layer deposition component 11 will deposit to the target insulating layer deposition thickness. Then, the insulating layer deposition component 11 performs insulating layer deposition according to the insulating layer deposition time and insulating layer deposition rate, wherein the insulating layer can be a silicon dioxide layer.

[0025] Before performing chemical mechanical polishing (CMP) on the deposited wafer, the insulating layer chemical mechanical polishing component 12 needs to use virtual measurement to predict the CMP parameters. That is, to predict the CMP time and CMP rate when the CMP component 12 is to polish the target CMP thickness. The target CMP thickness needs to be determined based on the insulating layer deposition thickness determined by virtual measurement and the insulating layer deposition thickness before polishing. This can, to a certain extent, avoid the CMP component 12 from polishing the insulating layer too much and damaging the wafer. The insulating layer deposition thickness before polishing can be obtained by the sensor set on the CMP component 12. Then, the CMP component 12 performs CMP polishing according to the CMP time and CMP rate.

[0026] Before applying antireflective coating and photoresist coating to the wafer after chemical mechanical polishing of the insulating layer, the antireflective coating and photoresist coating component 13 needs to use virtual measurement to predict the antireflective coating and photoresist coating parameters. That is, to predict the coating time and coating rate when the antireflective coating and photoresist coating component 13 is to coat the target coating thickness. The thickness of the insulating layer after polishing will affect the optical coefficient, and thus affect the thickness of the antireflective coating and photoresist. Therefore, the target coating thickness needs to be determined based on the thickness of the insulating layer after polishing. Then, the antireflective coating and photoresist coating component 13 will coat the wafer according to the coating time and coating rate.

[0027] The photolithography component 14 is used to perform photolithography on the wafer after the anti-reflective coating and photoresist coating are applied, for example, by performing deep multiple exposures.

[0028] Before etching the photolithographic wafer, the etching component 15 needs to use virtual measurement to predict the etching parameters, that is, to predict the etching time and etching rate when the etching component 15 etches the target etching critical dimension. The target etching critical dimension includes the etching depth, which needs to be determined based on the thickness of the anti-reflective coating and photoresist after coating and the thickness of the insulating layer after grinding. To a certain extent, this can avoid the wafer from being damaged by excessive etching depth. Then, the etching component 15 performs etching according to the etching time and etching rate.

[0029] Before the barrier layer deposition component 16 deposits a barrier layer on the etched wafer, it needs to use virtual measurement to predict the barrier layer deposition parameters, that is, predict the barrier layer deposition time and barrier layer deposition rate when the barrier layer deposition component 16 is to deposit the target barrier layer deposition thickness. Then, the barrier layer deposition component 16 performs barrier layer deposition according to the barrier layer deposition time and barrier layer deposition rate, such as performing cobalt atomic layer deposition.

[0030] Before electroplating the wafer after the barrier layer is deposited, the electroplating component 17 needs to use virtual measurement to predict the electroplating parameters, that is, to predict the electroplating time and electroplating rate when the electroplating component 17 is to electroplat the target electroplating layer thickness. Then, the electroplating component 17 performs electroplating according to the electroplating time and electroplating rate, such as electroplating copper.

[0031] Before performing electroplating chemical mechanical polishing (CMP) on the electroplated wafer, the electroplating layer CMP component 18 needs to use virtual measurement to predict the CMP parameters. That is, to predict the CMP time and CMP rate at which the electroplating layer CMP component 18 will polish the target electroplating layer CMP thickness. The target electroplating layer CMP thickness needs to be determined based on the electroplating layer thickness, which can, to a certain extent, prevent the electroplating layer CMP component 18 from polishing the electroplating layer too much and damaging the wafer. The target electroplating layer CMP thickness also needs to be determined based on the critical dimensions after etching, including the line density. The higher the line density, the thicker the electroplating layer will be. Therefore, the target electroplating layer CMP thickness should be increased at the locations with high line density, which can, to a certain extent, prevent the electroplating layer from being uneven after electroplating. Then, the electroplating layer CMP component 18 polishes according to the electroplating layer CMP time and electroplating layer CMP rate.

[0032] Before the cobalt cap atomic layer deposition component 19 deposits a cobalt cap atomic layer on the wafer after electroplating chemical mechanical polishing, it needs to use virtual measurement to predict the cobalt cap atomic layer deposition parameters, that is, predict the cobalt cap atomic layer deposition time and deposition rate when the cobalt cap atomic layer deposition component 19 is to deposit the target cobalt cap atomic layer thickness. The cobalt cap atomic layer deposition component 19 performs deposition according to the cobalt cap atomic layer deposition time and deposition rate to obtain the chip corresponding to the wafer.

[0033] This improves the accuracy of automated process control.

[0034] In some embodiments, the deposition correspondence is determined based on the operating parameters of the insulating layer deposition component 11 and a preset virtual measurement AI model, and the insulating layer deposition parameters are determined based on the target insulating layer deposition thickness and the insulating layer deposition correspondence. The insulating layer deposition parameters include the insulating layer deposition time and the insulating layer deposition rate. The insulating layer deposition correspondence is used to characterize the correspondence between the insulating layer deposition time, the insulating layer deposition rate, and the insulating layer deposition thickness. The insulating layer deposition thickness is determined based on the insulating layer deposition time and the insulating layer deposition rate.

[0035] Specifically, the operating parameters of the insulating layer deposition component 11 (which can be obtained by the sensors built into the insulating layer deposition component 11) are input into a preset virtual measurement AI model to predict the correspondence between the insulating layer deposition time, the insulating layer deposition rate and the insulating layer deposition thickness. Then, the insulating layer deposition time and the insulating layer deposition rate of the insulating layer deposition component 11 are determined according to the target insulating layer deposition thickness and the above correspondence. The insulating layer deposition time and the insulating layer deposition rate are stored in the SPC database. APC and RMS control the insulating layer deposition component 11 to perform insulating layer deposition according to the insulating layer deposition time and the insulating layer deposition rate in the SPC database.

[0036] In some embodiments, the chemical mechanical polishing (CMP) correspondence of the insulating layer is determined based on the operating parameters of the insulating layer chemical mechanical polishing component 12 and a preset virtual measurement AI model. The CMP parameters of the insulating layer are determined based on the target CMP thickness and the CMP correspondence. The CMP parameters include the CMP time and the CMP rate. The CMP correspondence is used to characterize the relationship between the CMP time, the CMP rate, and the CMP thickness. The thickness of the insulating layer deposited after polishing is determined based on the CMP time and the CMP rate.

[0037] Specifically, the operating parameters of the insulating layer chemical mechanical polishing component 12 (which can be obtained by the sensors built into the insulating layer chemical mechanical polishing component 12) are input into a preset virtual measurement AI model to predict the correspondence between the insulating layer chemical mechanical polishing time, the insulating layer chemical mechanical polishing rate and the insulating layer chemical mechanical polishing thickness. Then, the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate are determined according to the above target insulating layer chemical mechanical polishing thickness and the above correspondence. The insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate are stored in the SPC database. APC and RMS control the insulating layer chemical mechanical polishing component 12 to perform polishing according to the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate in the SPC database.

[0038] In some embodiments, the coating correspondence is determined based on the operating parameters of the anti-reflective coating and photoresist coating component 13 and a preset virtual measurement AI model. The anti-reflective coating and photoresist coating parameters are determined based on the target coating thickness and the coating correspondence. The anti-reflective coating and photoresist coating parameters include coating time and coating rate. The coating correspondence is used to characterize the correspondence between coating time, coating rate and coating thickness. The coating thickness is determined based on the coating time and coating rate.

[0039] Specifically, the operating parameters of the anti-reflective coating and photoresist coating component 13 (which can be obtained by the sensors built into the anti-reflective coating and photoresist coating component 13) are input into a preset virtual measurement AI model to predict the correspondence between coating time, coating rate and coating thickness. Then, the coating time and coating rate are determined according to the target coating thickness and the above correspondence, and the coating time and coating rate are stored in the SPC database. APC and RMS control the anti-reflective coating and photoresist coating component 13 to coat according to the coating time and coating rate in the SPC database.

[0040] In some embodiments, etching correspondence is determined based on the operating parameters of the etching component 15 and a preset virtual measurement AI model, and etching parameters are determined based on the target etching critical dimension and the etching correspondence. The etching parameters include etching time and etching rate, and the etching correspondence is used to characterize the correspondence between etching time, etching rate and the critical dimension after etching. The critical dimension after etching is determined based on the etching time and etching rate.

[0041] Specifically, the operating parameters of the etching component 15 (which can be obtained by the sensors built into the etching component 15) are input into a preset virtual measurement AI model to predict the correspondence between etching time, etching rate and key dimensions (e.g. etching depth) after etching. Then, the etching time and etching rate are determined according to the target etching key dimension and the above correspondence, and the etching time and etching rate are stored in the SPC database. APC and RMS control the etching component 15 to perform etching according to the etching time and etching rate in the SPC database.

[0042] In some embodiments, the barrier layer deposition correspondence is determined based on the operating parameters of the barrier layer deposition component 16 and a preset virtual measurement AI model. The barrier layer deposition parameters are determined based on the target barrier layer deposition thickness and the barrier layer deposition correspondence. The barrier layer deposition parameters include barrier layer deposition time and barrier layer deposition rate. The barrier layer deposition correspondence is used to characterize the correspondence between barrier layer deposition time, barrier layer deposition rate and barrier layer deposition thickness. The barrier layer deposition thickness is determined based on the barrier layer deposition time and barrier layer deposition rate.

[0043] Specifically, the operating parameters of the barrier layer deposition component 16 (which can be obtained by the sensors built into the barrier layer deposition component 16) are input into a preset virtual measurement AI model to predict the correspondence between barrier layer deposition time, barrier layer deposition rate and barrier layer deposition thickness. Then, the barrier layer deposition time and barrier layer deposition rate are determined according to the target barrier layer deposition thickness and the above correspondence, and the barrier layer deposition time and barrier layer deposition rate are stored in the SPC database. APC and RMS control the barrier layer deposition component 16 to perform deposition according to the barrier layer deposition time and barrier layer deposition rate in the SPC database.

[0044] In some embodiments, the electroplating correspondence is determined based on the operating parameters of the electroplating component 17 and the preset virtual measurement AI model, and the electroplating parameters are determined based on the target electroplating layer thickness and the electroplating correspondence. The electroplating parameters include electroplating time and electroplating rate, and the electroplating correspondence is used to characterize the correspondence between electroplating time, electroplating rate and electroplating layer thickness. The electroplating layer thickness is determined based on the electroplating time and electroplating rate.

[0045] Specifically, the operating parameters of the electroplating component 17 (which can be obtained by the sensors built into the electroplating component 17) are input into a preset virtual measurement AI model to predict the correspondence between electroplating time, electroplating rate and electroplating layer thickness. Then, the electroplating time and electroplating rate are determined according to the target electroplating layer thickness and the above correspondence, and the electroplating time and electroplating rate are stored in the SPC database. APC and RMS control the electroplating component 17 to perform electroplating according to the electroplating time and electroplating rate in the SPC database.

[0046] In some embodiments, the electroplating layer chemical mechanical polishing (CMP) correspondence is determined based on the operating parameters of the electroplating layer chemical mechanical polishing (CMP) component 18 and a preset virtual measurement AI model. Electroplating layer CMP parameters are determined based on the target electroplating layer CMP thickness and the CMP correspondence. These parameters include electroplating layer CMP time and electroplating layer CMP rate. The CMP correspondence is used to characterize the relationship between electroplating layer CMP time, electroplating layer CMP rate, and electroplating layer CMP thickness. The electroplating layer CMP thickness is determined based on the electroplating layer CMP time and electroplating layer CMP rate.

[0047] Specifically, the operating parameters of the electroplating layer chemical mechanical polishing (CMP) component 18 (which can be obtained by the sensors built into the CMP component 18) are input into a preset virtual measurement AI model to predict the correspondence between the electroplating layer CMP time, CMP rate, and CMP thickness. Then, the CMP time and CMP rate are determined based on the target electroplating layer CMP thickness and the above correspondence. The CMP time and CMP rate are stored in the SPC database. APC and RMS control the electroplating layer CMP component 18 to perform polishing based on the CMP time and CMP rate in the SPC database.

[0048] In some embodiments, the integrated layout and / or mask design are performed based on the critical dimensions after etching.

[0049] Specifically, the critical dimensions after etching include the line density. The higher the line density, the lower the etching rate. In order to maintain the same etching rate, it is necessary to re-integrate the layout and mask design or integrate the layout and mask design according to the critical dimensions after etching.

[0050] In some embodiments, the insulation deposition parameters of the insulation deposition component 11 are adjusted based on the insulation deposition thickness after grinding determined by virtual measurement and the insulation grinding thickness determined by virtual measurement.

[0051] Specifically, since the aging of the grinding disc during the grinding process will cause the grinding thickness of the insulating layer to become thinner and thinner, and the target grinding thickness cannot be achieved even after adjusting the grinding time and grinding rate, it is necessary to feed the grinding thickness of the insulating layer after grinding and the grinding thickness of the insulating layer determined by virtual measurement back to the insulating layer deposition component 11 to adjust the insulating layer deposition parameters, such as reducing the insulating layer deposition time or the insulating layer deposition rate, so as to reduce the thickness of the insulating layer deposition.

[0052] In summary, the virtual measurement system provides real-time predictions of component parameters to the automated process control system for precise adjustment. Based on process integration requirements, it offers rapid and effective data to relevant upstream and downstream process stations, enabling the automated process control system to make precise adjustments, promptly correct process parameters for the next chip, and even take timely downtime to mitigate the impact of incidents.

[0053] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0054] It should be understood that various parts of this disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0055] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0057] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0058] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. An automated back-end wiring process control system for an intelligent chip factory, the system comprising: An insulating layer deposition component is used to deposit an insulating layer on a wafer based on insulating layer deposition parameters determined by virtual measurement. An insulating layer chemical mechanical polishing (CMP) component is used to perform insulating layer CMP on the wafer after deposition based on the insulating layer deposition thickness determined by virtual measurement, the insulating layer deposition thickness before polishing, and the insulating layer CMP parameters determined by virtual measurement. An anti-reflective coating and photoresist coating component is used to coat the wafer after chemical mechanical polishing of the insulating layer with an anti-reflective coating and photoresist coating based on the deposit thickness of the insulating layer after polishing determined by virtual measurement and the anti-reflective coating and photoresist coating parameters determined by virtual measurement. A photolithography component for performing photolithography on the wafer after it has been coated with an anti-reflective coating and photoresist. An etching component is used to etch the photolithographically etched wafer based on the thickness of the coated anti-reflective coating and photoresist determined by virtual measurement, the thickness of the ground insulating layer deposited by the virtual measurement, and the etching parameters determined by the virtual measurement. A barrier layer deposition component is used to deposit a barrier layer on the etched wafer based on barrier layer deposition parameters determined by virtual measurement. An electroplating component is used to electroplat the wafer after the barrier layer has been deposited, based on electroplating parameters determined by virtual measurement. The electroplating chemical mechanical polishing component is used to perform electroplating chemical mechanical polishing on the electroplated wafer based on the electroplating thickness determined by virtual measurement, the electroplating polishing thickness determined by virtual measurement, and the key dimensions after etching determined by virtual measurement. A cobalt cap atomic layer deposition component is used to deposit a cobalt cap atomic layer on the wafer after electroplating and chemical mechanical polishing to obtain a chip corresponding to the wafer.

2. The intelligent chip factory advanced back-end wire automatic process control system according to claim 1, wherein, The deposition correspondence is determined based on the operating parameters of the insulating layer deposition component and the preset virtual measurement AI model. The insulating layer deposition parameters are determined based on the target insulating layer deposition thickness and the insulating layer deposition correspondence. The insulating layer deposition parameters include the insulating layer deposition time and the insulating layer deposition rate. The insulating layer deposition correspondence is used to characterize the correspondence between the insulating layer deposition time, the insulating layer deposition rate, and the insulating layer deposition thickness. The insulation layer deposition thickness is determined based on the insulation layer deposition time and the insulation layer deposition rate.

3. The intelligent chip factory advanced back-end wire automatic process control system according to claim 1, wherein, The chemical mechanical polishing (CMP) correspondence of the insulating layer is determined based on the operating parameters of the insulating layer CMP component and a preset virtual measurement AI model. The CMP parameters of the insulating layer are determined based on the target CMP thickness and the CMP correspondence. The CMP parameters include the CMP time and CMP rate. The CMP correspondence is used to characterize the relationship between the CMP time, CMP rate, and CMP thickness. The thickness of the insulating layer after grinding is determined based on the chemical mechanical polishing time and the chemical mechanical polishing rate of the insulating layer.

4. The intelligent chip factory advanced back-end wire automatic process control system according to claim 1, wherein, The coating correspondence is determined based on the operating parameters of the anti-reflective coating and photoresist coated components and a preset virtual measurement AI model. The coating parameters of the anti-reflective coating and photoresist are determined based on the target coating thickness and the coating correspondence. The coating parameters of the anti-reflective coating and photoresist include coating time and coating rate. The coating correspondence is used to characterize the correspondence between coating time, coating rate and coating thickness. The coating thickness is determined based on the coating time and the coating rate.

5. The intelligent chip factory advanced back-end wire automatic process control system according to claim 1, wherein, The etching correspondence is determined based on the operating parameters of the etched component and the preset virtual measurement AI model. The etching parameters are determined based on the target etching critical dimension and the etching correspondence. The etching parameters include etching time and etching rate. The etching correspondence is used to characterize the correspondence between etching time, etching rate and the critical dimension after etching. The critical dimensions after etching are determined based on the etching time and the etching rate.

6. The intelligent chip factory advanced back-end wire automatic process control system according to claim 1, wherein, The barrier layer deposition correspondence is determined based on the operating parameters of the barrier layer deposition component and the preset virtual measurement AI model. The barrier layer deposition parameters are determined based on the target barrier layer deposition thickness and the barrier layer deposition correspondence. The barrier layer deposition parameters include barrier layer deposition time and barrier layer deposition rate. The barrier layer deposition correspondence is used to characterize the correspondence between barrier layer deposition time, barrier layer deposition rate and barrier layer deposition thickness. The barrier layer deposition thickness is determined based on the barrier layer deposition time and the barrier layer deposition rate.

7. The intelligent chip factory advanced back-end wire automatic process control system according to claim 1, wherein, The electroplating correspondence is determined based on the operating parameters of the electroplated component and the preset virtual measurement AI model. The electroplating parameters are determined based on the target electroplating layer thickness and the electroplating correspondence. The electroplating parameters include electroplating time and electroplating rate. The electroplating correspondence is used to characterize the correspondence between electroplating time, electroplating rate and electroplating layer thickness. The thickness of the electroplated layer is determined based on the electroplating time and the electroplating rate.

8. The intelligent chip factory advanced back-end wire automatic process control system according to claim 1, wherein, The electroplating layer chemical mechanical polishing (CMP) correspondence is determined based on the operating parameters of the electroplating layer chemical mechanical polishing (CMP) component and a preset virtual measurement AI model. The electroplating layer CMP parameters are determined based on the target electroplating layer CMP thickness and the CMP correspondence. The electroplating layer CMP parameters include electroplating layer CMP time and electroplating layer CMP rate. The electroplating layer CMP correspondence is used to characterize the relationship between electroplating layer CMP time, electroplating layer CMP rate, and electroplating layer CMP thickness. The electroplating layer's chemical mechanical polishing thickness is determined based on the electroplating layer's chemical mechanical polishing time and the electroplating layer's chemical mechanical polishing rate.

9. The intelligent chip factory advanced back-end wire automatic process control system according to claim 1, wherein, Integrated layout and / or mask design are performed based on the critical dimensions after etching.

10. The intelligent chip factory advanced back-end wire automatic process control system according to claim 1, wherein, The insulation deposition parameters of the insulation deposition component are adjusted based on the insulation deposition thickness after grinding determined by the virtual measurement and the insulation grinding thickness determined by the virtual measurement.

Images