Phase drift reduction for multi-PLL system

Abstract

A phase detector interleaving / averaging circuit and technique effectively reduces phase drift between PLL circuits. Each phase detector's nonlinearity is shared, over time, among different PLL circuits. Accordingly, the average relative phase is the same for all PLL circuits, and phase shift is then controlled as desired though PLL phase control inputs.

Description

[0001] P110867WQ01

[0002] PHASE DRIFT REDUCTION FOR MULTI-PLL SYSTEM

[0003] TECHNICAL FIELD

[0004] The present disclosure relates generally to wireless communications, and in particular to a distributed Phase Lock Loop (PLL) system that averages phase detector circuit errors over the PLLS.

[0005] BACKGROUND

[0006] Wireless communication networks are ubiquitous in many parts of the world. These networks continue to grow in capacity and sophistication. To accommodate more users, different types of devices, and different use cases, the technical standards governing the operation of wireless communication networks continue to evolve. The fourth generation (4G) of network standards has been deployed, the fifth generation (5G) is in final development and is partially deployed, and the sixth generation (6G) is in design. With each generation, technological advances improve the capacity, spectral efficiency, and achieved bitrate of the wireless communication system, as well as introduce new use cases, such as Ultra Reliable and Low Latency Communications (URLLC) and Machine-to-Machine (M2M) communications. As spectrum in lower frequencies fills up, higher frequency spectrum is taken into use.

[0007] 5G added a second frequency range, FR2. This provided significant new available spectrum in the range 24.25-52.6 GHz (FR1 spans 410 - 7125 MHz). At these high frequencies, wavelengths are small. Correspondingly, antenna elements are small, and each captures / radiates less energy. Accordingly, more antenna elements are required to cover the same area with the same link performance and the same inter-site distance.

[0008] FIG. 1 shows one example antenna array, consisting of 8x8 dual-polarized antenna elements. The antenna elements are pairwise interconnected to form 2x1 subarrays, and thus reduce the number of active radio chains required to connect to the antenna and apply beamforming. The subarrays are numbered SAO to SA31 (moving left to right and top to bottom). In general, antenna elements of an array may be grouped into any number of subarrays, each comprising any number of individual antenna elements. Subarrays in an antenna array need not be the same - that is, some antennal elements may be grouped into one or more m x n subarrays, and other antennal elements may be grouped into one or more i x j subarrays, where m i and / or n j. As used herein, a subarray may include from one antenna element up to all of the antenna elements in an antenna array.

[0009] FIG. 2 shows one example of a transceiver front end, implemented on a Radio Frequency (RF) integrated circuit (RFIC), that can be used together with the antenna array of FIG. 1. This RFIC has 8 bidirectional IQ baseband ports, an internal port expansion by four, and thus 32 antenna connections. Each antenna branch, also referred to as an RF tile, has its own Phase Locked Loop (PLL), to enable beamforming (as discussed below) in both the uplink and P110867W001 downlink by controlling the relative phase between antenna elements or subarrays. In transmit (TX) mode, the IQ baseband signal is split to four branches, upconverted to RF using an IQ- modulator with a Local Oscillator (LO) signal generated by the PLL, and amplified by a Power Amplifier (PA). An antenna switch connects either the transmitter or the receiver branch to the antenna element subarray. As depicted in FIG. 2, the tiles connect to the antenna element subarrays in column 1 of the antenna system depicted in FIG. 1 (that is, subarrays SAO, SA8, SA16, and SA24). In receive (RX) mode, each antenna element subarray signal is amplified by a Low Noise Amplifier (LNA), downconverted to baseband using an LO signal generated by the PLL, and added to the other three branches sharing the IQ-interface. In both paths, precise control of the phase of the LO signal is required to implement beamforming.

[0010] Advanced Antenna System (AAS) implementations contemplate hundreds, or even thousands, of antenna elements. This increases the number of data streams to be processed, increasing the system computational load. Another problem with RF carriers at these high frequencies is that they suffer higher path loss, and hence have limited range, compared to conventional wireless telecom operating frequencies. Beamforming is one technique featured in 5G and 6G, to improve both coverage and capacity.

[0011] Beamforming refers to the use of antennas having increased and controllable directionality, whereby an RF transmission (or reception sensitivity) is narrowly focused, and is “aimed” in a specific direction. This is enabled by transmitting or receiving signals with controlled relative phase and gain in the antenna elements (or subarrays of antenna elements). The relative phases of, e.g., transmit signals sent to each antenna element are controlled to create constructive or destructive interference, thus amplifying the signal in some directions, and attenuating it in others, and hence controlling the direction in which the beam is transmitted. Similar phase manipulation of signals from antenna elements (or subarrays) in a receive antenna can also result in beamforming the sensitivity of an antenna array for receiving signals.

[0012] FIG. 3 shows how a successively larger phase shift at each of adjacent antenna elements results in a directionally steered RF beam.

[0013] Because beamforming combines the outputs of multiple antenna elements (or subarrays), it increases beam gain, concentrating greater RF signal energy towards a receiver. This mitigates the inherent path loss of higher frequency carrier signals and restores the rated equivalent isotropic radiated power (EIRP) rating of base stations operating in FR1 and FR2 to usable levels.

[0014] In addition to combatting path loss, another advantage to beamforming is that, particularly with large antenna arrays, multiple orthogonal beams can be formed and aimed in different directions, thus simultaneously addressing multiple wireless devices, also known as User Equipment (UE). For example, both a direct beam (line of sight) and a reflected beam may be targeted to a UE. Additionally, frequency-selective beamforming may be implemented, wherein subcarriers of the same Orthogonal Frequency Division Multiplexing (OFDM) symbol P110867W001 are assigned different weights, thus pointing beams in different directions as a function of frequency.

[0015] As mentioned above, PLL circuits, which may be implemented in the analog or digital domains, are critical to beamforming operations. The LO signals, with varying phase offsets to implement the beamforming, must be accurate across all RF signal processing paths. One challenge in modern RF front end design is to minimize phase drift between large numbers of PLLs, which are necessarily distributed across an integrated circuit (IC) and may suffer from different Process, Voltage, and Temperature (PVT) effects in operation.

[0016] The Background section of this document is provided to place aspects of the present disclosure in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches described in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.

[0017] SUMMARY

[0018] The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key / critical elements of aspects of the disclosure or to delineate the scope of the disclosure. The sole purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[0019] According to aspects of the present disclosure described and claimed herein, a phase detector interleaving / averaging circuit and technique effectively reduces phase drift between PLLs. Each phase detector’s nonlinearity is shared, over time, among different PLLs. Accordingly, the average relative phase is the same for all PLLs, and phase shift is then controlled as desired though PLL phase control inputs.

[0020] One aspect relates to a distributed system of Phase Locked Loop (PLL) circuits. The system includes a number N of PLL circuits. Each PLL circuit comprises a variable oscillator and a control loop. Each PLL circuit has an output to provide a PLL signal and an input to receive a representation of a phase difference signal. The system also includes a same number N of phase comparison circuits. Each phase comparison circuit has a first input configured to receive a PLL signal, a second input configured to receive a common reference clock signal, and an output configured to output a representation of a phase difference. The system further includes an input multiplexing bank interposed between the N PLL circuits and the N phase comparison circuits. The input multiplexing bank is configured to mutually exclusively connect the outputs of the N PLL circuits with the first inputs of the N phase comparison circuits, in response to a first control signal. The system additionally includes an output multiplexing bank P110867WG01 interposed between the N phase comparison circuits and the N PLL circuits. The output multiplexing bank is configured to mutually exclusively connect the outputs of the N phase comparison circuits to the inputs of the N PLL circuits in response to a second control signal. Finally, the system includes a controller. The controller is configured to generate the first and second control signals and to map the same PLL circuit to the first input and the output of each phase comparison circuit.

[0021] Another aspect relates to a Radio Frequency (RF) transceiver circuit connected to a plurality of antenna elements. The RF transceiver circuit includes the distributed PLL system described above.

[0022] Yet another aspect relates to a User Equipment (UE) operative in a wireless communication network. The UE includes a plurality of antenna elements and the RF transceiver circuit described above.

[0023] Still another aspect relates to a base station operative in a wireless communication network. The base station includes a plurality of antenna elements and the RF transceiver circuit described above.

[0024] Still another aspect relates to a method of reducing phase deviation for a number N of Phase Locked Loop (PLL) circuits. An output signal is received from each of the N PLL circuits. For a first duration, The N PLL circuit output signals are mutually exclusively mapped to N phase comparison circuits according to a first control signal; at each of the N phase comparison circuits, a PLL circuit output signal is compared to a common reference clock signal and a representation of a phase difference is output; and the outputs of the N phase comparison circuits are mutually exclusively mapped to the N PLL circuits according to a second control signal. The first and second control signals are configured to map the same PLL circuit to both the input and the output of each phase comparison circuit. For a second duration, the mapping and comparing steps are repeated, wherein the first and second control signals are configured to map each PLL circuit to a different phase comparison circuit than in the first duration.

[0025] BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which aspects of the disclosure are shown. However, this disclosure should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

[0027] FIG. 1 is a diagram of an antenna array.

[0028] FIG. 2. is a schematic diagram of an RFIC suitable for use with the antenna array of FIG. 1.

[0029] FIG. 3 is diagram showing the relationship between phase shift at adjacent antenna elements and directional beamforming. P110867WG01

[0030] FIG. 4 is a block diagram of an RF system comprising multiple front end circuits, each having a phase-adjustable PLL.

[0031] FIG. 5 is a block diagram of a digital PLL.

[0032] FIG. 6 is a graph of phase deviations of one PLL, relative to a reference PLL in a system such as that depicted in FIG. 4.

[0033] FIG. 7 is block diagram of a PLL system according to aspects of the present disclosure.

[0034] FIG. 8 is a detailed block diagram of the PLL system of FIG. 7 using digital PLLs.

[0035] FIG. 9 is a schematic diagram of a Linear Feedback Shift Register useful in the PLL system of FIG. 7.

[0036] FIG. 10 is a flow diagram of a method of reducing phase deviation for a number of PLLs.

[0037] FIG. 11A is block diagram of a wireless communication network.

[0038] FIG. 11 B is a block diagram of a UE employing the PLL system of FIG. 7.

[0039] FIG. 110 is a block diagram of a base station employing the PLL system of FIG. 7.

[0040] DETAILED DESCRIPTION

[0041] For simplicity and illustrative purposes, the present disclosure is described by referring mainly to an exemplary aspect thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be readily apparent to one of ordinary skill in the art that the present disclosure may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0042] Phase Locked Loops (PLL) are critical to RF front end circuits. A basic design choice regarding PLLs is between analog and digital operation. Analog PLLs are well known, but digital PLLs (DPLL) have lately become popular. Advantages of a DPLL include the absence of large area capacitors in the analog loop filter, and the possibility to support advanced digital algorithms, such as increasing loop bandwidth during operation to implement fast frequency hops. However, DPLLs are highly complex, requiring a major design effort and the complexity may be unfeasible for designs requiring operation at very high frequency (mm-wave) or with ultra-low power consumption.

[0043] On the other hand, advantages of an analog PLL include reduced design complexity, and excellent phase noise. As one example of the design trade-offs, the simplicity of an analog PLL makes it an excellent choice at very high frequencies or for very low power. However, the design of an analog PLL is inflexible. For example, the loop filter cannot be re-configured without introducing transients, the bandwidth is limited by the reference frequency used, and the phase detector has a limited range. These characteristics make it difficult to increase the speed of frequency acquisition of an analog PLL. Even without changing the bandwidth, the transfer function of an analog PLL is dependent on a number of parameters with wide variation, such as P110867WG01 loop filter resistance and capacitance, and VCO frequency tuning sensitivity. The transfer function will therefore also show a wide variation, decreasing the accuracy of signal modulation. Particularly the higher frequency components of the phase / frequency modulation, with modulation frequencies near the PLL bandwidth, will have a large variability in both magnitude and phase. This will cause problems in de-modulation, degrading the performance of the system. Additionally, analog PLLs do not scale down well, as reduced supply voltage and increased channel length modulation effect result in worse linearity.

[0044] The flexibility of DPLLs makes them attractive for AAS, where phase control is straightforward. In AAS, multiple front-ends are configured to send and receive signals with certain phase and gain relations to achieve beamforming of transmitted signals and receiver sensitivity.

[0045] Although the discussion herein focuses on DPLLs, those of skill in the art will recognize that aspects of the present disclosure are appliable to both analog and digital PLLs. Accordingly, the term “PLL” alone may refer to an analog or digital PLL, unless the context implies one or the other. As known in the art, in the case of analog PLLs, phase comparison between the PLL output clock CKO or divided clock CKV may be performed by a Phase / Frequency Detector (PFD), and in the case of DPLLs, may be performed by TDCs. It is well within the skill level of those of skill in the art to make the necessary substitutions to implement aspects of the present invention to either analog PLLs or DPLLs, given the teachings of the present disclosure.

[0046] FIG. 4 shows an RF circuit 10 comprising N PLLs 12, each generating a LO signal, which is supplied to one of N front end circuits 14. Each of the PLLs 12 includes a variable oscillator (e.g., a Digitally Controlled Oscillator, DCO) 16, and a phase control circuit 18. This system 10 of local LO synthesis for each RF front-end 14 with phase control capability 18 is a good solution with high flexibility. However, it imposes the expenses of chip area and energy consumption overhead. In multi-PLL systems 10, it is important to achieve well-known phase relations among the PLLs 12. Deviations from the desired phase relations affect the beam directivity and side lobe magnitude. DPLLs are attractive solutions with low phase drift and ease of adaptability and calibration. However, when used to generate an LO in a multi-LO beamforming system, there is a need to synchronize the phase of those DPLLs.

[0047] At mm-wave frequencies the phase drifts between DPLLs are substantial. This drift is induced by the mismatches in the delay line within the TDC, which accumulates the drift throughout the line. In an AAS with multiple DPLLs 12, comparing the phase difference between DPLLs 12 comprises several steps. As well known in the art, in a DPLL, the phase mismatch between a (divided) generated signal and a reference signal is converted to a digital delay value by a Time to Digital Converter (TDC). The DPLL control loop uses the TDC output to correct the phase and / or frequency of its output signal. For example, a TDC may have a 2 ps resolution, and operate in a DPLL outputting a frequency of 28 GHz. This resolution is smaller than what P110867W001 state-of-the-art technologies can achieve, therefore more advanced architectures such as vernier delay line are often used. When comparing the TDC outputs of different PLLs 12 while locked, the difference (tolerance) is expected to be one more or one less than the nominal. The maximum difference is then expected to be around 4 ps. The period at 28 GHz is ~36 ps. 360736 ps = 107ps, and 107ps x 4 ps uncertainty = 40°. This is quite a substantial difference that must be corrected. Correcting this using calibration requires characterizing each TDC’s cell in each PLL 12. Furthermore, this entire calibration must be performed at different temperatures, because the control loop of the PLL 12 will act to correct the phase despite temperature drift. This means that the TDC outputs will be different, even though the relative change in delay is similar for all PLLs 12 on the same chip.

[0048] FIG. 5 depicts a representative design of a DPLL 12. An output clock signal CKO, for example in the range 23.4 - 28.8 GHz, is generated by a DCO 16. That output CKO is divided, in this example by 4, in a frequency divider circuit 20, to a range of 5.85 - 7.2 GHz, to generate a divided clock signal CKV. As used herein, DPLL 12 without a frequency divider circuit 20 (CKV=CKO) may be considered to include a frequency divider circuit 20 having a divisor of 1. A high speed counter 22 measures the integer part of the phase error, by counting the number of pulses in the divided clock signal CKV per reference frequency FREF signal period.

[0049] The fractional part of the phase error is measured using a Time to Digital Converter (TDC) 24. Although normally considered a part of the DPLL 12, the TDC 24 is shown outside the bounding box of the DPLL 12, for reasons that will be made clear herein. The TDC 24 has two inputs - a reference clock signal FREF, and a PLL signal, depicted here as the divided clock signals CKV. In other aspects, the TDC may receive the PLL output clock signal CKO rather than the divided clock signal CKV. In either case, the TDC 24 outputs a digital representation of a phase difference between the reference clock signal FREF and the PLL clock signal CKO / CKV.

[0050] A phase control circuit 18 is used to steer the phase of the output signal. A fractional Frequency Control Word FCW_frac is input to a reference accumulator 26, which accumulates the wanted phase the DCO signal must follow. For example, FCW_frac of 0.1 means that the CKO must drift by a factor 0.1 period every FREF period. A full period is finished every 10 FREF cycles. If an integer case is required, then CKO and FREF must be in phase, and therefore no phase drift is required. In that case, FCW_frac=0.The integer and fractional parts of the (steered) phase error are summed at 28, shaped by a low pass filter 29, and provided to the DCO 16 input.

[0051] When a plurality of PLLs 12 operate together, significant phase drifts between them are inevitable. To demonstrate this, a system of 16 PLLs 12 was simulated at a mm Wave frequency of 27.525 GHz. A reference frequency FREF of 245.76 MHz was applied, with a division by 4 in the frequency divider 20, and a nominal integer count of 28 in the counter 22 - yielding an output frequency for the integer case of 245.76 MHz x 4 x 28 = 27.525 GHz. All 16 PLLs 12 were set to have the same phase. TDC nonlinearity and noise, as well as DCO phase, P110867WG01 quantization noise, and reference noise, were all included in the simulation. These factors were randomly varied using statistical models. To show the phase drift, the phase of each PLL 12 in the system was measured relative to an arbitrarily selected first PLL 12. Three different test cases were simulated: • An integer case where the reference clock was multiplied by 4x28;

[0052] • A fractional case where the reference clock was multiplied by 4x28.2; and

[0053] • A near-integer case reference clock was multiplied by 4x28.001

[0054] The phase relations, phase noise, and overall average phase were measured for each case. FIG. 6 shows the distribution of phase error for one PLL 12, relative to the first PLL 12, for the integer case. The other 14 distributions were similar; the mean and standard deviations are presented in Tables 1-3: Table 1: Separate PLLs, Integer case (4x28), FQUT = 27.525 GHz P110867W001

[0055] Table 2: Separate PLLs, Fractional case (4x28.2), FQUT = 27.72 GHz P110867WG01

[0056] Table 3: Separate PLLs, Near-integer case (4x28.001), FQUT = 27.5261 GHz

[0057] As the results in Tables 1-3 show, the mean phase drift among the PLLs can be close to 50°. For each test case, the overall phase drift was estimated by averaging the outputs from the 16 PLLs 12. The results are shown in Table 4 below.

[0058] Table 4: Separate PLLs, Combined Results

[0059] In all three cases, the average phase error is reduced, as compared to individual comparisons to the reference PLL 12. This is expected, and is due to the beamforming gain, and uncorrelated noise sources being averaged out.

[0060] FIG. 7 shows a general block diagram of a PLL array architecture 30 for an AAS system with a size of N, according to aspects of the present disclosure. N PLLs 12-1 , ... , 12-N (collectively, 12) each comprises a variable oscillator, frequency divider, and control loop, and have a divided PLL signal output and a phase difference input. Rather than performing the phase comparison locally, a PLL signal is output from each PLL 12, towards a bank 32 of centrally located comparison circuits ( / .e., TDCs 24 for a DPLL). In different aspects, the PLL signals may be the outputs of the variable oscillators or of the frequency dividers. Each phase P110867W001 comparison circuit (not shown individually) has a first input configured to receive a PLL signal, a second input configured to receive a common reference clock signal REF, and an output configured to output a representation of a phase difference. An input multiplexing bank 34 is interposed between the N PLLs 12 and the bank 32 of phase comparison circuits. The input multiplexing bank 34 is configured to mutually exclusively connect PLL signals with phase comparison circuit first inputs, in response to a first control signal from a controller 36. An output multiplexing bank 38 is interposed between the bank 32 of phase comparison circuits and the N PLLs 12. The output multiplexing bank 38 is configured to mutually exclusively connect phase comparison circuit outputs to PLL phase difference inputs in response to a second control signal from the controller 36. The controller 36 is configured to generate the first and second control signal so as to map the same PLL 12 to the first input and the output of each phase comparison circuit, so that each PLL 12 receives its own phase comparison, regardless of which phase comparison circuit is selected for it.

[0061] In one aspect, the controller 36 implements a cyclic time interleaving pattern, whereby a given PLL 12 will use a selected phase comparison circuit for a short time duration, determined by the interleaving period. That PLL 12 will then use the next phase detector in the sequence for a subsequent duration. On average, all PLLs 12 will use all the phase comparison circuits, which results in diminished phase difference among them by averaging out phase comparison errors. Placing the bank 32 of phase comparison circuits centrally is advantageous, as the layout effects can then be mitigated and the PVT effects are reduced, compared to the placement of N phase comparison circuits within N PLLs 12 at different locations across the Integrated Circuit (IC).

[0062] FIG. 8 shows a more detailed block diagram of the system 30. N divided clock signals CKV from N PLLs 12 are input into the input multiplexing bank 34. In this aspect, the controller 36 is configured to control the input multiplexing bank 34 to implement a rotator, or circular shifter, whereby for example the input CK i is initially output as CKVRI for a first duration, then shifted to CKVR2 for the next duration, then CK RS, etc. The CK RI, CKVR2, . . . CKVRN signals are compared to the same REF clock signal in corresponding TDCi, TDC2, . . . TDCN circuits 24 in the bank 32 of phase comparison circuits. These produce respective outputs TDC_outRi, TDC_outR2, ... TDC_outRN. The output multiplexing bank 38, controlled by the controller 36 to implement a de-rotator, routes each TDCn24 output to a corresponding TDC_outi, TDC_out2, . . . TDC_outN signal, which returns to the PLL 12 that generated the corresponding signal CKV1, CKV2, . . . CKVN.

[0063] In general, the controller 36 may implement any mapping of inputs to outputs at the input and output multiplexing banks 34, 38, so long as the mappings of PLL 12 to TDC 24 are mutually exclusive, and a PLL signal mapped to an input of the input multiplexing bank 34 appears at a corresponding output of the output multiplexing bank 38. The latter condition may be ensured by merging the first and second control signals - that is, applying the same bit P110867WG01 patterns to multiplexers in the input and output banks 34, 38, as shown in FIG. 8. As non-limiting examples, the mapping may be a rotation, as described above, a rotation that jumps 2, 3, etc. slots rather than one at each iteration, a back-and-forth shifting, a random or pseudo-random mapping, an N-step frequency hopping pattern employed elsewhere in a communications device, or any other pattern. The controller 36 may be implemented by a counter, a programmable processor, or the like.

[0064] FIG. 9 depicts a Linear Feedback Shift Register (LFSR) with a 5-bit width, outputting a 4-bit control signal, which is one implementation for controller 36 in a system 30 where N = 16. Which four of the five bits to use is a design choice, and the depiction in FIG. 10 is not limiting in this regard. To control a system 30 where N = 8, only three bits of the LFSR may be used. An

[0065] LFSR with a narrower bit width may be employed to shift frequency spurs, resulting from the interleaving, to be out of the band of interest, where they marginally contribute to the overall Error Vector Magnitude (EVM). The calculation for the first spur is: is the LFSR clock frequency and M is the width of the LFSR.

[0066] 2M The system 30 of FIG. 8 was simulated for the same three representative cases (integer

[0067] (4x28), fractional (4x28.2), and near-integer (4x28.001)), using a 245.76 MHz reference clock. The relations of the phase of each DPLL 12 to an arbitrarily designated first DPLL 12 for the three cases are shown in Tables 5-7: P110867WG01

[0068] Table 5: N=16, Integer case (4x28), FQUT = 27.525 GHz

[0069] Table 6: N=16, Fractional case (4x28.2), FQUT = 27.72 GHz P110867W001

[0070] Table 7: N=16, Near-integer case (4x28.001), FQUT = 27.5261 GHz

[0071] As the results in Tables 5-7 show, the mean phase drift among the PLLs has dropped to approximately 2°. For each test case, the overall phase noise was estimated by averaging the outputs from the 16 PLLs 12. The results are shown in Table 4 below.

[0072] Table 8: N=16, Combined Results

[0073] Interleaving spurs occur even in the integer case. However, the spurs are outside the band of interest and the overall phase noise of the AAS has reduced spur levels. Due to interleaving and different characteristics of each TDC in integer cases, the fractional spurs’ P110867W001 levels are heavily reduced when compared to single TDC performance. This is another advantage of aspects of the present disclosure.

[0074] As a practical matter, interleaving 16 TDCs 24 can be difficult, for example in the case that a tile is arranged to have groups of 8 RF front-ends on each side. For these applications, according to one aspect of the present disclosure, the PLLs 12 are divided into two groups, and the system 30 is replicated, but with eight TDCs 24 grouped in each bank 32 of phase comparison circuits, with concomitant size adjustments to the input and output multiplexing banks 34, 38, and of course the first and second control signals. Simulation results listed in Tables 9-11 show that the mean increases for the near-integer case to ~5-6°. The phase noise as well as the mean phase for DPLLs 12 shows that aspects of the present disclosure are still very effective for grouping eight TDCs 24, and compared to the phases of the two groups the phase difference still diminishes thanks to the dithered nonlinearity making the characteristics of both groups similar.

[0075] Table 9: N=8, Integer case (4x28), FQUT = 27.525 GHz P110867W001

[0076] Table 10: N=8, Fractional case (4x28.2), FQUT = 27.72 GHz P110867WG01

[0077] Table 11 : N=8, Near-integer case (4x28.001), FQUT = 27.5261 GHz

[0078] As the results in Tables 9-11 show, the mean phase drift among the PLLs has dropped to approximately 2°. For each test case, the overall phase noise was estimated by averaging the outputs from the eight PLLs 12. The results are shown in Table 12 below.

[0079] Table 12: N=8, Combined Results

[0080] FIG. 10 depicts the steps in a method 100 of reducing phase deviation for a number N of Phase Locked Loop (PLL) circuits 12. On an ongoing basis, an output signal is received from each of the N PLL circuits 12 (block 102). The N PLL circuit output signals are mutually exclusively mapped to N phase comparison circuits 24 according to a first control signal (block 104). At each of the N phase comparison circuits 24, a PLL circuit output signal is compared to a common reference clock signal, and a representation of a phase difference is output (block 106). The outputs of the N phase comparison circuits 24 are mutually exclusively mapped to the N PLL circuits 12 according to a second control signal (block 108). The first and second control signals are configured to map the same PLL circuit 12 to both the input and the output of each phase comparison circuit 24. This process continues for a first duration (block 110). At the P110867WG01 expiration of the first duration (block 110), the first and second control signals are configured to map each PLL circuit 12 to a different phase comparison circuit 24 than in the first duration (block 112), and the mapping and comparing steps (blocks 104-108) are repeated for a second duration (block 110). Those of skill in the art will recognize that the method 100 may continue, remapping the PLLs to different phase comparison circuits, through at least N durations using N unique, mutually exclusive mappings, and may then repeat. That is, although depicted as discrete steps in FIG. 10 for ease of explanation, those of skill in the art will recognize that the method 100 may be ongoing, in a continuous manner, for as long as a transceiver employing the system 30 is in operation.

[0081] Figure 11 A is a diagram of transmissions over the air interface of a Radio Access Network (RAN) of a wireless communication network 40, such as a 3GPP 4G (Long Term Evolution, or LTE) or 5G (New Radio, or NR), or 6G network. A User Equipment (UE) 50, such as a smartphone, receives and transmits modulated Radio Frequency (RF) signals, over one or more antennas, from and to a base station 60, such as an LTE eNB, an NR gNB or any RAN node serving as (part of) a base station or access point, for example an AAS installation.

[0082] One or both of the UE 50 and base station 60 includes a transceiver 56, 66 that employes a PLL system 30 according to aspects of the present disclosure.

[0083] Figure 11 B is a block diagram of the UE 50 of Figure 11 A. As used herein, the term UE may refer to a user-operated telephony terminal, a machine-to-machine (M2M) device, a machine-type communications (MTC) device, a Narrowband Internet of Things (NB-loT) device (in particular a UE implementing the 3GPP standard for NB-loT), etc. A UE 50 may also be referred to as a radio device, a radio communication device, a wireless communication device, a wireless terminal, or simply a terminal - unless the context indicates otherwise, the use of any of these terms is intended to include device-to-device UEs or devices, machine-type devices or devices capable of machine-to-machine communication, sensors equipped with a radio network device, wireless-enabled table computers, mobile terminals, smartphones, laptop-embedded equipped (LEE), laptop-mounted equipment (LME), USB dongles, wireless customer-premises equipment (CPE), and the like.

[0084] The UE 50 transmits and receives RF signals on at least one antenna 59, which may be internal or external, as indicated by dashed lines. In general, the antenna(s) 59 may implement beamforming, requiring tight control of relative phase between front end circuits 14. The RF signals are generated, and received, by a transceiver 56, which includes the PLL system 30 according to aspects of the present disclosure. The transceiver 56, as well as other components of the UE 50, are controlled by processing circuitry 52. Memory 54 operatively connected to the processing circuitry 52 stores software in the form of computer instructions operative to cause the processing circuitry 52 to control the transceiver 56, including the PLL system 30. For example, the controller 36 described herein may be implemented as a routine executed by the processing circuitry 52. A user interface 58 may include output devices such as a display and P110867WG01 speakers (and / or a wired or wireless connection to audio devices such as ear buds), and / or input devices such as buttons, a keypad, a touchscreen, and the like. As indicated by the dashed lines, the user interface 58 may not be present in all UEs 50; for example, UEs 50 designed for Machine Type Communications (MTC) such as Internet of Things (loT) devices, may perform dedicated functions such as sensing / measuring, monitoring, meter reading, and the like, and may not have any user interface 58 features.

[0085] Figure 11C is a block diagram of the base station 60 of Figure 11 A. A base station 60 - known in various network implementations as a Radio Base Station (RBS), Base Transceiver Station (BTS), Node B (NB), enhanced Node B (eNB), Next Generation Node B (gNB), or the like - is a node of a wireless communication network that implements a Radio Access Network (RAN) in a defined geographic area called a cell, by providing radio transceivers to communicate wirelessly with a plurality of UEs 50.

[0086] The base station 60 transmits and receives RF signals on a plurality of antennas 69. In particular, the antennas 69 may comprise an advanced antenna system (AAS) that enables beamforming. As indicated by the broken line, the antennas 69 may be located remotely from the base station 60, such as on a tower or building. The RF signals are generated, and received, by a transceiver 66, which includes the PLL system 30 according to aspects of the present disclosure. The transceiver 66, as well as other components of the base station 60, are controlled by processing circuitry 62. Memory 64 operatively connected to the processing circuitry 62 stores instructions operative to cause the processing circuitry 62 to control the transceiver 66, including PLL system 30. For example, the controller 36 described herein may be implemented as a routine executed by the processing circuitry 52. Although the memory 64 is depicted as being separate from the processing circuitry 62, those of skill in the art understand that the processing circuitry 62 includes internal memory, such as a cache memory or register file. Those of skill in the art additionally understand that virtualization techniques allow some functions nominally executed by the processing circuitry 62 to actually be executed by other hardware, perhaps remotely located (e.g., in the so-called “cloud”). Communication circuitry 68 provides one or more communication links to one or more other network nodes, propagating communications to and from UEs 50, from and to other network nodes or other networks, such as telephony networks or the Internet.

[0087] In all aspects, the processing circuitry 52, 62 may comprise any sequential state machine operative to execute machine instructions stored as machine-readable computer programs in memory 54, 64, such as one or more hardware-implemented state machines (e.g., in discrete logic, FPGA, ASIC, etc.), programmable logic together with appropriate firmware; one or more stored-program, general-purpose processors, such as a microprocessor or Digital Signal Processor (DSP), together with appropriate software; or any combination of the above.

[0088] In all aspects, the memory 54, 64 may comprise any non-transitory machine- readable media known in the art or that may be developed, including but not limited to magnetic media P110867W001

[0089] (e.g., floppy disc, hard disc drive, etc.), optical media (e.g., CD-ROM, DVD-ROM, etc.), solid state media (e.g., SRAM, DRAM, DDRAM, ROM, PROM, EPROM, Flash memory, solid state disc, etc.), or the like.

[0090] In all aspects, the transceiver 56, 66 is operative to communicate with one or more other transceivers via a Radio Access Network (RAN) according to one or more communication protocols known in the art or that may be developed, such as IEEE 802. xx, CDMA, WCDMA, GSM, LTE, NR, LITRAN, WiMax, NB-loT, or the like. The transceiver 56, 66 implements transmitter and receiver functionality appropriate to the RAN links (e.g., frequency allocations and the like).

[0091] In all aspects, the communication circuitry 68 may comprise a receiver and transmitter interface used to communicate with one or more other nodes over a communication network according to one or more communication protocols known in the art or that may be developed, such as Ethernet, TCP / IP, SONET, ATM, IMS, SIP, or the like. The communication circuitry 68 implements receiver and transmitter functionality appropriate to the communication network links (e.g., optical, electrical, and the like). The transmitter and receiver functions may share circuit components and / or software, or alternatively may be implemented separately.

[0092] Aspects of the present disclosure provide numerous advantages over the prior art, and may also provide one or more of the following technical advantage(s). By rotating (or other mapping of) the phase comparison circuits 42 utilized by each PLL 12, the phase errors average out, resulting in greatly reduced phase error between PLLs 12. This accuracy is critical to beamforming at mmWave frequencies. The PLL system 30 also facilitates collecting the phase comparison circuits centrally, simplifying and equalizing wiring, and reducing the effects of disparate temperature variations across an IC.

[0093] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used. All references to a / an / the element, apparatus, component, means, step, etc., are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step. Any feature of any of the aspects disclosed herein may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any other aspects, and vice versa. Other objectives, features and advantages of the enclosed aspects will be apparent from the description.

[0094] The term “unit” may have conventional meaning in the field of electronics, electrical devices and / or electronic devices and may include, for example, electrical and / or electronic circuitry, devices, modules, processors, memories, logic solid state and / or discrete devices, P110867W001 computer programs or instructions for carrying out respective tasks, procedures, computations, outputs, and / or displaying functions, and so on, as such as those that are described herein.

[0095] As used herein, the term “configured to” means set up, organized, adapted, or arranged to operate in a particular way; the term is synonymous with “designed to,” or with respect to processing circuitry, “programmed to.”

[0096] Some of the aspects contemplated herein are described more fully with reference to the accompanying drawings. Other aspects, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the aspects set forth herein; rather, these aspects are provided by way of example to convey the scope of the subject matter to those skilled in the art.

[0097] The present disclosure may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the disclosure. The present aspects are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended aspects are intended to be embraced therein.

Claims

P110867W001CLAIMSClaims:

1. A system (30) of Phase Locked Loop (PLL) circuits (12) characterized by: a number N of PLL circuits (12), each comprising a variable oscillator (16) and control loop, and having an output to provide a PLL signal (CKO / CKV) and an input to receive a representation of a phase difference signal; a same number N (32) of phase comparison circuits (24), each having a first input configured to receive a PLL signal (CKO / CKV), a second input configured to receive a common reference clock signal (REF), and an output configured to output a representation of a phase difference; an input multiplexing bank (34) interposed between the N PLLs (12) and the N phase comparison circuits (24), and configured to mutually exclusively connect the outputs of the N PLL circuits with the first inputs of the N phase comparison circuits, in response to a first control signal; an output multiplexing bank (38) interposed between the N phase comparison circuits (24) and the N PLL circuits (12), and configured to mutually exclusively connect the outputs of the N phase comparison circuit to the inputs of the N PLL circuits in response to a second control signal; and a controller (36) configured to generate the first and second control signals and to map the same PLL circuit (12) to the first input and the output of each phase comparison circuit (24).

2. The system (30) of claim 1, wherein the PLL signals (CKO) output by the N PLLs (12) are outputs of the variable oscillators (16).

3. The system (30) of claim 1, wherein each PLL circuit (12) is further characterized by a frequency divider (20), and wherein the PLL signals (CKV) output by the N PLLs (12) are outputs of the frequency dividers (20).

4. The system (30) of any preceding claim, whereby the controller (36) is further configured to periodically change the mutually exclusive mapping of PLLs (12) to phase comparison circuits (24) so as to average out errors in the phase comparison circuits among the PLLs (12).

5. The system (30) of any preceding claim, wherein the input multiplexing bank (34) comprises N multiplexers, each having N inputs connected to the N PLL signal outputs in the same order, and one output connected to the first input of a different one of the N phase comparison circuits (24).22P110867W0016. The system (30) of any preceding claim, wherein the output multiplexing bank (38) comprises N multiplexers, each having N inputs connected to the N phase comparison circuit (24) outputs in the same order, and one output connected to the phase difference input of a different one of the N PLLs (12).

7. The system (30) of any preceding claim wherein the PLLs (12) are digital PLLs (12); and the phase comparison circuits (24) comprise Time to Digital Converter, TDC, circuits (24).

8. The system (30) of any of claims 1-4 wherein the PLLs (12) are analog PLLs (12); and the phase comparison circuits (24) comprise Phase Detector, PD, circuits (24).

9. The system (30) of any preceding claim wherein the phase comparison circuits (24) are proximally located together on an integrated circuit, IC, and the PLLs (12) are distributed over the IC.

10. A Radio Frequency, RF, transceiver circuit (56, 66) connected to a plurality of antenna elements (59, 69), the RF transceiver circuit (56, 66) comprising the distributed PLL system (30) of any of claims 1-8.

11. A User Equipment, UE (50), operative in a wireless communication network (40), the UE (50) comprising: a plurality of antenna elements (59); and the RF transceiver circuit (56) of claim 10.

12. A base station (60) operative in a wireless communication network (40), the base station (60) comprising: a plurality of antenna elements (69); and the RF transceiver circuit (66) of claim 10.

13. A method (100) of reducing phase deviation for a number N of Phase Locked Loop, PLL, circuits (12), characterized by: receiving (102) an output signal (CKO / CKV) from each of the N PLL circuits (12); for a first duration (110),P110867W001 mutually exclusively mapping (104) the N PLL circuit (12) output signals (CKO / CKV) to N phase comparison circuits (24) according to a first control signal; at each of the N phase comparison circuits (24), comparing (106) a PLL circuit (12) output signal (CKO / CKV) to a common reference clock signal (REF) and outputting a representation of a phase difference; and mutually exclusively mapping (108) the outputs of the N phase comparison circuits (24) to the N PLL circuits (12) according to a second control signal; wherein the first and second control signals are configured to map the same PLL circuit (12) to both the input and the output of each phase comparison circuit (24); and for a second duration (110), repeating the mapping and comparing steps (104-108) wherein the first and second control signals are configured (112) to map each PLL circuit (12) to a different phase comparison circuit (24) than in the first duration.

14. The method (100) of claim 13, wherein the PLL circuit (12) output signals (CKO) are outputs of variable oscillators (16) in the PLL circuits (12).

15. The method (100) of claim 13, wherein the PLL circuit (12) output signals (CKV) are outputs of frequency dividers (20) in the PLL circuits (12).

16. The method (100) of any of claim 13-15, further comprising periodically changing the mutually exclusive mapping of PLL circuits (12) to phase comparison circuits (24) so as to average out errors in the phase comparison circuits among the PLL circuits (12).

17. The method (100) of any of claims 13-16 wherein the PLL circuits (12) are digital PLL circuits (12); and the phase comparison circuits (24) comprise Time to Digital Converter, TDC, circuits (24).

18. The method (100) of any of claims 13-16 wherein the PLL circuits (12) are analog PLL circuits (12); and the phase comparison circuits (24) comprise Phase Detector, PD, circuits (24).P110867W00119. The method (100) of any of claims 13-18 wherein the phase comparison circuits (24) are proximally located together on an integrated circuit, IC, and the PLL circuits (12) are distributed over the IC.

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