Digital circuits and communication devices

Abstract

The present disclosure relates to a kind of digital circuit and communication device, and it relates to communication technical field.The digital circuit includes first signal processing module, with baseband processing module connection, is configured to the input signal of first signal processing module carries out first sampling rate conversion and first frequency shift;Second signal processing module includes multiple sub-modules in cascade, multiple sub-modules include first sub-module and second sub-module, first sub-module is connected with first signal processing module, and is located in one end of multiple sub-modules, second sub-module is connected with data converter, and is located in the other end of multiple sub-modules, each sub-module in multiple sub-modules is configured to the input signal of sub-module carries out second sampling rate conversion and second frequency shift;Frequency shift configuration module is connected with each sub-module in first signal processing module and second signal processing module, is configured to set the frequency shift amount of each sub-module in first signal processing module and second signal processing module for frequency shift.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a digital circuit and communication device. Background Technology

[0002] The conversion between digital and analog signals is fundamental to electronic systems, achieved through analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). ADCs convert analog signals to digital signals, while DACs convert digital signals to analog signals; together, they support the signal interaction and functional implementation of electronic devices. Summary of the Invention

[0003] One of the technical problems that this disclosure aims to solve is: how to reduce the power consumption of digital circuits.

[0004] According to one aspect of some embodiments of this disclosure, a digital circuit is provided, comprising: a first signal processing module connected to a baseband processing module and configured to perform a first sampling rate transformation and a first frequency shift on an input signal of the first signal processing module; a second signal processing module including a plurality of cascaded sub-modules, the plurality of sub-modules including a first sub-module and a second sub-module, the first sub-module being connected to the first signal processing module and located at one end of the plurality of sub-modules, the second sub-module being connected to a data converter and located at the other end of the plurality of sub-modules, each of the plurality of sub-modules being configured to perform a second sampling rate transformation and a second frequency shift on an input signal of the sub-module; and a frequency shift configuration module connected to each of the first signal processing module and the second signal processing module and configured to set the frequency shift amount performed by each of the first signal processing module and the second signal processing module.

[0005] In some embodiments, the frequency shift amount of each submodule in the second signal processing module is determined from a plurality of specified values, and the frequency shift amount of the first signal processing module is determined based on the difference in frequency points of the signals processed by the baseband processing module and the data converter, and the frequency shift amount of the second signal processing module.

[0006] In some embodiments, for each submodule, the submodule includes a first filter and a frequency shifting module connected to the first filter. The first filter is configured to perform a second sampling rate transformation on the input signal of the first filter, and the frequency shifting module is configured to perform a second frequency shift on the input signal of the frequency shifting module. The frequency shift amount is determined from 0, fs / 4, -fs / 4, -fs / 2, and fs / 2, where fs is the sampling rate of the input signal of the frequency shifting module.

[0007] In some embodiments, the frequency shift configuration module is configured to: determine the frequency point corresponding to each submodule based on the sampling rate of the data converter and the frequency point of the signal processed by the data converter; determine the frequency shift amount of each submodule from 0, fs / 4, -fs / 4, -fs / 2, and fs / 2 based on the frequency point corresponding to each submodule; wherein, the frequency point corresponding to the second submodule is a first value, the first value being the frequency point of the signal processed by the data converter; for other submodules among the multiple submodules besides the second submodule, the frequency point corresponding to the submodule is a second value, the second value being the difference between the frequency point corresponding to the submodule connected to the submodule and the frequency shift amount, and the frequency point corresponding to the submodule closest to the data converter.

[0008] In some embodiments, the first filter is a half-band filter, the sampling rate of the input signal of the frequency shift module of the second submodule is the sampling rate of the data converter, and the frequency shift amount of the second submodule is 0, fs / 4, -fs / 4, -fs / 2 or fs / 2; for the other submodules among the multiple submodules besides the second submodule, the sampling rate of the submodule is 1 / 2 of the sampling rate of the submodule connected to the submodule and close to the data converter, and the frequency shift amount of the submodule is 0, fs / 4 or -fs / 4.

[0009] In some embodiments, the frequency shift module is configured to perform at least one of the logical processing of crossing and phase reversal on the real and imaginary parts of the input signal of the frequency shift module according to the frequency shift amount.

[0010] In some embodiments, the data converter is a digital-to-analog converter, the first filter is a half-band interpolation filter, the output signal of the half-band interpolation filter in the submodule is the input signal of the frequency shift module in the submodule, and the output signal of the frequency shift module is the output signal of the submodule.

[0011] In some embodiments, the data converter is an analog-to-digital converter, the first filter is a half-band decimation filter, the output signal of the frequency shift module in the submodule is the input signal of the half-band decimation filter in the submodule, and the output signal of the half-band decimation filter is the output signal of the submodule.

[0012] In some embodiments, for each submodule, the passband of the first filter in the submodule is determined based on the sampling rate and bandwidth of the input signal of the frequency shift module of the submodule.

[0013] In some embodiments, the data converter is a digital-to-analog converter, and the output signal of the baseband processing module is processed by the first signal processing module and the second signal processing module to form the input signal of the digital-to-analog converter.

[0014] In some embodiments, the data converter is an analog-to-digital converter, and the output signal of the analog-to-digital converter is processed by the second signal processing module and the first signal processing module to form the input signal of the baseband processing module.

[0015] In some embodiments, the first signal processing module includes a second filter and a digitally controlled oscillator (NCO) connected to the second filter. The second filter is configured to perform a first sampling rate transformation on the input signal of the second filter, and the NCO is configured to perform a first frequency shift on the input signal of the NCO. The frequency shift amount is the difference between the frequency point corresponding to the first submodule and the frequency shift amount.

[0016] According to another aspect of some embodiments of this disclosure, a communication device is provided, including: digital circuitry as described above; a baseband processing module; and a data converter.

[0017] The digital circuit disclosed herein performs sampling rate conversion and frequency shifting on the signal between the baseband processing module and the digital-to-analog converter in sequence through multiple modules. Compared with placing a digitally controlled oscillator at a high-rate position closest to the data converter, this can greatly reduce the power consumption of the digital circuit.

[0018] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a typical digital circuit for a direct RF sampling architecture is shown.

[0021] Figure 2 A schematic diagram of a digital circuit according to some embodiments of the present disclosure is shown.

[0022] Figure 3 A schematic diagram of a digital circuit according to some other embodiments of the present disclosure is shown.

[0023] Figure 4 A schematic diagram of a digital circuit according to some other embodiments of the present disclosure is shown.

[0024] Figure 5 A schematic diagram illustrating the determination of frequency shift amount according to some embodiments of the present disclosure is shown.

[0025] Figure 6 A schematic diagram of the passband of a first filter according to some embodiments of the present disclosure is shown.

[0026] Figure 7A schematic diagram illustrating the determination of frequency shift amount according to other embodiments of the present disclosure is shown.

[0027] Figure 8 A schematic diagram of a digital circuit according to some other embodiments of the present disclosure is shown.

[0028] Figure 9 A schematic diagram of the structure of a communication device according to some embodiments of the present disclosure is shown. Detailed Implementation

[0029] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0030] RF direct sampling architecture and zero-IF architecture are two different RF signal processing technologies. Compared to zero-IF architecture, RF direct sampling architecture can sample high-frequency RF signals without analog frequency conversion, thus eliminating the need for components such as analog local oscillators. This makes the analog circuit design simpler, and the digital frequency conversion accuracy is higher, avoiding problems such as IQ mismatch and local oscillator leakage.

[0031] However, the RF direct sampling architecture needs to process high-speed RF signals in the digital domain, which places high demands on the sampling rate of the analog-to-digital converter (ADC) or digital-to-analog converter (DAC), and the power consumption of digital circuits at high speeds is also relatively high, resulting in high power consumption.

[0032] Figure 1 A schematic diagram of a typical digital circuit for a direct RF sampling architecture is shown. Figure 1 Figure 1-1 illustrates the transmit link of the RF direct acquisition architecture. Figure 1 Figure 1-2 illustrates the receiving link of the RF direct acquisition architecture.

[0033] Figure 1 In 1-1, HBF represents a double interpolation anti-aliasing filter based on a half-band filter architecture, and RSMP represents an interpolation anti-aliasing filter with arbitrary multiple rate. Figure 1 In 1-2, HBF represents a 2x decimation anti-aliasing filter based on a half-band filter architecture, and RSMP represents an arbitrary decimation anti-aliasing filter with variable rate.

[0034] Because HBF (Hyper-Band Filter) features symmetrical passband and stopband and zero effective coefficient spacing, the number of multipliers is reduced from n to n / 2+1 compared to traditional finite impulse response (FIR) digital filters, making it particularly suitable for digital interpolation / decimation variable rate filter links. Therefore, in RF direct-sampling architectures, HBF is often placed at high rate (i.e., close to the DAC / ADC), while RSMP (Reduced Rate Multiplier) is placed at low rate. Figure 1 As shown, the HBF is positioned between the RSMP and the DAC / ADC. The digitally controlled oscillator (NCO) is positioned closest to the DAC / ADC at the highest possible speed.

[0035] for Figure 1 As shown in Figure 1-1, the baseband zero-frequency signal is interpolated by RSMP and multiple HBFs, then converted to the RF signal frequency (also called the RF frequency point) by the NCO, and finally converted to the RF signal output by the DAC. For Figure 1 As shown in Figure 1-2, the NCO first down-converts the RF signal output from the ADC to the baseband frequency, and then performs downsampling step by step. That is, the NCO operates at a high rate close to that of the ADC / DAC, resulting in significant power consumption. Statistics show that in typical RF direct sampling transmitter / receiver circuits, the NCO accounts for approximately 30% of the total power consumption of the digital circuit.

[0036] Therefore, in existing RF direct-sampling architectures, the final-stage NCO (i.e., the NCO located at the high-rate position closest to the DAC / ADC) results in significant power consumption, which is one of the key reasons for the power consumption disadvantage of RF direct-sampling architectures compared to other transceiver architectures. Based on this, this disclosure provides a digital circuit that eliminates the need for a final-stage NCO. Instead, it uses multiple modules to perform step-by-step frequency conversion, shifting the NCO to a lower-rate position, thereby reducing the power consumption of the digital circuit.

[0037] Figure 2 A schematic diagram of a digital circuit according to some embodiments of the present disclosure is shown. For example... Figure 2 As shown, the digital circuit of this embodiment includes the following modules.

[0038] The first signal processing module 21 is connected to the baseband processing module and is configured to perform a first sampling rate transformation and a first frequency shift on the input signal of the first signal processing module.

[0039] The second signal processing module 22 includes multiple cascaded sub-modules, including a first sub-module and a second sub-module. The first sub-module is connected to the first signal processing module and located at one end of the multiple sub-modules. The second sub-module is connected to a data converter and located at the other end of the multiple sub-modules. Each sub-module is configured to perform a second sampling rate transformation and a second frequency shift on the input signal of the sub-module. That is, one end of the cascaded multiple sub-modules is the first sub-module connected to the first signal processing module, and the other end is the second sub-module connected to the data converter. The first sub-module and the second sub-module are connected to each other through at least one sub-module.

[0040] The frequency shift configuration module 23 is connected to each sub-module in the first signal processing module and the second signal processing module, and is configured to set the frequency shift amount for each sub-module in the first signal processing module and the second signal processing module.

[0041] The first signal processing module 21 is a module located at a low-rate position in the digital circuit. It is connected to the baseband processing module and is used to process the output signal of the baseband processing module or process the signal into the input signal of the baseband processing module. The baseband processing module is also known as the baseband unit, and the output signal of the baseband unit is the baseband signal, which is the original electrical signal with a frequency concentrated near zero frequency.

[0042] The second signal processing module 22 includes multiple cascaded sub-modules, one end of which is connected to the first signal processing module 21, and the other end is connected to a data converter. The data converter is an analog-to-digital converter or a digital-to-analog converter.

[0043] In some embodiments, the data converter is a digital-to-analog converter. The output signal (i.e., the baseband signal) of the baseband processing module is processed by the first signal processing module and the second signal processing module to form the input signal (i.e., the signal at the radio frequency point) of the digital-to-analog converter, and then converted into a radio frequency signal output by the digital-to-analog converter.

[0044] In some embodiments, the data converter is an analog-to-digital converter. The output signal (i.e., radio frequency signal) of the analog-to-digital converter is processed by the second signal processing module and the first signal processing module to form the input signal (i.e., baseband signal) of the baseband processing module.

[0045] That is, the digital circuit disclosed herein can be either a transmit link or a receive link in a direct RF sampling architecture. When the second submodule is connected to a digital-to-analog converter, the first signal processing module 21 and the second signal processing module 22 include devices for converting baseband frequencies to RF frequencies, such as an interpolation filter for increasing the sampling rate and a frequency shifting module for shifting the baseband frequency to the RF signal frequency. When the second submodule is connected to an analog-to-digital converter, the first signal processing module 21 and the second signal processing module 22 include devices for converting RF frequencies to baseband frequencies, such as a decimation filter for reducing the sampling rate and a frequency shifting module for shifting the RF signal frequency to the baseband signal frequency.

[0046] The signal frequency shift is accomplished jointly by the first signal processing module 21 and the second signal processing module 22. For example, when the second submodule is connected to a digital-to-analog converter (DAC), the digital circuit of this disclosure serves as the transmit link. The first signal processing module 21 and the second signal processing module 22 shift the signal from zero frequency to an RF frequency. This RF frequency is predetermined and meets the input requirements of the DAC; for example, the RF frequency is located within the bandwidth range and Nyquist interval of the DAC. Similarly, when the second submodule is connected to an analog-to-digital converter (ADC), the frequency of the RF signal emitted by the ADC is shifted to zero frequency. The frequency of the RF signal emitted by the ADC is also predetermined. That is, the amount of frequency shift that the first signal processing module 21 and the second signal processing module 22 need to jointly accomplish is predetermined.

[0047] The frequency shift configuration module 23 is configured to set the frequency shift amount for each sub-module in the first signal processing module 21 and the second signal processing module 22. That is, the frequency shift configuration module 23 is configured to determine the frequency shift amount of each module according to the sampling rate and radio frequency of the data converter, so that the first signal processing module 21 and the second signal processing module 22 can jointly complete the frequency shift of the signal.

[0048] The digital circuit disclosed herein performs sampling rate conversion and frequency shifting on the signal between the baseband processing module and the digital-to-analog converter in sequence through multiple modules. Compared with placing a digitally controlled oscillator at a high-rate position closest to the data converter, this can greatly reduce the power consumption of the digital circuit.

[0049] Figure 3 Schematic diagrams of digital circuits according to other embodiments of the present disclosure are shown. For example... Figure 3 As shown, the second submodule is connected to the digital-to-analog converter, and the digital circuit in this embodiment is the transmission link.

[0050] Figure 4 Schematic diagrams of digital circuits according to other embodiments of the present disclosure are shown. For example... Figure 4As shown, the second submodule is connected to the analog-to-digital converter, and the digital circuit in this embodiment is the receiving link.

[0051] Figure 3 and Figure 4 Taking the first information processing module, which includes RSMP and NCO, and each submodule in the second information processing module, which includes HBF and a frequency shifting module, as an example. Figure 3 In the above, RSMP and HBF are interpolation filters, and NCO is used for up-conversion. Figure 3 In this configuration, RSMP and HBF are decimation filters, and NCO is used for down-conversion.

[0052] The frequency shift amount of each submodule in the second signal processing module is determined from a plurality of specified values. The frequency shift amount of the first signal processing module is determined based on the difference in frequency points of the signals processed by the baseband processing module and the data converter, and the frequency shift amount of the second signal processing module. It can be understood that when the second submodule is connected to a digital-to-analog converter, this difference is the RF frequency point minus the baseband frequency point; when the second submodule is connected to an analog-to-digital converter, this difference is the baseband frequency point minus the RF frequency point.

[0053] For example, for Figure 3 The transmission link shown requires shifting the signal from zero frequency to radio frequency point fc. Therefore, the total frequency shift required by the first and second signal processing modules is fc. The frequency shift amount for each sub-module is determined from multiple specified values. The frequency shift amount for the first signal processing module is the difference between the total frequency shift fc and the frequency shift amount for the second signal processing module. In other words, the sum of the first frequency shift amount from the first signal processing module and the second frequency shift amount from the second signal processing module is the total frequency shift amount fc.

[0054] The first signal processing module and the second signal processing module include a module for sampling rate conversion and a module for frequency shifting.

[0055] In the multiple sub-modules of the second signal processing module, each sub-module includes a first filter and a frequency shifting module connected to the first filter. The first filter is configured to perform a second sampling rate transformation on the input signal of the first filter, and the frequency shifting module is configured to perform a second frequency shift on the input signal of the frequency shifting module. The frequency shift amount is determined from 0, fs / 4, -fs / 4, -fs / 2, and fs / 2, where fs is the sampling rate of the input signal of the frequency shifting module.

[0056] The specified values ​​are 0, fs / 4, -fs / 4, -fs / 2, and fs / 2. When the frequency shift is 0, fs / 4, -fs / 4, -fs / 2, or fs / 2, circuit design is simplified and power consumption is reduced. This means the frequency shift module does not require complex multipliers; frequency shifting can be achieved through logic processing. In other words, the frequency shift module is configured to perform at least one of the following logical processes on the real and imaginary parts of the input signal based on the frequency shift amount: crossing and phase inversion.

[0057] Let the real part of the input signal of the frequency shift module be I and the imaginary part be Q, and the real part of the output signal be I' and the imaginary part be Q'. Then the relationship between the output signal and the input signal of the frequency shift module is shown in Table 1.

[0058] Table 1

[0059] .

[0060] Furthermore, when the frequency shift is 0, the input signal is not processed.

[0061] Taking a digital frequency shift of fs / 4 as an example, if the input signal samples are (1, 0), (0, 1), (-1, 0), (0, -1)..., then the output samples are (1, 0), (-1, 0), (1, 0), (-1, 0)... The output is then processed according to the rules shown in Table 1. In other words, when the digital frequency shift is fs / 4, the logic processing cycle of the frequency shift module is 4.

[0062] As shown in Table 1, the frequency shift module achieves digital frequency shift by performing crossover and phase reversal operations on the real and imaginary parts of the input signal. The frequency shift module is equivalent to an I / Q conversion module, eliminating the need for complex multipliers, thus reducing hardware resource consumption and noise introduction.

[0063] The frequency shift of each submodule in the second signal processing module is 0, fs / 4, -fs / 4, -fs / 2, or fs / 2. That is, the frequency shift of each submodule in the second signal processing module is determined from these values ​​and is relatively fixed. The frequency shift of the first signal processing module, however, is relatively variable; it is not determined from a specified value, but rather is the difference between the total frequency shift and the frequency shift of the second signal processing module.

[0064] This disclosure describes a frequency shift module that uses a specified value of frequency shift at high-rate positions in a digital circuit. This allows the NCO to be set at low-rate positions in the digital circuit to compensate for the remaining frequency shift, thus eliminating the need to set the NCO at high-rate positions in the digital circuit and reducing the power consumption of the NCO.

[0065] That is, the first signal processing module includes a second filter and a digitally controlled oscillator (NCO) connected to the second filter. The second filter is configured to perform a first sampling rate transformation on its input signal, and the NCO is configured to perform a first frequency shift on its input signal. The frequency shift amount is the difference between the frequency point corresponding to the first submodule and the frequency shift amount. Here, the difference between the frequency point corresponding to the first submodule and the frequency shift amount is the difference between the total frequency shift amount and the frequency shift amount of the second signal processing module, which will be explained later.

[0066] like Figure 3 and Figure 4 As shown, the frequency shift configuration module is connected to the NCO in the first signal processing module and the frequency shift module in each submodule of the second signal processing module, and is used to configure the frequency shift amount. The frequency shift configuration module configures the frequency shift amount according to the sampling rate and radio frequency of the data converter. That is, the frequency shift configuration module can configure the frequency shift amount of each module, enabling these modules to complete the transfer between the baseband frequency and the radio frequency.

[0067] In some embodiments, the frequency shift configuration module is configured to: determine the frequency point corresponding to each submodule based on the sampling rate of the data converter and the frequency point (i.e., the radio frequency point) of the signal processed by the data converter; determine the frequency shift amount of each submodule from 0, fs / 4, -fs / 4, -fs / 2, and fs / 2 based on the frequency point corresponding to each submodule; wherein, the frequency point corresponding to the second submodule is a first value, the first value being the frequency point (i.e., the radio frequency point) of the signal processed by the data converter; and for other submodules among the multiple submodules besides the second submodule, the frequency point corresponding to the submodule is a second value, the second value being the difference between the frequency point and the frequency shift amount of the submodule connected to the submodule and the submodule closest to the data converter.

[0068] The following is based on Figure 3 The process of determining the frequency shift amount of each module is described using the transmit link shown as an example. Figure 3 In the transmitted link shown, the data converter is a digital-to-analog converter, and the first filter is a half-band interpolation filter. The output signal of the half-band interpolation filter in the submodule is the input signal of the frequency shift module in the submodule, and the output signal of the frequency shift module serves as the output signal of the submodule. The input signal of the submodule serves as the input signal of the first filter of that submodule. Here, the first filter is a half-band interpolation filter because the characteristics of half-band filters are suitable for digital interpolation / decimation variable rate filter links. In fact, the first filter can also be other types of interpolation filters.

[0069] The sampling rate of the digital-to-analog converter (DAC) is fs(DAC), and the radio frequency is fc1. The core function of the DAC is to convert digital signals into analog signals; therefore, its input signal follows the Nyquist rule for the DAC's sampling rate fs, meaning fc1 lies within (-fs(DAC) / 2, fs(DAC) / 2). In other words, the output signal fc1 of the frequency shift module in the second submodule lies within (-fs(DAC) / 2, fs(DAC) / 2), and its sampling rate is fs(DAC). Since the output signal of the first filter in the second submodule is the input signal of the frequency shift module, and the first filter is used for sampling rate conversion, the sampling rate of the input signal of the frequency shift module is fs(DAC).

[0070] Figure 3 The output signal of the baseband processing module is shifted step-by-step to fc1 by the first and second signal processing modules to form the input signal of the DAC. During calculation, the frequency shift amount of the frequency shift module in the second sub-module can be determined first based on fs(DAC) and fc1, and then the frequency shift amounts of other modules can be deduced. That is, the frequency shift amount of each module is derived from the final RF signal, which is equivalent to calculating the frequency point from fc1 to 0 during the calculation process.

[0071] Let the first submodule in the second information processing module be Module 1, the submodules connected to the first submodule be Module 2, ..., and the second submodule be Module n. The frequency of the output signal of Module i is fc(i), the sampling rate is fs(i), and the frequency shift is f(i). At this time, the frequency corresponding to Module i is the frequency of the output signal of Module i.

[0072] Then fs(n) = fs(DAC), fc(n) = fc1. Figure 5 A schematic diagram illustrating the determination of frequency shift amount according to some embodiments of the present disclosure is shown. Figure 5 It is shown that when determining the frequency shift amount of module n, (-fs(n) / 2, fs(n) / 2) can be divided into 8 intervals, and the frequency shift amount of module n can be determined according to the interval hit by fc(n).

[0073] When fc(n) hits interval 1, the frequency shift f(n) is configured to be 0.

[0074] When fc(n) hits interval 2, the frequency shift f(n) is configured as fs(n) / 4.

[0075] When fc(n) hits interval 3, the frequency shift f(n) is configured as fs(n) / 4.

[0076] When fc(n) hits interval 4, the frequency shift f(n) is configured as fs(n) / 2.

[0077] When fc(n) hits interval 5, the frequency shift f(n) is configured as -fs(n) / 2 (equivalent to fs(n) / 2).

[0078] When fc(n) hits interval 6, the frequency shift f(n) is configured as -fs(n) / 4.

[0079] When fc(n) hits interval 7, the frequency shift f(n) is configured as -fs(n) / 4.

[0080] When fc(n) hits interval 8, the frequency shift f(n) is configured to be 0.

[0081] For module n, the frequency shift amount is determined by choosing the value among 0, fs(n) / 4, -fs(n) / 4, -fs(n) / 2, and fs(n) / 2 that is closest to the frequency point corresponding to module n. For example, when fc hits interval 2, among 0, fs(n) / 4, -fs(n) / 4, -fs(n) / 2, and fs(n) / 2, fc is closest to fs(n) / 4, so the frequency shift amount is configured as fs(n) / 4.

[0082] This configuration allows the radio frequency signal to be moved as close to zero as possible, thus improving frequency shift efficiency. Furthermore, because... Figure 3 The transmission link shown actually shifts the zero frequency to the radio frequency point. That is, the actual frequency shift is the opposite of the frequency shift calculated above. Therefore, for example, when fc hits interval 2, the frequency shift from fc to the zero frequency is -fs(n) / 4, but the actual frequency shift of the determined module n is configured as fs(n) / 4.

[0083] The remaining frequency shift amount allocated to module n-1 is fc(n-1) = fc(n) - f(n), and combined with Figure 5 It can be seen that |fc(n-1)| does not exceed fs(n) / 8. Taking fc hitting interval 2 as an example, the frequency of the output signal of module n-1 is fc(n-1), which falls within interval 8, that is, |fc(n-1)| does not exceed fs(n) / 8. Similarly, it can be calculated that when fc hits other intervals, |fc(n-1)| does not exceed fs(n) / 8.

[0084] In other words, for module n, the center frequency of its input signal is in the range of (-fs(n) / 8, fs(n) / 8). Therefore, the passband bandwidth of the first filter in module n can be set to fs(n) / 8 + BW / 2, where BW is the inherent bandwidth of the signal.

[0085] Similarly, the passbands of other modules are also set based on the sampling rate of the input signal of the frequency shift module. That is, for each submodule, the passband of the first filter in the submodule is determined based on the sampling rate and bandwidth of the input signal of the frequency shift module of the submodule.

[0086] Figure 6 A schematic diagram of the passband of a first filter according to some embodiments of the present disclosure is shown. Figure 6 As shown, the signal's own bandwidth is BW / 2. For the first filter in module n, its passband bandwidth can be set to fs(n) / 8+BW / 2.

[0087] The above describes the process of setting the passband of the first filter in module n and determining the frequency shift amount of the frequency shift module. The following describes the process of setting the passband of the first filter in module n-1 and determining the frequency shift amount of the frequency shift module.

[0088] As described above, |fc(n-1)| does not exceed fs(n) / 8, and the first filter is a half-band interpolation filter, meaning the sampling rate of the input signal of module i is half of the sampling rate of the input signal of module i. Therefore, fs(n) / 8 = fs(n-1) / 4. Thus, for module n-1, only the frequency shift range of (-fs(n-1) / 4, fs(n-1) / 4) needs to be considered.

[0089] Figure 7 A schematic diagram illustrating the determination of frequency shift amount according to other embodiments of the present disclosure is shown. Figure 7 It is shown that when determining the frequency shift amount of module n-1, (-fs(n-1) / 4, fs(n-1) / 4) can be divided into 4 intervals, and the frequency shift amount of module n-1 can be determined according to the interval hit by fc.

[0090] fs(n-1)=fs(n) / 2, fc(n-1)=fc(n)-f(n), and the following rules apply.

[0091] When fc(n-1) hits interval 1, the frequency shift f(n-1) is configured as -fs(n-1) / 4.

[0092] When fc(n-1) hits interval 2, the frequency shift f(n-1) is configured to be 0.

[0093] When fc(n-1) hits interval 3, the frequency shift f(n-1) is configured to be 0.

[0094] When fc(n-1) hits interval 4, the frequency shift f(n-1) is configured as fs(n-1) / 4.

[0095] The configuration logic for the frequency shift amount of module n-1 is similar to that of module n. It is to determine the frequency shift amount of module n-1 by taking the value among 0, fs(n-1) / 4, and -fs(n-1) / 4 that is closest to the frequency point corresponding to module n-1.

[0096] The remaining frequency shift amount allocated to module n-2 is fc(n-2) = fc(n-1) - f(n-1), and combined with Figure 7 We can conclude that |fc(n-2)| does not exceed fs(n-1) / 8. Therefore, for module n-1, the center frequency of its input signal is in the range of (-fs(n-1) / 8, fs(n-1) / 8). The passband of the first filter in module n-1 can be set to fs(n-1) / 8 + BW / 2.

[0097] The process of setting the passband of the first filter in modules n-2 to 1 and determining the frequency shift amount of the frequency shift module is similar to that described above. Furthermore, it can be concluded that the passband of the first filter in module i can be set to fs(i) / 8+BW / 2.

[0098] The above process combined Figure 3 This describes the process of determining the frequency shift and passband of each submodule in the second signal processing module when the data converter is a digital-to-analog converter. The process of determining the frequency shift and passband of each module in the second signal processing module is similar when the data converter is an analog-to-digital converter. The following section combines... Figure 4 Provide a brief description.

[0099] exist Figure 4 In the received link shown, the data converter is an analog-to-digital converter, the first filter is a half-band decimation filter, the output signal of the frequency shift module in the submodule is the input signal of the half-band decimation filter in the submodule, and the output signal of the half-band decimation filter serves as the output signal of the submodule. The input signal of the submodule serves as the input signal of the frequency shift module of that submodule.

[0100] The analog-to-digital converter (ADC) has a sampling rate of fs(ADC) and a radio frequency of fc2, where fc2 lies within (-fs(ADC) / 2, fs(ADC) / 2). That is, the input signal fc2 of the frequency shift module in the second submodule lies within (-fs(ADC) / 2, fs(ADC) / 2) and has a sampling rate of fs(ADC). Since the output signal of the frequency shift module in the second submodule is the input signal of the first filter, and the frequency shift module is used for frequency shifting, the sampling rate of the input signal of the first filter is fs(ADC).

[0101] Figure 5 The output signal of the analog-to-digital converter (ADC) is shifted from the radio frequency to zero frequency through the second and first signal processing modules, forming the input signal of the baseband processing module. Similar to the digital-to-analog converter (DAC) described above, during calculation, the frequency shift amount of the frequency shift module in the second sub-module can be determined first based on fs (ADC) and fc2, and then the frequency shift amounts of other modules can be calculated. That is, the frequency point is calculated from fc2 to 0 during the calculation process.

[0102] Let's still remember that in the second information processing module, the first submodule is module 1, the submodules connected to the first submodule are module 2, ..., and the second submodule is module n. The frequency of the input signal of module i is fc(i), the sampling rate is fs(i), and the frequency shift is f(i). At this time, the frequency corresponding to module i is the frequency of the input signal of module i.

[0103] Then fs(n) = fs(ADC), fc(n) = fc². This can still be combined with... Figure 5 The calculation is performed, but the rules for the frequency shift amount configured when fc(n) hits each interval need to be updated. This is because... Figure 4 The receiving link shown shifts the RF signal to the baseband zero-frequency signal. The actual frequency shift is the same as the calculated shift. Therefore, for example, when fc hits interval 2, the frequency shift from fc to zero is -fs(n) / 4, and the actual frequency shift should also be configured as -fs(n) / 4. The rules for configuring the frequency shift when fc(n) hits each interval are as follows.

[0104] When fc(n) hits interval 1, the frequency shift f(n) is configured to be 0.

[0105] When fc(n) hits interval 2, the frequency shift f(n) is configured as -fs(n) / 4.

[0106] When fc(n) hits interval 3, the frequency shift f(n) is configured as -fs(n) / 4.

[0107] When fc(n) hits interval 4, the frequency shift f(n) is configured as -fs(n) / 2.

[0108] When fc(n) hits interval 5, the frequency shift f(n) is configured as fs(n) / 2 (equivalent to -fs(n) / 2).

[0109] When fc(n) hits interval 6, the frequency shift f(n) is configured as fs(n) / 4.

[0110] When fc(n) hits interval 7, the frequency shift f(n) is configured as fs(n) / 4.

[0111] When fc(n) hits interval 8, the frequency shift f(n) is configured to be 0.

[0112] For module n, the frequency shift amount is determined by taking the inverse of the value among 0, fs(n) / 4, -fs(n) / 4, -fs(n) / 2, and fs(n) / 2 that is closest to the frequency point corresponding to the second sub-module. For example, when fc hits interval 2, among 0, fs(n) / 4, -fs(n) / 4, -fs(n) / 2, and fs(n) / 2, fc is closest to fs(n) / 4, so the frequency shift amount is configured as -fs(n) / 4.

[0113] The remaining frequency shift amount allocated to module n-1 is fc(n-1) = fc(n) - f(n), and combined with Figure 5 It can be seen that |fc(n-1)| does not exceed fs(n) / 8. Taking fc hitting interval 2 as an example, the frequency of the output signal of module n-1 is fc(n-1), which falls within interval 8, meaning |fc(n-1)| does not exceed fs(n) / 8. Similarly, through calculation, it can be concluded that when fc hits other intervals, |fc(n-1)| does not exceed fs(n) / 8.

[0114] The subsequent calculation process is similar to that when the data converter is a digital-to-analog converter. Furthermore, it can be concluded that the passband of the first filter in module i can be set to fs(i) / 8 + BW / 2.

[0115] From the calculation process of the above data converters being analog-to-digital converters and digital-to-analog converters, it can be deduced that when the first filter is a half-band filter, the sampling rate of the input signal of the frequency shift module of the second submodule is the sampling rate of the data converter, and the frequency shift amount of the second submodule is 0, fs / 4, -fs / 4, -fs / 2, or fs / 2; for the other submodules among the multiple submodules besides the second submodule, the sampling rate of the submodule is 1 / 2 of the sampling rate of the submodule connected to the submodule and close to the data converter, and the frequency shift amount of the submodule is 0, fs / 4, or -fs / 4.

[0116] The above describes the frequency shift amounts of each submodule in the second signal processing module when the data converter is an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). After determining the frequency shift amount of the second signal processing module, the frequency shift amount of the first signal processing module is also determined. The frequency shift amount of the first signal processing module is the difference between the total frequency shift amount and the frequency shift amount of the second signal processing module. Combined with... Figure 3 and Figure 4 It can be seen that the frequency shift of the first signal processing module is the difference between the frequency point corresponding to the first sub-module and the frequency shift, i.e., fc(1)-f(1).

[0117] Furthermore, after determining the sampling rate of the data converter and the first filter in the second signal processing module, the scaling factor of the second filter in the first signal processing module is also determined. That is, the second filter in the first signal processing module is an arbitrary scaling factor filter, and its actual application scaling factor is determined based on the sampling rate of the data converter, the sampling rate of the baseband processing module, and the scaling factor of the first filter in the second signal processing module. For example, if the first filter is a half-band filter and the sampling rate of the digital-to-analog converter is fs(DAC), the sampling rate of the input signal of the first filter in the first submodule can be determined based on fs(DAC) and the number of submodules included in the digital circuit. Therefore, the actual application scaling factor of the second filter is the quotient of the sampling rate of the input signal of the first filter and the sampling rate of the baseband processing module.

[0118] Figure 8 Schematic diagrams of digital circuits according to other embodiments of the present disclosure are shown. For example... Figure 8 As shown, this digital circuit is the transmission link. The second information processing module includes four cascaded sub-modules, and the second sub-module is connected to the digital-to-analog converter.

[0119] Taking a baseband sampling rate of 122.88MHz, a DAC sampling rate fs(DAC) of 4423.68MHz, a baseband signal bandwidth of BW=100MHz, and an RF frequency of fc of 1900MHz as an example, the frequency shift of each module and the passband settings of the filter can be obtained according to the above calculation process, as shown in Table 2.

[0120] Table 2

[0121] .

[0122] The baseband signal, after being processed by a second filter with a 9 / 4 ratio, has a sampling rate that changes from 122.88 MHz to 276.48 MHz. After being shifted by the NCO using fc_nco, the frequency point changes from 0 to -35.36 MHz. This signal forms the input signal for module 1. The input signal of module 1, after being processed by a half-band interpolation filter, has a sampling rate that changes from 276.48 MHz to 552.96 MHz. After being shifted by f(1), the frequency point changes from -35.36 to -35.26 MHz. This signal forms the input signal for module 2. After being processed by modules 2, 3, and 4, the resulting output signal has a sampling rate of 4423.68 MHz and a frequency point of 1900 MHz. This output signal meets the requirements for the input signal of the digital-to-analog converter.

[0123] Table 2 shows the calculations performed according to the calculation process described above. First, the frequency shift of module 4 is determined. The sampling rate fs(4) of the output signal of module 4 is 4423.68MHz, and the frequency point is 1900MHz. 1900MHz is closest to fs(4) / 2, which is 2211.84MHz, among 0, -fs(4) / 4, fs(4) / 4, -fs(4) / 2, and fs(4) / 2. Therefore, the frequency shift of module 4 is set to 2211.84MHz. The passband bandwidth of the first filter in module 4 is fs(4) / 8 + 100 / 2 = 602.96MHz.

[0124] The remaining frequency shift allocated to module 3 is 1900 - 2211.84 = -311.84 MHz. The sampling rate of the output signal of module 3 is fs(3) = fs(4) / 2 = 2211.84 MHz. -311.84 MHz is closest to -fs(3) / 4, i.e., -552.96 MHz, among 0, -fs(3) / 4, fs(3) / 4, -fs(3) / 2, and fs(3) / 2. Therefore, the frequency shift of module 4 is set to -552.96 MHz. The passband bandwidth of the first filter in module 3 is fs(3) / 8 + 100 / 2 = 326.48 MHz.

[0125] The remaining frequency shift allocated to module 2 is -311.84 - (-552.96 MHz) = 241.12 MHz. The sampling rate of the output signal of module 2 is fs(2) = fs(3) / 2 = 1105.92 MHz. 241.12 MHz is closest to fs(2) / 4 among 0, -fs(2) / 4, fs(2) / 4, -fs(2) / 2, and fs(2) / 2, i.e., 276.48 MHz. Therefore, the frequency shift of module 2 is set to 276.48 MHz. The passband bandwidth of the first filter in module 2 is fs(2) / 8 + 100 / 2 = 188.24 MHz.

[0126] The remaining frequency shift allocated to module 1 is 241.12 - 276.48 = -35.36 MHz. The sampling rate of the output signal of module 1 is fs(1) = fs(2) / 2 = 552.96 MHz. -35.36 MHz is closest to 0 MHz among 0, -fs(1) / 4, fs(1) / 4, -fs(1) / 2, and fs(1) / 2, so the frequency shift of module 1 is set to 0 MHz. The passband bandwidth of the first filter in module 1 is fs(1) / 8 + 100 / 2 = 119.12 MHz.

[0127] The remaining frequency shift allocated to the first information processing module is -35.36 - 0 = -35.36 MHz. The sampling rate of the output signal of the first information processing module is fs_nco = fs(1) / 2 = 276.48 MHz. The baseband sampling rate is 122.88 MHz, so RSMP is the second filter with a rate of 276.48 / 122.88 = 9 / 4 times.

[0128] The input signal of the second signal processing module is a baseband signal, so the bandwidth of the second filter can be set to 100 / 2=50MHz.

[0129] The order of the HBF filters in each stage of the above-described step-by-step frequency shifting scheme is slightly higher than that of the final stage direct frequency shifting scheme. Table 3 shows a comparison of the multiplication operations required for the two cascaded schemes.

[0130] Table 3

[0131] .

[0132] The number of multiplication operations in Table 3 takes into account the sampling rate. The calculation principle is HBF effective order * HBF sampling rate / baseband sampling rate. Therefore, although the HBF filter at high speed has a lower order, the equivalent number of multiplication operations is actually higher.

[0133] Although the step-by-step frequency shifting method increases the filter order, in actual circuit implementations, HBF half-band filters are all fixed-coefficient filters, which can be implemented using an adder tree structure without the need for multipliers. According to the circuit synthesis results, statistically speaking, the computational resources of fixed-coefficient multiplication are only about 1 / 6 of those of variable-coefficient multiplication. Therefore, as shown in Table 3, the optimization benefits of the final-stage NCO brought by the step-by-step frequency shifting scheme outweigh the negative effects of increasing the filter order, and the total computational load is reduced by 20% compared to the traditional scheme.

[0134] Figure 9 A schematic diagram of the structure of a communication device according to some embodiments of the present disclosure is shown. For example... Figure 9 As shown, the communication device 9 includes: a digital circuit 91 as described above; a baseband processing module 92; and a data converter 93. The data converter 93 can be a digital-to-analog converter or an analog-to-digital converter. The digital circuit 91 is connected between the baseband processing module 92 and the data converter 93.

[0135] The above description is only a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A digital circuit, comprising: A first signal processing module, connected to a baseband processing module, is configured to perform a first sampling rate transformation and a first frequency shift on the input signal of the first signal processing module; The second signal processing module includes multiple cascaded sub-modules, including a first sub-module and a second sub-module. The first sub-module is connected to the first signal processing module and is located at one end of the multiple sub-modules. The second sub-module is connected to the data converter and is located at the other end of the multiple sub-modules. Each of the multiple sub-modules is configured to perform a second sampling rate transformation and a second frequency shift on the input signal of the sub-module. A frequency shift configuration module, connected to each submodule of the first signal processing module and the second signal processing module, is configured to set the frequency shift amount for each submodule of the first signal processing module and the second signal processing module, including: determining the frequency point corresponding to each submodule based on the sampling rate of the data converter and the frequency point of the signal processed by the data converter; determining the frequency shift amount of each submodule based on the frequency point corresponding to each submodule, wherein the frequency point corresponding to the second submodule is a first value, the first value being the frequency point of the signal processed by the data converter; for other submodules among the plurality of submodules besides the second submodule, the frequency point corresponding to the submodule is a second value, the second value being the difference between the frequency point and the frequency shift amount of the submodule connected to the submodule and closer to the data converter.

2. The digital circuit according to claim 1, wherein, The frequency shift amount of each submodule in the second signal processing module is determined from a plurality of specified values, and the frequency shift amount of the first signal processing module is determined based on the difference in frequency points of the signals processed by the baseband processing module and the data converter, and the frequency shift amount of the second signal processing module.

3. The digital circuit according to claim 2, wherein, For each submodule, the submodule includes a first filter and a frequency shift module connected to the first filter. The first filter is configured to perform a second sampling rate transformation on the input signal of the first filter. The frequency shift module is configured to perform a second frequency shift on the input signal of the frequency shift module. The frequency shift amount is determined from 0, fs / 4, -fs / 4, -fs / 2, and fs / 2, where fs is the sampling rate of the input signal of the frequency shift module.

4. The digital circuit according to claim 3, wherein, The frequency shift configuration module is configured to determine the frequency shift amount of each submodule from 0, fs / 4, -fs / 4, -fs / 2 and fs / 2 according to the frequency point corresponding to each submodule.

5. The digital circuit according to claim 4, wherein, The first filter is a half-band filter, the sampling rate of the input signal of the frequency shift module of the second submodule is the sampling rate of the data converter, and the frequency shift amount of the second submodule is 0, fs / 4, -fs / 4, -fs / 2 or fs / 2. For the submodules other than the second submodule among the plurality of submodules, the sampling rate of the submodule is half of the sampling rate of the submodule connected to the submodule and close to the data converter, and the frequency shift of the submodule is 0, fs / 4 or -fs / 4.

6. The digital circuit according to claim 3, wherein, The frequency shift module is configured to perform at least one of the following logical processing operations on the real and imaginary parts of the input signal of the frequency shift module according to the frequency shift amount: crossover and phase reversal.

7. The digital circuit according to claim 3, wherein, The data converter is a digital-to-analog converter, the first filter is a half-band interpolation filter, the output signal of the half-band interpolation filter in the submodule is the input signal of the frequency shift module in the submodule, and the output signal of the frequency shift module is the output signal of the submodule.

8. The digital circuit according to claim 3, wherein, The data converter is an analog-to-digital converter, the first filter is a half-band decimation filter, the output signal of the frequency shift module in the submodule is the input signal of the half-band decimation filter in the submodule, and the output signal of the half-band decimation filter is used as the output signal of the submodule.

9. The digital circuit according to claim 3, wherein, For each submodule, the passband of the first filter in the submodule is determined based on the sampling rate and bandwidth of the input signal of the frequency shift module of the submodule.

10. The digital circuit according to claim 1, wherein, The data converter is a digital-to-analog converter. The output signal of the baseband processing module is processed by the first signal processing module and the second signal processing module to form the input signal of the digital-to-analog converter.

11. The digital circuit according to claim 1, wherein, The data converter is an analog-to-digital converter. The output signal of the analog-to-digital converter is processed by the second signal processing module and the first signal processing module to form the input signal of the baseband processing module.

12. The digital circuit according to claim 1, wherein, The first signal processing module includes a second filter and a digitally controlled oscillator (NCO) connected to the second filter. The second filter is configured to perform a first sampling rate transformation on the input signal of the second filter. The NCO is configured to perform a first frequency shift on the input signal of the NCO, and the frequency shift amount is the difference between the frequency point corresponding to the first sub-module and the frequency shift amount.

13. A communication device, comprising: The digital circuit as described in any one of claims 1 to 12; Baseband processing module; and Data converter.

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