Circuit board and semiconductor package comprising same

Abstract

In an embodiment of the present invention, disclosed is a circuit board comprising: a build-up insulating section including a plurality of insulating layers stacked in the vertical direction; a build-up electrode section including a plurality of wiring portions arranged on the upper surface of each of the plurality of insulating layers, and a plurality of via electrodes arranged between the plurality of wiring portions; a protective layer disposed on the build-up insulating section and including a plurality of pillars; and bonding portions arranged on the upper surface of the protective layer, wherein the build-up insulating section includes an insulating layer including a plurality of pillars, at least one via electrode from among the plurality of via electrodes passes through the insulating layer including the plurality of pillars, a pillar closest to the via electrode from among the plurality of pillars of the insulating layer is provided with a curved surface, the build-up electrode section includes a pad portion disposed on the upper surface of the build-up insulating section, the bonding portions each includes a protrusion portion disposed on the upper surface of the protective layer and a via portion connected to the pad portion through the protective layer, at least one of the plurality of pillars of the protective layer, which are adjacent to the via portions, includes a flat surface and a curved surface, and at least one of the plurality of pillars of the protective layer, which are adjacent to the protrusion portions, is provided with a curved surface.

Description

Circuit board and semiconductor package including the same

[0001] An embodiment according to the present invention relates to a circuit board and a semiconductor package.

[0002] As the performance of electrical and electronic products advances, technologies are being proposed and researched to attach a larger number of packages to substrates of limited size. However, since conventional packages are based on mounting a single semiconductor chip, there are limitations in achieving the desired performance.

[0003] A typical circuit board or package board consists of a processor package housing a processor chip and a memory package housing a memory chip, connected as a single unit. By manufacturing the processor and memory chips into a single integrated package, such package boards offer the advantages of reducing the chip mounting area and enabling high-speed signals through short paths. Due to these benefits, such package boards are widely applied in mobile devices and the like.

[0004] Meanwhile, recently, due to the high specifications of electronic devices such as servers and PCs, the size of packages is increasing. In addition, as the functions required of processors increase, there is a demand for circuit boards capable of configuring these functions separately as processor chips, mounting these processor chips, and interconnecting the processor chips. Furthermore, regarding the above processor, even when it is separated into two processor chips according to function, the number of terminals (Input / Output) provided on each processor chip is increasing.

[0005] Recently, due to factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speeds, the number of terminals on processor chips is gradually increasing as the number of power and signals grows. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of a circuit board increase, it becomes difficult to miniaturize the product, and problems such as increased reliability (e.g., board warping), yield, and product cost arise. Furthermore, to ensure inter-processor chips, miniaturization of circuit patterns is required to align the pitch between the chips and the circuit board. In other words, increasing the density of circuit patterns is more advantageous in terms of product cost, reliability (e.g., warping), and product characteristics than increasing the area and thickness of the circuit board. Therefore, miniaturization of circuit patterns or through-electrodes is required.

[0006] In particular, for package substrates (e.g., interposers) for HBM or multi-die combination, it is essential to have via holes with fine line widths or pitches and plating on the outermost layer. In this regard, when forming circuit patterns with fine line widths or pitches, bumps formed on the protective layer covering the fine pattern are also becoming miniaturized in correspondence with the fine pattern. Furthermore, due to this miniaturization, the volume of vias formed on the protective layer is decreasing. Consequently, there is a difficulty in that reliability is reduced due to a decrease in the adhesion strength between the bumps and the protective layer. Therefore, it is necessary to control whether the filler within the protective layer is exposed and to improve the adhesion strength between the plating of the build-up electrode portion and the protective layer even when exposed.

[0007] In addition, the protective layer includes a bonding portion that is adjacent to the semiconductor chip relative to the insulating layer below and is mostly directly electrically connected. At this time, the bonding portion is a part where a significant load is applied to the semiconductor chip compared to the wiring or via electrodes within the insulating layer, so structural reliability improvement is required.

[0008] An embodiment of the present invention provides a circuit board that improves the bonding strength between a protective layer and a bonding portion through the shape of a via hole in the protective layer and an internal filler adjacent to the upper surface of the protective layer, and a semiconductor package including the same.

[0009] In addition, the embodiment can provide a circuit board with improved reliability and a semiconductor package including the same, even if the protective layer and the upper build-up layer are made of a material including a resin and a plurality of fillers, the filler adjacent to the via portion in the protective layer has a flat surface and a curved surface, and the filler adjacent to the via electrode in the upper build-up layer has a curved surface, thereby easily dispersing the weight of a semiconductor device mounted on the upper part of the protective layer and easily dispersing the pressure applied during mounting.

[0010] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, wherein a plasma process of different gases is performed on via holes located on top of a micro pattern or connecting member so that the exposure of the filler varies depending on the location and the exposed surface has a smooth shape, thereby reducing the roughness on the inner surface of the via hole so that the plating layer is homogeneous and the occurrence of voids is suppressed.

[0011] In addition, the embodiment can provide a circuit board with improved reliability and a semiconductor package including the same by applying a filler structure in the protective layer to the lower part of the bonding portion, such as an upper build-up layer, or to various insulating layers.

[0012] The problems intended to be solved in the embodiments are not limited thereto, and may also include objectives or effects that can be identified from the means of solving the problems or the embodiments described below.

[0013] A circuit board according to an embodiment of the present invention comprises: a build-up insulating portion including a plurality of insulating layers stacked along a vertical direction; a build-up electrode portion including a plurality of wiring portions disposed on the upper surface of each of the plurality of insulating layers and a plurality of via electrodes disposed between the plurality of wiring portions; a protective layer disposed on the build-up insulating portion and including a plurality of fillers; and a bonding portion disposed on the upper surface of the protective layer; wherein the build-up insulating portion includes an insulating layer including a plurality of fillers, at least one of the via electrodes among the plurality of via electrodes penetrates the insulating layer including the plurality of fillers, and the filler closest to the via electrode among the plurality of fillers of the insulating layer is provided as a curved surface, the build-up electrode portion includes a pad portion disposed on the upper surface of the build-up insulating portion, and the bonding portion includes a protrusion disposed on the upper surface of the protective layer and a via portion connected to the pad portion by penetrating the protective layer, and among the plurality of fillers of the protective layer, at least one of the fillers adjacent to the via portion includes a flat surface and a curved surface, and among the plurality of fillers of the protective layer, at least one of the fillers adjacent to the protrusion is provided as a curved surface.

[0014] The bonding portion may be positioned outside the circuit board compared to the build-up electrode portion.

[0015] The above via portion is located in the via hole of the protective layer, and among the plurality of fillers of the protective layer, the filler in contact with the protrusion may be exposed at the inner wall of the via hole.

[0016] Among the plurality of fillers of the above protective layer, the filler located between adjacent protrusions may be provided with a curved surface.

[0017] The seed layer of the bonding portion above may come into contact with at least some of the plurality of fillers of the protective layer.

[0018] A plurality of fillers of the protective layer may include a first sub-filler that overlaps vertically with the protrusion and a second sub-filler that is offset vertically from the protrusion.

[0019] The first sub-pillar and the second sub-pillar may not be exposed on the upper surface of the protective layer.

[0020] The structure further includes a cavity formed in the above-mentioned build-up insulating portion; and a connecting member disposed in the cavity; wherein the bonding portion may overlap the cavity in a vertical direction.

[0021] The distance between the bonding part and the connecting member may be greater than the distance between the build-up electrode part and the connecting member.

[0022] The above protective layer may include a plurality of resin-rich regions in which the resin is greater than or equal to a predetermined ratio.

[0023] The plurality of resin-rich regions above may have at least a portion in contact with the via portion.

[0024] Among the plurality of resin-rich regions above, the resin-rich region in contact with the via may include a flat surface and a curved surface.

[0025] Among the plurality of resin-rich regions above, the resin-rich region closest to the via electrode may be provided as a curved surface.

[0026] The above via portion is located in the via hole of the protective layer, and at least some of the plurality of resin-rich regions may be exposed by the inner wall of the via hole.

[0027] The above bonding portion may have a pitch of 55㎛ or less.

[0028] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, which improves the bonding strength between a protective layer and a bonding portion when forming a seed layer for plating through the shape of a via hole in the protective layer and an internal filler adjacent to the upper surface of the protective layer.

[0029] In addition, even if the protective layer and the upper build-up layer are made of a material comprising a resin and a plurality of fillers, the filler adjacent to the via portion in the protective layer has a flat surface and a curved surface, and the filler adjacent to the via electrode in the upper build-up layer has a curved surface, thereby easily dispersing the weight of semiconductor devices mounted on the upper protective layer and easily dispersing the pressure applied during mounting, so that a circuit board with improved reliability and a semiconductor package including the same can be realized. That is, by evenly dispersing the supporting force of the bonding portion for semiconductor devices without affecting the fillers, structural reliability is improved, thermal dissipation is improved, and a circuit board with minimized electrical signal degradation can be realized.

[0030] In addition, the embodiment performs a plasma process of different gases on via holes located on top of a fine pattern or connecting member so that the exposure of the filler varies depending on the location and the exposed surface has a smooth shape, thereby reducing the roughness on the inner surface of the via hole, so that even if the volume of the via in the bonding part having a fine pitch is reduced, the plating layer in the protective layer is homogeneous on the inner surface of the via hole and the occurrence of via cracks is reduced by suppressing the occurrence of voids, thereby providing a circuit board and a semiconductor package including the same.

[0031] In addition, the embodiment can provide a circuit board with improved reliability and a semiconductor package including the same by applying a filler structure in the protective layer to the lower part of the bonding portion, such as an upper build-up layer, or to various insulating layers.

[0032] The various and beneficial advantages and effects of the present invention are not limited to those described above and may be more easily understood in the process of explaining specific embodiments of the present invention.

[0033] FIG. 1 is a plan view of a circuit board according to a first embodiment of the present invention, and

[0034] FIG. 2 is a cross-sectional view of a circuit board according to a first embodiment, and

[0035] FIG. 3 is an enlarged view of the K1 portion in FIG. 1, and

[0036] FIG. 4 is an enlarged view of the K2 portion in FIG. 1, and

[0037] FIG. 5 is an enlarged view of the K3 portion in FIG. 1, and

[0038] FIGS. 6 to 15 are drawings illustrating a method for manufacturing a circuit board according to a first embodiment, and

[0039] FIG. 16 is a cross-sectional view of a circuit board according to a second embodiment, and

[0040] FIG. 17 is an enlarged view of the K4 portion in FIG. 16, and

[0041] FIG. 18 is a cross-sectional view of a circuit board according to a third embodiment, and

[0042] FIG. 19 is an enlarged view of the K5 portion in FIG. 18, and

[0043] FIG. 20 is a cross-sectional view showing a semiconductor package according to a first embodiment, and

[0044] FIG. 21 is a cross-sectional view showing a semiconductor package according to a second embodiment, and

[0045] FIG. 22 is a cross-sectional view showing a semiconductor package according to a third embodiment, and

[0046] FIG. 23 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0047] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0048] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0049] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0050] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0051] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0052] Additionally, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “and at least one of B and C (or more than one),” it may include one or more of all combinations that can be combined with A, B, and C.

[0053] Terms including ordinal numbers, such as second, first, etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. The term "and / or" includes a combination of multiple related described items or any of the multiple related described items. Such terms are intended only to distinguish the component from other components and are not limited by the essence, order, sequence, etc. of the component.

[0054] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0055] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0056] Furthermore, when described as being formed or placed "above or below" each component, "above or below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0057] In addition, the expression that configuration A is positioned between configuration B and configuration C must include the meaning that configuration A is positioned such that at least a portion of it overlaps with configurations B and C in the horizontal and / or vertical directions.

[0058] Expressions referring to directions include horizontal and vertical directions, and the horizontal direction includes a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of being superimposed along the horizontal direction must include the meaning of being superimposed along the first horizontal direction and / or superimposed along the second horizontal direction.

[0059] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration A is covered by at least a portion of Configuration C.

[0060] Furthermore, when it is stated that Component A 'contacts' Component B, this may include not only cases where the component 'contacts' the other component directly, but also cases where it 'contacts' due to another component located between the component and the other component. Therefore, if Component A is to be understood only as 'directly contacting' Component B, it is described as 'directly contacting'.

[0061] In addition, when it is stated that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part intended for the function and purpose to be resolved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0062] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0063] Before describing the embodiments, the electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and a semiconductor device, and the semiconductor device may be mounted on the circuit board.

[0064] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions or more of devices are integrated into a single chip. Semiconductor chips may be logic chips, memory chips, etc. Logic chips may be non-memory chips such as central processors (CPUs), graphics processors (GPUs), and FPGAs (Field Programmable Gate Arrays). For example, a logic chip may be an application processor (AP) chip comprising at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a chip set comprising a specific combination of those listed above.

[0065] The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0066] Meanwhile, the product family to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0067] In addition, electronic devices may include smartphones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smartwatches, automotive devices, etc. However, they are not limited to these, and it goes without saying that they may be any other electronic devices that process data in addition to these.

[0068] FIG. 1 is a plan view of a circuit board according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a circuit board according to a first embodiment, FIG. 3 is an enlarged view of portion K1 in FIG. 1, FIG. 4 is an enlarged view of portion K2 in FIG. 1, and FIG. 5 is an enlarged view of portion K3 in FIG. 1.

[0069] Referring to FIGS. 1 and 2, a circuit board (100) according to the first embodiment may include a build-up insulating portion (110) and a build-up electrode portion (120). Furthermore, the circuit board (100) may further include a protective layer (SR) and a bonding portion (BP). In the embodiments of the present invention below, the build-up insulating portion (110) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are stacked. The build-up electrode portion (120) is embedded and disposed in each layer (e.g., insulating layer) of the build-up insulating portion (110), thereby enabling the function of transmitting signals and / or power from a main board (not shown) to a semiconductor device.

[0070] And if the circuit board includes a core layer, it may include a core layer disposed within a build-up insulating portion (110). Accordingly, the build-up insulating portion (110) of the circuit board may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). The upper build-up layer (112) may be located above the core layer (111). And the lower build-up layer (113) may be located below the core layer (111).

[0071] And the build-up electrode portion (120) may include a via electrode (121) and a wiring portion (122) as described below. At this time, the wiring portion (122) may include a wiring portion (or circuit pattern) disposed on the upper and lower surfaces of the core layer (111). And the via electrode (121) may include a via electrode penetrating the core layer (111). This will be described below.

[0072] Alternatively, the build-up insulating portion (110) may include an upper build-up layer (112) and a lower build-up layer (113) disposed on the upper and lower surfaces of the core layer (111). At this time, the core portion may be composed of the core layer (111), a wiring portion (or circuit pattern) disposed on the core layer (111), and / or via electrodes.

[0073] In an embodiment, the build-up insulating portion (110) may be composed of a core layer (111) and a build-up insulating portion (112, 113) comprising at least one insulating layer disposed above and below the core layer (111). Accordingly, the build-up insulating portion (112, 113) stacked on the core layer may include a plurality of vertically stacked insulating layers. The build-up insulating portion may include an upper build-up layer (112) and a lower build-up layer (113). As illustrated, the upper build-up layer (112) may be disposed above the core layer (111), and the lower build-up layer (113) may be disposed below the core layer (111). The upper build-up layer and / or the lower build-up layer may each be provided with a plurality of insulating layers stacked thereon. Additionally, the build-up layer (or build-up insulating portion) may be referred to as a build-up structure or a build-up insulating layer, etc. The following description is based on this.

[0074] As another example, the build-up insulation (110) is described as including a core layer, but the circuit board may be made of a coreless structure.

[0075] In an example, the build-up insulating portion (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). Additionally, a protective layer (SR) may be further disposed on the outer side of the build-up insulating portion (110). This will be described later.

[0076] And the upper build-up layer (112) may be an 'upper build-up insulating part (or upper build-up structure)'. The lower build-up layer (113) may be a 'lower build-up insulating part (or lower build-up structure)'. In this embodiment, the core layer (111) may be positioned in the center in the vertical direction of the build-up insulating part (110). When the build-up layer is laminated on both sides of the core layer (111), the core layer (111) may be located in the center of the build-up insulating part (110). That is, the upper build-up layer (112) may be positioned on the core layer (111), and the lower build-up layer (113) may be positioned below the core layer (111).

[0077] Additionally, the build-up insulating portion (110) of the circuit board (100) may be rigid or flexible. For example, the build-up insulating portion (110) of the circuit board (100) may include glass or plastic. For example, the build-up insulating portion (110) of the circuit board or each insulating layer forming the build-up insulating portion (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the build-up insulating portion (110) of the circuit board may include reinforced or flexible plastics such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the build-up insulating portion (110) of the circuit board may include sapphire. For example, the build-up insulating portion (110) of the circuit board may include an optically isotropic film. For example, the build-up insulating portion (110) of the circuit board may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the build-up insulating portion (110) of the circuit board may be formed from a material including a filler and an insulating resin. For example, the build-up insulating portion (110) of the circuit board may have a structure in which a silica or alumina filler is disposed in a thermosetting resin or a thermoplastic resin. Also, the build-up insulating portion (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure is described in more detail as follows. In the embodiment, the insulating layer of the build-up insulating portion (110) may include a plurality of fillers.

[0078] In one embodiment, the build-up insulating portion (110) may include a core layer containing a reinforcing member. Here, the core layer may refer to an insulating layer that includes a reinforcing member and has a thickness exceeding tens or hundreds (e.g., 100) μm in its vertical direction (Y-axis direction, or stacking direction). For example, the core layer may have a thickness of 100 μm or more in the vertical direction. Additionally, the upper build-up layer (112) and the lower build-up layer (113) may each include a plurality of layers that are disposed above and below the core layer and do not include a reinforcing member. In this case, the circuit board may be a core board. The reinforcing member may also be a reinforcing fiber or glass fiber embedded within the core layer. The following description is based on the upper build-up layer (112). Although the upper build-up layer is depicted in the drawings as including only a 'first insulating layer,' it may be composed of a plurality of insulating layers, and the upper build-up layer may be combined with the first insulating layer in the following description.

[0079] Reinforcing members may refer to glass fiber material extended along a direction perpendicular to the vertical direction of the insulation layer (e.g., horizontal direction (X-axis direction)), and may have a different meaning from spaced-apart fillers.

[0080] The core layer (111) may be made of various insulating materials. Additionally, the core layer (111) may be composed of multiple layers, and the multiple layers may be made of the same or different materials. Furthermore, the core layer (111) may include via electrodes penetrating the upper and lower surfaces of the core layer (111).

[0081] And the upper build-up layer (112) or the lower build-up layer (113) may be provided with any insulating resin, such as a thermosetting and / or photocurable resin. As a thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, may be used, and materials such as prepreg (PPG) containing glass fibers may be used. As a photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin may be used. The aforementioned any insulating resin may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and may include inorganic fillers such as silica. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. For example, when manufacturing the build-up insulating part (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric Resin), BT, etc. may be used. For example, if the circuit board (100) is coreless, the build-up insulating part (110) may be provided by laminating ABF, for example, without a core layer. The insulating resins described above may be freely combined to form the build-up insulating part (110), taking into account dielectric constant, insulating properties, and warping of the circuit board.

[0082] In addition, the circuit board (100) according to the first embodiment may further include a metal layer (MP) in addition to the protective layer (SR) and the bonding portion (BP).

[0083] The protective layer (SR) can function to protect the pad from external moisture or contaminants, and to prevent short-circuit problems during bonding between the semiconductor device and / or main board and the circuit board, the protective layer (SR) may, for example, be provided as a solder resist. Specifically, the semiconductor device and / or main board, etc., have multiple terminals for connecting the circuit board. In addition, multiple terminals may be arranged at a high density. When multiple terminals and the pad of the circuit board are bonded, solder may be used, for example. When solder is used, solder short-circuit problems may occur between terminals with high density; therefore, to solve such short-circuit problems, a solder resist with poor wettability with solder may be placed. In addition, the protective layer (SR) may be made of a material that has insulating properties for electrical connections. The protective layer (SR) may include resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photosolder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be composed of a filler, which is a reinforcing member, and a resin.

[0084] A protective layer (SR) may be disposed on a build-up insulating portion (110). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed below a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be spaced apart from each other along the stacking direction and may have different thicknesses to account for the bending of the circuit board. Hereinafter, the protective layer is described based on the first protective layer (SR1).

[0085] A bonding portion (BP) may be disposed on a protective layer (SR). For example, the bonding portion (BP) may be disposed on the upper surface of the protective layer (SR). The bonding portion (BP) may be located outside the build-up electrode portion (120). For example, in the upper build-up layer (112), the bonding portion (BP) may be located above the build-up electrode portion (120). The bonding portion (BP) may include a protrusion (PP) disposed on the upper surface of the protective layer (SR) and a via portion (TP) penetrating the protective layer (SR). In an embodiment, the via portion (TP) and the protrusion (PP) may each include a plurality of protrusions or convex portions protruding toward an adjacent protective layer (SR). For example, on the first protective layer (SR1), the via portion (TP) and the protrusion (PP) may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1). A detailed explanation of this will be provided later.

[0086] A metal layer (MP) may be disposed on a bonding portion (BP). Specifically, the metal layer (MP) may be disposed on the upper surface of a protrusion (PP). The metal layer (MP) is in contact with the bonding portion (BP) and can provide electrical connection and improve durability and reliability.

[0087] The metal layer (MP) may consist of at least one metal layer. The metal layer (MP) may consist of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. This improves the bonding strength with the bonding part (BP), improves the corrosion resistance and durability of the bonding part (BP), and minimizes the loss of electrical signals.

[0088] The width of the metal layer (MP) may differ from the width of the upper surface of the protrusion (PP) of the bonding portion (BP). For example, the width of the metal layer (MP) may be smaller than the width of the upper surface of the protrusion (PP) of the bonding portion (BP). The metal layer (MP) may be formed on the bonding portion (BP) by deposition, electroplating, etc., of various metals.

[0089] Additionally, the build-up electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor device, die), and the build-up electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad) and a via electrode. For example, the wiring portion (122) of the build-up electrode portion (120) may be arranged on the upper surface of each of the plurality of insulating layers of the build-up insulating portion (110). The wiring portion (122) of the build-up electrode portion (120) may include a circuit pattern and a pad. And the build-up electrode portion (120) may include a plurality of via electrodes (121) penetrating the insulating layer. The plurality of via electrodes may be located between the plurality of wiring portions. For example, the plurality of via electrodes may be located between the plurality of wiring portions spaced apart in the vertical direction.

[0090] In an embodiment, the build-up electrode portion (120) in the circuit board (100) may include a via electrode (121) and a wiring portion (122). In this case, the wiring portion (122) (or circuit pattern) in the build-up electrode portion (120) may be designed in various forms for signal and / or power transmission with a semiconductor device and is disposed within each insulating layer of the stacked build-up insulating portion (110).

[0091] In the build-up electrode section (120), the via electrode (121) is positioned to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns placed in each insulating layer of the build-up insulating section (110). And at least one of the plurality of via electrodes or via electrodes (121) can penetrate the insulating layer having a plurality of fillers. The via electrode (121) can connect a plurality of wiring sections (122) to each other. The via electrode (121) can also be made up of a plurality of units, like the wiring sections. That is, the insulating layer may include via holes for the placement of via electrodes. And the via electrode may have a width wider than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and can be freely designed.

[0092] In the build-up electrode portion (120), the wiring portion (122) can be placed in each insulating layer. The wiring portion (122) can be electrically connected to a circuit pattern. Additionally, the wiring portion (122) can be connected to each via electrode (121). Furthermore, the wiring portion (122) placed on the upper and lower surfaces of the build-up insulating portion (110) can be electrically connected to a semiconductor device and / or a main board or substrate, etc. For example, such a build-up electrode portion (120) can be located in the core layer (111), the upper build-up layer (112), and the lower build-up layer (113), respectively, in their respective layers (insulating layers).

[0093] According to an embodiment, the circuit pattern of the wiring portion (122) in the build-up electrode portion (120) may include a circuit pattern having a fine pitch (or mixed with the first pattern) and a second pattern having a pitch larger than the first pattern. For example, the first pattern is a fine pattern and may have a pitch of 55 μm or less. For example, the first pattern may be located on the upper part of the connecting member (SD) and may overlap with the connecting member (SD) in a vertical direction (Y-axis direction). The circuit board (100) may include a fine region (MA) that overlaps with the connecting member (SD) in a vertical direction and a general region (GA) that is offset from the connecting member (SD) in a vertical direction. The first pattern may be located in the fine region (MA), and the second pattern, which is a general pattern, may be located in the general region (GA). The first pattern may be placed on the upper build-up layer (112) and arranged to have a high wiring density for signal connection with semiconductor devices (CH1, CH2). In addition, the first pattern can be provided to provide a line function for signal connection between semiconductor devices (CH1, CH2), thereby preventing the semiconductor devices from becoming unnecessarily large and improving the yield of the semiconductor devices.

[0094] Additionally, although the second pattern is shown as being placed on the upper build-up layer (112), it is not limited thereto and the second pattern may also be placed on the lower build-up layer (113) to perform the function of electrically connecting the circuit board and the semiconductor devices (CH1, CH2).

[0095] As described above, according to the embodiment, the first pattern may be connected to the connecting member (SD). The second pattern may be spaced apart from the connecting member (SD) in a horizontal direction (X-axis direction). As described above, the horizontal direction (X-axis direction) may correspond to the first horizontal direction. The horizontal direction perpendicular to the vertical direction may include the first horizontal direction corresponding to the illustrated X-axis direction and the second horizontal direction perpendicular to both the X-axis direction and the vertical direction. Furthermore, it should be understood that the horizontal direction includes both the first horizontal direction and the second horizontal direction, and the following description is based on the X-axis direction. And similar to pitch, the width and / or spacing of the second pattern in the horizontal direction (X-axis direction) of the wiring section (122) is greater than the width and / or spacing of the first pattern in the horizontal direction (X-axis direction). The second pattern may mean a pattern having the same width and spacing as a pattern used in a conventional circuit board, and the first pattern means a fine circuit pattern having a width and spacing narrower than the pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or the formation of an inductor, for example, a width and spacing of 5 μm or less.

[0096] Furthermore, the wiring portion (122) of the build-up electrode portion (120) may include a pad portion (PD) disposed on the outer surface (e.g., upper surface / lower surface) of the build-up insulation portion (110). For example, in an embodiment, the pad portion (PD) may be disposed on the upper surface of the build-up insulation portion (110) or on the upper surface of the upper build-up layer (112).

[0097] The pad portion (PD) can be electrically connected to the via portion (TP) of the bonding portion (BP) described later. Additionally, the pad portion (PD) can also be electrically connected to the build-up electrode portion (120). Below, the description is based on the pad portion (PD) placed on the upper surface of the upper build-up layer (112) of the build-up insulating portion (110). Furthermore, the pad portion (PD) placed on the outermost side of the build-up insulating portion (110) can be bonded to a semiconductor device, substrate, board, etc., using solder, wire, conductive adhesive, etc., and can be placed with a width greater than the width of the circuit pattern to solve problems such as securing yield. However, it is not limited to this, and may have a width equal to or smaller than the width of the circuit pattern depending on the technical limitations of the bonding process.

[0098] And the pad placed on the inner side (inside the outer surface) of the build-up insulation part (110) of the build-up electrode part (120) functions to connect the via electrode and the circuit pattern. When the via electrode is placed with a width wider than the circuit pattern, a pad with a width wider than the circuit pattern is provided to ensure positional alignment during the manufacturing process of the via electrode to be placed on each circuit pattern. Accordingly, each via electrode may have an upper surface located on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface located on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that concave or convex surfaces that may appear depending on various processes may also be present.

[0099] Additionally, the build-up electrode portion (120) may include a conductive member or a conductive coupling portion (SB) disposed below the lower build-up layer (113) and the second protective layer (SR2). The conductive member or the conductive coupling portion (SB) can perform electrical connection with other substrates, etc. Accordingly, the conductive member or the conductive coupling portion (SB) can serve as an intermediate medium for electrical signal transmission. Furthermore, the conductive member or the conductive coupling portion (SB) can dissipate heat from the circuit board or package substrate through heat transfer.

[0100] Additionally, the circuit board (100) may include a cavity (CV) formed inside. The cavity (CV) may be formed within at least one of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113). For example, it may be formed across the core layer (111) and the upper build-up layer (112), or it may be formed only within the core layer (111). The cavity (CV) may consist of a plurality of cavities spaced apart along the horizontal direction. For example, the cavity (CV) may include a first cavity (CV1) and a second cavity (CV). A connecting member (SD), which will be described later, may be disposed in the first cavity (CV1), and a component (e.g., a passive component) having a function with the connecting member (SD) as well as other connecting members (SD) may be disposed in the second cavity (CV2). The first cavity (CV1) and the second cavity (CV2) can be positioned to overlap at least partially with the core layer (111) in the first horizontal direction (X-axis direction), and are arranged to have different vertical depths and different horizontal widths, thereby preventing bending of the circuit board and allowing components with various functions to be embedded within the circuit board. Below, the description is based on the first cavity (CV1) where the connecting member (SD) is placed.

[0101] The connecting member (SD) can be mounted within the first cavity (CV1). The connecting member (SD) can perform the function of electrically connecting multiple other chips (CH1, CH2) placed on the upper part of the circuit board (100) by being placed within the first cavity (CV1). For example, by interconnecting chiplets that are functionally divided from existing semiconductor chips, the size of the semiconductor chip can be reduced, thereby contributing to improving the yield of the semiconductor chip. The connecting member (SD) is made of, for example, an inorganic material (e.g., Si) or an organic material, and can be called a bridge. Additionally, the connecting member (SD) can be used interchangeably as a 'semiconductor device', 'chip', 'die', etc.

[0102] Additionally, the connecting member (SD) may include a connecting build-up electrode portion (SDE) on one side and / or on another side spaced perpendicular to the one side. For example, the connecting build-up electrode portion may be located on the upper side of the connecting member (SD). By this configuration, the connecting member (SD) may be electrically connected to a plurality of chips (CH1, CH2) disposed on the outside of the circuit board (100). For example, the connecting build-up electrode portion may be electrically connected to the build-up electrode portion of the circuit board and may be electrically connected to other semiconductor devices or chips (CH1, CH2) on the circuit board. Additionally, different chips (CH1, CH2) may be electrically connected through the connecting member (SD).

[0103] Furthermore, circuit boards can be classified into package boards and interposers based on their function. Package boards serve the function of mounting semiconductor devices and / or interposers. As data increases, the area of ​​the circuit board expands, or as the number of insulating layers increases, the yield of the circuit board can significantly decrease. Therefore, to improve the yield of circuit boards with high stacking counts, the yield can be enhanced by separating the circuit board into an interposer and a package board. In addition, as the density of semiconductor device terminals increases, it may be difficult to implement package board pads with an area corresponding to the terminals of the semiconductor devices. Accordingly, the interposer can act as a buffer between the pad size of the package board and the fine pattern size of the semiconductor device terminals.

[0104] The package substrate and interposer described above can be classified into a core substrate and a coreless substrate, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer containing a reinforcing member among the stacked insulating layers. The reinforcing member may refer to glass fiber. By being positioned thicker than other insulating layers, the core layer may have the function of preventing warping of the circuit board during the process. However, the core layer may cause problems such as voltage drop and signal loss, or make thinning difficult. Therefore, depending on the application, a coreless substrate that does not include a core layer may be used as the insulating layer of the circuit board.

[0105] Referring further to FIGS. 3 to 5, the core layer (111) may be positioned in the center of the vertical direction of the build-up insulation portion (110). When build-up layers are laminated on both sides of the core layer (111), the core layer (111) may be located in the center of the build-up insulation portion (110). That is, the upper build-up layer (112) may be positioned on the core layer (111), and the lower build-up layer (113) may be positioned below the core layer (111). As described above, in another example where the core layer (111) is absent, the upper build-up layer (112) and the lower build-up layer (113) may be in contact with each other, and a first cavity (CV1) may be formed in the upper build-up layer (112) and / or the lower build-up layer (113). Furthermore, the location of such a cavity may be varied.

[0106] The bonding portion (BP) may be located on the build-up electrode portion (120). The bonding portion (BP) may be located on the protective layer (SR). The bonding portion (BP) may be electrically connected to the wiring portion (122). The bonding portion (BP) may be located on the upper first protective layer (SR1). For example, the bonding portion (BP) may include a protrusion (PP) disposed on the upper surface of the first protective layer (SR1) as described above and a via portion (TP) penetrating the protective layer (SR). The via portion (TP) may be electrically connected to the pad portion (PD) described above.

[0107] And the bonding portion (BP) is located on the protective layer (SR) located on the upper part of the build-up insulating portion (110), so that it may be located outside the build-up electrode portion (120) on the circuit board. Accordingly, the distance between the build-up bonding portion (BP) and the connecting member (SD) may be greater than the distance between the build-up electrode portion (120) and the connecting member (SD).

[0108] Additionally, the bonding portion (BP) may include a first bonding portion (BP1) and a second bonding portion (BP2). The first bonding portion (BP1) may include a via portion (hereinafter the first via portion) and a protrusion (hereinafter the first protrusion). And the second bonding portion (BP2) may include a via portion (hereinafter the second via portion) and a protrusion (hereinafter the second protrusion).

[0109] The first bonding portion (BP1) and the second bonding portion (BP2) may be located in the first protective layer (SR1) among the protective layers (SR). Furthermore, the protective layer (SR) may include a resin (RS) and a plurality of reinforcing members, which are fillers (FL), spaced apart from the resin. In addition, in the first protective layer (SR1), a portion of the plurality of fillers (FL) may be spaced apart from each other. A portion of the filler (FL) may come into contact with the via portion (TP) of the bonding portion (BP). In this way, the filler (FL) may be located at various positions within the first protective layer (SR1).

[0110] Accordingly, among the multiple fillers of the protective layer (SR), the filler adjacent to the protrusion (PP) is hereinafter referred to as the "first filler." In particular, the first filler (FL1) may be the filler closest to the protrusion (PP) among the multiple fillers of the protective layer (SR). And among the multiple fillers of the protective layer (SR), the filler adjacent to the via (TP) of the bonding portion (BP) is hereinafter referred to as the "second filler." The second filler (FL2) may be the filler closest to the via (TP) among the multiple fillers of the protective layer (SR).

[0111] In other words, as an example, a plurality of fillers (FL) of the first protective layer (SR1) may include a first filler (FL1) closest to the upper surface of the first protective layer (SR1) and a second filler (FL2) closest to the via hole of the first protective layer. For example, the second filler (FL2) may be closest to the first via portion (TP) of the first bonding portion (BP1).

[0112] At this time, the first filler (FL1) may be provided with a curved surface. Additionally, among the plurality of fillers of the protective layer (SR), at least one of the fillers adjacent to the protrusion (PP) may be formed with a curved surface. The first filler (FL1) may have a spherical surface closest to the upper surface of the first protective layer (SR1).

[0113] In contrast, among the multiple fillers of the protective layer (SR), at least one of the fillers adjacent to the via portion (TP) may include a flat surface and a curved surface. In an embodiment, the second filler (FL2) may have a flat surface (or aspherical surface) and a spherical surface. The second filler (FL2) may have an aspherical surface (ES) closest to the via hole of the first protective layer (SR1). For example, the surface (ES) of the second filler (FL2) that contacts the first via portion (TP) of the first bonding portion (BP1) may be an aspherical surface. The surface of the second filler (FL2) that does not contact the via portion (TP) may be a spherical surface (SS1). Additionally, the first filler (FL1) may be in contact with the resin of the first protective layer (SR1), and its outer surface may be a spherical surface (SS2).

[0114] Additionally, among the plurality of fillers in the first protective layer (SR1), the filler located in the area between adjacent protrusions (PP) may be provided with a curved surface. That is, the second sub-filler may be provided with a curved surface.

[0115] In this way, at least a portion of the second filler (FL2) may be exposed by the inner wall of the via hole of the first protective layer (SR1). For example, the non-spherical and exposed surface (ES) of the second filler (FL2) may have an inclination equal to the inclination of the inner surface of the via hole (or the outer surface of the via portion (TP)) of the first protective layer (SR1). That is, the angle formed between the second filler (FL2) and the lower surface of the first protective layer (SR1) may be equal to the angle formed between the inner surface of the via hole (or the outer surface of the via portion) of the first protective layer (SR1) and the lower surface of the first protective layer (SR1), or may be within a range of 5%.

[0116] Additionally, the first filler (FL1) may be spaced apart from the protrusion (PP) of the first bonding portion (BP1). The first filler (FL1) may be spaced apart from the upper surface of the first protective layer (SR1) by a predetermined distance. However, the first filler (FL1) may be positioned so as not to be exposed on the upper surface of the first protective layer (SR1), and this does not mean that all of the first filler (FL1) does not exist within a predetermined distance from the upper surface of the first protective layer (SR1). In contrast, at least a portion of the second filler (FL2) may come into contact with the via portion (TP) of the first bonding portion (BP1). For example, the second filler (FL2) may come into contact with the outer surface of the via portion (TP) of the first bonding portion (BP1). Furthermore, the outer surface of the second filler (FL2) adjacent to the via hole of the first protective layer (SR1) may be non-spherical. In particular, the exposed surface (ES) of the second filler (FL2) may not protrude from the inner surface of the via hole of the first protective layer (SR1). For example, the seed layer of the first bonding portion (BP1) may come into contact with at least a portion of the second filler (FL2). And the seed layer of the first bonding portion (BP1) may be spaced apart from the first filler (FL1).

[0117] With this configuration, the roughness of the inner surface of the via hole in the first protective layer (SR1) can be reduced and the surface area improved. Accordingly, when forming a seed layer for plating, the bonding strength between the seed layer and the via hole can be improved through uniform plating. In particular, even if the volume of the via is reduced in the bonding portion having a fine pitch, the uniformity of the inner surface of the via hole in the first protective layer (SR1) is also improved by the filler or resin-rich region (RR), which is a reinforcing member, thereby eliminating factors that hinder bonding strength. In addition, the occurrence of via cracks by the reinforcing member (or resin-rich region (RR), etc.) within the first bonding portion, which is a fine pattern, can be suppressed.

[0118] In an example, the protective layer (first protective layer, SR1) may include a resin-rich region. The resin-rich region (RR) may be distinguished within the first protective layer (SR1) by the content of filler, etc. For example, the resin-rich region (RR) may have a filler or reinforcing material content of less than a predetermined ratio. For example, the resin-rich region (RR) may have a filler or reinforcing material content ratio of 10% or less. And this 10% or less may be measured based on a predetermined volume or area in the first protective layer. This may also exist in the upper build-up layer (112).

[0119] In addition, the resin-rich region (RR) has less filler compared to other regions of the first protective layer (SR1), so resin decomposition can be performed more easily. Accordingly, at least a portion of the resin-rich region (RR) may be exposed on the inner side of the via hole. At this time, the surface of the exposed resin-rich region (RR) may be flat or smooth. That is, the roughness may be smaller in the resin-rich region (RR) compared to the general region. As a result, a uniform plating layer can be formed due to the surface roughness, and the plating layer can be formed in close contact with the first protective layer (SR1) without voids. In particular, if the seed layer (or plating layer) of the via (TP) in the first bonding portion (BP1) is Ti among various metals, the bonding strength with the first protective layer (SR1) can be further improved.

[0120] Additionally, the contents of the plurality of fillers in the aforementioned first protective layer (SR1) may differ from those of the build-up layers (112, 113). Based on the upper build-up layer (112), the upper build-up layer (112) may include a resin (RS1) and a filler (FL3), similar to the first protective layer (SR1). At this time, among the plurality of fillers (FL3) of the upper build-up layer (112), the filler closest to the via electrode (121) may be provided as a curved surface. For example, among the plurality of fillers (FL3) of the upper build-up layer (112), the filler closest to the via electrode (121) may be exposed by the via hole of the upper build-up layer (112) where the via electrode (121) is located. That is, at least some of the plurality of fillers of the build-up layers (112, 113) may be exposed on the inner surface of the via hole of the build-up layer (112, 113). At this time, some of the multiple fillers (FL3) of the upper build-up layer (112) may have a spherical exposed surface adjacent to the via hole or via electrode of the upper build-up layer (112).

[0121] That is, the filler (FL3) in the upper build-up layer (112) may differ from the first filler or the second filler of the first protective layer (SR1). For example, the width or thickness of the first pattern, which is a fine pattern along the stacking direction or vertical direction, the pad portion (PD) corresponding to the first pattern, and the first bonding portion (BP1) connected to the pad portion (PD) may decrease sequentially according to the design. In this case, the bonding strength between the first protective layer (SR1) and the first bonding portion (BP1) may be greater than that between the lower first pattern or pad portion (PD). On the other hand, the lower first pattern or pad portion (PD) may provide structural reliability with a lower bonding strength compared to the bonding strength between the first protective layer (SR1) and the first bonding portion (BP1). In this case, improved bonding strength between the pad portion (PD) and the upper build-up layer (112) can be provided without the aforementioned plasma process. Thus, process simplification can be achieved.

[0122] In this way, the filler (FL3) of the upper build-up layer (112) may be exposed on the upper surface of the upper build-up layer (112) or on the inner surface of the via hole, or some of the filler (FL3) may detach from the upper build-up layer (112). As a result, the upper surface of the upper build-up layer (112) may have a concave groove (or concave portion), or the pad portion (PD) may have a concave groove (or concave portion) due to the exposed filler (FL3). Additionally, the inner surface of the via hole of the upper build-up layer (112) may also have a concave groove (or concave portion), or the pad portion (PD) may have a concave groove (or concave portion) due to the exposed filler (FL3).

[0123] Furthermore, the filler (FL3) and resin (RS1) of this upper build-up layer (112) can be applied equally in the micro-region as well as the general region.

[0124] As such, within the micro region (MA), the upper first protective layer (SR1) and the upper build-up layer (112) are made of similar materials including resin and a plurality of fillers, but the shape of the filler adjacent to the via portion or via electrode may be different. Accordingly, the filler adjacent to the via portion of the bonding portion (first bonding portion) located in the first protective layer (SR1) has a flat surface and a curved surface, thereby easily distributing the weight of the semiconductor device, etc. mounted on the upper portion. Furthermore, the reliability of the circuit board can be further improved by easily distributing the pressure applied during mounting. That is, the supporting force of the bonding portion for the semiconductor device, etc. can be evenly distributed without affecting the filler. In particular, a large load can be evenly distributed first to the protective layer that is closest to the semiconductor device and is positioned outside the upper build-up layer. By doing so, the structural reliability of the circuit board can be improved. Furthermore, since the filler adjacent to the via of the bonding part has a flat surface, thermal dispersion is improved and electrical signal degradation can be minimized.

[0125] Additionally, the first filler (FL1) may include a first sub-filler that overlaps vertically with the protrusion (PP) of the first bonding part (BP1) and a second sub-filler that is offset vertically with the protrusion (PP) of the first bonding part (BP1).

[0126] Both the first sub-pillar and the second sub-pillar may not be exposed to the upper surface of the first protective layer (SR1). That is, the first sub-pillar and the second sub-pillar may be spaced apart from the upper surface of the first protective layer (SR1).

[0127] Accordingly, the upper surface of the first protective layer (SR1) and the inner surface of the via hole may both have low roughness. Additionally, even if a filler (e.g., second filler) is exposed on the inner surface of the via hole in the first protective layer (SR1), the roughness may be reduced. Furthermore, since the filler (e.g., first filler) adjacent to the upper surface of the first protective layer (SR1) is not exposed and does not come into contact with the protrusion, the reduction in adhesion strength between the protrusion and the filler may also be suppressed.

[0128] Furthermore, the first bonding part (BP1) among the bonding parts may overlap in a vertical direction with the first cavity (CV1) or the connecting member (SD). Furthermore, the first filler (FL1) may have the aforementioned structure in an area (e.g., a micro area (MA)) that overlaps perpendicularly with the first cavity (CV1) or the connecting member (SD). For example, the first filler (FL1) may be in contact with the first bonding portion (BP1) on the first cavity (CV1) (or connecting member), and the exposed surface may be non-spherical. Alternatively, the first filler (FL1) may have a non-spherical surface exposed on the upper surface of the first protective layer (SR1). And the second filler (FL2) may be spaced apart from the first bonding portion (BP1) on the first cavity (CV1) (or connecting member) and may not be exposed. Thus, the second filler (FL2) may have a non-spherical surface closest to the upper surface of the first protective layer (SR1) on the first cavity (CV1) (or connecting member).

[0129] And the second bonding part (BP2) may be positioned offset from the first cavity (CV1) or the connecting member (SD) and may not overlap in a vertical direction. Furthermore, the first filler (FL1) may differ from the structure described above in an area that does not overlap vertically with the first cavity (CV1) or the connecting member (SD) (e.g., a general area (MA)). For example, the first filler (FL1) may come into contact with the second bonding portion (BP2) in the general area (GA). Additionally, the first filler (FL1) may have a spherical surface protruding toward the via portion (TP) of the second bonding portion (BP2). That is, the surface of the first filler (FL1) exposed in the first protective layer (SR1) may be spherical. Furthermore, in the general area (GA), the first filler (FL1) adjacent to the via hole of the first protective layer (SR1) may detach, so that a concave portion exists on the inner surface of the via hole of the first protective layer (SR1). This concave portion may be a spherical surface corresponding to the outer surface of the first filler (FL1). Additionally, the resin-rich area (RR) may also be the first The structure may be exposed on the inner side of the via hole of the protective layer (SR1) and protrude toward the via portion (TP) of the second bonding portion (BP2). Accordingly, the via portion (TP) of the second bonding portion (BP2) may have a concave groove on the outer side due to the resin-rich region (RR) and the exposed first filler (FL1). In addition, the second filler (FL2) may be spaced apart from the second bonding portion (BP2) in the general area and may not be exposed. That is, unlike the micro area, the surface area in the general area is large, so the bonding force between the first protective layer (SR1) and the second bonding portion (BP2) can be maintained significantly due to the size of the second bonding portion (BP2). In particular, the bonding force between the seed layer (via portion) of the first bonding portion (BP1) and the first protective layer (SR1) can be secured. Furthermore, the bonding force can also be secured for the first bonding portion (BP1) that contacts the micro pattern (first pattern). For example, the peel strength of the bonding portion (BP) can be significantly improved.

[0130] In addition, the first protective layer (SR1) may have a greater coefficient of thermal expansion than the insulating layer constituting the other build-up insulating layer. Therefore, the first bonding portion (BP1) may peel off from the first protective layer (SR1) due to heat applied during the process of the circuit board and / or heat generated during the operation of the semiconductor device. Furthermore, as the horizontal width and / or spacing of the first bonding portion (BP1) narrows, the problem of peeling off the first bonding portion (BP1) due to applied stress occurs. Accordingly, as described above, the exposure of the first filler (FL1) and the second filler (FL2) within the first protective layer (SR1) and the shape of the exposed surface are provided in accordance with the above description, thereby improving the fixing force between the first bonding portion (BP1) and the first protective layer (SR1). Accordingly, the problem of the bonding portion (BP) peeling off can be prevented.

[0131] Furthermore, in the present example, the filler (FL) in the first protective layer (SR1) may include a first filler (FL1) and a second filler (FL2). At this time, the filler closest to the upper surface of the first protective layer (SR1) in the micro region (MA) is described as the first filler (FL1). The filler closest to the via hole (or via portion of the first bonding part) of the first protective layer (SR1) in the micro region (MA) is described as the second filler (FL2). The filler closest to the upper surface of the first protective layer (SR1) in the general region (GA) is described as the third filler. The filler closest to the via hole (or via portion of the second bonding part) of the first protective layer (SR1) in the general region (GA) is described as the fourth filler.

[0132] The third and fourth pillars may each have the same shape as the first pillar (FL1) and the second pillar (FL2). The third pillar may be located closest to the upper surface of the first protective layer (SR1) in the general area (GA). Furthermore, the surface of the third pillar closest to the upper surface of the first protective layer (SR1) may be spherical. The fourth pillar may have an aspherical surface (ES) closest to the via hole of the first protective layer (SR1) in the general area (GA). In this case, the aspherical surface (ES) of the fourth pillar may be the surface exposed by the via hole, just like the second pillar (FL2). Additionally, the surface of the fourth pillar that is not exposed may be spherical. Likewise, the third pillar may not come into contact with the protrusion (PP) of the second bonding portion (BP2). That is, the third pillar may not overlap with the first bonding part (BP2) in the horizontal direction (X-axis direction). Likewise, the first pillar (FL1) and the third pillar may not overlap with the first bonding part or the second bonding part in the horizontal direction.

[0133] And the exposed surface of the fourth pillar may have a slope that is the same or similar to the slope of the inner surface of the via hole. Accordingly, the roughness of the inner surface of the via hole may be reduced on the exposed surface of the fourth pillar as well.

[0134] With this configuration, the bonding strength between the second bonding portion (BP2), which is connected to the general pattern on the upper surface of the general pattern rather than the fine pattern, and the first protective layer (SR1) can be further improved. Accordingly, the reliability of the circuit board can be further improved.

[0135] FIGS. 6 to 15 are drawings illustrating a method for manufacturing a circuit board according to a first embodiment.

[0136] First, the circuit board according to the embodiment may include the steps of providing a core layer, forming a cavity, mounting a connecting member in the cavity, laminating a build-up layer (insulating layer) and forming a build-up electrode portion, forming a protective layer and an opening in the protective layer, and forming a bonding portion and forming a metal layer. Except for the details described below, the descriptions for each component may be applied as described above. In particular, in the step of forming an opening in the protective layer, a film may be formed, then vias may be formed, then etched with a plasma gas, and then etched again with a different plasma gas. This will be described below.

[0137] Referring to FIG. 6, a core layer (111) may be provided. Then, via holes may be formed in the core layer (111), and a build-up electrode portion may be formed. In the core layer (111), a via electrode (121) penetrating the core layer (111) and a wiring portion (122) located on the upper and lower surfaces of the core layer (111) may be formed. A build-up electrode portion (120) may be formed in the core layer (111). The build-up electrode portion may be formed using the Additive Process, Subtractive Process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process) methods, which are manufacturing processes for printed circuit boards. Additionally, the pattern of the wiring portion may be formed by a dry film, etc.

[0138] Referring to FIG. 7, a cavity (CV) can be formed in the core layer (111). As previously described, there may be multiple cavities (CV). For example, the cavity (CV) may include a first cavity and a second cavity (CV), and the description below will be based on the first cavity. A bonding member (PF) may be disposed on one side (e.g., the bottom surface) of the core layer (111). The area within the side of the cavity (CV) in the core layer (111) may be exposed. That is, the bonding member (PF) within the cavity (CV) may be exposed by the cavity (CV).

[0139] After the cavity (CV) is formed, the core layer (111) can be placed on the bonding member (PF). Additionally, the cavity (CV) may be formed after the core layer (111) is seated on the bonding member (PF).

[0140] Additionally, a connecting member (SD) may be placed on the bonding member (PF). The connecting member (SD) may be located within the cavity (CV) of the core layer (111).

[0141] As the core layer (111) and the connecting member (SD) are placed on the bonding member (PF), the bonding member (PF) may include a convex portion extending upward between the side of the cavity (CV) and the connecting member (SD). Furthermore, the seating of the core layer (111) or the connecting member (SD) may be performed in various sequences. The following description is based on what is shown in the drawings.

[0142] Referring to FIG. 8, an upper build-up layer (112) and a lower build-up layer (113) may be formed on the upper and lower surfaces of the core layer (111). At this time, the lower build-up layer (113) may be formed with the bonding member (PF) removed. The upper build-up layer (112) and the lower build-up layer (113) may be formed sequentially. For example, the build-up layer (113) may be formed after the upper build-up layer (112) is formed.

[0143] Referring to FIG. 9, via holes (VH1, VH2) may be formed in the upper build-up layer (112) (or lower build-up layer (113)). The following description is based on the upper build-up layer, and the description of the upper build-up layer may be applied to the lower build-up layer with the same or slightly modified structure, excluding the bonding part structure.

[0144] Via holes (VH1, VH2) can penetrate the upper build-up layer (112). Via holes (VH1, VH2) may include a first via hole (VH1) and a second via hole (VH2). The width of the pattern of the first via hole (VH1) may be larger than that of the second via hole (VH2). For example, the first via hole (VH1) may correspond to the second pattern, and the second via hole (VH2) may correspond to the first pattern. There may be multiple via holes (VH1, VH2).

[0145] Referring to FIG. 10, a build-up electrode portion (120) may be formed in the upper build-up layer (112) and the lower build-up layer (113). A build-up electrode portion (120) may be formed in each insulating layer of the upper build-up layer (112) and the lower build-up layer (113). In the upper build-up layer and the lower build-up layer, via electrodes (121) penetrating each layer and wiring portions (122) located on the upper and lower surfaces of each layer may be formed. The build-up electrode portion may be formed using the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process) methods, which are manufacturing processes for printed circuit boards. Additionally, the pattern of the wiring portion may be formed by a dry film, etc.

[0146] Referring to FIG. 11, protective layers (SR1, SR2) may be formed on the upper build-up layer (112) and the lower build-up layer (113), respectively. The first protective layer (SR1) may be located on the upper build-up layer (112). The second protective layer (SR2) may be located below the lower build-up layer (113). The following description is based on the first protective layer (SR1).

[0147] Furthermore, a film (PET) may be formed on the first protective layer (SR1). For example, the film (PET) may be a thermoplastic polymer and may include a polyester series. The film (PET) protects the first protective layer (SR1) and may serve as a protective layer for forming vias during lamination.

[0148] Referring to FIG. 12, via holes (VH3, VH4) for forming a bonding portion (BP) can be formed for the first protective layer (SR1). At this time, a film (PET) can be patterned to form the via holes (VH3, VH4). A third via hole (VH3) and a fourth via hole (VH4) can be formed in the first protective layer (SR1) by various methods. The third via hole (VH3) and the fourth via hole (VH4) can be formed by drilling (laser, mechanical) (LI1) or etching. At this time, a filler (FL) located within the resin (RS) in the first protective layer (SR1) can be exposed.

[0149] In addition, plasma etching can be performed on the first protective layer (SR1). For example, a reactive gas (e.g., oxygen, CF₄, SF6, argon, etc.) can be used to apply a high-frequency power (RF Power) to make the gas into a plasma state, and this plasma-state material (Pla2) can be applied to the first protective layer (SR1). At this time, the exposed filler (e.g., the first filler) can be cut off by the plasma. In addition, the resin-rich region can also be cut off by the plasma. Thus, the exposed surface of the first filler or the resin-rich region in the via hole can be aspherical. Furthermore, in areas other than the third via hole (VH3) and the fourth via hole (VH4), the filler may not be exposed on the upper surface of the first protective layer (SR1) by a film (PET). That is, the second filler can be separated from the upper surface of the first protective layer (SR1).

[0150] Subsequently, etching of the upper surface of the first protective layer (SR1) can be performed using plasma. And the film (PET) can be removed by the plasma. At this time, the applied plasma (Pla2) is a plasma different from the plasma used for etching the third via hole (VH3) and the fourth via hole (VH4), and may be a gas that does not cause damage within the third via hole (VH3) and the fourth via hole (VH4).

[0151] Referring to FIG. 13, a dry film (DF) can be formed on the protective layer. An opening or via (PT) having a predetermined pattern can be formed on the dry film (DF). Such opening or via (PT) can be formed corresponding to the pad.

[0152] Referring further to FIG. 14, a bonding portion (BP) may be formed in an opening or via (PT). The via portion (TP) penetrates at least a portion of the first protective layer, and a protrusion (PP) may be located on the via portion (TP). And a metal layer (MP) may be formed on the bonding portion (BP).

[0153] Referring to FIG. 15, the aforementioned dry film can be removed. Additionally, a conductive member or a conductive bonding part (SB), etc., may be further formed on the lower part of the substrate.

[0154] FIG. 16 is a cross-sectional view of a circuit board according to a second embodiment, and FIG. 17 is an enlarged view of the K4 portion in FIG. 16.

[0155] Referring to FIGS. 16 and 17, a circuit board (100A) according to the second embodiment may include a build-up insulating portion (110) and a build-up electrode portion (120). Furthermore, the circuit board (100A) may further include a protective layer (SR) and a bonding portion (BP). Additionally, the circuit board (100A) may further include a metal layer (MP), etc. As described above, the build-up electrode portion (120) is embedded and disposed in each layer (e.g., insulating layer) of the build-up insulating portion (110), thereby enabling the function of transmitting signals and / or power from a main board (not shown) to a semiconductor device. Furthermore, the above description may be applied identically to the circuit board, except for the details described below.

[0156] Additionally, as described above, the filler (FL) in the first protective layer (SR1) may include a first filler (FL1) and a second filler (FL2). In this case, the filler closest to the upper surface of the first protective layer (SR1) in the micro region (MA) is described as the first filler (FL1). The filler closest to the via hole (or via portion of the first bonding part) of the first protective layer (SR1) in the micro region (MA) is described as the second filler (FL2). The filler closest to the upper surface of the first protective layer (SR1) in the general region (GA) is described as the third filler. The filler closest to the via hole (or via portion of the second bonding part) of the first protective layer (SR1) in the general region (GA) is described as the fourth filler.

[0157] In an embodiment, a plurality of fillers (FL) of the first protective layer (SR1) may include a first filler (FL1) closest to the upper surface of the first protective layer (SR1) and a second filler (FL2) closest to the via hole of the first protective layer. For example, the second filler (FL2) may be closest to the first via portion (TP) of the first bonding portion (BP1).

[0158] At this time, the first filler (FL1) may be provided with a curved surface. Additionally, among the plurality of fillers of the protective layer (SR), at least one of the fillers adjacent to the protrusion (PP) may be formed with a curved surface. The first filler (FL1) may have a spherical surface closest to the upper surface of the first protective layer (SR1).

[0159] In contrast, among the multiple fillers of the protective layer (SR), at least one of the fillers adjacent to the via portion (TP) may include a flat surface and a curved surface. In an embodiment, the second filler (FL2) may have a flat surface (or aspherical surface) and a spherical surface. The second filler (FL2) may have an aspherical surface (ES) closest to the via hole of the first protective layer (SR1). For example, the surface (ES) of the second filler (FL2) that contacts the first via portion (TP) of the first bonding portion (BP1) may be an aspherical surface. The surface of the second filler (FL2) that does not contact the via portion (TP) may be a spherical surface (SS1). Additionally, the first filler (FL1) may be in contact with the resin of the first protective layer (SR1), and its outer surface may be a spherical surface (SS2).

[0160] In this example, the plurality of fillers (FL) of the first protective layer (SR1) may include a third filler closest to the upper surface of the first protective layer (SR1) and a fourth filler closest to the via hole of the first protective layer. For example, the fourth filler may be closest to the second via (TP) of the second bonding portion (BP2).

[0161] At this time, the third filler may be provided as a curved surface. Additionally, among the plurality of fillers of the protective layer (SR), at least one of the fillers adjacent to the second protrusion (PP) may be formed as a curved surface. The third filler may have a spherical surface closest to the upper surface of the first protective layer (SR1).

[0162] Additionally, among the multiple fillers of the protective layer (SR), at least one of the fillers adjacent to the via portion (TP) may include a curved surface. In an example, the fourth filler may have a spherical surface. Furthermore, the fourth filler may have a spherical surface closest to the via hole of the first protective layer (SR1). Moreover, a concave portion where the fourth filler has fallen off may be formed in the via hole where the fourth filler is exposed. In this way, the surface of the fourth filler that contacts the second via portion (TP) of the second bonding portion (BP2) may be spherical. Additionally, the surface of the fourth filler that does not contact the via portion (TP) may also be spherical. Accordingly, the aforementioned plasma process is not performed multiple times, thereby making process simplification easier to achieve.

[0163] This allows the resin-rich region (RR) to be applied in the same way as the aforementioned filler to the general region and the micro region. For example, at least a portion of the resin-rich region (RR) is exposed and may come into contact with the via portion (TP) of the first bonding portion (BP1). With this configuration, the roughness of the inner surface of the via hole in the first protective layer (SR1) can be reduced and the surface area improved. Accordingly, the bonding strength between the seed layer and the via hole can be improved when forming a seed layer for plating. In particular, the uniformity of the reinforcing member, such as the filler or the resin-rich region (RR), on the inner surface of the via hole in the first protective layer (SR1) can also be improved, thereby eliminating factors that hinder bonding strength. Furthermore, the occurrence of via cracks caused by the reinforcing member (or resin-rich region (RR), etc.) within the first bonding portion, which is a micro pattern, can be suppressed.

[0164] FIG. 18 is a cross-sectional view of a circuit board according to a third embodiment, and FIG. 19 is an enlarged view of the K5 portion in FIG. 18.

[0165] A circuit board (100B) according to the third embodiment may include a build-up insulating portion (110) and a build-up electrode portion (120). Furthermore, the circuit board (100B) may further include a protective layer (SR) and a bonding portion (BP). Additionally, the circuit board (100B) may further include a metal layer (MP), etc. As described above, the build-up electrode portion (120) is embedded and disposed in each layer (e.g., insulating layer) of the build-up insulating portion (110), thereby enabling the function of transmitting signals and / or power from a main board (not shown) to a semiconductor device. Furthermore, the above description may be applied identically to the circuit board, except for the details described below.

[0166] In this example, the pad portion (PD) of the build-up electrode portion (120) may also be located on the build-up layer (112, 113) of the build-up insulation portion (110). The pad portion (PD) may be placed on the outermost surface (e.g., the top surface) of the build-up insulation portion (110). For instance, the pad portion (PD) may be a wiring portion located on the top or bottom surface of the build-up insulation portion (110). Furthermore, the following description will be based on the upper pad portion (PD) in the upper build-up layer (112).

[0167] Additionally, the first filler (FL1) and the second filler (FL2) in the aforementioned first protective layer (SR1) may be applied not only to the first protective layer (SR1) but also to the lower build-up layer (112, 113). For example, the build-up layer (112, 113) may include resin and filler. Furthermore, the filler of the build-up layer (112, 113) may not be exposed on the upper surface (or lower surface) of the build-up layer (112, 113). Moreover, the filler of the build-up layer (112, 113) may be exposed on the inner surface of the via hole of the build-up layer (112, 113). At this time, the filler exposed on the inner surface of the via hole of the build-up layer (112, 113) may have a flat surface and a curved surface. Conversely, the filler closest to the upper (or lower) surface of the build-up layer (112, 113) may have a spherical surface without being exposed. The exposed surface may be a flat surface or an aspherical surface. And the unexposed surface may be a spherical surface. With this configuration, the upper build-up layer has a structure similar to a protective layer, thereby improving the bonding strength between the insulating layer and the electrode portion in the fine pattern.

[0168] Furthermore, the filler (FL3) and resin (RS1) of this upper build-up layer (112) can be applied equally in the micro-region as well as the general region.

[0169] FIG. 20 is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 21 is a cross-sectional view showing a semiconductor package according to a second embodiment, FIG. 22 is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 23 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0170] In various semiconductor packages described below, the circuit board described above may be located in a part of the area or correspond to a single substrate.

[0171] Referring to FIG. 20, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor device (1300).

[0172] The first substrate (1100) may mean a 'package substrate' or a 'circuit board', or may include such meanings. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). Additionally, the external substrate may mean a main board included in an electronic device coupled to the lower part of the first substrate (1100).

[0173] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space for mounting at least one semiconductor device.

[0174] The first substrate (1100) may include at least one insulating layer and a build-up electrode portion disposed on at least one insulating layer.

[0175] A second substrate (1200) can be placed on the first substrate (1100).

[0176] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space for mounting at least one semiconductor device. The second substrate (1200) may be connected to at least one semiconductor device (1300). For example, the second substrate (1200) may provide a space for mounting a first semiconductor device (1310) and a second semiconductor device (1320). The second substrate (1200) may electrically connect the first semiconductor device (1310) and the second semiconductor device (1320), and electrically connect the first and second semiconductor devices (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between multiple semiconductor devices and a vertical connection function between a semiconductor device and a package substrate.

[0177] Additionally, although it has been illustrated that two semiconductor devices (1310, 1320) are disposed on the second substrate (1200) as in the example above, it is not limited thereto. For example, one semiconductor device may be disposed on the second substrate (1200), or three or more semiconductor devices may be disposed therein.

[0178] The second substrate (1200) can be placed between at least one semiconductor device (1300) and the first substrate (1100).

[0179] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a stacked structure in a vertical direction on the first substrate (1100) and may function as a plurality of logic chips. The ability to function as a logic chip may mean that it may have the functions of an active device and a passive device. In the case of an active device, unlike a passive device, the characteristics of current and voltage may not be linear, and in the case of an active interposer, it may have the function of an active device. Additionally, while the active interposer functions as a logic chip, it may perform a signal transmission function between the second logic chip placed on top of it and the first substrate (1100).

[0180] According to another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, capacitor, or inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IOT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between multiple terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of an electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for being connected to the semiconductor device (1300) and the main board, respectively, there is a problem in that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complex. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor device (1300). The second substrate (1200) may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor device (1300).

[0181] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stacked memory such as HBM.

[0182] Meanwhile, the semiconductor package of the first embodiment may include a connection portion.

[0183] For example, the semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) can electrically connect the two substrates while coupling the second substrate (1200) to the first substrate (1100).

[0184] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor device (1300). The second connection portion (1420) can electrically connect the semiconductor device (1300) while coupling it to the second substrate (1200).

[0185] The semiconductor package may include a third connection portion (1430) disposed on the lower surface of the first substrate (1100). The third connection portion (1430) can electrically connect the first substrate (1100) to the main board while coupling them together.

[0186] At this time, the first connection part (1410), the second connection part (1420), and the third connection part (1430) can electrically connect multiple components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection part (1410), the second connection part (1420), and the third connection part (1430) have the function of electrically connecting multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as an electrically connected part rather than solder or wire.

[0187] Wire bonding may refer to electrically connecting multiple components using a conductor such as gold (Au). Additionally, solder bonding may refer to electrically connecting multiple components using a material containing at least one of Sn, Ag, and Cu. Furthermore, direct metal-to-metal bonding may refer to directly bonding multiple components by applying heat and pressure between them to cause recrystallization without the use of solder, wire, conductive adhesive, etc. And direct metal-to-metal bonding may refer to a bonding method using the second connection part (1420). In this case, the second connection part (1420) may refer to a metal layer formed between multiple components by recrystallization.

[0188] Specifically, the first connection part (1410), the second connection part (1420), and the third connection part (1430) can join multiple components together by a thermal compression bonding method. A thermal compression bonding method may refer to a method of directly joining multiple components by applying heat and pressure to the first connection part (1410), the second connection part (1420), and the third connection part (1430).

[0189] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrode on which the first connection part (1410), the second connection part (1420), and the third connection part (1430) are disposed may be provided with a protrusion extending outwardly away from the insulating layer of the corresponding substrate. The protrusion may extend outwardly from the first substrate (1100) or the second substrate (1200).

[0190] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor device (1300) is disposed among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor device (1300) becomes finer, a short circuit may occur between a plurality of second connection portions (1420) that are each connected to a plurality of terminals of the semiconductor device (1300) by a conductive adhesive such as solder. Therefore, the embodiment may perform thermal compression bonding to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion on the electrode of the second substrate (1200) on which the second connection portion (1420) is disposed, in order to secure a degree of alignment, diffusion power, and a diffusion prevention power that prevents an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or substrate.

[0191] Additionally, looking further at FIG. 20, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0192] The connecting member (1210) can be a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) can function to electrically connect a plurality of semiconductor devices horizontally to each other. For example, because the area that a semiconductor device generally needs to have is too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or breadth of the circuit pattern, a buffering role for the circuit pattern for electrical connection is required. The buffering role may mean having an intermediate size between the size of the width or breadth of the circuit pattern of the semiconductor package and the size of the width or breadth of the circuit pattern of the semiconductor device, and the redistribution layer may include a function that performs the buffering role.

[0193] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate containing an organic material instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0194] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be disposed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements disposed on the second substrate (1200).

[0195] Referring to FIG. 21, the semiconductor package of the second embodiment may include a second substrate (1200) and a semiconductor device (1300). In this case, the semiconductor package of the second embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0196] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0197] The first connection part (1410) disposed on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0198] Referring to FIG. 22, the semiconductor package of the third embodiment may include a first substrate (1100) and a semiconductor device (1300).

[0199] At this time, the semiconductor package of the third embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0200] That is, the first substrate (1100) of the third embodiment functions as a package substrate and can also function to connect between a semiconductor device (1300) and a main board. To this end, the first substrate (1100) may include a connecting member (1110) for connecting between a plurality of semiconductor devices. The connecting member (1110) may be an organic bridge connecting between a plurality of semiconductor devices.

[0201] Referring to FIG. 23, the semiconductor package of the fourth embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the fourth embodiment. To this end, a fourth connection portion may be further disposed on one side of the first substrate (1100).

[0202] Thus, the semiconductor package of the fourth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively. At this time, the third semiconductor device (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0203] And a connecting member (1110) may be embedded in the first substrate (1100). The connecting member (1110) may horizontally connect the first and second semiconductor devices (1310, 1320).

[0204] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may protrude further from the first substrate (1100) toward the second semiconductor device (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, a post. The conductive coupling portion (1450) may be disposed having a structure protruding on an electrode disposed on the uppermost side of the first substrate (1100).

[0205] A third semiconductor device (1330) may be disposed on the conductive coupling portion (1450). At this time, the third semiconductor device (1330) may be connected to the first substrate (1100) through the conductive coupling portion (1450). Additionally, a second connection portion (1420) may be disposed between the first and second semiconductor devices (1310, 1320) and the third semiconductor device (1330).

[0206] Accordingly, the third semiconductor device (1330) can be electrically connected to the first and second semiconductor devices (1310, 1320) through the second connection part (1420).

[0207] That is, the third semiconductor device (1330) is connected to the first substrate (1100) through the conductive coupling portion (1450), and can also be connected to the first and second semiconductor devices (1310, 1320) through the second connection portion (1420).

[0208] At this time, the third semiconductor device (1330) can receive a power signal and / or power through the conductive coupling portion (1450). In addition, the third semiconductor device (1330) can exchange communication signals with the first and second semiconductor devices (1310, 1320) through the second connection portion (1420).

[0209] The semiconductor package of the fourth embodiment can supply a power signal and / or power to the third semiconductor device (1330) through the conductive coupling portion (1450), thereby enabling the provision of sufficient power for driving the third semiconductor device (1330) or smooth control of power operation.

[0210] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor device (1330). That is, the embodiment can solve the problem of insufficient power being supplied to the third semiconductor device (1330). Furthermore, the embodiment can allow at least one of the power signal, power, and communication signal of the third semiconductor device (1330) to be provided through different paths via the conductive coupling part (1450) and the second connection part (1420). By doing so, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0211] Meanwhile, the third semiconductor device (1330) in the fourth embodiment may be disposed on the first substrate (1100) having a POP (Package On Package) structure in which a plurality of package substrates are stacked. For example, the third semiconductor device (1330) may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling portion (1450). At this time, the memory package may not be connected to the first and second semiconductor devices (1310, 1320).

[0212] Furthermore, the semiconductor package of the modified example may include a first substrate (1100) and first and second semiconductor devices (1310, 1320) disposed on the first substrate (1100) as in the example above. Furthermore, the semiconductor package may include a first connection portion (1410) disposed between the first substrate (1100) and the first and second semiconductor devices (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the example above.

[0213] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0214] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0215] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0216] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0217] Although the above description has focused on the embodiments, this is merely an example and is not intended to limit the embodiments. A person skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For instance, each component specifically shown in the embodiments may be modified and implemented. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A build-up insulating part including a plurality of insulating layers stacked along the vertical direction; A build-up electrode portion comprising a plurality of wiring portions disposed on the upper surface of each of the plurality of insulating layers, and a plurality of via electrodes disposed between the plurality of wiring portions; A protective layer disposed on the above-mentioned build-up insulating portion and comprising a plurality of fillers; and A bonding portion disposed on the upper surface of the above protective layer; comprising, The above-mentioned build-up insulating portion includes an insulating layer comprising a plurality of fillers, and At least one of the plurality of via electrodes penetrates an insulating layer including the plurality of fillers, and Among the plurality of fillers of the insulating layer, the filler closest to the via electrode is provided with a curved surface, and The above-mentioned build-up electrode portion includes a pad portion disposed on the upper surface of the above-mentioned build-up insulating portion, and The bonding portion includes a protrusion disposed on the upper surface of the protective layer and a via portion connected to the pad portion by penetrating the protective layer, Among the plurality of fillers of the protective layer, at least one of the fillers adjacent to the via portion includes a flat surface and a curved surface, A circuit board having at least one of the plurality of fillers of the protective layer adjacent to the protrusion formed as a curved surface.

2. In Paragraph 1, The above bonding portion is a circuit board positioned on the outer side of the circuit board compared to the above build-up electrode portion.

3. In Paragraph 1, The above via portion is located in the via hole of the above protective layer, and Among the plurality of fillers of the protective layer, the filler in contact with the protrusion is a circuit board exposed at the inner wall of the via hole.

4. In Paragraph 1, Among the plurality of fillers of the above protective layer, the filler located between adjacent protrusions is a circuit board provided with a curved surface.

5. In Paragraph 1, The seed layer of the bonding portion above is a circuit board in contact with at least some of the plurality of fillers of the protective layer.

6. In Paragraph 1, A circuit board comprising a plurality of fillers of the protective layer, the first sub-filler overlapping in a vertical direction with the protrusion and a second sub-filler offset in a vertical direction with the protrusion.

7. In Paragraph 6, The first sub-pillar and the second sub-pillar are circuit boards that are not exposed on the upper surface of the protective layer.

8. In Paragraph 1, A cavity formed in the above-mentioned build-up insulating portion; and A connecting member disposed in the above cavity; further comprising, The above bonding portion is a circuit board that overlaps the above cavity in a vertical direction.

9. In Paragraph 8, A circuit board where the distance between the bonding portion and the connecting member is greater than the distance between the build-up electrode portion and the connecting member.

10. In Paragraph 1, The above protective layer is a circuit board comprising a plurality of resin-rich regions in which the resin is greater than or equal to a predetermined ratio.

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