Pulsed voltage overshoot control

Abstract

Methods and apparatus for processing a substrate using a plasma processing system. One example plasma processing system includes a pulser circuit configured to deliver a pulsed voltage waveform to a bias electrode of the plasma processing system, a junction box circuit coupled between the pulser circuit and the bias electrode, a shunt branch including a first end selectively coupled to the junction box circuit and a second end coupled to a reference potential node, and a system controller. The system controller includes one or more processors configured to ( / ) couple, in response to a first trigger based on a first swing of a pulse of the pulsed voltage waveform, the first end of the shunt branch to the junction box circuit, and (77) decouple, in response to a second trigger based on a second swing of the pulse, the first end of the shunt branch from the junction box circuit.

Description

PATENTAttorney Docket No.: 44025194WO01PULSED VOLTAGE OVERSHOOT CONTROLBACKGROUNDField

[0001] Embodiments described herein generally relate to a system and methods used in semiconductor device fabrication. More specifically, embodiments of the present disclosure relate to a plasma processing system used to process a substrate.Description of the Related Art

[0002] Reliably producing high aspect ratio features is one of the key technology challenges for the next generation of semiconductor devices. One method of forming high aspect ratio features uses a plasma-assisted etching process to bombard a material formed on a surface of a substrate through openings formed in a patterned mask layer formed on the substrate surface.

[0003] With technology node advancing towards 2 nanometers (nms), the fabrication of smaller features with larger aspect ratios requires atomic precision for plasma processing. For etching processes where the plasma ions play a major role, ion energy control is always challenging the semiconductor equipment industry. In a typical plasma-assisted etching process, the substrate is positioned on an electrostatic chuck (ESC) disposed in a processing chamber, a plasma is formed over the substrate, and ions are accelerated from the plasma towards the substrate across a plasma sheath, i.e. , region depleted of electrons, formed between the plasma and the surface of the substrate. Traditional radio frequency (RF) substrate biasing methods, which use sinusoidal RF waveforms to excite the plasma and form the plasma sheath, have been unable to desirably form these smaller device feature sizes. Recently, it has been found that utilizing pulsed power sources to deliver high voltage direct current (DC) pulses to one or more electrodes within a processing chamber can be useful in desirably controlling the plasma sheath formed over the surface of the substrate.

[0004] Pulsed power sources provide pulsed DC bias to a cathode, a metal plate that can be coupled to the plasma using capacitive coupling through a dielectric layer. During the plasma processing of a substrate, each of the delivered voltage pulses willPATENTAttorney Docket No.: 44025194WO01 typically be configured to generally include a sheath collapse stage, an ion current stage, and a sheath formation stage that is disposed between the sheath collapse stage and an ion current stage. The sheath collapse stage may be implemented by generating a positive voltage (e.g., 100 volts) to be used to collapse a sheath generated over a surface of the substrate disposed on a substrate support positioned in a processing chamber. During the ion current stage, ions within the processing chamber flow to the surface of the substrate due to a generated negative voltage (e.g., -1600 volts) that is applied to an electrode disposed adjacent to the substrate. In some cases, the utilization of pulsed power sources to deliver voltage pulses in plasma processing may undesirably increase plasma potential to a positive value relative to a ground reference during a portion of the delivery of each delivered pulse within a processing chamber due to a large voltage overshoot during the transition from the ion current stage to the sheath collapse stage. The positive voltage swing in the applied bias can result in the generation of contamination inside of the processing chamber due to ion bombardment and sputtering of the pulse biased process chamber surfaces.

[0005] Accordingly, there is a need in the art for improved plasma processing systems and methods that solve the problems described above.SUMMARY

[0006] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the appended drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed.

[0007] Embodiments provided herein generally include apparatus, plasma processing systems, and methods for plasma processing of a substrate in a plasma processing chamber.

[0008] Embodiments of the present disclosure provide a plasma processing system. The plasma processing system generally includes a pulser circuit configured to deliver a pulsed voltage waveform to a bias electrode of the plasma processing system, aPATENTAttorney Docket No.: 44025194WO01 junction box circuit coupled between the pulser circuit and the bias electrode, a shunt branch including a first end selectively coupled to the junction box circuit and a second end coupled to a reference potential node, and a system controller comprising one or more processors. The one or more processors are configured to ( / ) couple, in response to a first trigger based on a first swing of a pulse of the pulsed voltage waveform, the first end of the shunt branch to the junction box circuit, and ( / / ) decouple, in response to a second trigger based on a second swing of the pulse, the first end of the shunt branch from the junction box circuit.

[0009] Embodiments of the present disclosure are directed to a method for waveform generation. The method generally includes ( / ) delivering, using a pulser circuit, a pulsed voltage waveform to a bias electrode of a plasma processing system through a junction box circuit, ( / / ) coupling, in response to a first trigger based on a first swing of a pulse of the pulsed voltage waveform, a shunt branch between the junction box circuit and a reference potential node, and (Hi) decoupling, in response to a second trigger based on a second swing of the pulse, the shunt branch from the junction box circuit.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] So that the manner in which the above recited features of embodiments of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

[0011] Figure 1 is a schematic representation of an example plasma processing system, in which embodiments of the present disclosure may be implemented.

[0012] Figure 2 illustrates a graph of two separate asymmetric voltage waveforms that are established on a substrate due to a voltage waveform applied to an electrode of a processing chamber, in accordance with certain embodiments of the present disclosure.PATENTAttorney Docket No.: 44025194WO01

[0013] Figure 3 is a block diagram of an example plasma processing system that includes a shunt branch, in accordance with certain embodiments of the present disclosure.

[0014] Figure 4A is a block diagram of an example plasma processing system with a discharge path through the shunt branch enabled, in accordance with certain embodiments of the present disclosure.

[0015] Figure 4B is a block diagram of an example plasma processing system with a discharge path through the shunt branch disabled, in accordance with certain embodiments of the present disclosure.

[0016] Figures 5A and 5B are block diagrams of portions of example plasma processing systems that include shunt branches during shunt branch enablement, in accordance with certain embodiments of the present disclosure.

[0017] Figure 6 is a flow diagram illustrating example operations for waveform generation, in accordance with certain embodiments of the present disclosure.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.DETAILED DESCRIPTION

[0019] Certain embodiments of the present disclosure generally relate to apparatus and methods for minimizing (or at least reducing) a pulsed voltage (PV) overshoot commonly found during the application of a series of voltage pulses of a pulsed voltage waveform provided to an electrode disposed within a plasma processing system. Such a plasma processing system may include a pulser circuit, a junction box circuit, a plasma processing chamber, and a shunt branch (which may, in some cases, be implemented inside the junction box circuit). The shunt branch may be selectively coupled to a portion of the junction box circuit to provide a discharge path from the junction box circuit to a reference potential node (e.g., electrical ground). The coupling (and decoupling) of the shunt branch to the junction circuit box may be controlled based on a first transistor-transistor logic (TTL) synchronization signal that representsPATENTAttorney Docket No.: 44025194WO01 the pulsing state (e.g., on state or off state) of the pulsed voltage waveform provided by the pulser circuit. That is, the discharge path from the junction box circuit to the reference potential node may be enabled when the pulsing circuit is in the off state (e.g., in an off period and not generating a pulse), and disabled when the pulsing circuit is in the on state (e.g., in an on period and generating a pulse).

[0020] In some embodiments, a multivibrator circuit included in the plasma processing system may provide a second TTL synchronization signal to trigger the coupling (and decoupling) of the shunt branch to the junction circuit box. In some cases, the second TTL synchronization signal may be a modified version of the first TTL synchronization signal, whereas in other cases, the second TTL synchronization signal may be generated by the multivibrator circuit. By utilizing the second TTL synchronization signal to trigger the coupling and decoupling of the shunt branch, the discharge path through the shunt branch may be provided during only a portion of the applied voltage pulse, such as the off state of the pulsing circuit (as opposed to the entirety of the off state).Processing System Examples

[0021] Figure 1 is a schematic representation of an example plasma processing system 10. The plasma processing system 10 is configured for plasma-assisted substrate processing process, such as a plasma-assisted etching process or deposition process. In some examples, a plasma-assisted process include a plasma- assisted etching process, such as a reactive ion etch (RIE) process. The plasma processing system 10 can also be used in other plasma-assisted processes, such as plasma-enhanced deposition processes (for example, plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processing, plasma-based ion implant processing, or plasma doping (PLAD) processing. In some embodiments, as shown in Figure 1 , the plasma processing system 10 is configured to form a capacitively-coupled-plasma (CCP). In other embodiments, a plasma may alternately be generated by an inductively coupled plasma (ICP) source disposed over a processing region of the plasma processing system 10.PATENTAttorney Docket No.: 44025194WO01

[0022] The plasma processing system 10 includes a processing chamber 100, a substrate support assembly 136, a gas delivery system 182, a high voltage direct current (DC) supply 173, a RF generator 171 , and a RF match 172 (e.g., RF impedance matching networks). A chamber lid 123 includes one or more sidewalls and a chamber base that are configured to withstand the pressures and energy applied to them while a plasma 101 is generated within a vacuum environment maintained in a processing volume 129 of the processing chamber 100 during processing.

[0023] The gas delivery system 182, which is coupled to the processing volume 129 of the processing chamber 100 is configured to deliver at least one processing gas from at least one gas processing source 119 to the processing volume 129 of the processing chamber 100. The gas delivery system 182 includes the gas processing source 119 and one or more gas inlets 128 positioned through the chamber lid 123. The gas inlets 128 are configured to deliver one or more processing gasses to the processing volume 129 of the processing chamber 100.

[0024] The processing chamber 100 includes a chamber lid 123 and a substrate support assembly 136 positioned in the processing volume 129 of the processing chamber 100. In some embodiments, the chamber lid 123 is grounded and thus acts as an upper electrode during plasma processing. In some embodiments, the RF generator 171 is electrically coupled to a first lower electrode, such as the RF baseplate 137. The RF generator 171 is configured to deliver an RF signal to ignite and maintain the plasma 101 between the upper and lower electrodes. In one example, the RF generator 171 may deliver an RF source power to the RF baseplate 137 within the substrate support assembly 136 (e.g., a cathode assembly) for plasma production. However, in some alternative configurations, the RF generator 171 can be electrically coupled to the upper electrode. A center frequency of the RF source power can be from 13.56 megahertz (MHz) to very high frequency band such as 40 MHz, 60 MHz, 120 MHz or 162 MHz. The RF source power can be operated in a continuous mode or a pulsed mode. A pulsing frequency of the RF power can be from 100 to 10 kHz, and duty cycles are ranging from 5% to 95%. The RF generator 171 has a frequency tuning capability and can adjust its RF power frequency within e.g., ±5% or ±10%. In some embodiments, the RF generator 171 switches the RF power frequency at a predefined speed (e.g., two nanoseconds, fifty nanoseconds, etc.).PATENTAttorney Docket No.: 44025194WO01

[0025] The substrate support assembly 136 is coupled to the RF generator 171 configured to deliver an RF signal to the processing volume 129 of the processing chamber 100. The RF generator 171 is electronically coupled to the RF match 172 disposed between the RF generator 171 and the processing volume 129 of the processing chamber 100. For example, the RF match 172 is an electrical circuit used between the RF generator 171 and a plasma reactor (e.g., the processing volume 129 of the processing chamber 100) to optimize power delivery efficiency. One or more RF filters (e.g., within the RF match 172) are designed to only allow powers in a selected frequency range, and to isolate RF power supplies from each other. In some cases, a bandwidth of an RF filter has to be larger than a frequency tuning range of the RF generator 171 .

[0026] During the plasma processing, the RF generator 171 delivers an RF signal to the RF baseplate 137 of the substrate support assembly 136 via the RF match 172. For example, the RF signal is applied to a load (e.g., gas) in the processing volume 129 of the processing chamber 100. If an impedance of the load is not properly matched to an impedance of a source (e.g., the RF generator 171 ), a portion of a waveform can reflect back in an opposite direction. Accordingly, to prevent a substantial portion of the waveform from reflecting back, it is necessary to find a match impedance (e.g., a matching point) by adjusting one or more components of the RF match 172 as the source and load impedances change.

[0027] The RF match 172 is electrically coupled to the RF generator 171 , the substrate support assembly 136, and a voltage waveform generator 175. The RF match 172 is configured to receive a synchronization signal from either or both of the RF generator 171 and the voltage waveform generator 175.

[0028] The substrate support assembly 136 may be coupled to a high voltage DC supply 173 that supplies a chucking voltage thereto. The high voltage DC supply 173 may be coupled to a filter assembly 111 that is disposed between the high voltage DC supply 173 and the substrate support assembly 136. The filter assembly 111 is configured to electronically isolate the high voltage DC supply 173 during plasma processing. In one configuration, a static DC voltage is between about -5000V and about +5000V, and is delivered using an electrical conductor (such as a coaxial powerPATENTAttorney Docket No.: 44025194WO01 delivery line). The filter assembly 111 may include multiple filtering components or a single common filter.

[0029] The substrate support assembly 136 is also coupled to a voltage waveform generator 175 configured to supply a voltage to a bias electrode 138 within the substrate support assembly 136 to bias a substrate disposed on the substrate support assembly 136. The voltage waveform generator 175 may alternately be coupled to the RF baseplate 137 or a second electrode disposed within the substrate support assembly 136. The voltage waveform generator 175 is coupled to the filter assembly 111 , which is coupled to the electrode disposed within the substrate support assembly 136. The filter assembly 111 is disposed between the voltage waveform generator 175 and the substrate support assembly 136. The filter assembly 111 is configured to electronically isolate the voltage waveform generator 175 from at least the RF signal provided by the RF generator 171 during plasma processing.

[0030] The RF generator 171 and the voltage waveform generator 175 are each directly coupled to a system controller 126. The system controller 126 synchronizes the respective generated RF signal and voltage waveform.

[0031] Voltage and current sensors can be placed at an input and / or output of the RF match 172 to measure impedance and other parameters. These sensors can be synchronized using an external transistor-transistor logic (TTL) synchronization signal from an advanced waveform generator and / or RF generators or using measured voltage and current data to determine timing internally. For example, an output sensor 117 is configured to measure the impedance of the processing chamber 100, and other characteristics such as the voltage, current, harmonics, phase, and / or the like. An input sensor 116 is configured to measure the impedance of the RF generator 171 and other characteristics such as the voltage, current, harmonics, phase, and / or the like. Based on either of the synchronization signals or the characteristics of the processing chamber 100, the RF match 172 is able to capture fast impedance changes and optimize impedance matching.

[0032] The voltage waveform generator 175 is used to supply a voltage waveform and / or a tailored voltage waveform, which includes a series of voltage pulses that are provided to the bias electrode 138. The voltage waveform generator 175 may outputPATENTAttorney Docket No.: 44025194WO01 a synchronization TTL signal to the RF match 172. The voltage waveform is coupled to the bias electrode 138 through the filter assembly 111. Typically, the bias electrode 138 is formed of one or more electrically conductive parts, such as one or more metal meshes, foils, plates, or combinations thereof. The high voltage DC supply 173 is applied to chuck a wafer during a process for a thermal control. In some cases, there can be a third electrode at an edge of the cathode assembly for edge uniformity control.

[0033] The system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU), a memory, and support circuits. The system controller 126 is used to control the process sequence used to process the substrate, including the substrate biasing described herein. The CPU is a general- purpose computer processor configured for use in an industrial setting for controlling the processing chamber and sub-processors related thereto. The memory described herein, which is generally non-volatile memory, may include random access memory, read-only memory, floppy or hard disk drive, or other suitable forms of digital storage, local or remote. The support circuits are conventionally coupled to the CPU and comprise cache, clock circuits, input / output subsystems, power supplies, and the like, and combinations thereof. Software instructions (program) and data can be coded and stored within memory to instruct a processor within CPU. A software program (or computer instructions) readable by CPU in the system controller 126 determines which tasks are performable by the components in the plasma processing system 10.

[0034] Typically, the program, which is readable by the CPU in the system controller 126, includes code, which, when executed by the CPU, performs tasks relating to the plasma processing schemes described herein. The program may include instructions that are used to control the various hardware and electrical components within the plasma processing system 10 to perform the various process tasks and various process sequences used to implement the methods described herein. In some embodiments, the program includes instructions that are used to perform one or more of the operations described below in relation to Figures 3-6.Voltage Waveform ExamplesPATENTAttorney Docket No.: 44025194WO01

[0035] Figure 2 illustrates a graph 200 of two separate non-sinusoidal voltage waveforms established at a substrate disposed on the substrate support assembly 136 of the processing chamber 100 due to the delivery of a voltage waveform to the bias electrode 138 of the processing chamber 100. A first waveform (e.g., a waveform 225) is an example of a non-com pensated voltage waveform established at the substrate during the plasma processing. A second waveform (e.g., a waveform 230) is an example of a compensated voltage waveform established at the substrate by applying a negative slope waveform to the bias electrode 138 of the processing chamber 100 during an “ion current stage” portion of the voltage waveform cycle by use of a current source. The compensated voltage waveform can alternatively be established by applying a negative voltage ramp during the ion current stage of the voltage waveform generated by the voltage waveform generator 175. The voltage waveform cycle of the waveforms 225, 230 each have a period TP, which is, for example, typically between 2 microsecond (ps) and 10 ps, such as 2.5 ps. The ion current stage of the voltage waveform cycle will typically take up between about 50% and about 95% of the period TP, such as from about 80% to about 90% of the period TP.

[0036] The waveforms 225 and 230 include two main stages: an ion current stage and a sheath collapse stage. Both portions (e.g., the ion current stage and the sheath collapse stage) of the waveforms 225 and 230, can be alternately and / or separately established at the substrate during the plasma processing. At a beginning of the ion current stage, a drop in the voltage at the substrate is created, due to the delivery of a negative portion of the voltage waveform (e.g., the ion current portion) provided to the bias electrode 138 by the voltage waveform generator 175, which creates a high voltage sheath above the substrate. The high voltage sheath allows the plasma generated positive ions to be accelerated towards the biased substrate during the ion current stage, and thus, for RIE processes, controls the amount and characteristics of the etching process that occurs on the surface of the substrate during the plasma processing. The sheath collapse stage includes a positive voltage swing 240 (e.g., as a result of the positive wafer voltage), and the ion current stage includes a negative voltage swing (e.g., as a result of the positive wafer voltage), as illustrated in Figure 2.PATENTAttorney Docket No.: 44025194WO01

[0037] In some embodiments, it is desirable for the ion current stage to include a region of the voltage waveform that achieves the voltage at the substrate that is stable or minimally varying throughout the stage, as illustrated in Figure 2 by the waveform 230. One will note that significant variations in the voltage established at the substrate during the ion current stage, such as shown by the positive slope in the waveform 225, will undesirably cause a variation in the ion energy distribution (IED) and thus cause undesirable characteristics of the etched features to be formed in the substrate during the RIE process. Plasma sheath impedance varies with supplied voltage waveform voltages. The RF match 172 can use either or both of the synchronization signals and / or use its internal sensors to sample impedances in different processing phases. In one example, a synchronization signal or characteristics determined by the input sensor 116 or the output sensor 117 are used to trigger the RF match 172 to determine at least two different impendences at different processing stages. Then, the RF match 172 updates its matching point based on the at least two different impedances.Pulsed Voltac / e Overshoot Control Examples

[0038] Plasma processing systems may utilize pulsed power sources (e.g., voltage waveform generator 175) to generate pulsed voltage (PV) voltage waveforms during plasma-assisted processing. Pulsed power source operation involves an “on” state (e.g., an on period when the pulsed power source is generating pulses) and an “off” state (e.g., an off period when the pulsed power source is not generating pulses). In some cases, when the pulsed power source transitions from the on state to the off state (when the pulsed power source turns off), positive voltage overshoot may occur. The positive voltage overshoot may increase plasma potential inside the processing chamber of the plasma processing system. As a result of the increased plasma potential, ions may bombard surfaces inside the processing chamber during the pulsed power source off state, which leads to sputtering of the surfaces within the processing chamber and to contamination of the processing chamber. In addition, undesirable processing variation may also be introduced in the plasma processing system. Certain embodiments of the present disclosure generally relate to apparatus and methods for minimizing (or at least reducing) positive voltage overshoot during a pulsing operation performed in a plasma processing system. In this manner,PATENTAttorney Docket No.: 44025194WO01 contamination of a substrate and processing chamber of the plasma processing system may be reduced.

[0039] Figure 3 is a block diagram of an example plasma processing system 300 that includes a shunt branch 330, in accordance with certain embodiments of the present disclosure. The plasma processing system 300 may also include a pulser circuit 310, a junction box circuit 320, and a plasma processing chamber 340 (e.g., processing chamber 100). The pulser circuit 310 may be coupled to a reference potential node 350 (e.g., electrical ground, labeled “Ground”) and to the junction box circuit 320. The pulser circuit 310 may be configured to deliver a pulsed voltage waveform to a bias electrode (e.g., bias electrode 138) of the plasma processing system through the junction box circuit 320 and generate a first transistor-transistor logic (TTL) synchronization signal 360. The plasma processing chamber 340 may be coupled to the junction box circuit 320 and the reference potential node 350. That is, a discharge path may exist between the plasma processing chamber 340 and the reference potential node 350 as well as between the pulser circuit 310 and the reference potential node 350. In some cases, the junction box circuit 320 may be coupled between the pulser circuit 310 and the bias electrode. The shunt branch 330 may include a first end selectively coupled to the junction box circuit 320 and a second end coupled to the reference potential node 350, thereby forming an additional possible discharge path.

[0040] In some embodiments, the plasma processing system 300 may include a system controller (e.g., system controller 126, not shown). The system controller may include one or more processors configured, individually or collectively, to ( / ) couple (e.g., connect), in response to a first trigger based on a first swing of a voltage pulse of the pulsed voltage waveform generated by the pulser circuit 310, the first end of the shunt branch 330 to the junction box circuit 320, and ( / / ) decouple (e.g., disconnect), in response to a second trigger based on a second swing of the pulse, the first end of the shunt branch 330 from the junction box circuit 320. In some embodiments, the first swing of the pulse may be a positive swing and the second swing of the pulse may be a negative swing, whereas in other embodiments, the first swing of the pulse may be a negative swing and the second swing of the pulse may be a positive swing. The positive swing of the pulse refers to the transition of the pulse from a negative voltagePATENTAttorney Docket No.: 44025194WO01 to a positive voltage (e.g., positive voltage swing 240 in the sheath collapse stage illustrated in Figure 2). The negative swing of the pulse refers to the transition of the pulse from a positive voltage to a negative voltage (e.g., negative voltage swing in the ion current stage illustrated in Figure 2).

[0041] In some embodiments, the first swing of the pulse may be associated with a first edge of the first TTL synchronization signal 360, and the second swing may be associated with a second edge of the first TTL synchronization signal 360. In this manner, the first trigger (for coupling the first end of the shunt branch 330 to the junction box circuit 320) may be based on a first edge of the first TTL synchronization signal 360 provided by the pulser circuit 310, and the second trigger (for decoupling the first end of the shunt branch 330 from the junction box circuit 320) may be based on the second edge of the first TTL synchronization signal 360. The first edge of the first TTL synchronization signal 360 may be associated with the first swing, and the second edge of the first TTL synchronization signal 360 may be associated with a start of the second swing. An “on” period of the first TTL synchronization signal 360 may be associated with a voltage pulse (or a swing of the voltage pulse) of the pulsed voltage waveform.

[0042] The first TTL synchronization signal 360 may represent the pulsing state (e.g., “on” state or “off” state) of the pulser circuit 310. In other words, the first TTL synchronization signal 360 is high when the pulser circuit is in the on state (e.g., in an on period), and low (or zero) when the pulser circuit is in the off state (e.g., in an off period). In one configuration, the discharge path from the junction box circuit 320 to the reference potential node 350 may be enabled when the pulser circuit 310 is off (e.g., in the off state and not generating any pulses), and disabled when the pulser circuit 310 is on (e.g., in the on state and generating pulses). In this manner, the additional discharge path through the shunt branch 330 may be used to more quickly discharge the stored charge (e.g., including parasitic capacitance) inside the pulser circuit 310, the junction box circuit 320, and / or the plasma processing chamber 340, thereby reducing the voltage overshoot during the pulser circuit 310 off state, and minimizing (or at least reducing) contamination inside the plasma processing system 300.PATENTAttorney Docket No.: 44025194WO01

[0043] Figure 4A is a block diagram of an example plasma processing system 400A with a discharge path 460 through the shunt branch 330 enabled, in accordance with certain embodiments of the present disclosure. Figure 4B is a block diagram of an example plasma processing system 400B with the discharge path 460 through the shunt branch 330 disabled, in accordance with certain embodiments of the present disclosure. Figures 5A and 5B are block diagrams of portions of example plasma processing systems 500A and 500B that include shunt branches 330 during shunt branch enablement, in accordance with certain embodiments of the present disclosure. Due to their relationship, Figures 4A, 4B, 5A, and 5B are herein described together for clarity.

[0044] Referring to Figures 4A and 4B, the plasma processing systems 400A and 400B may include the pulser circuit 310, the junction box circuit 320, the shunt branch 330, the plasma processing chamber 340, and the reference potential node 350. The pulser circuit 310 may include a pulser 412 (e.g., voltage waveform generator 175) for generating the voltage pulses of the pulsed voltage waveform and a damping circuit 414. The junction box circuit 320 may include a direct current (DC) block capacitor circuit 422 and a radio frequency (RF) filter 424. In some embodiments, the DC block capacitor circuit 422 may include (or be implemented by) one or more capacitive elements. The plasma processing chamber 340 may include parasitic capacitance 442, electrostatic chuck (ESC) capacitance 444 (which may represent the substrate or wafer in the plasma processing chamber 340), and plasma 446 (e.g., plasma 101 in Figure 1 (e.g., complex impedance)).

[0045] The shunt branch 330 may include a switch circuit 432. The first end of the shunt branch 330 may be coupled between the DC block capacitor circuit 422 and the RF filter 424, while the second end of the shunt branch 330 may be coupled to the reference potential node 350. In some cases, the shunt branch 330 may be included in the junction box circuit 320. The switch circuit 432 may include or be implemented by one or more switches. For example, the switch circuit 432 may include one switch selectively coupled between the junction box circuit 320 and the shunt branch 330. In another example, the switch circuit 432 may include a plurality of switches (e.g., two switches, three switches, or any number of switches) selectively coupled in series between the junction box circuit 320 and the shunt branch 330. In some cases, thePATENTAttorney Docket No.: 44025194WO01 one or more switches may be implemented by one or more metal-oxide-sem iconductor field-effect transistors (MOSFETs). The one or more MOSFETs may be implemented as silicon carbide (SiC) and / or gallium nitride (GaN) MOSFETS.

[0046] In some embodiments, the shunt branch 330 may include a current limiter 434. The current limiter 434 may include or be implemented by one or more resistive elements coupled in series between the switch circuit 432 and the reference potential node 350. The one or more resistive elements may be configured to limit the inrush current to protect the switch circuit (and the switch(es) thereof) from failure, due to, for example, a safe operating area (SOA) violation.

[0047] As shown in Figure 4A, the shunt branch 330 may be coupled between the junction box circuit 320 and the reference potential node 350 in response to a first trigger based on a first edge of a first TTL synchronization signal 360 provided by the pulser circuit 310. In this manner, the discharge path 460 may be provided. As shown in Figure 4B, the shunt branch 330 may be decoupled from the junction box circuit 320 and the reference potential node 350 in response to a second trigger based on the second edge of the first TTL synchronization signal 360. As described above, the first TTL synchronization signal 360 may represent the pulsing state (e.g., on state or off state) of the pulser circuit 310. Referring to Figure 5A, the first TTL synchronization signal 360 may include a plurality of on periods (e.g., on periods 502 and 504, also referred to and / or understood as high signal periods) that are provided by the pulser circuit 310 when the pulser 412 is in the on state and a plurality of off periods (e.g. , off period 503, also referred to and / or understood as low signal periods) when the pulser 412 is in the off state. It is to be understood that the on periods 502 and 504 and the off period 503 of the first TTL synchronization signal 360 may be cyclical and repeat any number of times.

[0048] Each of the periods 502 and 504 may include a falling edge 506 and a rising edge 508. In some cases, the first edge of the first TTL synchronization signal 360 (e.g., on which the first trigger is based) may be the falling edge 506 of the first TTL synchronization signal, and the second edge of the first TTL synchronization signal 360 (e.g., on which the second trigger is based) may be the rising edge 508 of the first TTL synchronization signal 360. In other cases, the first edge of the first TTL synchronization signal 360 (e.g., on which the first trigger is based) may be the risingPATENTAttorney Docket No.: 44025194WO01 edge 508 of the first TTL synchronization signal, and the second edge of the first TTL synchronization signal 360 (e.g., on which the second trigger is based) may be the falling edge 506 of the first TTL synchronization signal. In yet other cases, the first trigger and the second trigger may both be a falling edge of the first TTL synchronization signal 360 (e.g., a falling edge in consecutive but different on periods), or the first trigger and the second trigger may both be a rising edge of the first TTL synchronization signal 360 (e.g., a rising edge in consecutive but different on periods).

[0049] In some embodiments, the first TTL synchronization signal 360 may be provided to a multivibrator circuit 510. The multivibrator circuit 510 may be included in the system controller and may include a resistor-capacitor network (labeled R-C Network) 520. The multivibrator circuit 510 may be configured to generate a second TTL synchronization signal 512 based on the first TTL synchronization signal 360. In some cases, the second TTL synchronization signal 512 may be a modified version of the first TTL synchronization signal 360, whereas in other cases, the second TTL synchronization signal 512 may generated without directly using the first TTL synchronization signal 360. In some embodiments, the second TTL synchronization signal 512 may be provided by the system controller. The second TTL synchronization signal 512 may include an on period (e.g., on period 514, when the signal is high) and an off period (e.g., off period 516, when the signal is low (or zero)) when the pulser 412 is in the off state. It is to be understood that the on period 514 and the off period 516 of the second TTL synchronization signal 512 may be cyclical and repeat any number of times. In some embodiments, the on period 514 of the second TTL synchronization signal 512 generates the first trigger and the off period 516 of the second TTL synchronization signal 512 generates the second trigger. In some cases, the off period 503 of the first TTL synchronization signal 360 may be defined by the falling edge 506 and the rising edge 508, and the on period 514 of the second TTL synchronization signal 512 may occur during a portion of the off period 503 of the first TTL synchronization signal 360, as illustrated.

[0050] In some embodiments, the trigger for the creation of the “on” period of the second TTL synchronization signal 512 or the creation of the “off’ period of the second TTL synchronization signal 512 is based on or triggered by a characteristic of and / or state of the first TTL synchronization signal 360. In one example, the start of an “on”PATENTAttorney Docket No.: 44025194WO01 period of the second TTL synchronization signal 512 is triggered based on the rising edge 508 or falling edge 506 of the first TTL synchronization signal 360. As a result and as discussed further below, the generated second TTL synchronization signal 512 can be used to separately control the timing and duration of the open and closed states of the switch circuit 432 and thus not be limited by the characteristics of a voltage pulse controlled by the delivery of the first TTL synchronization signal 360.

[0051] In some cases, a duration of the on period (e.g., time Tw, or in other words, the width) of the second TTL synchronization signal 512 may be controlled (e.g., set) by the resistor-capacitor network 520. In this manner, the width of the second TTL synchronization signal 512 may be adjustable for different plasma- assisted processes and thus not be linked to or limited by a characteristic (e.g., TTL pulse duration) of the first TTL synchronization signal 360. In one example, the duration of the on period 514 of the second TTL synchronization signal 512 (e.g., the duration of the switch circuit 432 being closed) may be less than the duration of the on period of the first TTL synchronization signal 360 (e.g., which may be associated with the voltage pulse delivered by the pulser 412). In another example, a duration of the on period 514 of the second TTL synchronization signal 512 may be shorter than a duration of the voltage pulse delivered by the pulser 412. In yet another example, the first TTL synchronization signal 360 may include an on time and an off time, and a duration of the on period 514 of the second TTL synchronization signal 512 may be shorter than a duration of the off time of the first TTL synchronization signal 360. In yet another example, a duration of time that the shunt branch 330 is coupled to the junction box circuit, in response to the first trigger, is less than a duration of time between the first swing and the second swing.

[0052] The second TTL synchronization signal 512 may be provided to a driver 540, which may be coupled to a biasing circuit 530. The driver 540 may be configured to control the enabling and disabling of the discharge path 460 (e.g., operation of the switch circuit 432 (and the switch(es) thereof)). That is, the driver 540 may open (turn off) or close (turn on) the switches (or transistors) of the switch circuit 432 based on the characteristic of the second TTL synchronization signal 512. In some cases, the first trigger, for coupling the shunt branch 330 between the junction box circuit 320 and the reference potential node 350 to provide the discharge path 460 through the shuntPATENTAttorney Docket No.: 44025194WO01 branch 330, may be the on period 514 (or any on period) of the second TTL synchronization signal 512, and the second trigger (for decoupling the shunt branch 330 from the junction box circuit 320) may be the off period 516 (or any off period) of the second TTL synchronization signal 512. The duration Twof the on period 514 may be referred to as a discharge time Tw, representing the duration of time that the discharge path 460 through the shunt branch 330 is provided.

[0053] In cases where the first TTL synchronization signal 360 is used as the trigger to couple and decouple the shunt branch 330 between the junction box circuit 320 and the reference potential node 350, the current limiter 434 may produce undesirable high heat and may even be destroyed as a result of providing the discharge path 460 for the entirety of the off period of the pulser circuit 310. However, it has been found that the stored charge (e.g., including parasitic capacitance) in the plasma processing system 300 is highest at the onset of the off period of the pulser circuit 310 (e.g., during the pulser 412 transition from the “on” period (e.g., ion current stage) to the “off” period (e.g., sheath collapse stage)). During other parts of the off period of the pulser circuit 310, the other discharge paths (e.g., the discharge paths from the pulser circuit 310 to the reference potential node 350 and / or from the plasma processing chamber 340 to the reference potential node 350) may be sufficient for the plasma processing system 300. As a result, and in some cases, the discharge path 460 may be used only during part of the off period of the pulser circuit 310, which can be controlled by the characteristics of the second TTL synchronization signal 512. By utilizing the second TTL synchronization signal 512 (instead of the first TTL synchronization signal 360) as the enabling trigger (e.g., the first trigger) and the disabling trigger (e.g., the second trigger) for providing the discharge path 460, the time when the shunt branch 330 is coupled between the junction box circuit 320 and the reference potential node 350 may be better controlled such that the discharge path 460 is only provided during only part of the off period of the pulser circuit 310. As a result, potential damage to the current limiter 434 may be limited (or at least reduced).

[0054] In some cases, the on period 514 of the second TTL synchronization signal 512 may begin a first period of time (e.g., time TPd) after the falling edge 506 of the first TTL synchronization signal 360. The first period of time TPd may be referred to as the first propagation delay, and may represent the delay between the beginning of the offPATENTAttorney Docket No.: 44025194WO01 period 503 of the first TTL synchronization signal 360 and the beginning of the on period 514 of the second TTL synchronization signal 512. The first period of time TPd may be controlled by the system controller. The on period 514 of the second TTL synchronization signal 512 may end a second period of time (e.g., time Tpe) before the rising edge 508 of the first TTL synchronization signal 360. The second period of time Tpemay be referred to as the second propagation delay, and may represent the delay between the beginning of the on period 504 of the first TTL synchronization signal 360 and the ending of the on period 514 of the second TTL synchronization signal 512. The second period of time Tpemay be also be controlled by the system controller.

[0055] In some embodiments, when greater voltage operation capability is desired, the switch circuit 432 may be implemented by a plurality of MOSFETs, as illustrated in Figure 5B. The portion of the plasma processing system 500B may be similar to the portion of the plasma processing system 500A, except that the driver 540 may be replaced by a plurality of drivers, such as three drivers 542, 544, 546, the biasing circuit 530 may be replaced with biasing circuits 532, 534, 536, and the switch circuit 432 may be implemented with three switches 552, 554, 556 and three balance resistors 562, 564, 566. The three switches 552, 554, 556 may be implemented with MOSFETs (e.g., SiC or GaN MOSFETs), and the three balance resistors 562, 564, 566 may each be implemented with one or more resistive elements. The drivers 542, 544, 546 may be similar to the driver 540 and may be configured to control operation of the switch circuit 432 (and the switches thereof), in accordance with the second TTL synchronization signal 512 and as described with respect to Figure 5A.

[0056] The inclusion of the shunt branch described herein in a plasma processing system may provide an additional discharge path (e.g., in addition to the other discharge paths in the plasma processing system through the pulser circuit and / or the plasma processing chamber) for quicker discharge of the stored charge (e.g., including parasitic capacitance) inside the plasma processing chamber and the junction box circuit, thereby reducing the positive voltage overshoot during a positive swing of an applied voltage pulse (e.g., pulser off state), and minimizing (or at least reducing) contamination inside the plasma processing chamber. The shunt branch may also reduce the fall time of the PV pulse, thereby enabling the pulser in the plasma processing system to operate with a lower pulse-on-time (POT), which may open upPATENTAttorney Docket No.: 44025194WO01 additional process space during plasma-assisted processes. Furthermore, the shunt branch may share the discharge current load with the pulser, thereby enabling additional pulser circuit modifications. For example, the damping circuit may be modified to enable the PV pulses to have a more square-like shape, because the increase in discharge current from the damping circuit modification may be handled by the combination of the additional discharge path through the shunt branch and the discharge path through the pulser circuit (e.g., such that the pulser circuit does not have to handle as much current discharge).

[0057] In some cases, a plasma processing system may utilize series resistorbased damping to introduce a voltage drop across a series resistor in a plasma processing system during PV formation (e.g., in the on state and during the on period). As a result, the potential of a substrate in the plasma processing system may be decreased for similar voltage setpoints without a damping resistor. Embodiments described herein may incorporate stored energy discharge during the pulser off state, which may avoid any reduction in the potential of the substrate.

[0058] In some cases, power dissipation across a series resistor in a plasma processing system may occur during both the pulser on period and the pulser off period transition periods (e.g., when transitioning from one state to another). Embodiments described herein may involve power dissipation across the current limiter during only a fraction of the pulser off period. As a result, average power dissipation may be lower across the current limiter (and a current-limiting resistor included therein) compared to a damping resistor.

[0059] In addition, resistor-based damping techniques may have little to no impact on reducing the rise time and the fall time of the pulser. Embodiments described herein may share the discharge current (e.g., across the discharge path 460 through the shunt branch and the other discharge paths), therefore enabling modification of the damping circuit to reduce the rise and fall times of the pulser, enabling shorter POT operation.Operations for Waveform Generation

[0060] Figure 6 is a flow diagram illustrating example operations 600 for waveform generation, in accordance with certain embodiments of the present disclosure. ThePATENTAttorney Docket No.: 44025194WO01 operations 600 may be performed by a plasma processing system, such as the plasma processing systems 300, 400A, 400B of Figure 3, 4A, and 4B, respectively. In some cases, the operations 600 may be performed by control circuitry (e.g., system controller 126) included in the plasma processing system.

[0061] The operations 600 may include, at block 610, delivering, using a pulser circuit (e.g., pulser circuit 310), a pulsed voltage (PV) waveform to a bias electrode (e.g., bias electrode 138) of a plasma processing system (e.g., plasma processing systems 300, 400A, 400B) through a junction box circuit (e.g., junction box circuit 320).

[0062] At block 620, the operations 600 may include coupling (e.g., connecting), in response to a first trigger based on a first swing of a pulse of the pulsed voltage waveform, a shunt branch (e.g., shunt branch 330) between the junction box circuit and a reference potential node (e.g., reference potential node 350). In one example, the junction box circuit is formed between a pulser (e.g., pulser 412) and a load (e.g., complex load created by a plasma) through an electrode disposed in the process chamber. In this manner, the shunt branch may provide an additional discharge path for stored charge within the junction box circuit to the reference potential node.

[0063] At block 630, the operations 600 may include decoupling (e.g., disconnecting), in response to a second trigger based on a second swing of the pulse, the shunt branch from the junction box circuit. In some embodiments, the first swing of the pulse may be a positive swing and the second swing of the pulse may be a negative swing, whereas in other embodiments, the first swing of the pulse may be a negative swing and the second swing of the pulse may be a positive swing. The positive swing of the pulse refers to the transition of the pulse from negative voltage to a positive voltage (e.g., positive voltage swing 240 in the sheath collapse stage illustrated in Figure 2). The negative swing of the pulse refers to the transition of the pulse from a positive voltage to a negative voltage (e.g., negative voltage swing in the ion current stage illustrated in Figure 2). In some embodiments, the second trigger is created by a start of the second swing of the pulse. In one example, the second trigger is created by a start of a transition from a positive swing to a negative swing. However, in some embodiments, the second trigger may be created by a preset lapse of time stored in the memory of the system controller after a first trigger was generated.PATENTAttorney Docket No.: 44025194WO01

[0064] According to some embodiments, the pulser circuit may be further configured to generate a first transistor-transistor logic (TTL) synchronization signal, where the first swing is associated with a first edge (e.g., falling edge 506 or rising edge 508) of the first TTL synchronization signal (e.g., first TTL synchronization signal 360), and the second swing is associated with a second edge (e.g., falling edge 506 or rising edge 508) of the first TTL synchronization signal.

[0065] In some embodiments, an on period (e.g., on period 514) of a second TTL synchronization signal (e.g., second TTL synchronization signal 512) generates the first trigger and an off period (e.g., off period 503) of the second TTL synchronization signal generates the second trigger. The second TTL synchronization may be provided by a multivibrator circuit (e.g., multivibrator circuit 510). The first trigger may be (or include) the on period of the second TTL synchronization signal. In some cases, the duration of the on period of the second TTL synchronization signal (e.g., the duration of the switch circuit being closed) may be less than the duration of the on period of the first TTL synchronization signal (e.g., which may be associated with the voltage pulse delivered by the pulser). The second trigger may be (or include) an off period (e.g., off period 516) of the second TTL synchronization signal. The second trigger may also be created by a defined lapse of time stored in the memory of the system controller after the first trigger was generated.

[0066] The on period may begin a first period of time (e.g., first propagation delay TPd) after the first edge of the first TTL synchronization signal is provided. The on period may end a second period of time (e.g., second propagation delay Tpe) before the second edge of the first TTL synchronization signal. A duration (e.g., time Tw) of the on period may be controlled (e.g., set) by a resistor-capacitor network (e.g., resistor-capacitor network 520) or controller coupled to the multivibrator circuit.

[0067] The shunt branch may include a switch circuit (e.g., switch circuit 432) selectively coupled to the junction box circuit, the switch circuit including one or more metal-oxide-sem iconductor field-effect transistor (MOSFETs). The MOSFETs may include silicon carbide (SiC) and / or be SiC MOSFETs, or the MOSFETs may include gallium nitride (GaN) and / or be an GaN MOSFETs.PATENTAttorney Docket No.: 44025194WO01

[0068] The shunt branch may further include one or more resistive elements (e.g., current limiter 434, which may include one or more resistive elements) coupled between the switch circuit and the reference potential node.Additional Considerations

[0069] In the above description, details are set forth by way of example to facilitate an understanding of the disclosed subject matter. It should be apparent to a person of ordinary skill in the field, however, that the disclosed implementations are exemplary and not exhaustive of all possible implementations. Thus, it should be understood that reference to the described examples is not intended to limit the scope of the disclosure. Any alterations and further modifications to the described devices, instruments, methods, and any further application of the principles of the present disclosure are fully contemplated as would normally occur to one skilled in the art to which the disclosure relates. In particular, it is fully contemplated that the features, components, and / or steps described with respect to one implementation may be combined with the features, components, and / or steps described with respect to other implementations of the present disclosure. As used herein, the term “about” may refer to a + / -10% variation from the nominal value. It is to be understood that such a variation can be included in any value provided herein.

[0070] As used herein, “a processor,” “at least one processor,” or “one or more processors” generally refers to a single processor configured to perform one or multiple operations or multiple processors configured to collectively perform one or more operations. In the case of multiple processors, performance of the one or more operations could be divided amongst different processors, though one processor may perform multiple operations, and multiple processors could collectively perform a single operation. Similarly, “a memory,” “at least one memory” or “one or more memories” generally refers to a single memory configured to store data and / or instructions, multiple memories configured to collectively store data and / or instructions.

[0071] As used herein, a phrase referring to “at least one of” or “one or more of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, andPATENTAttorney Docket No.: 44025194WO01 a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

[0072] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and / or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0073] The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B and object B touches object C, then objects A and C may still be considered coupled to one another — even if objects A and C do not directly physically touch each other. For instance, a first object may be coupled to a second object even though the first object is never directly physically in contact with the second object.

[0074] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

PATENTAttorney Docket No.: 44025194WO01We claim:1 . A plasma processing system comprising: a pulser circuit configured to deliver a pulsed voltage waveform to a bias electrode of the plasma processing system; a junction box circuit coupled between the pulser circuit and the bias electrode; a shunt branch including a first end selectively coupled to the junction box circuit and a second end coupled to a reference potential node; and a system controller comprising one or more processors being configured to: couple, in response to a first trigger based on a first swing of a pulse of the pulsed voltage waveform, the first end of the shunt branch to the junction box circuit; and decouple, in response to a second trigger based on a second swing of the pulse, the first end of the shunt branch from the junction box circuit.

2. The plasma processing system of claim 1 , wherein the first swing is a positive swing and wherein the second swing is a negative swing.

3. The plasma processing system of claim 1 , wherein the pulser circuit is further configured to generate a first transistor-transistor logic (TTL) synchronization signal and wherein the first swing is associated with a first edge of the first TTL synchronization signal.

4. The plasma processing system of claim 3, wherein an on period of a second TTL synchronization signal provided by a multivibrator circuit generates the first trigger and an off period of the second TTL synchronization signal generates the second trigger.

5. The plasma processing system of claim 4, wherein the on period of the second TTL synchronization signal occurs during a portion of an off period of the first TTL synchronization signal.PATENTAttorney Docket No.: 44025194WO016. The plasma processing system of claim 3, wherein the first swing is a positive swing, wherein the second swing is a negative swing, and wherein an on period of the first TTL synchronization signal is associated with the first swing of the pulse.

7. The plasma processing system of claim 1 , wherein a duration of time that the shunt branch is coupled to the junction box circuit, in response to the first trigger, is less than a duration of time between the first swing and the second swing.

8. The plasma processing system of claim 1 , wherein the pulser circuit is further configured to generate a first transistor-transistor logic (TTL) synchronization signal that comprises an on time and an off time, the first swing is associated with a first edge of the first TTL synchronization signal, an on period of a second TTL synchronization signal, provided by the system controller, generates the first trigger and an off period of the second TTL synchronization signal generates the second trigger, and a duration of the on period of the second TTL synchronization signal is shorter than a duration of the off time of the first TTL synchronization signal.

9. The plasma processing system of claim 8, wherein the on period of the second TTL synchronization signal begins a first period of time after the first edge of the first TTL synchronization signal.

10. The plasma processing system of claim 9, wherein the on period of the second TTL synchronization signal ends a second period of time before a second edge of the first TTL synchronization signal is generated and wherein the second edge of the first TTL synchronization signal is associated with a start of the second swing.11 . The plasma processing system of claim 8, wherein the on period of the second TTL synchronization signal is controlled by a resistor-capacitor network coupled to a multivibrator circuit.PATENTAttorney Docket No.: 44025194WO0112. The plasma processing system of claim 3, wherein the first edge comprises a falling edge of the first TTL synchronization signal and wherein a second edge of the first TTL synchronization signal comprises a rising edge of the first TTL synchronization signal.

13. The plasma processing system of claim 1 , wherein the shunt branch comprises a switch circuit selectively coupled to the junction box circuit, the switch circuit comprising a metal-oxide-sem iconductor field-effect transistor (MOSFET), and wherein the MOSFET comprises: silicon carbide (SiC); orGallium nitride (GaN).

14. The plasma processing system of claim 13, wherein the shunt branch further comprises one or more resistive elements coupled between the switch circuit and the reference potential node.

15. The plasma processing system of claim 1 , wherein the shunt branch comprises a switch circuit selectively coupled to the junction box circuit, the switch circuit comprising a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) coupled in series.

16. The plasma processing system of claim 1 , wherein: the pulser circuit comprises a pulser and a damping circuit; and the junction box circuit comprises one or more capacitive elements and a radio frequency (RF) filter.

17. A method for waveform generation, the method comprising: delivering, using a pulser circuit, a pulsed voltage waveform to a bias electrode of a plasma processing system through a junction box circuit; coupling, in response to a first trigger based on a first swing of a pulse of the pulsed voltage waveform, a shunt branch between the junction box circuit and a reference potential node; andPATENTAttorney Docket No.: 44025194WO01 decoupling, in response to a second trigger based on a second swing of the pulse, the shunt branch from the junction box circuit.

18. The method of claim 17, wherein the first swing is a positive swing and wherein the second swing is a negative swing.

19. The method of claim 17, wherein the pulser circuit is further configured to generate a first transistor-transistor logic (TTL) synchronization signal, wherein the first swing is associated with a first edge of the first TTL synchronization signal, and wherein the second swing is associated with a second edge of the first TTL synchronization signal.

20. The method of claim 19, wherein an on period of a second TTL synchronization signal provided by a multivibrator circuit generates the first trigger and an off period of the second TTL synchronization signal generates the second trigger.

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