Fault-tolerant atomic quantum computation

Abstract

Provided herein are techniques for developing fault-tolerant quantum computation (FTQC) systems by leveraging quantum error correction (QEC) strategies in a neutral atom quantum information processing system. Techniques describe herein leverage error correction methods to correct errors and replenish lost qubits during operation of the quantum computer. To implement such error correction strategies, the quantum information processing system described herein uses a combination of various syndrome extraction (SE) methods and selective-state readout (SSR). These SE methods enable high-fidelity quantum computing with reduced computational overhead.

Description

Attorney Docket No.: H0776.70187WO00FAULT-TOLERANT ATOMIC QUANTUM COMPUTATIONCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit under 35 U. S. C. § 119(e) of U. S. Provisional Patent Application No. 63 / 730,321, filed December 10, 2024, and titled “LEVERAGING LOSS ERRORS IN LOGICAL ALGORITHMS,” and to U. S. Provisional Patent Application No. 63 / 738,880, filed December 26, 2024, and titled “LEVERAGING LOSS ERRORS IN LOGICAL ALGORITHMS,” each of which is incorporated herein by reference in its entirety.FEDERALLY SPONSORED RESEARCH

[0002] This invention was made with government support under 2012023 awarded by National Science Foundation (NSF) and under W911NF-23-2-0219 awarded by U. S. Army Research Office (ARO) and under HR0011-23-3-0012 and HR0011-24-9-0359 awarded by U. S. Department of Defense / Defense Advanced Research Projects Agency (DOD / DARPA). The government has certain rights in the invention.BACKGROUND

[0003] Quantum information processing techniques perform computation by manipulating one or more quantum objects (e.g., objects that can store quantum states and / or manipulate quantum states). These techniques are sometimes referred to as "quantum computing." The field of quantum error correction (QEC) represents one illustrative approach to realizing large-scale quantum computers. In these approaches, one or more qubit systems are coupled to each other inside a vacuum chamber to form a quantum circuit. Qubit systems in a quantum circuit physically and electronically interact to perform quantum computation. QEC focuses on reducing error propagation within quantum circuits in an effort to realize fault-tolerant quantum computation (FTQC) systems.SUMMARY

[0004] In some embodiments, the techniques described herein relate to a method of performing error correction during a quantum computation, the method comprising: encoding first quantum information into a first logical qubit comprising a first plurality of physical qubits; performing at least one quantum operation on the first logical qubit by applying one or more quantum gates to qubits of the first plurality of physical qubits; measuring an error syndrome - 1 - #14554048v3Attorney Docket No.: H0776.70187WO00of the first logical qubit; generating a list of potential loss events based on the measured error syndrome, the potential loss events identifying a loss of one or more of the first plurality of physical qubits during the performance of the at least one quantum operation; generating a decoding hypergraph based at least in part on the list of potential loss events; generating, by providing the decoding hypergraph as input to a quantum decoder, at least one quantum error correction operation to correct errors that occurred during the performance of the at least one quantum operation; and applying the at least one quantum error correction operation to the first logical qubit to correct the errors that occurred during the performance of the at least one quantum operation.

[0005] In some embodiments, the method further comprises cancelling quantum gates applied to one or more lost first plurality of physical qubits after the loss is identified.

[0006] In some embodiments, generating the decoding hypergraph comprises: constructing a loss circuit of a plurality of loss circuits for a physical qubit lifecycle, wherein the loss circuit of the plurality of loss circuits represents a loss event of the first physical qubit for the physical qubit lifecycle, wherein the loss circuit comprises: a plurality of detectors; a plurality of hyperedges configured to connect the plurality of detectors; and combining the plurality of loss circuits into the decoding hypergraph of the physical qubit lifecycle.

[0007] In some embodiments, connecting the plurality of detectors comprises using a hyperedge to: represent a possible error event; connect the plurality of detectors flipped by the possible error event; and extract a corresponding probability for the possible error event.

[0008] In some embodiments, extracting a corresponding probability for the possible error event comprises assigning a first probability to a first hyperedge associated with a lost qubit, wherein the first probability is associated with a first weight of the decoding hypergraph.

[0009] In some embodiments, the first probability is approximately equal to 0.5 and the first weight is approximately equal to 0.

[0010] In some embodiments, combining the loss circuits, wherein the loss circuit corresponds to a syndrome of the loss event, results in a lifecycle syndrome, wherein the lifecycle syndrome corresponds to a syndrome of the physical qubit for the lifecycle of the physical qubit.

[0011] In some embodiments, the method of performing error correction during a quantum computation further comprises measuring the first plurality of physical qubits.

[0012] In some embodiments, measuring the first plurality of physical qubits comprises determining a state of a physical qubit of the plurality of physical qubits.- 2 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0013] In some embodiments, determining the state of the physical qubit comprises determining that the state of the physical qubit is at least one of |0〉, |1〉, or loss (|L〉).

[0014] In some embodiments, applying quantum gates between the physical qubits of the first plurality comprises applying Hadamard gates, Pauli-X gates, Pauli-Y gates, Pauli-Z gates, S gates, T gates, CZ gates, SWAP gates, CNOT gates, and / or Toffoli gates.

[0015] In some embodiments, the method of performing error correction during a quantum computation further comprises performing quantum error correction using the decoding hypergraph, the quantum error correction comprising: extracting a set of decoding hypergraphs from detected loss events; summing the decoding hypergraphs of the set of decoding hypergraphs; applying a normalized weight associated with the decoding hypergraph; generating a final decoding hypergraph, wherein the final decoding hypergraph comprises lifestyles and statistical weights for lifecycles of lost physical qubits; and inputting the final decoding hypergraph into a decoder, wherein the decoder is configured to perform quantum error correction.

[0016] In some embodiments, performing the quantum error correction is performed by a trained neural network and / or machine learning model.

[0017] In some embodiments, performing the quantum error correction is performed by applying most likely error (MLE) decoding, minimum weight perfect matching (MWPM) decoding, belief propagation decoding, and / or delayed-erasure decoding..

[0018] In some embodiments, measuring the error syndrome comprises: performing a first quantum gate between at least two physical qubits of the first plurality of physical qubits; performing a physical SWAP movement between the at least two physical qubits of the first plurality of physical qubits; and after performing the physical SWAP movement, measuring an error syndrome of the first logical qubit.

[0019] In some embodiments, measuring the error syndrome comprises: entangling the first logical qubit in a first cluster state; encoding second quantum information into a second logical qubit comprising a second plurality of physical qubits; entangling the second logical qubit in a second cluster state; and teleporting the first quantum information from the first logical qubit to the second logical qubit by: applying a Hadamard gate to physical qubits of the first plurality of physical qubits; applying at least one quantum operation between the first logical qubit and the second logical qubit to entangle one or more quantum states of the first and second logical qubits; and measuring, using state- selective readout, quantum states of the first plurality of- 3 - #14554048v3Attorney Docket No.: H0776.70187WO00physical qubits, wherein the measuring obtains an error syndrome associated with the first logical qubit.

[0020] In some embodiments, the techniques described herein relate to a method for performing syndrome extraction during operation of a quantum computer, the method comprising: encoding quantum information into a logical qubit comprising a plurality of physical qubits; performing a first quantum gate between at least two physical qubits of the plurality of physical qubits; performing a physical SWAP movement between the at least two physical qubits of the plurality of physical qubits; and after performing the physical SWAP movement, measuring an error syndrome of the logical qubit.

[0021] In some embodiments, performing the first quantum gate comprises: applying a CNOT gate to the at least two physical qubits; and applying a SWAP gate to the at least two physical qubits, wherein the SWAP gate comprises three alternating CNOT gates.

[0022] In some embodiments, the first quantum gate is canceled if at least one of the two physical qubits of the plurality of physical qubits is lost prior to performing the first quantum gate.

[0023] In some embodiments, all quantum gates applied to a lost qubit of the plurality of physical qubits are canceled if at least one of the two physical qubits of the plurality of physical qubits is lost prior to performing the first quantum gate.

[0024] In some embodiments, in response to the first quantum gate being canceled, the lost qubit is replaced with a fresh qubit.

[0025] In some embodiments, the method for performing syndrome extraction during operation of a quantum computer further comprises measuring a quantum state of a physical qubit of the plurality of physical qubits.

[0026] In some embodiments, measuring the quantum state of the physical qubit comprises determining that the quantum state is at least one of |0〉, |1〉, or lost (|L〉).

[0027] In some embodiments, the method further comprises replacing a lost physical qubit with a new physical qubit, wherein the lost physical qubit is a physical qubit with a quantum state that is measured to be |L).

[0028] In some embodiments, the techniques described herein relate to a method for performing syndrome extraction during operation of a quantum computer, the method comprising: encoding first quantum information into a first logical qubit comprising a first plurality of physical qubits; entangling the first logical qubit in a first cluster state; encoding- 4 - #14554048v3Attorney Docket No.: H0776.70187WO00second quantum information into a second logical qubit comprising a second plurality of physical qubits; entangling the second logical qubit in a second cluster state; teleporting the first quantum information from the first logical qubit to the second logical qubit by: applying a Hadamard gate to physical qubits of the first plurality of physical qubits; and applying at least one quantum operation between the first logical qubit and the second logical qubit to entangle one or more quantum states of the first and second logical qubits; and measuring, using state-selective readout, quantum states of the first and / or second plurality of physical qubits, wherein the measuring obtains an error syndrome associated with the first and / or logical qubit.

[0029] In some embodiments, applying the Hadamard gate to the physical qubits of the first plurality of physical qubits comprises applying a Hadamard gate to every physical qubit of the plurality of physical qubits.

[0030] In some embodiments, entangling the first logical qubit in the first cluster state comprises entangling the first plurality of physical qubits in a Raussendorf-Harrington-Goyal (RHG) cluster state or a XZZX cluster state. In some embodiments, after entangling the first and / or second logical qubit into an XZZX cluster state, Hadamard gates are applied to at least half of the XZZX cluster state.

[0031] In some embodiments, at least one quantum operation is applied transversally between a first physical qubit of the first logical qubit and a second physical qubit of the second logical qubit.

[0032] In some embodiments, encoding the first quantum information comprises encoding the first quantum information into an arbitrary quantum state of the first logical qubit.

[0033] In some embodiments, the method for performing syndrome extraction during operation of a quantum computer further comprises teleporting the first quantum information to a third logical qubit by: encoding third quantum information into the third logical qubit comprising a third plurality of physical qubits; applying at least one quantum operation between the second logical qubit and the third logical qubit to entangle one or more quantum states of the second and third logical qubits; applying a Hadamard gate to each of the second and third logical qubits; and measuring, using state- selective readout, quantum states of the second plurality of physical qubits, wherein the measuring obtains an error syndrome associated with the second logical qubit.

[0034] In some embodiments, the method for performing syndrome extraction during operation of a quantum computer further comprises encoding third quantum information into- 5 - #14554048v3Attorney Docket No.: H0776.70187WO00a third logical qubit comprising a third plurality of physical qubits; performing a first quantum operation, between the first logical qubit and the second logical qubit, the first quantum operation comprising: performing at least one quantum operation on the first logical qubit, the quantum operation comprising performing a first-type quantum gate between the first and the second logical qubit; performing a SWAP gate between the first and the second logical qubit; performing a physical SWAP movement between the first and the second logical qubit; and performing a first measurement; and performing a second quantum operation, between the first logical qubit and the third logical qubit, the second quantum operation comprising: performing at least one quantum operation on the first logical qubit, the quantum operation comprising performing a first-type quantum gate between the first and the third logical qubit; performing a SWAP gate between the first logical qubit and the third logical qubit; performing a physical SWAP movement between the first logical qubit and the second logical qubit; and performing a second measurement.

[0035] In some embodiments, performing the first measurement and / or second measurement provides loss information.

[0036] In some embodiments, the techniques described herein relate to method for performing syndrome extraction during operation of a quantum computer, the method comprising: encoding quantum information into a logical qubit comprising a plurality of physical qubits; performing at least one quantum operation between a physical data qubit of the plurality and a measurement qubit, the quantum operation comprising performing a first-type quantum gate between the physical data qubit and the measurement qubit; performing erasure detection following the at least one quantum operation; and measuring a quantum state of the physical data qubit to obtain an error syndrome of the logical qubit.

[0037] In some embodiments, the erasure detection is performed after each quantum operation.

[0038] In some embodiments, the erasure detection is performed after a plurality of quantum operations.

[0039] In some embodiments, the method for performing syndrome extraction during operation of a quantum computer further comprises replacing the physical data qubit after measuring the physical data qubit.

[0040] In some embodiments, the techniques described herein relate to a quantum information processing system, comprising: a computation chamber, comprising a storage zone, an entangling zone, a readout zone, and a reservoir zone; a spatial light modulator configured to- 6 - #14554048v3Attorney Docket No.: H0776.70187WO00load qubits into arrangements of qubit traps in at least one of the storage zone, the entangling zone, the readout zone, and / or the reservoir zone; a first laser configured to illuminate arrays of qubits in at least one of the storage zone, the entangling zone, the readout zone, and the reservoir zone with a global Raman beam; a first pair of crossed acousto-optical deflectors configured to move qubits between the arrangements of qubit traps; a second pair of cross acousto-optical deflectors configured to form a local Raman beam to perform single-qubit rotations using the global Raman beam; a second laser configured to generate a laser beam to illuminate qubits in the storage zone; a third and fourth laser configured to perform entangling gates between qubits disposed in the entangling zone using two-photon excitation; at least one camera configured to image qubits in the readout zone; and at least one controller configured to control components of the plurality of components to perform the methods of any one of claims 1-31. In some embodiments, the third and fourth lasers are configured to emit 420-nm and 1013-nm Rydberg beams, respectively, configured to excite the qubits disposed in the entangling zone to n = 53 Rydberg states.BRIEF DESCRIPTION OF DRAWINGS

[0041] FIG. 1 is an experimental layout illustrating optical tools, with the addition of beams for local cooling, imaging and hiding to enable qubit re-use experiments, in accordance with some embodiments of the technology described herein. The gray panel is a schematic view of control infrastructure for programming quantum circuits. The entire waveform for all AWGs (except for rearrangement) was uploaded at the start of each experimental run. For qubit re-use experiments, the Moving, Raman AOD and Rydberg AWGs loop the same memory segment each layer. The full waveform was programmed for the Raman AWG to ensure phase continuity. For mid-circuit rearrangement, waveforms were calculated on-the-fly using a desktop computer and sent to the Rearrangement AWG operated in first-in first-out (FIFO) mode.

[0042] FIG. 2 shows a processor layout used for qubit re-use experiments and relevant laser beams, in accordance with some embodiments of the technology described herein. Atoms were arranged into storage, entangling and readout zones, with an additional reservoir for refilling lost atoms mid-computation. The 1529-nm hiding beam illuminated the storage zone to preserve coherence of active qubits during imaging in the readout zone. Parallel two-qubit gates were performed in the entangling zone with global Rydberg beams, and local detunings were- 7 - #14554048v3Attorney Docket No.: H0776.70187WO00optionally applied to selected gate sites using an SLM. The readout zone was illuminated with local beams for ID PGC imaging and EIT cooling, as well as two counter- propagating lattice beams to form a spin-dependent potential for readout via spin-to-position conversion. The entire array was addressed with global Raman control for dynamical decoupling. The same Raman light was directed through a pair of crossed AODs for local single-qubit gates. Global imaging and lambda-enhanced gray molasses cooling light were used for the initial loading.

[0043] FIG. 3 shows an exemplary quantum information architecture, in accordance with some embodiments of the technology described herein.

[0044] FIGs. 4A-4B show loss errors in logical circuits. FIG. 4A depicts a logical algorithm with loss- detecting SE and gate teleportation. Physical qubit losses (crosses) may generate correlated errors within and between logical qubits. FIG. 4B shows a space-time diagram of a logical circuit, focusing on a measurement qubit lifecycle during syndrome extraction. Physical qubits progressed through time, undergoing initialization, gate operations, idling, and measurement. A loss event caused future gates to be canceled, generating correlated errors between the qubits in the gate and flipping the corresponding stabilizers.

[0045] FIG. 5 provides an illustration of a qubit lifecycle and its usage in the delayed-erasure decoder. From initialization to measurement, each physical qubit may be lost at multiple possible time points, each occurring with a potentially different probability and corresponding syndrome. Upon detection of a qubit loss, the decoder accounted for these possibilities in order to improve the accuracy of the assigned correction.

[0046] FIG. 6 shows logical error rate for a logical memory as a function of the number of conventional SE rounds before logical measurement, here with distance d = 5 and loss errors with probability Ploss= 1% per entangling gate. The delayed-erasure decoder (stars) outperformed a decoder which did not account for loss information (black). Even without loss location information, the delayed-erasure decoder achieved comparable performance to a decoder with perfect loss time-location (gray, dashed).

[0047] FIG. 7 is a flow chart illustrating a process for performing SWAP syndrome extraction (SE) during operation of a quantum computer, in accordance with some embodiments of the technology described herein.

[0048] FIG. 8 shows modified SWAP SE: data and measurement qubits were swapped each round to detect loss via state- selective readout (SSR); the SWAP’s CNOT decomposition- 8 - #14554048v3Attorney Docket No.: H0776.70187WO00cancelled with existing parity-extraction gates, with the remaining CNOT replaced by classical feedforward, so no additional entangling gates were required.

[0049] FIG. 9 is a flow chart illustrating a process 900 for performing teleportation-based SE during operation of a quantum computer, in accordance with some embodiments of the technology described herein.

[0050] FIG. 10 shows teleportation based syndrome extraction: logical qubits were teleported to fresh blocks prepared in alternating bases, detecting loss via SSR and shortening lifecycles, at the cost of extra qubits.

[0051] FIG. 11 A shows an example Steane syndrome extraction (SE) circuit and logical qubits connections illustration.

[0052] FIG. 11B shows an adjusted Steane SE with logical SWAP, giving a version of Knill SE, which was capable of correcting Pauli errors but also loss errors. Here, every SSR measurement was used to detect both errors, but teleporting the quantum information to another logical qubit.

[0053] FIG. 12 is a flow chart illustrating a process 1200 for performing direct conversion syndrome extraction (SE) during operation of a quantum computer, in accordance with some embodiments of the technology described herein.

[0054] FIG. 13 shows direct conversion SE: mid-circuit measurement and replacement converted loss to erasure using additional hardware; detection / replacement frequency was varied in simulations.

[0055] FIG. 14 is a flow chart illustrating a process for performing error correction during quantum computation, in accordance with some embodiments of the technology described herein.

[0056] FIGs. 15A-15B provide an overview of the approximate MEE decoding procedure. FIG. 15A shows that, for a given qubit lifecycle, potential loss locations (crosses) were identified and modified circuits were simulated for each, generating a set of decoding hypergraphs (DEMij). These included updated stabilizer syndromes (detectors) and correlated error edges resulting from the truncated loss circuits. FIG. 15B shows that when multiple qubit losses were present in a given shot, the decoding hypergraph was computed for each lifecycle independently (left), optionally included a combined loss decoding hypergraph (right), and summed with the standard Pauli decoding hypergraph to generate the final decoding hypergraph (DEMfinal), according to Eq. B5. This formed the input to the decoder.- 9 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0057] FIGs. 16A-17B show examples of detector activations generated by different loss events in a d = 3 surface code over four time steps (t = 1-4). FIGs. 16A-16F show two potential loss locations for the same data qubit q, in round t = 2 and t = 3, respectively, each after the first gate. These correspond to different loss circuits within the same lifecycle and were combined into a single decoding hypergraph for that lifecycle (labeled “lifecycle syndrome”). FIGs. 17A-17B show a loss of a measurement qubit m' in round t = 2, which belonged to a separate lifecycle and contributed a separate decoding hypergraph. Detectors 0- 4 are highlighted. Each row (E,) in the decoding hypergraph tables corresponds to one error mechanism (hyperedge), i.e., a correlated set of detector activations triggered by a single loss event. Superchecks that were activated in all loss circuits of a given lifecycle also appeared in the final decoding hypergraph, such as the shared activation of £>3 in FIGs. 16A-16F.

[0058] FIG. 18 is a level diagram showing87Rb atomic levels, according to some embodiments.

[0059] FIG. 19 is a schematic diagram of an illustrative classical computer, which may be used to implement aspects of the technology described herein.

[0060] FIG. 20 shows logical error rates vs. SE rounds d = 7, p = 1%) using the delayed-erasure decoder. Comparable performance was observed across SE methods in regimes with short lifecycles.

[0061] FIG. 21 A shows error thresholds vs. loss fraction, showcasing the improvement with loss for all SE methods.

[0062] FIG. 2 IB shows effective distance vs. loss fraction (d = 7), improving with loss for all SE methods.

[0063] FIG. 21C shows space-time overhead to reach PL = 1012at / ? = 0.5% vs. loss fraction.

[0064] FIG. 22A shows linking thresholds for different SE methods for different loss and Pauli error rates. The curves are linear fits to numerical finite-size data, with the region below each curve representing the correctable region.

[0065] FIG. 22B shows linking thresholds as a function of lifecycle length for various SE methods, in the loss error only limit.

[0066] FIG. 23A shows a deep Clifford logical algorithm comprising random logical singlequbit and transversal CX gate layers, with periodic SE rounds at varying frequencies.

[0067] FIGs. 23B-23C show circuit-level simulation results showing the logical error rate as a function of the number of SE rounds per transversal gate layer, for different loss fractions, (p- 10 - #14554048v3Attorney Docket No.: H0776.70187WO00= 1%, d = 5, 24 layers). The SWAP SE method in FIG. 23C effectively mitigated loss errors, restoring the optimal SE frequency observed in Pauli- dominated scenarios. In contrast, conventional SE (FIG. 23B) exhibited varying error correction regimes, where loss may improve or degrade performance depending on the lifecycle length.

[0068] FIG. 24A shows logical qubit teleportation during gate teleportation, shortening lifecycles and naturally detecting loss without loss- detecting SE rounds.

[0069] FIG. 24B shows SE rounds per logical qubit before logical measurement for various algorithmic subroutines. Each subroutine used frequent gate teleportation, keeping lifecycles short and detecting loss without additional experimental overhead.

[0070] FIGs. 25A-25B show deep logical algorithms with teleported gates. FIG. 25A shows a deep circuit comprising teleported X and Z logical gates, similar in structure to published smallangle synthesis algorithms. FIG. 25B shows circuit-level simulation results for 11 layers of random teleported Z and X logical gates, with all logical qubits initialized in the presence of noise (physical error rate p = 1% and d = 1). The delayed-erasure decoder (stars) outperformed an MEE decoder that did not account for loss (black) and improved with increasing loss fraction. It also matched the performance of a decoder with perfect loss information (gray, dashed), and for loss fractions less than 1, approached that of the erasure channel (crossed circles, dashed). The erasure channel performance was achieved using direct conversion SE with period 0.25, corresponding to loss detection and qubit replacement after every gate, thus providing a lower bound.

[0071] FIGs. 26A-26B show logical memory simulations with d rounds of the conventional SE method. Variation of the logical error rate is shown as a function of the combination weight co for distance 9, across different physical error rates (p = 0.01 and p = 0.03). The results indicated that nonzero values of co deteriorated the decoder’s performance.

[0072] FIGs. 27-32 show thresholds for various values of erasure and bias fractions, in cases: (FIG. 27) without bias preserving gates and erasure is not biased, (FIG. 28) with bias preserving gate and erasure is biased, and (FIG. 29) without biased preserving gates and erasure is biased. FIGs. 30-32 provide numerical values for the thresholds illustrated in FIGs. 27-29, respectively.

[0073] FIGs. 33A-33B show thresholds for various values of loss fractions and Pauli bias fractions, for methods: direct conversion SE with a period 1 (FIG. 33A) and teleportation-based SE (FIG. 33B). Bias-preserving gates were not used.- 11 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0074] FIGs. 34A-34B show the lifecycle analysis of qubits under SWAP SE with different periods depicted in FIGs. 34A and 34B. In FIGs. 34A and 34B, ”X” marks represent losses detected via SSR. FIG. 34A shows continuous SWAP operations (SWAP SE period = 1), where each loss of measurement qubits was converted to data qubit loss in the next cycle. FIG. 34B illustrates a SWAP SE period of 2, alternating between SWAP and conventional SE rounds. Note that edge cases, not shown here, typically exhibit even longer lifecycles due to their lack of SWAP pairs.

[0075] FIG. 35 shows a plot of the average qubit lifecycles for both methods, calculated for d = 9. Both periods exhibited the same average lifecycle length, which approaches 8 in the limit of large distances.

[0076] FIGs. 36 and 37 show an optimizing SWAP period given movement errors. FIG. 36 shows logical error as a function of the number of SE rounds, implementing the SWAP method with movement errors, for a physical error rate of 0.5%, and distances of 5 and 7. Square (circle) curves show results for distance 7 (5), with a grayscale gradient representing different SWAP periods. A period of 100 (which effectively meant no loss detection) resulted in the worst errors. FIG. 37 shows logical error as a function of the number of periods for different physical error rates, focusing on 20 SE rounds. The two subplots illustrate the results for loss fractions of 0.5 and 1. As indicated, the SWAP period varied with both the loss fraction and the physical error rates.

[0077] FIG. 38 shows lifecycle analysis for SWAP SE and conventional SE for distance 9. The plot shows that the average lifecycle over all qubits was equal in both methods. However, as the number of noisy SE rounds increased, the lifecycle of data qubits in the conventional SE approach increased, but for the SWAP SE approach it remained constant.

[0078] FIG. 39 shows logical error as a function of number of SE rounds for SWAP SE and conventional SE, for physical error rate p = 1% and various distances. Top to bottom panels showcase different loss fractions: L = 0, 0.5, 1. For loss errors only (L = 1), the bottom panel shows that SWAP started to be beneficial over no loss detection after approximately 6 SE rounds.

[0079] FIGs. 40 and 41 show an implementation of teleportation-based SE, including building the RHG cluster state (FIG. 40) and XZZX cluster state (FIG. 41) for teleportation-based SE with the surface code.- 12 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0080] FIGs. 42A-43B show the connection between Steane SE with logical SWAP and teleportation-based SE, showcasing an intermediate scheme. (FIG. 42A) Circuit for Steane SE (without Pauli corrections), showing logical data qubits and logical measurement qubits with error propagation and detection. This circuit may repeat k e {1,.., d} times, where k = 1 was standard Steane SE, and k > 1 used non-FT logical measurement qubits, which may be preselected on the side. (FIG. 42B) Teleportation in the modified Steane QEC. (FIG. 43A) teleportation-based SE circuit (without Pauli corrections), equivalent to (FIG. 42 A) for k = d. This demonstrated that in the limit of multiple logical measurement qubits, Steane SE with SWAP was equivalent to teleportation-based SE. (FIG. 43B) Teleportation process in teleportation-based SE. The circles with X and Z inside in FIGs. 42A and 43A represent errors and how they propagated and detected.

[0081] FIGs. 44-48 show example logical algorithmic procedures. FIG. 44 shows average and maximum lifecycle lengths of the common algorithms are presented in FIGs. 45-48.

[0082] FIG. 49 shows a representation of the error model on a sphere.

[0083] FIG. 50 shows a comparison of different SE methods with different loss fractions (L). Logical memory circuit-level simulation, showcasing logical error rate is shown as a function of the number of SE rounds, for various SE methods. (Left) L = 0, (Middle) L = 0.5, (Right) L = 1. Here, the physical error rate was 1% and the code distance was d = 7.

[0084] FIGs. 51A-51F provide threshold data. Logical error rate is shown as a function of physical error rates for different SE methods, for loss errors only (L = 1). (FIG. 51A) SWAP SE, (FIG. 51B) Direct conversion SE period 1, (FIG. 51C) Teleportation-based SE, (FIG. 51D) Direct conversion SE period 1 with detection period 0.25 (providing perfect loss location information), (FIG. 51E) Direct conversion SE period 0.25, with loss detection and replacement after every gate (erasure channel), (FIG. 51F) Direct conversion SE period 2. These data were used to find the threshold of each SE method.

[0085] FIGs. 52A-52F show effective distance data. Logical error rate is shown as a function of physical error rates for different SE methods, for loss errors only (L = 1). (FIG. 52A) SWAP SE, (FIG. 52B) Direct conversion SE period 1, (FIG. 52C) Teleportation- based SE, (FIG. 52D) Direct conversion SE period 1 with detection period 0.25 (providing perfect loss location information), (FIG. 52E) Direct conversion SE period 0.25, with loss detection and replacement after every gate (erasure channel), (FIG. 52F) Direct conversion SE period 2. These data were used to find the effective distance of each SE method.- 13 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0086] FIGs. 53A-53F: Same as FIGs. 51A-51F, but with a different error channel. Here, a correlated Z-loss error channel was considered, as described in Section S3.1.

[0087] FIGs. 54A-54F: Same as FIGs. 52A-52F, but with a different error channel. Here, a correlated Z-loss error channel was considered, as described in Section S3.1.

[0088] FIGs. 55 and 56 show illustrations of deep random Clifford circuits with multiple layers of transversal CX and logical single-qubit gates, with periodic SE rounds. (FIG. 55) 1 / 2 SE rounds per CX. (FIG. 56) 3 SE rounds per CX.DETAILED DESCRIPTION

[0089] In classical computers, bits are a unit of information representing a logical state of one of two classical values, 0 or 1. Similarly, a quantum bit (a “qubit” herein) is a unit of information in a quantum computer. Like classical bits, qubits can occupy two distinct states, such as |0) and |1), or any quantum superposition of the two states. In some cases, qubits are encoded in quantum systems with two or more distinct quantum states. Many physical realizations of qubits may be employed. As an example, physical qubits may include neutral atoms isolated within a vacuum chamber. These isolated neutral atoms have many distinct quantum states corresponding to the orientation of electron spins, electron orbits, nuclear spins, molecular rotations, and / or the like. Alternatively or additionally, physical qubits may include superconducting circuit components (e.g., transmon, fluxonium, charge, or other qubits), trapped ions, and / or photonic qubits, and it should be appreciated that aspects of the technology described herein are not limited to implementations using neutral atom qubits.

[0090] Quantum computers generally contain many qubits (e.g., tens, hundreds, and / or thousands of qubits) and perform computational operations, including initializing the qubits for computation, manipulating the state and / or position of the qubits, and reading out the state of the qubits at a given time. Manipulation of the qubit state may be performed using quantum logic gates, which perform mathematical operations on qubits. Two such types of quantum logic gates include a single-qubit gate and / or a multi-qubit gate. A single-qubit gate is a quantum logic gate applied to an individual qubit. For example, a single qubit gate may operate on a qubit in state |0) and change (e.g., flip) the qubit state to state |1). In contrast, a multiqubit gate operates on at least two qubits. A multi-qubit gate may, as an example, entangle two qubits, wherein entangling describes linking the two qubits such that the state of one influences the state of the other. One common multi-qubit gate is a controlled NOT gate (“CNOT gate”),- 14 - #14554048v3Attorney Docket No.: H0776.70187WO00which can entangle two qubits and conditionally change the state of one or both qubits. For example, a CNOT gate may be configured to flip the state of a second qubit if and only if the state of a first qubit is |0).

[0091] According to various embodiments of a quantum computer, individual particles (e.g., atoms, ions, molecules, etc.) can first be trapped in an array and arranged into particular configurations. Next, one or more of the arranged particles are prepared in a desired quantum state to act as a qubit. Quantum circuits may then be implemented by performing a sequence of qubit operations, which act on individual qubits (“single-qubit gates”) or on groups of two or more qubits (“multi-qubit gates”). Finally, the state of the qubits can be read out in order to observe the result of the quantum circuit. The readout can be accomplished using an observation system that typically includes an electron-multiplied CCD (EMCCD) or optical camera image to detect particles’ loaded positions, and a second camera image to read out the qubits’ final states by, for example, detecting fluorescence generated by the particles in their final quantum states.

[0092] The operation of quantum information platforms are based on interactions between qubits. However, qubits often interact locally, which limits the connectivity of the circuit or the analog simulation and constrains the possible computations. While some platforms can communicate in a non-local way through the use of a shared bus, these shared-bus approaches are limited to small systems and thus still require a way to dynamically move qubits around in order to truly scale up the platform.

[0093] In many embodiments of a quantum computer, a qubit may be encoded in two nearground-state energy levels of an atom, ion, or molecule. An example of this is a hyperfine qubit. In a hyperfine qubit, the two near-ground-states differ by the relative orientation of the nuclear spin with respect to the outer electron spin. The two states are split by the interaction energy between the nuclear spin and electron spin, typically ranging from frequencies of 1-13 GHz. Hyperfine qubits are frequently chosen owing to their resistance to environmental perturbations and long lifetimes.

[0094] Performing single-qubit gates on hyperfine qubits can be done by applying coherent microwave radiation at the frequency of the energy splitting between the first and second hyperfine qubit states. However, due to the physical proximity of the qubits in the quantum computer, in some systems on the scale of a few microns, microwaves cannot be- 15 - #14554048v3Attorney Docket No.: H0776.70187WO00applied to the first qubit without the microwaves affecting the states of qubits proximate to the first qubit.

[0095] Alternatively, some quantum information processing systems may apply a specific type of laser field to the qubits to perform quantum logic gates. This laser field is nearly resonant with an optical transition from one of the ground states to an optically excited state of a particular qubit. By applying the laser field to the qubit (i.e. pumping into the qubit), the qubit absorbs a nearly resonant first wavelength and generates a second wavelength, and in doing so changes its state. This state change is defined as a stimulated Raman transition (SRT) and the laser field defined as a Raman pulse. Beneficially, the Raman pulse can focus on individual qubits and / or subsets of qubits, mitigating the unintended state changes faced in microwave state transitions. Additionally, Raman pulses can be applied with high intensity, resulting in faster quantum gate operations.

[0096] Neutral atom quantum computers are a specific type of quantum computer that encode qubits in neutral atoms. These neutral atoms are trapped in a vacuum chamber and levitated by one or more trapping lasers. Commonly, individual atoms are trapped in an optical lattice, which is formed from standing waves of laser light that produces a periodic structure of nodes and anti-nodes. Alternatively or additionally, optical tweezers may be used to trap individual atoms by using tightly focused laser beams.

[0097] Neutral atom qubits can be used as hyperfine qubits, wherein a first and second ground state is split by frequencies of approximately 1-13 GHz. Multi-qubit gates in neutral atom quantum computers are realized using a third state, which is an excited Rydberg state. Beneficially, when an atom is excited to a Rydberg state, proximal atoms are prevented from exciting to the Rydberg state. This conditional behavior forms the basis for multi-qubit gates, including the CNOT gate previously described. The Rydberg state is used to temporarily mediate the multi-qubit gate before Rydberg excited atoms return to ground state, preserving their coherence. Coherence is a measure of the lifetime of the qubit before its information is lost, and is a parameter frequently used to describe qubits.

[0098] Neutral atom arrays can be dynamically reconfigured while preserving quantum coherence and entanglement between qubits by storing quantum information in hyperfine states and shuttling atoms in optical tweezers. This approach offers a scalable way to realize a quantum information system with large numbers of qubits and arbitrary programmability -where any qubit can perform an entangling gate with any other qubit in the array. Using high-- 16 - #14554048v3Attorney Docket No.: H0776.70187WO00fidelity two-qubit Rydberg gates, various quantum information circuits are described herein that leverage the programmability and nonlocal connectivity achievable with these approaches.

[0099] In quantum computers, ideal qubits are encoded to have long coherence properties and, consequently, maintain their lifetime before information is lost. Short coherence properties result in a higher error rate and increased information loss. One common error in quantum computation is a bit-flip error, wherein a qubit’ s state changes unexpectedly. For example, a quantum qubit encoded in state |0) may change to state |1) after a characteristic time scale, wherein the characteristic time scale defines the qubit’s coherence. As another example, a qubit in a superposition state (|0) + |1)) / 2 may change to state (|0) — |1)) / 2 after a characteristic time scale.

[0100] Qubit loss errors constitute a dominant source of noise in many quantum hardware systems, particularly in neutral atom quantum computers. A theoretical framework to effectively detect and correct loss errors in logical algorithms and leverage such loss information in decoding was developed. Considering general quantum error correction codes and logical circuits, a delayed-erasure decoder was introduced for experimentally-motivated error models which leveraged information from delayed loss detection to accurately correct loss errors, even when the precise moment of the error was unknown. Using this decoder, strategies for detecting and correcting loss errors were identified based on the logical circuit structure. For deep circuits prior to logical measurement, methods to integrate loss detection into syndrome extraction with minimal overhead were explored, identifying optimal strategies depending on the qubit loss fraction in the noise and hardware capabilities. In contrast, it was found that many algorithmic subroutines involve frequent gate teleportation, shortening the circuit depth before logical measurement and naturally replacing qubits with no additional experimental overhead. This setting was simulated using a toy model algorithm for small-angle synthesis, and significant performance improvement was found as the loss fraction increased.

[0101] Quantum error correction (QEC) is important for realizing large-scale quantum computation, as it enables suppression of errors. However, its practical implementation remains challenging due to its substantial resource overhead. Recent experimental advancements have demonstrated remarkable progress in implementing quantum operations across multiple logical qubits and operating below error thresholds. These advances make it clear that practical QEC performance can be substantially improved by tailoring the error correction strategy to the- 17 - #14554048v3Attorney Docket No.: H0776.70187WO00particular experimental error model, choice of logic gates, and the structure of the algorithm itself.

[0102] In particular, qubit loss and leakage from computational subspace are dominant noise sources in many hardware systems and may affect the performance of quantum processors. In the absence of loss correction, qubits within a QEC code can eventually disappear, destroying the encoded quantum information. Conversely, directly detecting loss provides valuable information about the error location, in contrast with Pauli errors, which are indirectly inferred from syndrome information. Recent work has shown that the rich information provided by so-called erasure detection can in fact improve QEC performance substantially. Similarly, noise bias present in many platforms may be leveraged to improve performance. These studies motivate developing strategies that incorporate loss detection and harness bias to improve practical QEC performance.

[0103] The inventors have recognized and appreciated that incorporating loss detection into quantum circuit decoding methods may improve QEC performance and overall quantum circuit fidelity. Accordingly, the inventors have developed systems and techniques for performing error correction during a quantum computation. In some embodiments, the method includes encoding first quantum information (e.g., an arbitrary quantum state, |ψ〉 into a first logical qubit comprising a first plurality of physical qubits (e.g., individual qubits such as neutral atom, trapped ion, superconducting circuit, or photonic qubits). For example, the arbitrary quantum state I ) may be encoded into quantum states of one or more of the first plurality of physical qubits. Thereafter, at least one quantum operation may be performed on the first logical qubit by applying one or more quantum gates (e.g., Hadamard gates, Pauli-X gates, Pauli- Y gates, Pauli-Z gates, S gates, T gates, CZ gates, SWAP gates, CNOT gates, and / or Toffoli gates) to qubits of the first plurality of physical qubits.

[0104] In some embodiments, after applying at least one quantum operation to the first logical qubit, an error syndrome of the first logical qubit may be measured. For example, the error syndrome may be measured using one or more of syndrome extraction (SE) and / or single- state readout (SSR) techniques. For example, the error syndrome may be measured using one or more of SWAP SE, teleportation-based SE, and / or mid-circuit erasure conversion SE, as described herein. Measuring the error syndrome may include determining a state of one or more of the physical qubits forming the first logical qubit. For example, state of the physical qubits may be determined to be at least one of |0), |1), or loss (|L)). Based on the measured error- 18 - #14554048v3Attorney Docket No.: H0776.70187WO00syndrome, a list of potential loss events may be generated. The list of potential loss events may identify a loss of one or more of the first plurality of physical qubits during the performance of the at least one quantum operation.

[0105] In some embodiments, a decoding hypergraph may then be generated based at least in part on the list of potential loss events. For example, generating the decoding hypergraph may include constructing a loss circuit for a physical qubit lifecycle, wherein the loss circuit represents a loss event of the physical qubit for the physical qubit lifecycle. The loss circuit may include information associated with a plurality of detectors and a plurality of hyperedges configured to connect the plurality of detectors. A number of loss circuits may be generated to account for different potential loss events. Thereafter, the multiple loss circuits may be combined to form the decoding hypergraph describing the physical qubit lifecycle.

[0106] In some embodiments, the decoding hypergraph may be provided as input to a quantum decoder. The quantum decoder may be configured to, using the provided decoding hypergraph, generate at least one quantum error correction operation to correct errors (e.g., including correcting qubit losses) that occurred during the performance of the at least one quantum operation. Thereafter, the at least one quantum error correction operation may be applied to the first logical qubit (e.g., by applying one or more quantum gates to one or more qubits of the first plurality of physical qubits) to correct errors that occurred during the performance of the at least one quantum operation. In this manner, loss events may be accounted for and corrected using quantum decoding techniques.

[0107] Following below are more detailed descriptions of various concepts related to, and embodiments of, techniques for performing loss-resolved quantum decoding. It should be appreciated that various aspects described herein may be implemented in any of numerous ways. Examples of specific implementations are provided herein for illustrative purposes only. In addition, the various aspects described in the embodiments below may be used alone or in any combinations and are not limited to the combinations explicitly described herein.

[0108] FIG. 1 is an illustration of a quantum information processing system 100, including a control infrastructure 102 for a quantum computer, according to some embodiments of the technology described herein. In some embodiments, and as shown in the example of FIG. 1, the system 100 includes a vacuum chamber 104 in which a plurality of atoms 105 are trapped. The vacuum chamber 104 may be made of a transparent material (e.g., glass, quartz, sapphire, etc.) such that the atoms 105 can be optically addressed to implement quantum information- 19 - #14554048v3Attorney Docket No.: H0776.70187WO00processing (e.g., the performance of quantum logical gates, error correction processes, etc.). The atoms 105 may be atoms of an atomic species suitable for use as neutral atom qubits, for example alkali metals (e.g., Rubidium or Cesium), alkali earth metals (e.g., Strontium), and / or the like.

[0109] In some embodiments, the system 100 includes a control infrastructure 102, as shown in FIG. 1. The control infrastructure 102 includes circuitry and / or computing devices configured to control one or more components of the system 100 to implement quantum information processing using atoms 105. The control infrastructure 102 may be implemented using any suitable classical computing systems and / or circuitry (e.g., ASICs, FPGAs, etc.) as described in connection with the example of FIG. 19 herein. In some embodiments, the control infrastructure 102 includes one or more of a Rydberg arbitrary waveform generator (AWG) 154, a Raman AWG 156, a rearrangement AWG 158, a moving AWG 160, and / or a Raman AOD AWG 162, the operations of which are described in more detail below.

[0110] In some embodiments, the system 100 includes a spatial light modulator (SLM) 106, a first pair of acousto-optical deflectors (AODs) 108 (also known as “optical tweezers”), a second pair of AODs 116, and a local SLM detuner 118. Light (e.g., laser beams) generated by the SLM 106 and the first pair of AODs 108 passes through a first polarized beam splitter (PBS) 110 and subsequently a first dichroic mirror 112 before passing through a trapping objective 114. Light (e.g., laser beams) generated by the second pair of AODs 116 and the local SLM detuner 118 is steered to the trapping objective 114 by dichroic mirrors 112 and 120. Thereafter, light passing through the trapping objective 114 is focused into the vacuum chamber 104.

[0111] During operation of the system 100, in some embodiments, the SLM 106 is configured to load atoms 105 disposed within the vacuum chamber 104 into static magneto-optical traps, referred to herein as static traps. The static traps may be 852-nm static traps, although it should be appreciated that alternative static trap sizes (e.g., as suitable for the atomic size of atoms 105) may be utilized, as aspects of the technology described herein are not limited in this respect.

[0112] In some embodiments, once atoms 105 are disposed in static traps generated by SLM 106, the rearrangement AWG 158 and / or the moving AWG 160 are configured to control the operation of the first pair of AODs 108 to rearrange the atoms 105 into a plurality of arrays using sets of moving traps. Static traps are optical traps that remain in a fixed spatial position- 20 - #14554048v3Attorney Docket No.: H0776.70187WO00during operation of the system 100. Moving traps are optical traps configured to spatially move in the vacuum chamber 104. The first pair of AODs 108 may be configured to generate 852-nm moving traps, although it should be appreciated that alternative moving trap sizes (e.g., as suitable for the atomic size of atoms 105) may be utilized, as aspects of the technology described herein are not limited in this respect.

[0113] In some embodiments, while atoms 105 are being arranged into static and / or moving traps, a camera 124 (e.g., a CMOS camera) may be used to capture optical signals generated by the atoms 105 and exiting the vacuum chamber 104 through an imaging objective 126. The captured optical signals may be passed from the camera 124 to CPU 122, which may be configured to analyze the optical signals to determine the spin-state and / or position of the atoms 105. For example, the CPU 122 may be configured to determine whether any atom losses have occurred, which result in unoccupied spaces in the atom arrangements and may produce undesirable or incorrect computation results.

[0114] In some embodiments, the output from CPU 122 may be provided as feedback to the rearrangement AWG 158. The rearrangement AWG 158 and moving AWG 160 may be connected to a switch 180 coupled to two optical channels 181A, 181B, each of which are coupled to one AOD of the first pair of AODs 108. The optical channels 181A, 181B permit control, by either the rearrangement AWG 158 or the moving AWG 160, of the movement of trapped atoms in the x- and y-direction, respectively. Based on the feedback received from CPU 122 (e.g., that there has been a loss of atoms in the moving traps, etc.), the rearrangement AWG 158 may be configured to cause the first pair of AODs 108 to further rearrange the atoms 105 in the moving traps and perform real-time rearrangement of atoms.

[0115] In some embodiments, the atoms 105 may be further optically addressed (e.g., to implement quantum logical gates or to implement other processes) by one or more lasers. A first laser 128 is configured to generate a global Raman beam that passes through a PBS 130 and dichroic mirror 132 before entering the vacuum chamber 104. The global Raman beam generated by the first laser 128 is configured to control global rotations of the quantum states encoded in the atoms 105 and to perform dynamic decoupling throughout the circuit by illuminating the arrays of qubits with the global Raman beam. In some embodiments, the first laser 128 is controlled by the Raman AWG 156 and the acousto-optical modulator (AOM) 174.

[0116] In some embodiments, a second laser 134 generates a hiding beam that passes through a fourth dichroic mirror 136 before subsequently passing through the third dichroic mirror 132- 21 - #14554048v3Attorney Docket No.: H0776.70187WO00and then entering the vacuum chamber 104. The second laser 134 may be configured to shield qubits in a given lattice from light contamination from other lasers in the system 100. In some embodiments, the second laser 134 is configured to focus the laser beam is configured to focus an elliptical waist, wherein a semi-major axis of the elliptical waist is aligned in a vertical direction relative to a quantum lattice on which it is incident. In some embodiments, the second laser 134 may be configured to have a wavelength of approximately 1529-nm.

[0117] In some embodiments, a third laser 138 is configured to generate a first Rydberg beam that passes through a fifth dichroic mirror 140 before entering the vacuum chamber 104. A fourth laser 142 is configured to generate a second Rydberg beam that passes through the fourth dichroic mirror 136 before subsequently passing through the third dichroic mirror 132 and entering the vacuum chamber 104. As shown in FIG. 1, the third and fourth laser 138, 142 perform single-qubit control using two-photon Raman excitation with the first and second Rydberg beams generated by the two lasers, respectively. This two-photon excitation is the basis for entangling gates performed during operation of the quantum computer. In some embodiments, the first Rydberg beam generated by the third laser 138 is of wavelength 420-nm and the second Rydberg beam generated by the fourth laser 142 is of wavelength 1013-nm. In some embodiments, wherein the neutral atom qubits comprise87Rb, the Rydberg beams generated by the third and fourth laser 138, 142 are configured to excite the neutral atoms to n = 53 Rydberg states

[0118] In some embodiments, a fifth laser 144 generates a first counter-propagating light beam of a first polarization that passes through the second PBS 130 before subsequently passing through the third dichroic mirror 132 and entering the vacuum chamber 104. A sixth laser 146 generates a second counter-propagating light beam of a second polarization that passes through a third PBS 148 before subsequently passing through the fifth dichroic mirror 140 and entering the vacuum chamber 104.

[0119] In some embodiments, the first and second polarizations are in opposite directions. In some embodiments, the counterpropagating beams generated by the fifth and sixth laser are configured to perform local cooling with ID polarization gradient cooling (PGC) and electromagnetically induced transparency (EIT).

[0120] In some embodiments, a seventh laser 150 generates a lattice beam of a third polarization that passes through the second PBS 130 before subsequently passing through the third dichroic mirror 132 and entering the vacuum chamber 104. Additionally, an eighth laser- 22 - #14554048v3Attorney Docket No.: H0776.70187WO00152 generates a lattice beam of the third polarization passes through the third PBS 148 before passing through the fifth dichroic mirror 140 and entering the vacuum chamber 104. In some embodiments, seventh and eighth lasers are configured to generate the counter-propagating laser beams with wavelength of 795-nm and a blue detuning between 50 GHz to 200 GHz from a DI line of the neutral atom qubits. The counterpropagating light beams are configured to form a one-dimensional potential lattice to trap the qubits, forming a one-dimensional qubit lattice. In some embodiments, the fifth laser 144 and seventh laser 150 generate their respective beams in parallel. In some embodiments, the sixth laser 146 and the eighth laser 152 generate their beams perpendicular to each other.

[0121] In some embodiments, the same Raman beam generated by the first laser 128 is simultaneously redirected through a local path which focuses on the second pair of AODs 116 direct the Raman beam to individual atoms. Consequently, the Raman beam focused by the second pair of AODs 116 performs local single-qubit rotations. The Raman AOD AWG 162 includes two optical channels 183A, 183B that control the programmable light grids generated by the local Raman AOD 116 in the x- and y-direction, respectively. The Raman AOD AWG 162 may be configured to create light grids for local single-qubit control.

[0122] In some embodiments, the Rydberg AWG 154 includes a plurality of acousto-optic modulators (AOMs) and at least two generators to perform through-the-lens (TTL) metering. In the Rydberg AWG 154, a first and second AOM 164, 166 controls the third laser 138 and fourth laser 142, respectfully. The Rydberg AWG 154 may be configured to generate entangling gate pulses to entangle qubits and / or to perform local detunings of the local SLM detuner 118. In the embodiment in FIG. 1, the first and second AOM 164, 166 are configured at 420-nm and 1013-nm wavelengths, respectively. A third AOM 168 is configured to control the local SLM detuner 118. A first TTL generator 170 performs TTL metering on the first pair of AODs 108 and a second TTL 172 performs TTL metering on the SLM 106.

[0123] In some embodiments, a fifth AOM 176 controls the local Raman AOD 116. The Raman AWG 156 includes a laser source 178, which, in the embodiment in FIG. 1, is configured to operate at 6.8 GHz. The Raman AWG 156 may be configured to perform in-phase and quadrature control of the qubits and / or pulse- shaping of a global and a local Raman driving.

[0124] FIG. 2 shows a schematic of the quantum computer processor 200 within the vacuum chamber 104, according to some embodiments. As shown in the example of FIG. 2, in some- 23 - #14554048v3Attorney Docket No.: H0776.70187WO00embodiments, the plurality of atoms 105 are arranged in a storage zone 202, an entangling zone 204, a readout zone 206, and a reservoir zone 208. A global Raman beam 210 (e.g., a beam generated by the first laser 128) illuminates the qubits in all four zones. A hiding beam 212 (e.g., a beam generated by the second laser 134) illuminates the qubits in the storage zone 202. A first Rydberg tophat beam 218 (e.g., a beam generated by the sixth laser 146) and a second Rydberg tophat beam 220 (e.g., a beam generated by the fourth laser 142) both illuminate the entangling zone 204. A first and second counterpropagated lattice beam 214, 216 (e.g., beams generated by the seventh laser 150 and the eighth laser 152, respectively) illuminate the readout zone 206. Additionally, a first and second counterpropagated imaging beam 222, 224 (e.g., beams generated by the fifth laser 144 and the sixth laser 146, respectively) also illuminates the readout zone 206.

[0125] In some embodiments, the storage zone 202 contains qubits that, during operation of the quantum computer, will entangle with qubits in the entangling zone 204. The hiding beam 212 illuminates the qubits in the storage zone 202 to reduce decoherence in the storage qubits induced by imaging in the readout zone 206. Additionally, the hiding beam 212 is configured to reduce error from the Rydberg beams 218, 220. In some embodiments, the storage zone 202 is above the entangling zone 204 by 52-pm. In some embodiments, each column of storage qubits is separated by 11-pm.

[0126] In some embodiments, a local SLM beam 225 (e.g., a beam generated by the local SLM detuner 118) may perform local detunings at selected gate sites in the entangling zone 204. The global Raman beam 210 may perform parallel two-qubit gates in the entangling zone. A local Raman beam 226 (e.g., a Raman beam generated by the first laser 128 and directed by the second pair of AODs 116), performs local single-qubit gates. In some embodiments, the entangling zone 204 is separated by 40-pm from the storage zone 202 and readout zone 206 to ensure negligible error on stored qubits from the tails of the Rydberg beams 218, 220.

[0127] In some embodiments, measurement and re-initialization of qubits occurs in the readout zone 206, positioned beneath the entangling zone 204. In some embodiments, the readout zone is 12 rows tall (e.g., approximately 55 pm tall) with two rows of traps per atom for the lattice readout. In some embodiments, six blocks of qubits are interlaced horizontally for storage, corresponding to five 6x6 ancilla blocks and one 5x5 data block. In other embodiments, six blocks of qubits are interlaced horizontally for storage, corresponding to four 6x6 ancilla blocks and two 5x5 data block.- 24 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0128] In some embodiments, and as shown in the example of FIG. 2, the reservoir zone 208 shown is positioned beneath the readout zone 206 to replenish lost atoms in any of the storage zone 202, entangling zone 204, and / or the readout zone 206.

[0129] FIG. 3 shows an exemplary quantum entangling architecture 300 including a first zone 302 and a second zone 304. In some embodiments, the first zone 302 and the second zone 304 may contain a plurality of atoms 306 trapped in an optical lattice. The first zone 302 may be configured to store atoms 306. In some embodiments, the first zone 302 may be configured like the storage zone 202 of the quantum computer processor 200 described in connection with FIG. 2. The second zone 304 may be configured to facilitate quantum entanglement. In some embodiments, the second zone 304 may be configured like the entangling zone 204 of quantum computer processor 200 described in connection with FIG. 2.

[0130] As shown, an inset 308 indicates possible atomic states of an atom of the plurality of atoms 306, including |0) and |1). The |0) and |1) states may refer to hyperfine states of a hyperfine qubit. As an example, for87Rb atomic qubits, the |0) and |1) states may refer to the mF=0 clock states of87Rb atoms, though it should be appreciated that aspects of the technology described herein are not limited to only an87Rb, as alternative neutral atom species (e.g., Cs, Yb, Sr, etc.) or qubit types (e.g., superconducting, ionic, photonic, etc.) may be used. Returning to FIG. 3, the inset 308 also indicates a Rydberg state, |r). In some embodiments, the plurality of atoms 306 are excited to |r) before entanglement. As an example, a first and second atom may be excited to |r) and subsequently entangled in the first zone 302.

[0131] In some embodiments, entanglement may occur in the form of applied quantum gates 310. In the embodiment of FIG. 3, CZ quantum gates 310 are applied to entangle a pair of atoms. In various embodiments, other multi-qubit gates (e.g., CNOT gates, CZ gates, SWAP gates, and Toffoli gates) may be applied to the plurality of atoms 306 in the second zone 304. In various embodiments, single-qubit gates (e.g., Pauli-X, Pauli- Y, Pauli-Z, Hadamard, S, and T gates) may be applied to the plurality of atoms 306 in the second zone 304.

[0132] In some embodiments, gate teleportation 312 may occur in the second zone 304. In the example of FIG. 3, a first qubit from a first entangled pair may teleport 312 to a second qubit to form a second entangled pair.

[0133] FIGs. 4A-4B shows loss errors in logical circuits 400, in accordance with some embodiments of the technology described herein. FIG. 4A depicts a logical algorithm 402 with loss- detecting syndrome extraction (SE) 404 and gate teleportation 406. Physical qubit loss- 25 - #14554048v3Attorney Docket No.: H0776.70187WO00events 408 (depicted as crosses) may generate correlated errors within and between logical qubits. The loss-detecting SE 404 may be configured to detect and replace lost qubits. The details of loss- detecting SE is described in connection with FIG. 23A herein. The gate teleportation 406 may include a state-selective readout 410 and a qubit teleportation 412. The state-selective readout 410 may be a projective measurement configured to distinguish between |0), |1), and loss (|L)). The qubit teleportation 412 may follow the state-selective readout 410.

[0134] FIG. 4B shows a space-time diagram 414 of a logical circuit 400, focusing on a measurement qubit lifecycle during SE. Physical qubits may progress through time, undergoing initialization, gate operations, idling, and measurement. As shown, the physical qubits include data qubits 416 and measurement qubits 418.

[0135] Entanglement between measurement qubit 418 and a plurality of data qubits 416 makes up a qubit lifecycle. As shown, the plurality of data qubits 416 are trapped in a lattice 420. The lattice 420 may be configured like the entangling zone 204 of the quantum computer processor 200, as described in connection with FIG. 2. For example, the lattice 420 may be a static trap generated by the SLM 106 of the system 100 of FIG. 1, wherein the atoms 105 (i.e., plurality of data qubits 416) are trapped in the static trap. In some embodiments, the measurement qubits 418 may entangle with any number of the plurality of data qubits 416 proximate the measurement qubits 418 by moving the measurement qubits 418 with moving lattice traps. For example, the measurement qubits 418 may be loaded into moving optical traps generated by the first pair of AODs 108 wherein the moving optical traps move the plurality of data qubits 416 to the lattice 420. The local Raman beam 226, as described in connection with FIG. 2, may apply entanglement gates between the plurality of data qubits 416 and the measurement qubits 418.

[0136] In the embodiment of FIG. 4B, a first Hadamard gate 422A is applied to a measurement qubit 418 prior to applying entanglement gates. The first Hadamard gate 422A may be applied with the local SEM beam 225 of the quantum computer processor 200, as described in connection with FIG. 2. As shown, a number of multi-qubit gates 424 are applied between the measurement qubit 418 and nearby data qubits until the measurement qubit 418 experiences the loss event 408. Following the measurement qubit loss event 408, the subsequent multi-qubit gate 424 may be cancelled. In some embodiments, all multi qubit gates 424 applied to the measurement qubit 418 are canceled. As shown, a second Hadamard gate 422B applied to the lost measurement qubit 418 is cancelled. A loss event may cause future and / or previous gates- 26 - #14554048v3Attorney Docket No.: H0776.70187WO00to be canceled, generating correlated errors between the qubits in the gate and flipping the corresponding stabilizers. The state-selective readout 410 may be performed on the measurement qubit 418 after the application of single- and multi-qubit gates. In some embodiments, the state-selective readout 410 may be performed in the readout zone 206 of the quantum computer processor 200, as described in connection with FIG. 2.

[0137] FIG. 5 provides an illustration 500 of a qubit lifecycle and its usage in the delayed-erasure decoder, in accordance with some embodiments of the technology described herein. From initialization to measurement, each physical qubit may be lost at multiple possible time points, each occurring with a potentially different probability and corresponding syndrome. As shown in FIG. 5, the measurement qubit 418 may experience a loss event 408 at any one of a number of time points. Each measurement collected by the state-selective readout 410 may correspond to a syndrome 502 of a given qubit lifecycle. For example, a first syndrome 502A may correspond with a first loss event 408A at a first time point, a second syndrome 502B may correspond with a second loss event 408A at a second time point, and a third syndrome 502C may correspond with a third loss event 408C at a third time point. By combining the first, second, and third syndrome 502A, 502B, 502C, a lifecycle syndrome 504 may be calculated. The lifecycle syndrome 504 may describe an error syndrome for the measurement qubit 418 during the qubit lifecycle of the measurement qubit 418.

[0138] In some embodiments, detection of the loss event 408 may be used during error correction. A decoder may account for possible the error syndromes 502 to perform a quantum error correction (QEC), as described in connection with FIG. 14 herein.

[0139] FIG. 6 shows the logical error rate for a logical memory as a function of the number of conventional SE rounds before logical measurement, here with distance d = 5 and loss errors with probability Ploss= 1% per entangling gate. The delayed-erasure decoder (stars) outperformed a decoder which did not account for loss information (black). Even without loss location information, the delayed-erasure decoder achieved comparable performance to a decoder with perfect loss time-location (gray, dashed).

[0140] FIG. 7 is a flow chart illustrating a process 700 for performing SWAP SE during operation of a quantum computer, in accordance with some embodiments of the technology described herein. Though the process 700 is described herein as implemented using a neutral atom computer, it should be appreciated that the description herein is only one example of the implementation of the process 700. In some embodiments, the process 700 may be performed- 27 - #14554048v3Attorney Docket No.: H0776.70187WO00using any suitable quantum computing device, including but not limited to a neutral atom quantum computer, a superconducting circuit quantum computer, a trapped ion quantum computer, and / or a photonic quantum computer.

[0141] The process 700 begins at block 702 when quantum information is encoded into a logical qubit, wherein the logical qubit is formed by a plurality of physical qubits. In some embodiments, an arbitrary state |ψ⟩Lmay be encoded in quantum states of the plurality of physical qubits. For example, the arbitrary state |ψ⟩Lmay be encoded in the logical qubit wherein each physical qubit of the plurality of physical qubits is of either state |0) or |1). The quantum state of each physical qubit of the plurality of qubits may be set using the first Rydberg tophat beam 218 and the second Rydberg tophat beam 220 of the quantum computer processor 200, as described in connection with FIG. 2 herein, wherein the first and second tophat beams 218, 220 excite the physical qubits of the plurality of physical qubits into state |0) or 11>.

[0142] In some embodiments, encoding a plurality of physical qubits into the logical qubit may include loading the plurality of physical qubits into an optical lattice. As an example, the logical plurality of physical qubits may be trapped in the entangling zone 204 of the quantum computer processor 200 described in connection with FIG. 2. As another example, the plurality of physical qubits may be the plurality of data qubits 416 trapped in the lattice 420, as described in connection with FIG. 4B.

[0143] In some embodiments, the process 700 continues at block 704, wherein a first quantum gate is performed between at least two physical qubits of the plurality of physical qubits. In some embodiments, applying the first quantum gate includes applying a CNOT gate to the at least two physical qubits and subsequently applying a SWAP gate to the at least two physical qubits. The SWAP gate may include three alternating CNOT gates. The first quantum gate may be performed by the local Raman beam 226 of the quantum computer processor 200 as described in connection with FIG. 2. In some embodiments, a plurality of multi-qubit gates may be applied prior to performing the first quantum gate.

[0144] In some embodiments, the process 700 proceeds to block 706 wherein a physical SWAP movement is performed between the at least two physical qubits of the plurality of physical qubits. In some embodiments, the physical SWAP movement includes changing the physical position of the at least two physical qubits. As an example, a physical SWAP may be performed on a first qubit at a first position and a second qubit in a second position. In such an example, the first qubit is moved to the second position and the second qubit is moved to the first position.- 28 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0145] The process 700 may end at block 708 after performing the physical SWAP movement, an error syndrome of the logical qubit is measured. The error syndrome may be measured by measuring quantum states of the plurality of physical qubits. In embodiments where the plurality of physical qubits include data qubits 416 and measurements qubit 418, measuring the error syndrome of the logical qubit may include performing state-selective readout 410 of the measurement qubit 418, as described in connection with FIGs. 4A-4B. In some embodiments, the error syndrome is determined using state- selective readout performed on the plurality of data qubits 416. In some embodiments,, the error syndrome is determined using state- selective readout performed on the plurality of data qubits 416 and the measurement qubits 418.

[0146] An error correction may be applied following the measurement of the error syndrome of the logical qubit. In some embodiments, the error correction may include replacing a lost physical qubit with a new physical qubit. For example, the state-selective readout 410 may determine a quantum state of the lost physical qubit to be |L) and replace the lost physical qubit with a new physical qubit. In some embodiments, the new physical qubit may be a physical qubit from the storage zone 202 of the quantum computer processor 200, as described in connection with FIG. 2.

[0147] FIG.8 shows an example of a modified SWAP syndrome extraction (SE) 800 in which data qubits 416 and measurement qubits 418 may be swapped each round to detect loss via state- selective readout (SSR) 410, in accordance with some embodiments of the technology described herein. The SWAP SE 800 method may be performed by pairing each data qubit 416 with a measurement qubit 418 for each stabilizer check round. As shown, the measurement qubit 418 interacts with each neighboring data qubits 416 through four gates, 802 and 804. In some embodiments, any one of the four gates may be a quantum operation including but not limited to a multi-qubit gate (e.g., CNOT, CZ, SWAP, and / or Toffoli). In the example of FIG.8, the quantum operation includes a CNOT gate 802 followed by a SWAP gate 804. The SWAP gate 804 may include three alternating CNOT gates (e.g., wherein the target qubit is alternated between the measurement qubit 418 and the data qubit 416A such that a bit- flip operation may be applied to, altematingly, the measurement qubit 418 and / or the data qubit 416A).

[0148] After the quantum operation, in some embodiments, the measurement qubit 418 and a final data qubit 416A may swap quantum information and / or physical locations during a SWAP movement 806. As an example, if the final data qubit 416A is present (e.g., has not been lost),- 29 - #14554048v3Attorney Docket No.: H0776.70187WO00the following the SSR 410 measurement of the measurement qubit 418 may yield |0) or |1), reflecting the state of the stabilizer. As another example, if the final data qubit 416A is missing (e.g., has been lost), the CNOT gate 802 and / or the SWAP gate 804 fail, and the measurement qubit 418 heralds |L) using SSR 410. The CNOT gate 802 and / or SWAP gate 804 failure and heralded loss state enables detection of the data qubit loss event 408 and replacement with a fresh measurement qubit 418. As shown, the lost final data qubit 416A is replaced with the measurement qubits 418 using the SWAP movement 806.

[0149] In a conventional SE round (e.g., without the SWAP movement 806), application of an SSR 410 detects the loss of measurement qubits 418 only. However, during a SWAP SE 800 round, the SSR 410 detects the loss of data qubits 416. In various embodiments, the loss of measurement qubits 418 before the SWAP is undetected in the SWAP SE 800, resulting in the valid data qubit 416 being replaced with a lost measurement qubit 418. In such an embodiment, the resulting lost measurement qubit 418 is detected in the next SWAP SE round and replaced with a fresh measurement qubit 418.

[0150] In the embodiment of FIG. 8, a software correction 808 may be applied to correct for the detected loss event 408. Details of the software correction will be discussed further in connection with FIG. 14.

[0151] FIG. 9 is a flow chart illustrating a process 900 for performing teleportation-based SE during operation of a quantum computer, in accordance with some embodiments of the technology described herein. Though the process 900 is described herein as implemented using a neutral atom computer, it should be appreciated that the description herein is only one example of the implementation of the process 900. In some embodiments, the process 900 may be performed using any suitable quantum computing device, including but not limited to a neutral atom quantum computer, a superconducting circuit quantum computer, a trapped ion quantum computer, and / or a photonic quantum computer.

[0152] In some embodiments, the process 900 begins at block 902, wherein first quantum information is encoded into a first logical qubit comprising a first plurality of physical qubits. Encoding the first quantum information may include encoding the first quantum information into an arbitrary quantum state of the first logical qubit. Encoding the first quantum information into the first logical qubit may be performed as described for block 702 of the process 700 described in connection with FIG. 7 herein.- 30 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0153] In some embodiments, the process 900 continues to block 904, wherein the first logical qubit is entangled in a first cluster state. In various embodiments, the first logical qubit in the first cluster state includes entangling the first plurality of physical qubits according to a foliated quantum error correction code. As two non-limiting examples, the first cluster state may be Raussendorf-Harrington-Goyal (RHG) cluster state or an XZZX cluster state, though other suitable cluster states may be implemented.

[0154] In some embodiments, the process 900 proceeds to block 906, wherein second quantum information is encoded into a second logical qubit comprising a second plurality of physical qubits. Encoding the second quantum information into the second logical qubit may be performed as described for block 702 of the process 700 described in connection with FIG. 7.

[0155] In some embodiments, the process 900 continues to block 908, wherein the second logical qubit is entangled in a second cluster state. The second logical qubit may be entangled in a second cluster state as described for entangling the first logical qubit in the first cluster at block 904 above.

[0156] In some embodiments, the process 900 proceeds to block 910, wherein the first quantum information from the first logical qubit is teleported to the second logical qubit. Teleporting the quantum information may be performed by applying a quantum operation (e.g., between the first and second logical qubits, including but not limited to a CNOT gate) and subsequently a measurement to physical qubits of the first plurality of physical qubits.

[0157] In some embodiments, one quantum operation may subsequently be applied between the first logical qubit and the second logical qubit to entangle one or more quantum states of the first and second logical qubits. In some embodiments, the quantum operation includes a multi-qubit gate (e.g., CNOT, CZ, SWAP, and / or Toffoli gate).

[0158] Any number of teleportation events may occur during operation of the quantum system. In some embodiments, teleportation is triggered by detection of a loss event. For example, in response to a detected loss event of a physical qubit of the first plurality, the lost physical qubit of the first plurality is replaced by a physical qubit of the second plurality using teleportation of the physical qubit of the second plurality into the first logical qubit.

[0159] In some embodiments, the process 900 concludes at block 912, wherein state- selective readout (SSR) is used to measure quantum states of the first and / or second plurality of physical qubits, wherein the measuring obtains an error syndrome associated with the first and / or logical qubit. In some embodiments, the error syndrome of both the first logical qubit and the second- 31 - #14554048v3Attorney Docket No.: H0776.70187WO00logical qubit is measured. In some embodiments, the error syndrome of either the first logical qubit or the second logical qubit is measured. The SSR 410 may be performed as described for the logical algorithm 402 in connection with FIGs. 4A-4B. The SSR may take place in the readout zone 206 of the quantum computer processor 200, as described in connection with FIG.2.

[0160] FIG. 10 shows an example of teleportation-based SE 1000, in which logical qubits are teleported to fresh blocks prepared in alternating bases, loss is detected via SSR (e.g., thereby shortening lifecycles), at the cost of utilizing extra physical qubits. In some embodiments, teleportation-based SE 1000 includes performing quantum operations between a first logical qubit 1002 A, a second logical qubit 1002B, and a third logical qubit 1002C (collectively “1002”). The logical qubits 1002 are formed by physical qubits, which may include data qubits 1004 and / or measurement qubits 1006. For example, the second logical qubit 1002B may include a second plurality of data qubits 1004B and a second plurality of measurement qubits 1006B. The third logical qubit 1002 A may include a third plurality of data qubits 1004C and a third plurality of measurement qubits 1006C. The data qubits 1004 and measurement qubits 1006 may be configured as described for the data qubits 416 and measurement qubits 418 of the logical algorithm 402 in connection with FIG. 4B.

[0161] In some embodiments, the first logical qubit 1002 A may be initialized by encoding an arbitrary quantum state, |ψL⟩. into the physical qubits (e.g, the data qubits 1004A) forming the first logical qubit 1002A. Similarly, a quantum state (e.g., |+ ) may be encoded into the physical qubits (e.g., the data qubits 1004B). Thereafter, the physical qubits forming the logical qubits 1002 may be entangled to form respective cluster states. As shown, in some embodiments, a first Hadamard gate 1008 A is applied to the first logical qubit 1002A after the first logical qubit 1002A has been initialized. In some embodiments, applying the first Hadamard gate 1008 A includes applying a Hadamard gate to each physical qubit of the first plurality of physical qubits making up the first logical qubit 1002 A. In embodiment where the first and / or second logical qubit is entangled into an XZZX cluster state, Hadamard gates are applied to at least half of the physical qubits forming the XZZX cluster state. A loss event 1010 may occur, affecting the first logical qubit 1002A (e.g., a data qubit 1004B may be lost).

[0162] To detect the loss event 1010, a teleportation operation may be used as part of a syndrome extraction measurement, in some embodiments. To do so, a first quantum operation (e.g., a CNOT gate) may first entangle the first and second logical qubit 1002A, 1002B, and- 32 - #14554048v3Attorney Docket No.: H0776.70187WO00thereafter a first measurement 1012A of the first logical qubit 1002 A may be performed. The first measurement 1012A may cause information from the first logical qubit 1002 A to move to the second logical qubit 1002B. The measurement 1012A may also provide information indicative of a loss event. In some embodiments, the teleportation may be performed as described in block 910 as described in connection with FIG. 9.

[0163] In some embodiments and as shown, a second quantum operation (e.g., a CNOT gate) may then entangle the second logical qubit 1002B with a third logical qubit 1002C which has been initialized in a |0) quantum state. In some embodiments, the second quantum operation is applied transversally, wherein the second quantum operation is applied between a first physical qubit of the second logical qubit 1002B and a second physical qubit of the third logical qubit 1002C. Subsequently, Hadamard gates 1008 may be applied to the second and third logical qubits 1002B, 1002C, in some embodiments. As shown, a second Hadamard gate 1008B is applied to the third logical qubit 1002C and a third Hadamard gate 1008C is applied the second logical qubit 1002B. The teleportation is then completed by performance of the second measurement 1012B (e.g., an SSR measurement) of the second logical qubit 1002B, which may further provide information indicative of the loss event 1010.

[0164] FIG. 11A shows an example of a Steane SE circuit 1100, according to some embodiments. FIG. 11B shows an adjusted Steane SE circuit 1140 including a logical SWAP 1142, giving a version of Knill SE, which is capable of correcting Pauli errors but also loss errors. In the adjusted Steane SE circuit 1140, every SSR measurement is used to detect Pauli errors and loss errors while also teleporting the quantum information to another logical qubit.

[0165] As shown, the Steane SE circuit 1100 uses transversal CX gates (e.g., CNOT gates) applied to fault- tolerant logical measurement qubits 1104A, 1104B to extract syndromes and detect errors in the quantum information stored in logical qubit 1102. The logical qubit 1102 and logical measurement qubits 1104A, 1104B may each include a plurality of physical qubits. The plurality of physical qubits may contain data qubits and measurement qubits. The first and second measurement qubits 1104A, 1104B may be logical qubits encoded in code blocks (e.g., according to error correction codes such as but not limited to Steane codes, surface codes, Shor codes, etc.). The code blocks may undergo < d SE rounds, as shown in FIG. 11 A.

[0166] In some embodiments, the Steane SE circuit 1100 may be executed by first performing a first quantum operation (e.g., a CX gate) between the logical qubit 1102 and the first logical measurement qubit 1104 A. A first measurement 1106 A may thereafter be performed on the- 33 - #14554048v3Attorney Docket No.: H0776.70187WO00first logical measurement qubit 1104A following the first quantum operation to extract a syndrome measurement indicative of a state of the logical qubit 1102. A second quantum operation (e.g., a CX gate) may then be performed between the logical qubit 1102 and the second logical measurement qubit 1104B. A second measurement 1106B may be performed on the second logical measurement qubit 1104B following the second quantum operation to extract a syndrome measurement indicative of a state of the logical qubit 1102.

[0167] Transversal gates (e.g., CX gates), which may apply the same quantum operation across corresponding physical qubits in each code block, may ensure that errors propagate predictably from data qubits to measurement qubits. If the measurement qubits are prepared fault-tolerantly with d SE rounds, one round of Steane SE may suffice to accurately capture the syndromes in a given basis. However, conventional Steane SE circuits 1100 lack a native mechanism for detecting loss, as losses on data qubits are not detected by the measurement qubits and remain hidden until the end.

[0168] In some embodiments, the conventional Steane SE circuit 1100 may be modified by incorporating logical SWAP operations (e.g., a SWAP gate 1142A and SWAP movement 1144B) to form the adjusted Steane SE circuit 1140, as illustrated in FIG. 1 IB, thereby enabling loss detection through SSR at each logical measurement. The adjusted Steane SE circuit 1140 leverages the teleportation of logical information and resembles Knill SE.

[0169] In some embodiments, the modified Steane SE circuit 1140 may be an interpolation between SWAP SE 800 (FIG. 8) and teleportation-based SE 1000 (FIG. 10). Conversely, multiple rounds of SE may be used to prepare a higher-quality logical measurement qubit, providing flexibility to adapt to various error models and resource constraints. Steane SE also supports pre-selection of measurement qubit blocks based on quality (e.g., data quality and imaging quality), potentially increasing fidelity without significant overhead.

[0170] FIG. 12 is a flow chart illustrating a process 1200 for performing direct conversion syndrome extraction (SE) during operation of a quantum computer, in accordance with some embodiments of the technology described herein. Though the process 1200 is described herein as implemented using a neutral atom computer, it should be appreciated that the description herein is only one example of the implementation of the process 1200. In some embodiments, the process 1200 may be performed using any suitable quantum computing device, including but not limited to a neutral atom quantum computer, a superconducting circuit quantum computer, a trapped ion quantum computer, and / or a photonic quantum computer.- 34 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0171] In some embodiments, the process 1200 begins with a block 1202 of encoding quantum information into a logical qubit comprising a plurality of physical qubits. Encoding quantum information into the logical qubit may be performed as described in block 702 of the process 700 (FIG. 7) and blocks 902 and 906 of the process 900 (FIG. 9), as described herein.

[0172] In some embodiments, the process 1200 continues at block 1204 by performing at least one quantum operation between a physical data qubit of the plurality and a measurement qubit, the quantum operation comprising performing a first-type quantum gate between the physical data qubit and the measurement qubit. The first-type quantum gate may include a multi-qubit gate (e.g., CNOT, CZ, SWAP, and / or Toffoli).

[0173] In some embodiments, the process 1200 proceeds to block 1206 by performing erasure detection following the at least one quantum operation. Erasure detection may be performed by detecting a location where a loss event occurs. In some embodiments, the identified lost logical qubit may be replaced by a fresh logical qubit. As one example and in the context of neutral atom computing, after detecting a logical qubit loss in the entangling zone 204, a fresh qubit from the storage zone 202 may be moved by optical tweezers to replace the lost logical qubit in the entangling zone 204, as described in connection with FIG. 2 herein.

[0174] In some embodiments, the process 1200 may finish by measuring a quantum state of the physical data qubit to obtain an error syndrome of the logical qubit. Obtaining the error syndrome of the logical qubit may be performed as described in block 708 of process 700, as described in connection with FIG. 7 herein.

[0175] FIG. 13 shows an example of direct conversion SE 1300 including mid-circuit measurement and replacement-converted loss-to-erasure, according to some embodiments described herein. The direct conversion SE 1300 may be performed by pairing each data qubit 416 with a measurement qubit 418 for each stabilizer check round. As shown, the measurement qubit 418 interacts with each neighboring data qubits 416 through quantum gates. In some embodiments, any one of the quantum gates may be a quantum operation including but not limited to a multi-qubit gate (e.g., CNOT, CZ, SWAP, and / or Toffoli). In the example of FIG.13, the quantum operation includes a CNOT gate.

[0176] In the embodiment of FIG. 13, an erasure detection 1302 is applied subsequent each quantum operation between the measurement qubit 418 and the plurality of data qubits 416. In response to a positive erasure detection signaling a loss event 408 of a data qubit 418, the lost data qubit 418 may be replaced by a fresh qubit (e.g., from a store of prepared qubits or by re-- 35 - #14554048v3Attorney Docket No.: H0776.70187WO00initializing a quantum state in the qubit). In some embodiments, a lost measurement qubit 418 may be replaced by a fresh qubit. Erasure detection and replacement may be performed as described in block 1206 of the process 1200 described in connection with FIG. 12 herein. In some embodiments, the erasure detection 1302 may be performed either after each quantum operation (e.g., as shown in FIG. 13) or after a plurality of applied quantum operations.

[0177] In some embodiments, a measurement 1304 is performed on the measurement qubit 418 to extract information stored in the measurement qubit 418. In some embodiments, the measurement 1304 may measure a state of the measurement qubit 418. In some embodiments, the measurement 1304 may be a SSR 410, as described in connection with FIGs. 4A-4B herein.

[0178] As shown, FIG. 13 includes a schematic at right summarizing direct conversion SE 1300 of Rydberg qubits. The physical qubits (e.g., data qubits and / or measurement qubits) may be hyperfine qubits, wherein |0) and |1) states may refer to hyperfine states 1306. The hyperfine qubits may be excitable to a Rydberg state 1308 (|r)), as described in connection with FIGs. 1, 2, and 3 herein. In some embodiments, the erasure detection 1302 may be applied to the qubits in the Rydberg state 1308, as shown in FIG. 13. In other embodiments, the erasure detection 1302 may be performed on qubits in the hyperfine states 1306.

[0179] FIG. 14 is a flow chart illustrating a process 1400 for performing error correction during quantum computation, in accordance with some embodiments of the technology described herein. Though the process 1400 is described herein as implemented using a neutral atom computer, it should be appreciated that the description herein is only one example of the implementation of the process 1400. In some embodiments, the process 1400 may be performed using any suitable quantum computing device, including but not limited to a neutral atom quantum computer, a superconducting circuit quantum computer, a trapped ion quantum computer, and / or a photonic quantum computer.

[0180] In some embodiments, the process 1400 begins at block 1402 by encoding first quantum information into a first logical qubit comprising a first plurality of physical qubits. Encoding the first quantum information into the first logical qubit may be performed as described for block 702 of the process 700 and / or block 902 of the process 900 as described in connection with FIGs. 7 and 9 herein.

[0181] In some embodiments, the process 1400 continues to block 1404 by performing at least one quantum operation on the first logical qubit by applying one or more quantum gates to- 36 - #14554048v3Attorney Docket No.: H0776.70187WO00qubits of the first plurality of physical qubits. In some embodiments, the quantum operation includes a multi-qubit gate (e.g., CNOT, CZ, SWAP, and / or Toffoli gate).

[0182] In some embodiments, the process 1400 proceeds to block 1406 by measuring an error syndrome of the first logical qubit. Obtaining the error syndrome may be performed as described in block 708 of process 700, block 912 of the process 900, and / or block 1208 of the process 1200 as described in connection with FIGs. 7, 9, and 12 herein.

[0183] In some embodiments, the process 1400 continues to block 1408 by generating a list of potential loss events based on the measured error syndrome, the potential loss events identifying a loss of one or more of the first plurality of physical qubits during the performance of the at least one quantum operation.

[0184] In response to detecting a loss event, quantum gates applied to the one or more lost first plurality of physical qubits may be canceled, in some embodiments.

[0185] In some embodiments, the process 1400 proceeds to block 1410 by generating a decoding hypergraph based at least in part on the list of potential loss events. Generating the decoding hypergraph may be performed by generating a plurality of loss circuits, wherein a loss circuit represents a loss event of the physical qubit for the physical qubit lifecycle, and combining the plurality of loss circuits into the decoding hypergraph.

[0186] In some embodiments, a loss circuit may include a plurality of detectors and a plurality of hyperedges configured to connect the plurality of detectors. The hyperedges may be configured to represent a possible error event, connect the plurality of detectors flipped by the possible error event, and extract a corresponding probability for the possible error event.

[0187] In some embodiments, extracting a corresponding probability for the possible error event comprises assigning a first probability to a first hyperedge associated with a lost qubit, wherein the first probability is associated with a first weight of the decoding hypergraph. In some embodiments, the first probability is approximately equal to 0.5 and the first weight is approximately equal to 0.

[0188] In some embodiments, the process 1400 continues to block 1412 by generating, by providing the decoding hypergraph as input to a quantum decoder, at least one quantum error correction operation to correct errors that occurred during the performance of the at least one quantum operation.

[0189] In some embodiments, generating the quantum error correction includes extracting a set of decoding hypergraphs from detected loss events, summing the decoding hypergraphs of- 37 - #14554048v3Attorney Docket No.: H0776.70187WO00the set of decoding hypergraphs, applying a normalized weight associated with the decoding hypergraph, generating a final decoding hypergraph, and inputting the final decoding hypergraph into the quantum decoder. The final decoding hypergraph may comprise the lifestyles and statistical weights for lifecycles of lost physical qubits. Details on how the lifecycle syndrome and final decoding hypergraph is described further in connection with FIGs.15A-15B herein.

[0190] In some embodiments, the quantum decoder may be configured to identify errors in a quantum computation and to enable the performance of quantum error correction. In some embodiments, the quantum decoder is a trained machine learning model and / or neural network configured to perform quantum error correction. In some embodiments, performing the quantum error correction is performed by applying most likely error (MLE) decoding, minimum weight perfect matching (MWPM) decoding, belief propagation decoding, and / or delayed-erasure decoding.

[0191] In some embodiments, the process 1400 ends at block 1414 by applying the at least one quantum error correction operation to the first logical qubit to correct the errors that occurred during the performance of the at least one quantum operation.

[0192] While exact most-likely-error (MLE) decoding may be computationally challenging, it served as a theoretical benchmark that guided the development of efficient approximate methods. The framework was generalized by incorporating both Pauli and loss errors. Let E = represent binary variables for Pauli error events, and L = (L1L2- - -) represent binary variables for loss events. It was assumed that Pauli and loss errors occurred independently across circuit locations, although correlated models may be incorporated in some embodiments.

[0193] Measurement outcomes provided two kinds of information: (1) Flags F, indicating when qubit loss was detected; and (2) Detectors D, constructed as products of stabilizer measurement outcomes that were predicted to be +1 in the absence of error. Because loss rendered some measurements invalid, the set of active detectors was dynamically redefined based on the observed flags.

[0194] The most likely error problem sought to find the assignment of Pauli errors E and loss errors L that maximize the following quantity:P(E, L\F, D, (Bl)- 38 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0195] Namely, given the observed flags, and the resulting detectors that were defined conditionally on seeing those flags, what was the most likely error.

[0196] This expression was rewritten using Bayes’ ruleP(E, L | F, D) = P(E, L) · P(F, D | E, L) / P(F, D)

[0197] Since there was a fixed observation F, D, the denominator was fixed. Therefore, focus was on maximizing the product of the probability of the error configuration P(E, L ) and the conditional probability of observing these syndromes. In the presence of loss, one distinction from the usual case is that the latter factor was no longer always 0 or 1.

[0198] The error probability P(E, L ) may be calculated based on the log likelihood ratios of individual events. However, since only one loss event occurs per qubit lifecycle, the effective probability of loss at location j was pj nk<7(l — Pk)- This correction was relevant when the loss probabilities varied significantly across locations.

[0199] The more challenging factor to evaluate was P(F, D |E, L ). First, given a loss pattern, detectors were updated by replacing invalidated measurements with combinations of adjacent ones (e.g., superchecks). While the exact choice was irrelevant in full MLE decoding due to stabilizer equivalence, it may affect the performance of heuristic decoders. After forming the detectors, an evaluation as to whether a given loss and error pattern was consistent with the observed loss flags and detectors was performed. The flag check was straightforward: at most one loss event should be active per qubit lifecycle. Evaluating the detector consistency was more subtle. In the presence of loss, certain detector activations were probabilistic, depending on both the location and timing of the loss event. Given a specific loss pattern, the circuit was fixed, and the resulting conditional detector distribution may be computed by propagating the error configuration through the modified circuit.

[0200] One such approach was edge reweighting, where known correlations between loss and downstream Pauli errors were captured by modifying decoder edge weights. For instance, published models leaked qubits as inducing depolarizing noise on all subsequent interactions, assigning higher error weights to gates further in time. While this captured leading-order effects, it neglected correlations introduced by the fact that leaked qubits persisted across time- 39 - #14554048v3Attorney Docket No.: H0776.70187WO00steps, resulting in temporally correlated error patterns. Accounting for this structure may improve heuristic approximations to MLE decoding.

[0201] Ultimately, the goal was to identify practical heuristic methods that approximate MLE decoding while capturing the effects of loss. This was pursued by analyzing which errors were commonly misclassified by a given weighting scheme or by benchmarking against exact MLE decoding on small instances. Neural network decoders offered a complementary strategy by directly learning mappings from syndrome and flag data to logical corrections, implicitly capturing both error and loss correlations.

[0202] Below, the decoding strategy that approximated the MLE decoding introduced above is described. The goal was to capture the features of loss-induced error correlations, particularly the way loss truncated gate sequences and altered detector structure, without solving the full combinatorial problem.

[0203] As described herein, the goal was to automatically construct a decoding hypergraph based on the observed loss, which served as the input to any general decoder for the QEC code analyzed. The general approach relied on precomputing the decoding hypergraph for each possible loss location within a qubit’s lifecycle. Given a heralded loss upon measurement, it was inferred that the loss occurred at some earlier location in the lifecycle, and a probability was assigned to each possible location. Given a specific experiment with a given loss pattern, the relevant precomputed lifecycle decoding hypergraphs were summed, as described below. FIGs. 25A-25B illustrate this procedure, showing how the loss locations in each lifecycle contributed to the overall decoding hypergraph for a given shot.

[0204] This approach was formalized. G denoted the lifecycle of qubit i, and {Ly } denoted the set of possible loss locations for that qubit, each associated with a probability py. For each possible loss event Ly, the loss circuit, a modified circuit generated by removing all gates after the loss and setting the qubit’s final measurement to a uniformly random outcome were simulated. Using Stim’s gauge detector infrastructure, the decoding hypergraph denoted DEMy was extracted, which comprised a set of hyperedges (error events) and their associated detector configurations.

[0205] Each decoding hypergraph DEMy was a matrix, a collection of error probabilities pnand corresponding detector configurations DnDEMij= {(pn, Dn)}, (B3)- 40 - #14554048v3Attorney Docket No.: H0776.70187WO00where the columns Dn= [Dn(0), Dn(1),... ] represented the list of detectors triggered by the error event in each row. This process was repeated for all potential loss events Ltj within a lifecycle Ciresults in a set of decoding hypergraphs DEMijand their associated probabilities pij. This was done in a pre-processing stage.

[0206] To compute the final decoding hypergraphs for a lifecycle G of a lost qubit i, all decoding hypergraphs in the lifecycle were summed:DEMi= ∑jp̃ij· DEMij. (B4)

[0207] with normalized weights p̃ij= Pr(Lij|flag in Ci); this was an approximation that assumed at most one loss per lifecycle and neglected cross-lifecycle combinations.

[0208] When multiple qubit losses occurred in different lifecycles, loss errors may result in correlated Clifford errors. Combining syndromes from distinct lifecycles may interfere non-linearly, resulting in syndromes that cannot be derived from independent consideration of loss events. While the optimal decoder considered all combinations of potential loss locations for all qubits, this approach scaled poorly with multiple lossy lifecycles and potential loss events, making it impractical for small code distances (d < 1).

[0209] To address this, a decoder that evaluated each lifecycle Ciindependently and averaged over them (DEMi) was explored. Additionally, the option to include a single combination of losses across different lifecycles was introduced. Specifically, the first potential loss locations Li1for all lossy lifecycles Liwas considered and a corresponding decoding hypergraph, DEMfirst combwas generated.

[0210] The decoding hypergraphs for individual potential loss locations Ltj were generated in a pre-processing step, independent of any specific error model or probabilities of Pauli and loss errors. During real-time decoding, these hypergraphs were summed using the specific error model probabilities ptj. Loss errors and Pauli errors were accounted for separately. Lossless circuits (without losses) were used to efficiently generate the decoding hypergraph for Pauli errors, denoted DEMPauli.

[0211] For a specific shot with a heralded loss pattern using SSR and a given error model, the final decoding hypergraph was computed by summing: 1. Lossy lifecycle decoding hypergraphs DEMi, 2. The Pauli decoding hypergraph DEMPauli, and 3. The first potential loss combination decoding hypergraph DEMfirst comb.

[0212] The final decoding hypergraph was given by:- 41 - #14554048v3Attorney Docket No.: H0776.70187WO00DEMfinal= ∑iDEMi+ DEMPauli+ ω · DEMfirst comb(B5)

[0213] where ω is a combination weight determined based on the analysis in Appendix Section B.2.a of the Example Section below.

[0214] The summation of probabilities was calculated using the following equation:i i l l 2 PI na -p>)+E S 2p,p,p‘ n Pm)- 1=1 j±i 1=1 j=i+l k=j+l m±i,j,k(B6)

[0215] This ensured accuracy up to O(p3).

[0216] Once DEMfinalwas constructed for a given shot, any decoder that accepted a hypergraph-based detector error model may be used — such as MLE, minimum weight perfect matching (MWPM), belief propagation or others, depending on the QEC code in use.

[0217] FIGs. 15A-15B provide an overview of the approximate MLE decoding procedure. FIG. 15A shows that, for a given qubit lifecycle, potential loss locations (crosses) were identified and modified circuits were simulated for each, generating a set of decoding hypergraphs (DEMij). These include updated stabilizer syndromes (detectors) and correlated error edges resulting from the truncated loss circuits. FIG. 15B shows that when multiple qubit losses were present in a given shot, the decoding hypergraph was computed for each lifecycle independently (left), optionally included a combined loss decoding hypergraph (right), and summed with the standard Pauli decoding hypergraph to generate the final decoding hypergraph (DEMfinal), according to Eq. B5. This forms the input to the decoder.

[0218] Each loss mechanism may induce a modified circuit, which may alter the set of stabilizer detectors and introduced correlated error configurations. The resulting decoding hypergraph may include a set of detectors (vertices) and hyperedges, where each hyperedge represented a possible error event, connected a subset of detectors it flips, and was assigned a corresponding probability, as described in connection with FIG. 14 herein. This hypergraph may serve as the input to the decoder. Given a heralded loss at measurement (e.g., using SSR or erasure conversion), the lifecycle of the affected qubit (defined as the sequence of operations from initialization to measurement) was reconstructed and its potential loss locations were enumerated. Each potential loss point defined a distinct “loss circuit,” which produced a different set of hyperedges in the decoding hypergraph, as shown in FIG. 15 A.- 42 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0219] Loss may require two decoder-level adjustments: (1) modifying detectors to remove dependence on the lost measurement (via superchecks), and (2) accounting for error edges arising from truncated circuits after loss. Below, each adjustment is further described and a specific example is provided for clarity.

[0220] First, in each loss circuit, the measurement of the lost qubit may be set to a random result. This may result in assigning a probability of 0.5 to the relevant edge, which corresponded to a weight of 0 in the decoding hypergraph. This process may generate a supercheck operator, defined as the product of neighboring checks, effectively eliminating the lost qubit’s contribution. Since the loss was detected in all loss circuits for the potential loss locations, the supercheck operator appeared in all decoding hypergraphs of the qubit’s lifecycle. Consequently, the supercheck may be incorporated into the final decoding hypergraph of the lifecycle.

[0221] Second, when an atomic qubit was lost, subsequent gates involving this qubit may act trivially. Therefore, each loss circuit may omit certain gates due to the lost qubit. As a result, the decoding hypergraph for the circuit may include new edges that correspond to these missing gates, capturing the errors associated with the specific loss under consideration. These edges may appear in the final decoding hypergraph of the lifecycle, with probabilities reflecting the likelihood of the associated events.

[0222] FIGs. 16A-17B show examples of detector activations generated by different loss events in a d = 3 surface code over four time steps (t = 1-4). FIGs. 16A-16F show two potential loss locations for the same data qubit q, in round t = 2 and t = 3, respectively, each after the first gate. These correspond to different loss circuits within the same lifecycle and were combined into a single decoding hypergraph for that lifecycle. FIGs. 17A-17B show a loss of a measurement qubit m' in round t = 2, which belonged to a separate lifecycle and contributed a separate decoding hypergraph. Detectors / J0- / J4 are highlighted. Each row (£)) in the decoding hypergraph tables (FIGs. 16B, 16E, and 17B) corresponds to one error mechanism (hyperedge), i.e., a correlated set of detector activations triggered by a single loss event. Superchecks that were activated in all loss circuits of a given lifecycle also appeared in the final decoding hypergraph, such as the shared activation of £>3 in FIGs. 16A-16F.

[0223] FIGs. 16A-17B illustrate a specific example using a d = 3 surface code over four time steps: an initialization round (t = 1), two syndrome extraction (SE) rounds (t = 2, 3), and a final transversal measurement (t = 4). In this example, the syndrome patterns caused by losses at- 43 - #14554048v3Attorney Docket No.: H0776.70187WO00different locations and times are presented. FIGs. 16A, 16D, and 17A show the circuits with canceled gates and heralding, while FIGs. 16B, 16E, and 17B display the decoding hypergraph, listing which detectors are activated and their correlations. This example used a conventional SE scheme with measurement qubits read out every round and data qubits only at the end, but the decoding approach applied to any SE method.

[0224] Each row in the decoding hypergraph (FIGs. 16B, 16E, and 17B) corresponds to a distinct detector activation pattern produced by propagating a specific loss through the truncated circuit. For example, when data qubit q was lost at t = 2, all subsequent CZ gates on q canceled and the final readout was randomized. The missing CZs made stabilizers involving q inconsistent across rounds, producing time-like detector flips such as {Do, D\ ] or {£>1 }. In some branches, the loss heralding itself introduced a plaquette mismatch (D3), or the neighboring stabilizer of q registered a time-like inconsistency (£>2). Thus the multiple rows for a single loss represented different deterministic ways a single heralded loss may violate stabilizer checks, depending on timing and Pauli by-product branches. The following section explicitly explains each row.

[0225] Detectors D0-D4 correspond to parity checks between stabilizer outcomes across rounds: Do and £>1 compared the same stabilizer across t = 1 — 2 and t = 2 — 3 respectively, D2 monitored the neighboring stabilizer of q across t = 2 — 3, £>3 was the final plaquette stabilizer containing q given by the final transversal measurement and compared with previous round, and £>4 compared measurement qubit m across t = 1 — 2.(a) Loss of data qubit q at t = 2. All subsequent gates on qcanceled, and the final measurement was probabilistic. The missing CZs disrupted stabilizers involving q. The decoding hypergraph contained five rows:{£>o, £>1 } (mismatches in both t = 1 — 2 and t = 2 — 3), {£>1 } (only t = 2 — 3), {£>1, £>3} (round t = 2 — 3 plus the plaquette check containing q), { / Z2 } (neighbor stabilizer at t = 2 — 3), and {£>3} (plaquette t = 3 — 4 inconsistency).(b) Loss of data qubit q at t = 3. Since stabilizers remained intact through t = 2, only the final checks were affected: {£>1} (round t = 2 — 3), {£>1, £>3} (round t = 2 — 3 plus plaquette t = 3 — 4), and {£>3} (plaquette t = 3 — 4 inconsistency).

[0226] Since both (a) and (b) correspond to different loss locations within the same data qubit lifecycle, any detectors that were activated in all loss circuits became part of the supercheck structure for that lifecycle. In this case, detector £>3, which corresponds to the final plaquette- 44 - #14554048v3Attorney Docket No.: H0776.70187WO00stabilizer involving q, was activated in both loss circuits and thus appeared in both decoding hypergraphs. As a result, £>3 was retained in the final decoding hypergraph for the lifecycle and served as a supercheck.(c) Loss of measurement qubit m at t = 2. The round-2 measurement of m was missing, invalidating detectors £>2 and £>4. Their product formed a valid supercheck, O2O4= Mm t=1Mm t=3, correlating rounds 1 and 3 directly. Additionally, the canceled CZ introduced an error on the paired data qubit, activating Do.

[0227] These examples show how a single loss modified the circuit and produced specific correlated detector patterns.

[0228] FIG. 18 shows a schematic level diagram 1800 of the atomic transitions of87Rb, which is used as a neutral atom qubit in some embodiments. In particular, the level diagram 1800 shows a Rydberg excitation scheme from a qubit state |1) to the Rydberg excitation state |r), where the total angular momentum (F) is shown on the left. The level diagram 250 shows the quantum numbers of an excited87Rb atom, wherein the excitation state of the87Rb atom is controlled by the plurality of lasers in the quantum computer, though it should be appreciated that aspects of the technology described herein are not limited to only an87Rb, as alternative neutral atom species (e.g., Cs, Yb, Sr, etc.) or qubit types (e.g., superconducting, ionic, photonic, etc.) may be used.

[0229] As shown in FIG. 18, the87Rb qubit is initially encoded into one of two states, a |0) state located at the ground state of87Rb and a 11) state located at a 5S1 / 2state of87Rb. The 11) state 254 is 6.8 GHz higher in energy than the |0) state. When illuminated by the local Raman beam 226 of the quantum computer processor 200, the |0) state may be excited above the 5P1 / 2state to a first excitation state 1802, which is detuned about the 5P1 / 2state.

[0230] As shown in FIG. 18, the first Rydberg tophat beam 218 may excite the 11) state below a 6P3 / 2state to a second excited state 1804. Subsequently, the second Rydberg tophat beam 220 may excite the atom from the second excited state 1804 to a 70S1 / 2 state, which may be equivalent to a Rydberg state (|r)) of87Rb. The double excitation of the |1) state with the first and second Rydberg tophat beams 218, 220 illustrates the two-photon excitation that may be performed in the readout zone 206.

[0231] An illustrative implementation of a classical computer system 1900 that may be used in connection with any of the embodiments of the technology described herein (e.g., such as a- 45 - #14554048v3Attorney Docket No.: H0776.70187WO00controller implementing the method of FIGs. 9, 12 or 14) is shown in FIG. 19. The computer system 1900 includes one or more processors 1910 and one or more articles of manufacture that comprise non-transitory computer-readable storage media (e.g., memory 1920 and one or more non-volatile storage device 1930). The processor 1910 may control writing data to and reading data from the memory 1920 and the non-volatile storage device 1930 in any suitable manner, as the aspects of the technology described herein are not limited to any particular techniques for writing or reading data. To perform any of the functionality described herein, the processor 1910 may execute one or more processor-executable instructions stored in one or more non-transitory computer-readable storage media (e.g., the memory 1920), which may serve as non-transitory computer-readable storage media storing processor-executable instructions for execution by the processor 1910.

[0232] The computer system 1900 may also include a network input / output (VO) interface 1940 via which the computing device may communicate with other computing devices (e.g., over a network), and may also include one or more user VO interfaces 1950, via which the computing device may provide output to and receive input from a user. The user VO interfaces may include devices such as a keyboard, a mouse, a microphone, a display device (e.g., a monitor or touch screen), speakers, a camera, and / or various other types of VO devices.

[0233] In this respect, it should be appreciated that one implementation of the embodiments described herein comprises at least one computer-readable storage medium (e.g., RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or other tangible, non-transitory computer-readable storage medium) encoded with a computer program (i.e., a plurality of executable instructions) that, when executed on one or more processors, performs the above-discussed functions of one or more embodiments. The computer-readable medium may be transportable such that the program stored thereon can be loaded onto any computing device to implement aspects of the techniques discussed herein. In addition, it should be appreciated that the reference to a computer program which, when executed, performs any of the above-discussed functions, is not limited to an application program running on a host computer. Rather, the terms computer program and software are used herein in a generic sense to reference any type of computer code (e.g., application software, firmware, microcode, or any other form of computer instruction)- 46 - #14554048v3Attorney Docket No.: H0776.70187WO00that can be employed to program one or more processors to implement aspects of the techniques discussed herein.

[0234] It will be apparent that example aspects, as described above, may be implemented in many different forms of software, firmware, and hardware in the implementations illustrated in the figures. Further, certain portions of the implementations may be implemented as a “module” that performs one or more functions. This module may include hardware, such as a processor, an application- specific integrated circuit (ASIC), or a field-programmable gate array (FPGA), or a combination of hardware and software.

[0235] The terms “program” or “software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects as described above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present disclosure need not reside on a single computer or processor but may be distributed in a modular fashion among a number of different computers or processors to implement various aspects of the present disclosure.

[0236] Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically, the functionality of the program modules may be combined or distributed as desired in various embodiments.

[0237] Also, data structures may be stored in computer-readable media in any suitable form. For simplicity of illustration, data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationship between the fields. However, any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationship between data elements.

[0238] When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

[0239] Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet- 47 - #14554048v3Attorney Docket No.: H0776.70187WO00computer, as non-limiting examples. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smartphone, a tablet, or any other suitable portable or fixed electronic device.

[0240] Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible formats.

[0241] Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, and intelligent network (IN) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks.EXAMPLE

[0242] In this Example, the role of loss errors in error-corrected circuits across a range of quantum hardware platforms was explored, including alkali and alkaline-earth-like neutral atoms, as well as superconducting qubits or trapped ions. Focus was on a scenario in which detection and correction of loss were delayed for several gate operations, and techniques were developed that leveraged this delayed information with minimal experimental overhead. In particular, a delayed-erasure decoder was developed to accurately interpret logical measurement results from the measured syndromes and loss detections, despite uncertainty in the exact moment of the loss error.

[0243] Using this delayed-erasure decoder, the impact of loss errors in logical circuits was investigated. The algorithmic structure influenced the optimal strategy to detect and correct loss, as summarized in FIGs. 4A-4B. Concretely, for high-depth circuits prior to logical measurement, hardware-efficient methods were developed to detect and replace lost qubits during syndrome extraction (SE) with minimal additional overhead. Circuit-level simulations were performed to compare modified circuit-based and measurement-based approaches which- 48 - #14554048v3Attorney Docket No.: H0776.70187WO00incorporate loss detection upon measurement, alongside other state-of-the-art approaches such as erasure conversion techniques. QEC performance may be improved by optimizing circuit design to leverage loss errors in cases where it constitutes a substantial fraction of the error budget. By analyzing biased errors, it was found that loss had a stronger impact on performance than bias, even with bias-preserving gates. Loss-detecting SE rounds were investigated to determine optimal interleaving between transversal gates in multi-qubit deep logical Clifford circuits.

[0244] Many algorithmic subroutines had short circuit depth before logical measurement, including magic state distillation, quantum arithmetic, and small-angle synthesis. In such circuits, it was found that because gate teleportation naturally detects and replaces lost qubits, no loss-detecting SE was needed. Through numerical simulations of a teleportation-based algorithm, it was found that as the frequency of gate teleportation increased, the performance approached that of frequent erasure conversion. These results provided a comparative analysis of experimental solutions for leveraging loss, and highlight that algorithmic structure plays a central role in how these factors impact performance.

[0245] Loss-to-erasure conversion has been explored at the memory level, using mid-circuit measurement in alkaline-earth-like atomic systems and superconducting qubits, as well as using leakage-reduction units with extra qubits and gates. More recently, loss-resolving readout was demonstrated experimentally in alkali atoms systems and dual-rail superconducting qubits and its implications for logical qubit performance were explored. The present example describes an end-to-end analysis of loss handling techniques, comparing all these approaches across a range of quantum computing platforms. This study extends beyond single logical qubits to examine the role of loss at every level of computation, from decoding strategies and QEC architectures to full logical algorithms. Different loss detection and correction methods were systematically compared, including their frequencies and associated space-time overheads. By focusing on logical algorithms, insights into how circuit structure influences the algorithmic performance were realized and improved strategies for circumventing loss errors were developed.

[0246] This example is organized as follows. DETECTING AND DECODING DELAYED ERASURES discusses the effect of qubit loss and its detection using state- selective readout, and the delayed-erasure decoder developed in this work. In TECHNIQUES FOR ADDRESSSING QUBIT LOSS IN DEEP CIRCUITS, different SE techniques were- 49 - #14554048v3Attorney Docket No.: H0776.70187WO00tailored, compared, and designed to handle loss with minimal overhead. THE EFFECT OF LOSS ERRORS IN DEEP LOGICAL ALGORITHMS DESIGN explores the optimal frequency of interleaving loss-detecting SE with transversal gates in deep logical Clifford circuits. In NATIVE LOSS DETECTION FROM LOGICAL TELEPORTATION, the prevalent use of teleportation in many algorithmic subroutines is highlighted and its effect with and without the delayed-erasure decoder on a toy model for the small-angle synthesis algorithm is evaluated. Conclusions are presented in CONCLUSION.DETECTING AND DECODING DELAYED ERASURES

[0247] General logical algorithms subject to loss errors were considered, in which loss is periodically detected using hardware- specific mechanisms. In alkali neutral atom systems or dual rail superconducting qubits, this can be done via state- selective readout (SSR), a projective measurement that distinguishes between |0), |1), and loss (|L)). As it occurs as part of the qubit measurement, it can be realized through various methods with minimal experimental overhead. In contrast, mid-circuit erasure conversion, demonstrated in alkaline-earth-like atoms and superconducting qubits, identifies loss or leakage events during circuit execution by monitoring auxiliary degrees of freedom without performing a full projective measurement. These detection mechanisms, combined with methods like teleportation-based protocols, feed into the syndrome extraction and decoding framework (see FIGs. 4A-4B).

[0248] Two closely related error types were differentiated. A loss error is defined as one in which a qubit leaves the computational subspace and becomes unavailable until detection and replacement, encompassing both loss and leakage (depending on hardware platform). An erasure error, by contrast, is a loss that was detected at the gate layer where it occurred and was immediately reinitialized; both the time and qubit index were known to the decoder.

[0249] Loss events led to correlated errors: in neutral-atom systems, a lost qubit cancelled subsequent gates, while its intended interaction partner may have experienced an effective single-qubit error; in superconducting platforms, a qubit interacting with a lost qubit suffered from depolarizing noise. In both cases, correlated errors may propagate within or across logical qubits during entangling operations (see FIGs. 4A-4B), and were handled carefully by the decoder. The present example adopted the gate-cancellation model for loss.

[0250] While in principle these errors can be corrected by detecting and replacing the lost qubits and treating them as erasure errors, unlike the erasure channels, where the moment in time of the loss error is precisely known, in a natural QEC cycle, the loss event is detected- 50 - #14554048v3Attorney Docket No.: H0776.70187WO00when the SSR or other loss detection mechanism is performed and can correspond to a number of different potential loss locations (FIG. 5), each resulting in a potentially different set of correlated errors. These loss detection events can be viewed as delayed erasure detections, and the information revealed by the detection mechanism can be leveraged by the appropriate decoder to improve logical performance.

[0251] As a result, loss events required two adjustments to the decoder: first, when a qubit was lost, its associated stabilizer checks were no longer valid. Therefore, they needed to be replaced with a so-called “supercheck”, a product of multiple stabilizer checks into a single check which was independent of the lost qubit. For example, consider a lost qubit that participated in neighboring stabilizers S₁ = Z₁Z₂Z₃Z₄ and S₂ = Z₄Z₅Z₆Z₇. The resulting supercheck operator was. S₁S₂ = Z₁Z₂Z₃Z₅Z₆Z₇, which was independent of the lost qubit q. Second, loss caused correlated errors, necessitating updates to the circuit error model to account for the likelihood of error propagation from the possible loss locations (see FIG. 15 A).

[0252] A delayed-erasure decoder was developed which included these two adjustments to effectively utilize imperfect information about the location of losses in time obtained from SSR. The qubit lifecycle was considered as a quantity in predicting the performance of different loss detection and correction methods, defined as the number of circuit locations where a given qubit can potentially be lost, starting at initialization and ending at measurement. Formalizing this approach, the goal was to construct a decoding hypergraph based on the observed loss, which captured how errors (hyperedges) triggered checks (vertices that compare consecutive stabilizer checks in time) and was the input to the decoder. The most-likely-error (MLE) decoding problem was solved, which identified the most likely configuration of Pauli and loss errors consistent with both the observed error syndromes and loss events (see Appendix Section B.l). However, a full MLE solution would require considering all combinations of loss locations, since loss-induced errors can produce non-Pauli, correlated error patterns, making them non-additive, as observed numerically.

[0253] Instead, the MLE solution was approximated by handling each loss event independently (see Appendix A for full details). For each loss event, the qubit’s lifecycle was traced back, accounting for all potential loss events and their associated probabilities. Each potential loss event corresponded to a loss circuit, in which certain gates were canceled due to the loss. Using Stim, a Clifford circuit simulator, the hyperedges and their probabilities were constructed for each loss circuit. Next, all hyperedges were integrated within a qubit’s lifecycle, reweighting- 51 - #14554048v3Attorney Docket No.: H0776.70187WO00them based on the probabilities of their corresponding potential loss locations. In cases of multiple losses, each loss event was calculated independently, and the results were combined to construct the final decoding hypergraph used by the decoder, calculated by:∑ᵢ Dᵢ = DPauli+ ω · Dfirst comb(1)t where Di is the decoding hypergraph for a lossy lifecycle i, £>pauii is the decoding hypergraph for Pauli errors generated from the lossless circuit, and Dfirst combis the decoding hypergraph built from the earliest potential loss in each lossy lifecycle i. The weighting parameter co tunes the contribution of first comb, and was set to co = 0 in the simulations (see Appendix A for details). Empirically, this heuristic achieved performance comparable to methods that consider combinations of loss events, while reducing computational overhead.

[0254] The updated decoding hypergraph may then be processed using a standard decoder appropriate for the QEC code in use. For example, one may use a MLE decoder, minimum weight perfect matching (MWPM) for topological codes, belief propagation with ordered statistics decoding (BP+OSD) for sparse codes, or machine learning-based decoders. Unlike previous approaches to decoding loss errors, the decoder described herein automatically adjusted the error model based on any general circuit and loss information, eliminating the need for hand-tuned models that may not easily generalize to complex logical algorithms or different SE methods. This work primarily used the MLE decoder, as it can decode generic stabilizer codes and logical algorithms. Results for the MWPM decoder are presented in Appendix D.

[0255] To benchmark the decoder, a surface-code logical memory with repeated SE rounds was used in which loss was detected only by SSR: losses on measurement qubits were detected each round, whereas losses on data qubits were detected only at the final projective readout. Unless otherwise noted, this Example considered loss and Pauli errors occurring during entangling operations, as this represented a dominant source of error in many quantum computing architectures. Details of the error model, along with results using alternative error models, can be found in Section S3 and Table I. As shown in FIG. 6, a delayed-erasure decoder that used only SSR information lowered the logical error rate by orders of magnitude relative to an MLE decoder that ignores loss information and remains comparable to a decoder with perfect loss time-location, even for deeper circuits with longer lifecycles.TECHNIQUES FOR ADDRESSING QUBIT LOSS IN DEEP CIRCUITS

[0256] In deep logical circuits prior to logical measurement, qubit lifecycles were extended, introducing many correlated errors and degrading performance. While the delayed-erasure - 52 - #14554048v3Attorney Docket No.: H0776.70187WO00decoder mitigated these effects, its effectiveness deteriorated when lifecycles became too long due to error accumulation. To maintain high performance, loss detection and qubit replacement were integrated into the QEC process. In this section, practical syndrome extraction (SE) methods that enable such replenishment with minimal overhead were explored. Focus was primarily on: (i) conventional SE, which resembles traditional circuit-based quantum computing (CBQC) with various modifications for delayed-erasure conversion utilizing SSR or erasure conversion capabilities, and (ii) teleportation-based SE, which resembles measurement-based quantum computing (MBQC). Additionally, a description of a modified Steane SE approach, which bridges conventional and teleportation-based SE but was not simulated here, is provided in Appendix C. These methods differ in their qubit overhead, gate operations, loss detection capabilities, and experimental requirements, as analyzed below.

[0257] It was found that the underlying circuits and resulting performance of the methods were similar, but not identical: all approaches successfully removed qubit loss and had trade-offs in logical error rates and qubit overheads depending on the specific ratios between loss and Pauli errors. Each SE approach was first detailed before analyzing numerical results in Comparison ofSE Methods. In Predicting Performance by Error Counting, these performance differences were compared to several metrics such as lifecycle length and number of entangling gates to predict performance based on the noise model for each SE method.Modified Conventional SE

[0258] The conventional SE method involves repeated stabilizer checks using physical measurement qubits. Data qubits are not directly measured or replaced when lost, and thus over time, logical performance can degrade in the presence of loss. Conventional SE was augmented by utilizing SSR and physical SWAP gates to detect losses on all qubits (SWAP SE). At the end of each SE round, a SWAP gate and physical SWAP movement were performed between data and measurement qubits. Conveniently, this approach did not require any additional entangling gates by applying gate cancellation identities (see FIG. 8). If the data qubit was not lost, the SWAP operations cancelled each other, such that the resulting measurement qubit stored the stabilizer outcome. Conversely, if the data qubit was lost, the loss was directly identified through the SSR measurement and automatically replaced. Thus, using this method, losses of all types of qubits were corrected, each cycled through both roles of data and measurement qubits, ensuring a uniform lifecycle length of ~ 8 for all qubits in the bulk even in deep circuits (see Section Sl.l).- 53 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0259] Each SWAP operation incurred a cost due to qubit movement, making it important to evaluate different SWAP periods to balance performance and experimental complexity. The SWAP period defined how often loss-detecting SE rounds were interspersed with conventional SE rounds, occurring at a fixed interval. A trade-off between the lifecycle lengths of data and measurement qubits was identified for different SWAP periods, demonstrating that a period of 2 may be competitive with a period of 1 (see FIGs. 34A-34B, 36, and 37). A period of 2 reduced experimental complexity while maintaining a similar average lifecycle length.Teleportation-Based SE

[0260] Teleportation-based SE uses repeated logical teleportation to fresh code blocks, inherently detecting loss via SSR at each step (see FIG. 10). In the present implementation, logical qubits were prepared in one initialization round and then entangled in the XZZX pattern, which was equivalent to the XZZX cluster state used in MBQC (See Section S1.5 for full details). While typically associated with MBQC, it may also be implemented in a circuit-based framework where gates are directly applied to qubits. Under the present error model with noise only on entangling gates, this construction yielded short lifecycles of length four for all physical qubits in the bulk. Among the SSR-based approaches considered, it achieved the shortest lifecycles without experimental operations beyond SSR, though at the cost of additional qubits. These features make it well-suited for neutral-atom architectures and particularly effective in loss-dominant regimes, as discussed in Sec. 3.4.Mid-Circuit Erasure Conversion SE Approaches

[0261] Mid-circuit erasure conversion offers an alternative to SSR-based detection by converting physical qubit loss into flagged erasure events during circuit execution (See FIG.13) This has been demonstrated in alkaline-earth-like atoms and superconducting qubits, using auxiliary fluorescence imaging, auxiliary qubits, or leakage monitors, followed by reset or transport. The resulting erasure is often delayed and requires active intervention, such as qubit replacement or reset, imposing experimental overhead in real-time implementations.

[0262] This is referred to as the direct conversion SE method, and multiple detectionreplacement schedules were explored: (i) detection and replacement after each gate layer or QEC round (periods 0.25,1), and (ii) detection after each gate but replacement only at the end of the round (period 1 + loss location information). Frequent detection improved decoder- 54 - #14554048v3Attorney Docket No.: H0776.70187WO00performance; frequent replacement reduced logical error by halting loss propagation, but might have extended circuit duration due to feed-forward control. This flexibility was a practical advantage of erasure conversion.Comparison of SE methods

[0263] The performance of these approaches was compared in the context of a surface code memory, using circuit-level simulations with varying loss fractions L = ploss / (ploss+ pPauli) where plossand pPauliare physical loss and Pauli error probabilities,7\Ploss Ppauli)respectively. The optimal SE approach was studied at different loss fractions and Pauli error biases (see Appendix D for detailed results with bias).

[0264] FIG. 20 compares the logical error rates of conventional SE without loss detection, approaches with loss detection — such as SWAP SE, teleportation-based SE, and direct conversion SE — and direct conversion SE with perfect loss information, in a single logical memory experiment at an experimentally-motivated loss fraction of 0.5, comparable to that observed in recent neutral atom experiments. For a small number of SE rounds (< 10), all protocols behaved similarly. However, as the number of SE rounds increased, loss detection and the replacement of lost qubits enhanced performance, providing a convenient approach to achieving high circuit depths without additional experimental gate overhead.

[0265] FIG. 21 A shows the threshold of each SE method as a function of the loss fraction. The threshold was determined by calculating the logical error rate for different code distances d, using a noiseless initialization, followed by d - 1 rounds of noisy stabilizer checks and a final noiseless transversal measurement. It was found that the thresholds of all methods improved with increasing loss fraction. Methods with shorter lifecycles, such as teleportation-based SE, benefit more from increasing loss fraction. In the Predicting Performance by Error Counting, further insight is provided into the thresholds of each SE method by linking it to simple characterizations such as qubit lifecycles.

[0266] FIG. 2 IB presents the effective code distance of each SE method as a function of the loss fraction, for distance d = 7. The effective distance d refers to the number of errors required to cause a logical failure, as the logical error rate scales as (^ / pth)efar below the threshold pth, where p is the physical error rate. For Pauli noise, de= (d+1) / 2 and for erasure noise de= d. To determine defor each loss fraction, the logical error rate data were fit below the - 55 - #14554048v3Attorney Docket No.: H0776.70187WO00threshold to the function apβ, where a and P are fitting parameters (see FIGs. 52A-52F). All SE methods, while utilizing the delayed-erasure decoder, experienced increased effective distance with an increased loss fraction. For loss errors only, teleportation-based SE and direct conversion SE methods (periods 0.25 and 1) achieved an effective distance of de~ d, while SWAP SE achieved de~ d - 1, likely due to longer lifecycles. Additional threshold and effective distance results under an alternative error model are presented in Table I.

[0267] To account for the qubit overhead required in different SE methods, the space-time overhead for performing d SE rounds of each method was evaluated in FIG. 21C. Space-time overhead was defined as the product of the total number of physical qubits and the circuit depth required for the computation. This metric provided a platform-independent measure of logical performance. However, it did not include experimental considerations such as real-time qubit transport, additional laser resources, or mid-circuit measurement overhead. These factors may affect implementation and are discussed qualitatively in Sections 3.1-3.3. For a given physical error rate of 0.5%, the required code distance to achieve a logical error rate of 10“12was determined by fitting the logical error as a function of distance for d = 3, 5, 7, 9. The spacetime overhead of each approach was presented as a function of the loss fraction, highlighting the overhead reduction as the loss fraction increased for all SE approaches. These results highlight that although teleportation-based SE required more qubits, its better error suppression when the loss fraction was high led to a more favorable space-time volume compared to SWAP SE (see space-time overhead for each SE method in Table I).

[0268] At the experimentally relevant loss fraction of ~ 0.5, seen in multiple different hardware systems such as neutral atoms and ions, the thresholds of the different methods ranged from 1.5% to 2.5%, and all SE methods achieved similar effective distances. However, their experimental feasibility differed. Direct conversion SE required erasure conversion with mid-circuit detection and real-time replacement of lost qubits, often demanding extra lasers and fast feedback. By contrast, SSR-based approaches such as SWAP or teleportation SE avoided these requirements. Thus, while all methods benefit from accurate loss detection, the choice may depend on hardware- specific capabilities and constraints.

[0269] Another aspect of neutral atom qubits was their intrinsic bias, as Z-type Pauli errors were much more common than X-type Pauli errors. In Appendix D, the interplay between biased errors and delayed erasure errors was investigated across multiple SE methods, employing the XZZX surface code and the XZZX cluster state for teleportation-based SE. This- 56 - #14554048v3Attorney Docket No.: H0776.70187WO00analysis considered scenarios both with and without bias-preserving gates, as well as the presence of biased erasure noise. Bias-preserving gates, such as native CX gates, preserved the bias of the errors, in contrast to CX gates decomposed into CZ and H gates. Biased erasure noise occurred when a qubit exited the computational subspace exclusively from the state |1). As a result, the replaced qubit followed a biased error channel instead of a depolarizing error channel. Additionally, scenarios where Pauli errors were biased were investigated, examining the two-dimensional space defined by the bias ratio and the loss fraction. Thresholds were calculated at each point in this space for various SE methods (see FIGs. 27-33). One observation emerged across all SE methods: increasing the loss fraction had a greater impact on thresholds than increasing the bias ratio, even when using bias-preserving gates and biased-erasure. This difference in impact between the loss fraction and the bias ratio was even more pronounced in the absence of bias-preserving gates.Predicting Performance By Error Counting

[0270] A unified model for analyzing SE methods was introduced by linking performance to simple characterizations such as lifecycle length and the number of entangling gates. FIG. 22A shows the thresholds in the parameter space of loss and Pauli error rates for various SE methods. Thresholds were plotted in terms of the loss error rate and Pauli error rate, with the region below each curve representing the range of correctable errors. A good fit to a linear model (solid lines) was numerically determined based on finite- size data, given by ploss= ploss,th− (ploss,th / pPauli,th) · pPauliwhere ploss,thand pPauli,thare the respective thresholds for loss and Pauli errors only. The linear behavior suggested that the threshold depended on the loss fraction L according to the relationship pthreshold=Pioss, thPpauii, th / (^(ppauii,th Pioss, th 3” Pioss, th) and was qualitatively similar to previously reported behavior.

[0271] The curve intersections with the axes provided several insights. The y-axis intersection, representing the threshold in the absence of Pauli errors, was related to the lifecycle length. For the direct conversion SE period 1 with perfect loss information, the threshold was ploss,th~ 7.2%. Increasing the lifecycle reduced the threshold, which decayed with the lifecycle length, as shown in FIG. 22B (see Section S1.7 for further details). The SWAP SE, with an average lifecycle length of 8, had a lower threshold of ploss,th~ 2.3%, deviating from the heuristic. This lower performance was attributed to additional factors unique to SWAP SE, such as the - 57 - #14554048v3Attorney Docket No.: H0776.70187WO00loss of stabilizer information when the swapped in data qubit was lost and the fact that measurement qubit loss was only detected in the following round, after it propagated as a data qubit loss, as discussed in Modified Conventional SE.

[0272] The x-axis intersection, representing Pauli error thresholds, correlated with the number of entangling gates, which impacted the number of Pauli errors in the final state. For example, over d SE rounds, teleportation-based SE uses 1.5x more entangling gates than SWAP SE and direct conversion SE approaches, resulting in a proportional decrease in the Pauli error threshold.THE EFFECT OF LOSS ERRORS IN DEEP LOGICAL ALGORITHMS DESIGN

[0273] Loss errors in logical algorithms may have different effects compared to standard memory benchmarks. The present Example explores the effects of loss errors on the QEC design of multi-qubit deep logical algorithms. Specifically, how physical loss errors detection influenced the optimal frequency of SE rounds between transversal gates was analyzed. This analysis revealed that SWAP-based SE achieved comparable SE frequencies in both the presence and absence of loss.

[0274] Focus was on the effects of loss in random Clifford logical algorithms (FIG. 23A), where multiple logical qubits interacted through transversal gates interspersed with periodic SE rounds at tunable frequencies. Circuit-level simulations were performed for logical circuits comprising 24 layers of logical CX and single-qubit logical gates (X, Y, Z), with SE rounds applied at varying intervals. Two scenarios were analyzed: conventional SE without explicit loss detection, which detected only measurement qubit loss in each SE round (FIG. 23B), and SWAP-based SE (FIG. 23C). The x-axis represents the number of SE rounds per gate layer, ranging from no SE (nr= 1 / 24) to multiple SE rounds after every gate layer (nr= 3).

[0275] In the absence of SWAP operations (but still leveraging SSR detection and delayed-erasure decoding), several distinct error correction regimes were observed. For a small number of SE rounds per gate, loss improved the logical error rate due to short qubit lifecycles. However, as the number of SE rounds per gate increased, performance degraded due to the cumulative effects of loss over longer lifecycles. By contrast, incorporating SWAP-based SE, loss consistently enhanced error correction performance. Loss detection via SWAP stabilizer checks restored the previous SE rounds per CX. Consequently, when employing SWAP SE and SSR, the presence of loss did not alter the heuristic conclusions made for logical algorithms dominated by Pauli errors and can, in fact, improved overall performance.- 58 - #14554048v3Attorney Docket No.: H0776.70187WO00NATIVE LOSS DETECTION FROM LOGICAL TELEPORTATION

[0276] While there are techniques for handling algorithmic structures with long qubit lifecycles, it was observed that in many cases, qubit lifecycles were short in realistic logical algorithms. In particular, teleportation was a powerful technique for loss detection and correction that avoided additional overhead, and it naturally emerged within logical algorithms through gate teleportation (see FIG. 24A). Specifically, the SWAP-teleported gates exchanged the logical data qubit with a teleported logical qubit that implemented the desired gate, detecting loss using SSR and terminating the qubit lifecycles without the need for additional SE rounds.

[0277] This approach was further enhanced by correlated decoding and algorithmic fault tolerance, which capitalized on the use of transversal gates and teleportation in universal quantum computation. These ensured that lifecycles were inherently short in many logical algorithms, simplifying loss management while enabling regular qubit replacement.

[0278] One observation was that a wide range of known logical subroutines naturally employed teleportation, inherently keeping qubit lifecycles short. FIG. 24B illustrates the average number of SE rounds per physical qubit, from initialization to measurement, across various essential subroutines. The results show that most algorithms had relatively brief lifecycles. Detailed descriptions of these algorithms are provided in Section S2. For this analysis, one SE round per logical operation was conservatively assumed. However, as shown in FIG. 23C, this number may be further reduced. Additionally, FIG. 20 and FIGs. 54A-54F reveal that, at an experimentally-motivated loss fraction of 0.5, for fewer than 10 SE rounds, performance remained nearly unchanged without any active loss correction added to the SE rounds, relying solely on SSR and delayed-erasure decoding. These findings suggested that while memory benchmarks provide useful performance metrics, transversal logical algorithms are inherently well-equipped to manage loss, with minimal to no loss detecting SE. Leveraging SSR and delayed-erasure decoding may enhance the performance of the logical algorithm without incurring additional experimental complexity.

[0279] As a proof of concept, the teleportation-based logical circuit shown in FIG. 25A was considered, which mirrors the structure of the small-angle synthesis algorithm. This algorithm constructed small-angle rotations through sequences of H and T gates, with the latter often realized via teleportation. Consequently, loss detection and correction were integrated into the process of executing the logical algorithm. The logical error rates for the circuit in FIG. 25A- 59 - #14554048v3Attorney Docket No.: H0776.70187WO00are plotted in FIG. 25B as a function of the loss fraction using various decoders: a delayed-erasure decoder leveraging SSR, a regular MLE decoder, and an MLE decoder with perfect loss time-location information. The delayed-erasure decoder demonstrated significant performance improvements, with algorithmic logical error rates rapidly decreasing as the loss fraction increased, achieving the performance of the decoder with perfect loss information. Furthermore, for loss fractions less than 1, it achieved the lower bound set by the erasure channel — corresponding to loss detection and qubit replacement after every gate. This circuit was similar to the teleportation-based SE method investigated here in the memory setting, both utilizing SSR and replacing atoms frequently through teleportation without additional overhead. These results highlight the advantages of exploiting native loss detection within teleportation gadgets in logical circuits while also utilizing loss information to improve decoding. Finally, while these simulations focused on Clifford gate teleportation, they may extend to non-Clifford gates, as the underlying loss detection principles remain consistent. CONCLUSION

[0280] These results provide a general framework for managing qubit loss or leakage errors across diverse quantum computing platforms, primarily neutral atoms but also including superconducting qubits and trapped ions, and highlight the impact of loss detection and bias on logical algorithm performance. This analysis across a wide range of loss fractions and detection strategies revealed how loss detection and decoding may be leveraged in a number of regimes, and was already employed in the recent experimental studies of architectural mechanisms for universal fault-tolerant quantum computing using neutral atom arrays.

[0281] Central to this approach is the use of the delayed-erasure decoder, which leverages loss information to approximate an MLE decoding solution, substantially improving the logical error rate. Using the decoder, algorithmic structure was examined for how it influences the optimal strategy for detecting and correcting loss. For high-depth circuits involving a large number of gate layers prior to logical measurement, the performance depended on both loss decoding and frequent loss detection and replacement. Using a surface code logical memory, different SE methods were explored under various loss fractions. These findings indicated that, with appropriate decoding strategies, all methods enhanced performance with increasing loss fraction. Teleportation-based SE may be used for neutral atom quantum computing, as it leveraged SSR to achieve comparably high thresholds for high loss fractions, albeit with an- 60 - #14554048v3Attorney Docket No.: H0776.70187WO00additional space overhead. Determining the SE method for a given system may depend on experimental validation and the specific noise characteristics of the hardware.

[0282] By applying these results to multi-qubit deep logical algorithms, several insights emerged. Loss errors, when managed using loss detection operations and SSR detection, were fully compatible with correlated decoding, allowing for a number of approximately four logical operations per SE round using the delayed-erasure MLE decoder. This framework showed effective for error correction even in the presence of high loss rates.

[0283] By considering subroutines involving extensive logical teleportation, it was found that the use of transversal gates and correlated decoding kept the number of SE rounds sufficiently small, such that loss was natively detected and managed by the gate teleportation intrinsic to universal processing. Examining a toy model of a small-angle synthesis algorithm, it was observed that loss errors, decoded using the delayed erasure decoder, enhanced performance compared to Pauli channels solely through logical teleportation. As such, while the logical memory benchmark provided valuable insights into various strategies for loss management and detection to enhance performance, behavior may change when realizing logical algorithms.

[0284] Finally, although the simulations described herein focused on the surface code, the core techniques presented in this work are broadly applicable to a wide range of QEC codes and logical algorithms. In particular, the delayed-erasure decoder was agnostic to the underlying code and may be applied to any stabilizer code with a suitable decoding backend. Moreover, several loss-handling strategies explored in this Example, such as erasure conversion and teleportation-based syndrome extraction, were compatible with a wide class of codes, including high-rate qLDPC codes.Appendix A: Delayed-Erasure Decoder

[0285] In this section, the influence of the weight of the combination, co, on the efficacy of the delayed erasure decoder, which considers both independent error events and the first combination of potential loss events, was explored. As described earlier, the decoder’s decision-making process involved summing different decoding hypergraphs (see Eq. B5). To incorporate the impact of individual loss events, the first loss combination event was scaled by co along with the standard Pauli error decoding hypergraph. To benchmark the performance of the decoder and determine the value of co, circuit-level simulations were performed on a memory logical qubit with multiple rounds of conventional syndrome extraction (SE). co was- 61 - #14554048v3Attorney Docket No.: H0776.70187WO00varied between 0 and 1. For co = 0, each lifecycle’s decoding hypergraph was considered independently, without including an additional decoding hypergraph for the first combination.

[0286] The results for the conventional SE method are presented in FIGs. 26A-26B. Non-zero values of co degraded the decoder’s performance. However, these results pertained to the conventional SE method, and different SE methods employing distinct gate sets may behave differently. For simplicity, the numerical simulations presented in this Example assume co = 0.Appendix B: Comparing SE Methods Lifecycles and Space-time Overheads

[0287] This Example considered multiple approaches for detecting loss and converting to delayed-erasure errors. Methods based on mid-circuit loss detection, known as erasure conversion in different frequencies (every gate, few gates, rounds), named direct conversion SE were considered. Furthermore, methods based solely on SSR, which require adjusting the SE approach to utilize teleportation, such as SWAP SE, and teleportation-based SE were also considered. Another SE approach that may be modified to utilize teleportation was the Steane SE, which was named the modified Steane SE and described herein. This approach offered extra flexibility and bridged the gap between the SWAP SE and teleportation-based SE. Table I summarizes the average lifecycles, error thresholds, and space-time overheads for each SE method considered numerically in this Example. Results for various error models, considering independent loss channels or correlated loss between the qubits performing an entangling gate are shown.Direct Direct SWAPDirect Direct conversion SE period conversion SE Category Conventional SE Conversion SE TeleportationSE period conversion SE 1 period period 2 based SE1 period 1 + exact loss 0.25 + exact loss information information Averagelifecycle length 1 (detection) / 1 (detection) / 4d 8 8 4 4 4 1 of (replacement) (replacement) data qubitsAveragelifecycle length 1 (detection) / 1 (detection) / of 4 8 4 4 4 4 1 measurement (replacement) (replacement) qubits~ 2d2~ 2d2- 1 ~ 2d2- 1 ~3d2- 1 ~ 2d2- 1 ~ 2d2- 1 ~ 2d2- 1 Space overhead - 1Time overhead ~4d ~4d ~4d ~ 6d ~4d - 1 ~4d - 1 ~4d - 1 Erasure Erasure Erasure Erasure Extra conversion, conversion, conversion, detection conversion, experimental None SSR detection and SSR detection and every gate, and detection and requirements replacement every 2 replacement every replacement every SE replacement every SE rounds SE round round gate Threshold for L2.27 ±= 1 [%] NA 3.98 ±0.06 4.78 ±0.01 5.07 ±0.02 7.16 ±0.01 9.51 ±0.04 0.02(Channel 1)- 62 - #14554048v3Attorney Docket No.: H0776.70187WO00Effectivedistance for d = 6.41 ±NA 6.77 ±0.2 7.19 ±0.45 6.83 ±0.37 6.97 ± 0.24 7.46 ± 0.36 7 0.27(Channel 1)Threshold for L1.94 ±= 1 [%] NA 2.75 ±0.07 3.5 ±0.05 3.76 ±0.01 5.12 ±0.01 6.5 ±0.01 0.01(Channel 2)Effectivedistance for d = 6.13 ±NA 5.5 ±0.23 6.5 ±0.21 6.32 ±0.87 6.45 ± 0.47 7.47 ± 0.49 7 0.26(Channel 2)TABLE I. Comparison of SE methods under various error models. Each column represents a method, and each row describes a property such as average qubit lifecycles, thresholds, effective distance and overheads. The final column estimates performance under very frequent detection and replacement, providing the erasure channel bound. Channel definitions for L = 1 are as follows. Channel 1: p’ L ® I, I ® L. Channel 2: p’2 L ® Z, Z ® L, L ® I, I ® L. p’ = 1-1 - p ~ p2 where p is the entangling gate physical error rate.Appendix C: Modified Steane SE

[0288] Steane SE used transversal CX gates applied to fault-tolerant logical measurement qubits to extract syndromes and detect errors. Transversal gates, which applied the same operation across corresponding physical qubits in each code block, ensured that errors propagated predictably from logical data qubits to logical measurement qubits. If the measurement qubits were prepared fault-tolerantly with d SE rounds, one round of Steane SE sufficed to accurately capture the syndromes in a given basis. However, conventional Steane SE lacks a native mechanism for detecting loss, as losses on data qubits are not detected by the logical measurement qubits and remain hidden until the end. The conventional Steane SE approach was modified by incorporating logical SWAP operations (SWAP gate and SWAP movement), as illustrated in FIG. 13, thereby enabling loss detection through SSR at each logical measurement. This approach leveraged the teleportation of logical information and resembled Knill SE.

[0289] The modified Steane SE can be thought of as an interpolation between modified conventional SE and teleportation-based SE. In the limit of multiple logical measurement qubits, each prepared with one SE round, the modified Steane SE was equivalent to teleportation-based SE (see Section S1.6). Conversely, multiple rounds of SE may be used to prepare a higher-quality logical measurement qubit, providing flexibility to adapt to various error models and resource constraints. Steane SE also supported pre-selection of measurement - 63 - #14554048v3Attorney Docket No.: H0776.70187WO00qubit blocks based on quality, potentially increasing fidelity without significant overhead. To provide a comprehensive perspective on SE techniques, Steane SE was included in this work despite not numerically analyzing herein.Appendix D: The interplay between loss, erasure and biased errors1. The interplay between erasure and biased errors

[0290] The effect of bias and erasure and the interplay between them on the logical memory level was explored. The direct conversion SE with period 0.25 (erasure channel), and the error model presented in Section S3.1 was used, performing circuit-level simulations on the XZZX surface code for various values of bias under bias-preserving gates and biased erasure. The data were decoded with the delayed-erasure decoder combined with a MWPM decoder. The delayed-erasure decoder provided an adjusted decoding hypergraph for each shot given the heralded loss pattern. The full results are presented in FIGs. 27-32. Three cases were considered: (a) with bias-preserving gates and erasure is biased, (b) with bias-preserving gate and erasure is not biased, and (c) without bias preserving gates and erasure is not biased. Below the plot, tables with the exact numerical thresholds values are provided. As illustrated in the plots, increasing the erasure ratio affected the thresholds much more than increasing the bias fraction, even for the cases with bias preserving gates. Moreover, without bias preserving gates, the effect of bias was minimized, providing a factor of two in the threshold for infinite bias (only Z errors).2. The interplay between loss and biased errors

[0291] The present section describes simulations with loss in the presence of biased Pauli errors. The error model presented in Section S3.1 was used and the bias and loss fractions were varied, and the threshold for each set of parameters was calculated.

[0292] For the teleportation-based SE, a previously reported XZZX cluster state was used, however, without biased- preserving gates. For the direct conversion SE with period 1, the surface code was used, again, without bias-preserving gates. At this limit, it was confirmed that the regular surface code was equivalent to the XZZX surface code in terms of behavior under biased noise. Circuit-level simulations were performed to estimate the thresholds of each SE method under both loss and biased Pauli errors. The data were decoded with the delayed-- 64 - #14554048v3Attorney Docket No.: H0776.70187WO00erasure decoder combined with an MLE decoder. The results are presented in FIGs. 33A-33B. As observed in the erasure and bias plots above, bias did not improve the threshold by approximately a factor of 2 in the limit of infinite bias. Additionally, increasing loss affected the thresholds more than increasing bias fraction.SI Syndrome extraction (SE) methods with loss detection

[0293] As explained above, there were multiple approaches to obtaining syndrome measurements and performing QEC, each with its own advantages and disadvantages. Specifically, each method provided different lifecycle lengths and required varying levels of overhead. Additionally, each method demanded different experimental capabilities. Here, further information on each method is provided, along with the assumptions made in this Example to simulate and compare all methods.51.1 Loss detection using physical SWAP SE

[0294] This section explored the physical SWAP method for loss detection and correction during rounds of stabilizer measurements. This method combined stabilizer measurements with loss detection by leveraging the ability to SWAP the locations and quantum information of data and measurement qubits during each round. By using SSR, it exploited all three outcomes (|0), 11 ), or lost (|L» to infer both the stabilizer measurement and the loss status of the data qubits.51.1.1 Optimizing SWAP period

[0295] Each SWAP operation incurred a cost, such as idling errors due to movement. Evaluating different SWAP periods was used to identifying the optimal frequency that minimized the number of SWAP operations required in practical settings. Generally, increasing the SWAP period extended the operational lifetime of each qubit. Both SWAP periods of 1 and 2 had the same average qubit lifecycle, as illustrated in FIGs. 34A-34B and 35. In brief, with a period of 1, both the data and measurement qubits had an average lifecycle of ~ 8, as they were replaced in every round. Conversely, with a period of 2, the data qubits had an average lifecycle of 12 because they were not always subject to loss detection in every round. Meanwhile, during conventional SE rounds, the measurement qubits had an average lifecycle of just ~ 4, as they were not converted to data qubits. This made a period of 2 competitive with a period of 1 in terms of loss detection while reducing complexity.- 65 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0296] Movement error costs were incorporated into the SWAP logical memory circuit-level simulations to determine the optimal SWAP period for varying loss fractions and physical error rates. According to the data presented in FIGs. 36 and 37, the optimal SWAP period depended on the specific error model, enabling reduced experimental demands by selecting the most efficient configuration.SI. 1.2 Details of implementation

[0297] The strength of the physical SWAP method lay in its ability to detect data qubit loss and replace it with a fresh measurement qubit. However, several challenges were considered:• SWAP Pairs: SWAP pairs were organized based on the final gate executed in each round, with 0(d) qubits along the lattice edge remaining unpaired. To address this without introducing additional qubits and to ensure every qubit in the lattice was paired, the gate order between even and odd SWAP rounds was alternated.• Movement Errors: During the execution of SWAP rounds, the physical movement of qubits introduced an opportunity for error. These errors, termed ’movement errors’, arose due to idle errors that occurred during the qubit’ s idle time. Idle errors were characterized by the error rate pidle =(Px,p Pz)f°r each axis of the Bloch sphere. A movement taking time T and occurring in time slot r added an error to the data qubit as follows:Pmovement error 1 - (1 - pidle)T / r(S1)This error represented the aggregate effect of idle errors over the duration of the movement and was assumed to apply uniformly across all qubits.S1.2 Comparing SWAP SE and conventional SE

[0298] SWAP-based syndrome extraction (SE) enabled loss detection during each round, but it had certain disadvantages, as described earlier, primarily the sacrifice of syndrome information and the limitation of detecting loss on only one type of qubit at a time. For small circuits with short lifecycle lengths, it was advantageous to avoid SWAP operations altogether.

[0299] FIGs. 37 and 39 showcase the average lifecycle for data qubits and measurement qubits, for different SE methods. Data qubits’ lifecycles in the conventional SE approach increased rapidly as the number of noisy SE rounds grew, whereas they remained constant for the SWAPbased SE. The conventional approach kept the measurement qubits’ lifecycles short at the - 66 - #14554048v3Attorney Docket No.: H0776.70187WO00expense of the data qubits’ lifecycles. In contrast, the SWAP-based SE approach maintained constant lifecycles for both.

[0300] Both methods were compared in numerical circuit-level simulations, as shown in FIGs.37 and 39. Both SE methods utilized the delayed-erasure decoder developed in this work, with the first SE round assumed to be noiseless. For a small number of rounds, the conventional SE method outperformed SWAP-based loss detection. The number of noisy SE rounds k ~ 6 at which the logical error rates intersected did not depend on the code distance.

[0301] The numerical circuit-level simulation results were then connected with the lifecycle plots to explain why, in the limit of a small number of SE rounds, it was preferable to perform conventional SE.51.3 Loss Detection Using Erasure Conversion

[0302] Another method considered in this Example was the use of erasure conversion, applied after every gate or after every round. In this approach, the experiment was assumed to be capable of detecting loss errors without requiring additional gates or qubits, but instead using other experimental capabilities, as demonstrated for Yb atoms and superconducting qubits. This method required mid-circuit measurement and the replacement of lost qubits, which introduced costs that depended on the details of the physical implementation.

[0303] To simplify the analysis, a case of this direct conversion approach was simulated, where the decoder gained access to loss information and replaced all lost qubits. Different detection and replacement periods were explored, ranging from 0.25 (detection and replacement after every gate) to k > 1 (detection after every k SE rounds). This simulation provided an upper bound on the threshold and effective distance that may be achieved using mid-circuit erasure conversion methods.51.4 Loss detection using Steane QEC

[0304] In Steane QEC, the syndrome was extracted using transversal CX gates that coupled data qubits with encoded logical measurement qubit blocks. Each measurement qubit block was prepared in a fault-tolerant (FT) logical state corresponding to the stabilizer being measured (X) or (Z). The transversal nature of the gates ensured that errors on individual physical qubits did not propagate catastrophically, maintaining fault tolerance. After- 67 - #14554048v3Attorney Docket No.: H0776.70187WO00interacting with the data qubits, the logical measurement qubits were measured, yielding the syndromes that indicated errors on the data.

[0305] However, in this approach, there was no mechanism for native loss detection on the data qubits, as loss events remained hidden until the data qubits were directly measured at the end of the algorithm. This limited the system’s ability to manage loss dynamically during computation.

[0306] To address this limitation, Steane SE was adapted by introducing logical SWAP operations inspired by physical SWAPs used in the SWAP SE scheme. These logical SWAPs allowed the logical data qubits to exchange their information with logical measurement qubits at each transversal CX gate. This effectively teleported the logical data qubits at every syndrome extraction step, similar to the process in, ensuring that no physical qubit retained a long lifecycle. Frequent loss detection was achieved through SSR at each transversal measurement step, enabling the system to manage loss dynamically.

[0307] This modified Steane SE scheme combined the benefits of teleportation-based techniques with the simplicity of transversal operations, minimizing qubit lifecycles while integrating loss detection into the syndrome extraction process.

[0308] An advantage of Steane SE compared to the other methods studied herein was the ability to pre-select on the quality of the measurement qubits logical qubits. To gauge the quality of the prepared measurement qubits blocks, one may employ the logical gap method for pre-selection. This method involved using the syndrome information collected during the preparation of the measurement qubits blocks to calculate the difference between the probability of the proposed error and the probability of the proposed error conditioned on applying the logical operator. A large (small) gap indicated that the decoder was confident (not confident) in its correction. One may apply a cutoff on the calculated gap and only keep the measurement qubits blocks with gap above this threshold.S1.5 Loss detection using teleportation-based SE

[0309] The teleportation-based SE method explored in this Example is described herein, using teleportation of all qubits in every step to both measure stabilizers and detect loss.Sl.5.1 Implementing the RHG cluster state - surface code teleportation-based SE- 68 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0310] Here, the implementation of the teleportation-based SE architecture, using the foliated surface code, also known as the RHG cluster state is described. To build the cluster state, all gates were CZ gates, and qubits were initialized in |+), except for the first layer, which encoded the logical qubit according to regular surface code encoding. The results provided herein were for the XZZX cluster state, which in the case of non-biased-preserving gates, reproduced the RHG cluster state.

[0311] FIGs. 40 and 41 show the complete construction, with a detailed example for distance d = 3 surface code. The figures also illustrate how the logical operators Xi, and ZL propagated on the cluster, demonstrating both even and odd distance cases. Since each layer detected only X or Z errors, 2d layers for all threshold and effective distance plots presented in this Example were simulated. This approach resulted in a space-time overhead: a d x d x d comprising d ■ (2d2+ d2— 1) = d ■ (3d2— 1) physical qubits. As in other SE methods simulations, the first and last layers to be noiseless were considered.51.6 Connecting Steane SE with logical SWAP to teleportation-based SE

[0312] Steane SE with logical SWAP corrected loss in a manner similar to teleportation-based SE by using teleportation to detect and manage loss errors.

[0313] In the limit where Steane SE utilized multiple logical measurement qubits, each one executing only a single SE cycle for preparation, it became equivalent to teleportation-based SE in terms of loss correction (see FIGs. 42A-43B). However, Steane SE offered flexibility by supporting multiple sub-layers within each logical layer (for logical measurement qubit preparation), enabling efficient use of logical measurement qubits. This flexibility allowed Steane SE to achieve high performance with fewer logical layers compared to teleportationbased SE.51.7 Thresholds as a function of lifecycle length

[0314] In FIG. 22B, the thresholds of multiple SE methods are presented as a function of lifecycle length. Fitting these points — excluding SWAP SE — to both an exponential and a polynomial curve yielded the numerical result that the decay follows a polynomial scaling. Specifically, a decay of 7 / (lifecycle length)1 / 3 / 3>) was numerically observed.S2 Algorithmic procedures- 69 - #14554048v3Attorney Docket No.: H0776.70187WO00

[0315] The approach used to count the average and maximum lifecycle for each algorithmic procedure is presented in FIGs. 44-48 and described herein. For each algorithm, the number of noisy SE rounds per logical qubit, from initialization to SSR was counted. Non-Clifford gates were assumed to be implemented through a teleported gate, increasing the lifecycle but also allowing for natural loss detection and end of the lifecycle for one of the data logical qubits in the teleported gate circuit.

[0316] Inspired by previously reported results and the numerical results presented herein, a single round of QEC for state preparation and a single round after every gate was considered. Therefore, in the following, the number of logical CX gates per logical qubit was counted: 1. GHZ: the logarithmic depth implementation, presented in FIG. 45 was used. For n qubits, the average number of CX gates per qubit was approximately log n / 2 and the maximum was [logn],2. Magic state distillation: For each input qubit, there were 3 or 4 entangling gates before the logical T gate, which added another entangling gate and ended the lifecycle of this input qubit. The T gate was performed through a teleportation process, which measured out the input qubits, leaving them with 4 or 5 entangling gates in total from initialization to measurement. The output qubit passed through 3 CX gates before being transferred to the next layer of distillation, where it was teleported inside and measured. Therefore, the average number of CX gates per qubit was 4. It was concluded that for this specific implementation and the counting of lifecycle lengths according to the number of entangling Clifford operations, the average lifecycle length was 4, and the maximum was 5, for any number of layers.3. HT decomposition algorithm (small-angle synthesis algorithm): As seen from the circuit in FIG. 47, each qubit was measured short time after initialization, with a very short lifecycle. An input magic state had only 2 entangling (transversal) gates before measurement. Assuming it was an output of a magic state distillation algorithm, the average lifecycle length was 7, and the maximum was 8.4. Adder: Here, the counting was different for each logical qubit in each row. Counting the number of entangling gates, based on T gate teleportation without SWAP, provided an average of 9 for the limit of multiple logical qubits, with a maximum of 13. More details: for the top 3 qubits, the calculated lifecycle lengths were: 6,6,11. For the bottom 2: it was 1 and 2. For the middle logical qubits in the limit of multiple qubits in the algorithm, it was 8, 7, 13.- 70 - #14554048v3Attorney Docket No.: H0776.70187WO00S3 Numerical SimulationsS3.1 Error models and parameters

[0317] The meta parameters considered in this work were first outlined and set by the experimental system.• Bias-Preserving Gates: This parameter may be true or false. It depended on the system’s approach to executing 2-qubit gates. Gates that maintained error types (Z errors remain Z errors) were considered bias preserving. While bosonic systems have shown this ability, atom-based systems relying solely on CZ gates without direct CX execution lacked this capability.• Loss is Bias: This may be true or false, depending on the primary causes of loss. For instance, in neutral-atom systems where losses predominantly occur in the 11 ) state, loss was considered biased. This implied that replacing a lost qubit with a fresh |1) qubit may primarily result in Z errors, indicating a bias in the error channel.• Architecture: Differentiated between measurement-based and circuit-based quantum computation.• Period of Loss Detection Rounds: Integer, varied based on the chosen loss detection approach.• Cost of Loss Detection Rounds: Dependent on the selected loss detection strategy.• QEC Code: Any CSS code was considered, with particular emphasis on the results for the regular and the XZZX surface code.• State-Selective-Readout (SSR): Indicated whether the system was capable of resolving loss during measurement to produce three outcomes: |0), |1), and |L).

[0318] Next, the error model was outlined, considering both loss and bias Pauli errors. In this Example, errors during a 2-qubit gates were primarily considered. An error occurred with probability pcz(this was the error parameter cited in different plots in this work). Multiple- 71 - #14554048v3Attorney Docket No.: H0776.70187WO00error models were simulated - with correlations between losses to Pauli, losses between the 2 qubits in the gates, and more. The following error models were considered:• Loss-biased Pauli channel correlations on each qubit: Each qubit had an independent error channel with probability p = 1 — ^ / l — pcz, ensuring channel normalization. There were two parameters: bias and loss fraction, thus, it can be represented on a sphere with unit radius, as illustrated in FIG. 49. The Z axis represented loss errors, which took the qubit out of the computational subspace. The XY plane was the domain of Pauli errors, which remained within the computational basis. Pauli errors may range from uniform (depolarizing errors) to single-channel (highly biased). The spectrum of partially biased errors was defined by the angle (|). The angle 9 linked loss and Pauli errors, determining the loss fraction. Errors were normalized similarly to the Bloch sphere qubit vector. Given an error probability p, thelikelihood of a loss event was controlled by L = cos2θ = - -. The error model for Ploss+ PPauliPauli errors was a biased channel described as:Px = Py = Pz = P ■ (px+ Py) = (S2)Here, r is the bias parameter, linked to the parameter (|>. Normalization check:P(error) = L · p + (1 — L) · (px+ py+ pz) = p (S3) biased Pauli channel

[0319] Unless otherwise noted, this was the error model used in the numerical simulations throughout this Example. Specifically, results based on this error model are disclosed herein, as well as Table 1 of Appendix B, FIGs. 33A-33B of Appendix D, and FIGs. 36-38, 39, 50, 51A-51F, and 52A-52F.• Loss-Pauli correlations between the qubits: for L = 1 (loss errors only), correlations between the two qubits in the gates, where a loss of a single qubit caused the Z Pauli error channel on its neighbor were considered. Therefore, the channel was {Z ® L, L ® I, Z ® L, L ® 1}, where p ~ Pcz / ^-- Every time a qubit was lost, its neighbor received a error channel. The results are presented in Table 1 ofAppendix B and FIGs. 53A-54F.• Erasure-biased Pauli channel correlations on each qubit: This was the same model as the first error channel presented herein, except, instead of loss channels there - 72 - #14554048v3Attorney Docket No.: H0776.70187WO00were perfect erasure errors, meaning perfect loss detection and replacement of all qubits after every gate (direct conversion SE period 0.25). This was a previously reported error model, and the results using this error model can be found herein and in Table 1 of Appendix B and FIGs. 27-32.S3.2 Logical memoryS3.2.1 Comparing all SE methods

[0320] Circuit-level simulation results are provided herein to add to the results presented herein. For decoding, the delayed-erasure decoder was combined with an MLE decoder.

[0321] FIG. 50 presents the logical error as a function of the number of SE rounds, for the various SE methods. Each subplot presented different loss fractions L: 0, 0.5, and 1, respectively. For L = 0: all methods presented comparable results, and teleportation-based SE showed a slightly higher logical error due to extra gate overhead. For L = 0.5, all methods utilizing loss detection: SWAP SE, teleportation-based SE and direct conversion SE, showed comparable results and allowed for deep circuits. For L = 1, with only loss errors, SWAP SE provided a larger logical error than the other methods due to the longer lifecycles.

[0322] FIGs. 51A-51F and 53A-53F present the logical error as a function of physical error for various SE methods, for a loss fraction of 1, considering two different error models: loss-only error model, and a correlated loss-Z channel (see Section S3.1).S3.2.2 Comparison with published errors models

[0323] To verify the simulations described herein, published error models were used to compare the numerical results. First, circuit-level simulation was performed for the case of erasure errors (detected immediately after leaving the qubit subspace), corresponding to direct conversion SE with period 0.25 and perfect operations, and the numerical results were compared to published results. The XZZX surface code was used, for various values of erasure fractions, using a published 2-qubit error model. The data were decoded with the delayed-erasure decoder (simplified, for the erasure channel only, similar to a published decoder) combined with a MWPM decoder. The same thresholds have been published and are illustrated in FIGs. 27-32.

[0324] Furthermore, the teleportation-based SE was benchmarked with the error model of loss and Z correlated errors between the two qubits. The delayed-erasure decoder was used and- 73 - #14554048v3Attorney Docket No.: H0776.70187WO00achieved comparable thresholds of around 3.5% with a loss fraction of 1. Results are presented in Table 1 and FIGs. 53A-53F.S3.3 Logical algorithmsS3.3.1 Random deep logical transversal Clifford circuits

[0325] Deep logical Clifford circuits were investigated, with multiple layers of transversal gates. Each layer comprised single-qubit logical gates from {XL, YL, ZL}, and transversal CNOT gates between all random pairs in random order. After each layer, nrrounds of syndrome extraction were performed. For nr< 1, after every 1 / nrthere was a single QEC round. For nr> 1 after every gate layer there were nrQEC rounds. The circuit-level biased noise model described in Section S3.1 was used. The figures show that the algorithmic logical error PL.xPL, max= 1—pywasthe error of a maximally mixed logical state with N logical qubits.

[0326] Unless otherwise noted, these noise channels were applied throughout the full circuit, except during the state preparation step, final stabilizer measurements in the last transversal gate layer, and final logical stabilizer measurements.Equivalents

[0327] Having thus described several aspects and embodiments of the technology set forth in the disclosure, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described herein. For example, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the embodiments described herein. Those skilled in the art will recognize or be able to ascertain using no more than routine experimentation many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, kits, and / or methods described herein, if such features, systems, articles, materials,- 74 - #14554048v3Attorney Docket No.: H0776.70187WO00kits, and / or methods are not mutually inconsistent, is included within the scope of the present disclosure.

[0328] Also, as described, some aspects may be embodied as one or more methods. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0329] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0330] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0331] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B,” when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0332] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”)- 75 - #14554048v3Attorney Docket No.: H0776.70187WO00can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0333] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively.

[0334] The use of “coupled” or “connected” is meant to refer to circuit elements, or signals, which are either directly linked to one another or through intermediate components. Elements that are not “coupled” or “connected” are “decoupled” or “disconnected.”

[0335] The terms “approximately,” “substantially,” and “about” may be used to mean within ±20% of a target value in some embodiments, within ±10% of a target value in some embodiments, within ±5% of a target value in some embodiments, within ±2% of a target value in some embodiments, and / or within ±1% of a target value in some embodiments. The terms “approximately,” “substantially,” and “about” may include the target value.- 76 - #14554048v3

Claims

Attorney Docket No.: H0776.70187WO00ClaimsWhat is claimed is:

1. A method of performing error correction during a quantum computation, the method comprising:encoding first quantum information into a first logical qubit comprising a first plurality of physical qubits;performing at least one quantum operation on the first logical qubit by applying one or more quantum gates to qubits of the first plurality of physical qubits;measuring an error syndrome of the first logical qubit;generating a list of potential loss events based on the measured error syndrome, the potential loss events identifying a loss of one or more of the first plurality of physical qubits during the performance of the at least one quantum operation;generating a decoding hypergraph based at least in part on the list of potential loss events;generating, by providing the decoding hypergraph as input to a quantum decoder, at least one quantum error correction operation to correct errors that occurred during the performance of the at least one quantum operation; andapplying the at least one quantum error correction operation to the first logical qubit to correct the errors that occurred during the performance of the at least one quantum operation.

2. The method of claim 1, further comprising cancelling quantum gates applied to one or more lost first plurality of physical qubits after the loss is identified.

3. The method of claim 1, wherein generating the decoding hypergraph comprises: constructing a loss circuit of a plurality of loss circuits for a physical qubit lifecycle, wherein the loss circuit of the plurality of loss circuits represents a loss event of the first physical qubit for the physical qubit lifecycle, wherein the loss circuit comprises:a plurality of detectors;a plurality of hyperedges configured to connect the plurality of detectors; and- 77 - #14554048v3Attorney Docket No.: H0776.70187WO00combining the plurality of loss circuits into the decoding hypergraph of the physical qubit lifecycle.

4. The method of claim 3, wherein connecting the plurality of detectors comprises using a hyperedge to:represent a possible error event;connect the plurality of detectors flipped by the possible error event; andextract a corresponding probability for the possible error event.

5. The method of claim 4, wherein extracting a corresponding probability for the possible error event comprises assigning a first probability to a first hyperedge associated with a lost qubit, wherein the first probability is associated with a first weight of the decoding hypergraph.

6. The method of claim 5, wherein the first probability is approximately equal to 0.5 and the first weight is approximately equal to 0.

7. The method of claim 3, wherein the loss circuit corresponds to a syndrome of the loss event, and combining the loss circuits results in a lifecycle syndrome, wherein the lifecycle syndrome corresponds to a syndrome of the physical qubit for the lifecycle of the physical qubit.

8. The method of any one of claims 1-7, further comprising measuring the first plurality of physical qubits.

9. The method of claim 8, wherein measuring the first plurality of physical qubits comprises determining a state of a physical qubit of the plurality of physical qubits.

10. The method of claim 9, wherein determining the state of the physical qubit comprises determining that the state of the physical qubit is at least one of |0〉, |1〉, or loss (|L〉).- 78 - #14554048v3Attorney Docket No.: H0776.70187WO0011. The method of any one of claims 1-7, wherein applying quantum gates comprises applying Hadamard gates, Pauli-X gates, Pauli-Y gates, Pauli-Z gates, S gates, T gates, CZ gates, SWAP gates, CNOT gates, and / or Toffoli gates.

12. The method of any one of claims 1-7, further comprising performing quantum error correction using the decoding hypergraph, the quantum error correction comprising:extracting a set of decoding hypergraphs from detected loss events;summing the decoding hypergraphs of the set of decoding hypergraphs; applying a normalized weight associated with the decoding hypergraph; generating a final decoding hypergraph, wherein the final decoding hypergraph comprises lifestyles and statistical weights for lifecycles of lost physical qubits; and inputting the final decoding hypergraph into a decoder, wherein the decoder is configured to perform quantum error correction.

13. The method of claim 12, wherein performing the quantum error correction is performed by a trained neural network and / or machine learning model.

14. The method of claim 12, wherein performing the quantum error correction is performed by applying most likely error (MLE) decoding, minimum weight perfect matching (MWPM) decoding, belief propagation decoding, and / or delayed-erasure decoding.

15. The method of any one of claims 1-7, wherein measuring the error syndrome comprises:performing a first quantum gate between at least two physical qubits of the first plurality of physical qubits;performing a physical SWAP movement between the at least two physical qubits of the first plurality of physical qubits; andafter performing the physical SWAP movement, measuring an error syndrome of the first logical qubit.

16. The method of any one of claims 1-7, wherein measuring the error syndrome comprises:- 79 - #14554048v3Attorney Docket No.: H0776.70187WO00entangling the first logical qubit in a first cluster state;encoding second quantum information into a second logical qubit comprising a second plurality of physical qubits;entangling the second logical qubit in a second cluster state; andteleporting the first quantum information from the first logical qubit to the second logical qubit by:applying a Hadamard gate to physical qubits of the first plurality of physical qubits;applying at least one quantum operation between the first logical qubit and the second logical qubit to entangle one or more quantum states of the first and second logical qubits; andmeasuring, using state- selective readout, quantum states of the first plurality of physical qubits, wherein the measuring obtains an error syndrome associated with the first logical qubit.

17. A method for performing syndrome extraction during operation of a quantum computer, the method comprising:encoding quantum information into a logical qubit comprising a plurality of physical qubits;performing a first quantum gate between at least two physical qubits of the plurality of physical qubits;performing a physical SWAP movement between the at least two physical qubits of the plurality of physical qubits; andafter performing the physical SWAP movement, measuring an error syndrome of the logical qubit.

18. The method of claim 17, wherein performing the first quantum gate comprises:applying a CNOT gate to the at least two physical qubits; andapplying a SWAP gate to the at least two physical qubits, wherein the SWAP gate comprises three alternating CNOT gates.- 80 - #14554048v3Attorney Docket No.: H0776.70187WO0019. The method of claim 17 or 18, wherein the first quantum gate is canceled if at least one of the two physical qubits of the plurality of physical qubits is lost prior to performing the first quantum gate.

20. The method of claim 19, wherein all quantum gates applied to a lost qubit of the plurality of physical qubits are canceled if at least one of the two physical qubits of the plurality of physical qubits is lost prior to performing the first quantum gate.

21. The method of claim 19, wherein, in response to the first quantum gate being canceled, the lost qubit is replaced with a fresh qubit.

22. The method of claim 17 or 18, further comprising measuring a quantum state of a physical qubit of the plurality of physical qubits.

23. The method of claim 22, wherein measuring the quantum state of the physical qubit comprises determining that the quantum state is at least one of |0〉, |1〉, or lost (|L〉).

24. The method of claim 23, wherein the method further comprises replacing a lost physical qubit with a new physical qubit, wherein the lost physical qubit is a physical qubit with a quantum state that is measured to be |L).

25. A method for performing syndrome extraction during operation of a quantum computer, the method comprising:encoding first quantum information into a first logical qubit comprising a first plurality of physical qubits;entangling the first logical qubit in a first cluster state;encoding second quantum information into a second logical qubit comprising a second plurality of physical qubits;entangling the second logical qubit in a second cluster state;teleporting the first quantum information from the first logical qubit to the second logical qubit by:- 81 - #14554048v3Attorney Docket No.: H0776.70187WO00applying a Hadamard gate to physical qubits of the first plurality of physical qubits; andapplying at least one quantum operation between the first logical qubit and the second logical qubit to entangle one or more quantum states of the first and second logical qubits; andmeasuring, using state- selective readout, quantum states of the first and / or second plurality of physical qubits, wherein the measuring obtains an error syndrome associated with the first and / or logical qubit.

26. The method of claim 25, wherein applying the Hadamard gate to the physical qubits of the first plurality of physical qubits comprises applying a Hadamard gate to every physical qubit of the plurality of physical qubits.

27. The method of claim 25, wherein entangling the first logical qubit in the first cluster state comprises entangling the first plurality of physical qubits in a Raussendorf-Harrington-Goyal (RHG) cluster state or an XZZX cluster state.

28. The method of claim 27, wherein entangling the first and / or second logical qubit into a cluster state comprises entangling the first and / or second logical qubit into an XZZX cluster state, and further comprising applying Hadamard gates to at least half of the physical cubits forming the XZZX cluster state.

29. The method of claim 25, wherein the at least one quantum operation is applied transversally between a first physical qubit of the first logical qubit and a second physical qubit of the second logical qubit.

30. The method of claim 25, wherein encoding the first quantum information comprises encoding the first quantum information into an arbitrary quantum state of the first logical qubit.

31. The method of claim 25, further comprising teleporting the first quantum information to a third logical qubit by:- 82 - #14554048v3Attorney Docket No.: H0776.70187WO00encoding third quantum information into the third logical qubit comprising a third plurality of physical qubits;applying at least one quantum operation between the second logical qubit and the third logical qubit to entangle one or more quantum states of the second and third logical qubits;applying a Hadamard gate to each of the second and third logical qubits; and measuring, using state- selective readout, quantum states of the second plurality of physical qubits, wherein the measuring obtains an error syndrome associated with the second logical qubit.

32. The method of any one of claims 25-31, further comprising:encoding third quantum information into a third logical qubit comprising a third plurality of physical qubits;performing a first quantum operation, between the first logical qubit and the second logical qubit, the first quantum operation comprising:performing at least one quantum operation on the first logical qubit, the quantum operation comprising performing a first-type quantum gate between the first and the second logical qubit;performing a SWAP gate between the first and the second logical qubit; performing a physical SWAP movement between the first and the second logical qubit; andperforming a first measurement; andperforming a second quantum operation, between the first logical qubit and the third logical qubit, the second quantum operation comprising:performing at least one quantum operation on the first logical qubit, the quantum operation comprising performing a first-type quantum gate between the first and the third logical qubit;performing a SWAP gate between the first logical qubit and the third logical qubit;performing a physical SWAP movement between the first logical qubit and the second logical qubit; andperforming a second measurement.- 83 - #14554048v3Attorney Docket No.: H0776.70187WO0033. The method of claim 32, wherein performing the first measurement and / or second measurement provides loss information.

34. A method for performing syndrome extraction during operation of a quantum computer, the method comprising:encoding quantum information into a logical qubit comprising a plurality of physical qubits;performing at least one quantum operation between a physical data qubit of the plurality and a measurement qubit, the quantum operation comprising performing a first-type quantum gate between the physical data qubit and the measurement qubit;performing erasure detection following the at least one quantum operation; and measuring a quantum state of the physical data qubit to obtain an error syndrome of the logical qubit.

35. The method of claim 34, wherein the erasure detection is performed after each quantum operation.

36. The method of claim 34, wherein the erasure detection is performed after a plurality of quantum operations.

37. The method of any one of claims 34-36, further comprising replacing the physical data qubit after measuring the physical data qubit.

38. A quantum information processing system, comprising:a computation chamber, comprising a storage zone, an entangling zone, a readout zone, and a reservoir zone;a spatial light modulator configured to load qubits into arrangements of qubit traps in at least one of the storage zone, the entangling zone, the readout zone, and / or the reservoir zone;- 84 - #14554048v3Attorney Docket No.: H0776.70187WO00a first laser configured to illuminate arrays of qubits in at least one of the storage zone, the entangling zone, the readout zone, and the reservoir zone with a global Raman beam;a first pair of crossed acousto-optical deflectors configured to move qubits between the arrangements of qubit traps;a second pair of cross acousto-optical deflectors configured to form a local Raman beam to perform single-qubit rotations using the global Raman beam;a second laser configured to generate a laser beam to illuminate qubits in the storage zone;a third and fourth laser configured to perform entangling gates between qubits disposed in the entangling zone using two-photon excitation;at least one camera configured to image qubits in the readout zone; andat least one controller configured to control components of a plurality of components to perform the methods of any one of claims 1-31.

39. The quantum information processing system of claim 38, wherein the third and fourth lasers are configured to emit 420-nm and 1013-nm Rydberg beams, respectively, configured to excite the qubits disposed in the entangling zone to n = 53 Rydberg states.- 85 - #14554048v3

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