Time domain reflectometry (TDR) controlled-impedance testing systems for significantly low impedance applications

Abstract

A time domain reflectometry (TDR) controlled-impedance testing system includes one or more ultra-low impedance testing channels (e.g., having a characteristic impedance of less than 10 ohms, or less than 5 ohms, or less than 2 ohms) to couple a test signal to a test target ("device under test"). In one example, the TDR testing system includes one or more printed circuit boards (PCBs) on which at least a portion of the testing channel is implemented. The PCB includes an ultra-wide impedance-controlled trace and one or more return conductors constituting at least a portion of an ultra-low impedance PCB RF transmission line having a characteristic impedance of less than 10 ohms (or less than 5 ohms, or less than 2 ohms).

Description

Attorney Docket No.: BRLN-009W001TIME DOMAIN REFLECTOM ETRY (TDR) CONTROLLED-IMPEDANCE TESTING SYSTEMS FOR SIGNIFICANTLY LOW IMPEDANCE APPLICATIONSCROSS-REFERENCES TO RELATED APPLICATIONS(0001] The present application claims a priority benefit to U.S. Provisional Application Serial No. 63 / 730,900, filed December 11, 2024, entitled “Time Domain Reflectometry (TDR) Controlled-Impedance Testing Systems for Significantly Low Impedance Applications,” which is hereby incorporated by reference herein in its entirety, and PCT Application Serial No. PCT / US25 / 58954, filed December 10, 2025, entitled “Printed Circuit Boards Including Impedance-Controlled Traces for Significantly Low Impedance Applications and Methods for Fabricating Same,” which is hereby incorporated herein by reference in its entirety.BACKGROUND(0002] Time Domain Reflectometry (TDR) is an effective technique used to evaluate the controlled-impedance design of printed circuit boards (PCBs) and other components (that generally include conductors and dielectric materials). Generally speaking, TDR measures reflections of electrical signals traveling through a transmission line (and associated connectors, if any), thereby providing insights into impedance consistency and discontinuities.(0003] A conventional TDR controlled-impedance testing system sends a fast electrical pulse into a transmission line, and reflections of the fast electrical pulse occur at points where impedance changes (discontinuities, mismatches) along the pulse propagation path. By analyzing these reflections, the TDR testing system reveals the impedance profile of the transmission line. In particular, the time delay between the pulse injection and its reflection is used to calculate the distance to the discontinuity using:where d is the distance, t is the time delay, and v is the signal propagation velocity (which depends on the dielectric constant of the dielectric material used in the transmission line). Since TDR testing is influenced by the dielectric constant, accurate knowledge of this dielectric constant is important for precise impedance and distance calculations.[0004 The general goals of conventional TDR testing are to 1) ensure that the transmission line matches the designed characteristic impedance, 2) detect and locate impedance mismatches caused by vias, connectors, or manufacturing issues, and 3) in the context of PCBAttorney Docket No.: BRLN-009W001 transmission lines, confirm uniform impedance along PCB traces (which is an important consideration for high-speed PCB circuit designs).(0005] A conventional TDR testing system typically involves specialized equipment capable of generating fast rise-time pulses (e.g., 10-100 ps rise times). Such a system typically includes one or more high-bandwidth probes, and in some instances one or more calibration standards to facilitate calibration of the TDR testing system for accuracy (e.g., using short, open, and load standards). Important considerations for accurate measurements using a TDR testing system include appropriate connectivity using high-quality connectors and probes to ensure low-loss and minimize test-induced reflections and, more particularly, ensuring a good connection between a TDR system’s probe ground to the ground of the object being tested (e.g., PCB ground plane) to maintain a proper reference. It is also generally beneficial to minimize external noise and ensure a stable testing environment.(0006] Regarding the test signals provided by conventional TDR testing systems, typically a test signal would include a pulse rise time that is faster than the signal rise time on the component under test (also referred to herein as the “test target”) to detect impedance variations at the smallest geometry of interest (i.e., the rise time must be shorter than the electrical length of the smallest features to ensure accurate detection). The test signal also would have a pulse width that is wide enough to ensure analysis of the entire transmission line. With respect to analyzing the TDR waveform, a flat line indicates consistent impedance, whereas spikes or dips in the raw TDR waveform represent impedance discontinuities (e.g., a spike represents a transition to a higher impedance, such as from a narrowing of a trace, and a dip represents a transition to a lower impedance, such as from a widening trace or a ground short). Software then converts the raw reflections into a graph of impedance variations.(0007] More specifically, the reflection coefficient T in TDR is a measure of the proportion of an electrical signal that is reflected at an impedance discontinuity. It is calculated using the following formula:where T is the reflection coefficient (a dimensionless value between -1 and 1), ZL is the Load impedance (impedance at the point of the discontinuity), and Zo is the characteristic impedance of the transmission line or trace. According to the reflection coefficient:• T = 0 indicates no reflection (perfect impedance match);Attorney Docket No.: BRLN-009W001• r > 0 indicates a partial reflection due to a higher impedance of the load as compared to the characteristic impedance;• T < 0 indicates a partial reflection due to a lower impedance of the load as compared to the characteristic impedance;• T = 1 indicates a total reflection from an open circuit; and• T = -1 indicates a Total reflection from a short circuit.Thus, the polarity and magnitude of the reflection coefficient T indicate the nature and severity of the impedance discontinuity. In some conventional TDR applications, the reflection coefficient T can also be calculated from the voltage of the incident signal Vine and reflected signal Vref according to:This relationship is used in some conventional TDR testing systems to directly determine the reflection coefficient by measuring the incident and reflected voltages.(0008] In the context of TDR testing systems, a testing channel refers to a specific signal path or port within the TDR equipment that is used to inject a test signal into the device under test (DUT; also referred to herein as a “test target”) and receive reflected signals. Testing channels are integral to the operation of TDR systems and enable precise measurement and characterization of transmission lines or other structures. A given testing channel generally includes circuitry for generating the test signal (e.g., a test pulse), transmitting it to the DUT (test target), and capturing any reflected signals for analysis. A given testing channel is designed with a specific characteristic impedance (e.g., 50Q) to ensure proper signal injection and minimize distortion. Some TDR systems support both single-ended and differential testing channels. High-end TDR systems often have multiple testing channels, enabling simultaneous or sequential testing of multiple traces, cables, or transmission lines. This is particularly useful fortesting multi-layer PCBs, analyzing multiple signal paths in parallel, and comparing single- ended and differential traces. Conventional TDR testing systems are capable of verifying the characteristic impedance of individual traces on a PCB, as well as measuring differential pairs of traces to measure differential impedance.|0009] To this end, a “coupon” refers to a small, representative section of a PCB (or other transmission line) that is designed and fabricated specifically for testing and characterizationAttorney Docket No.: BRLN-009W001 purposes. Coupons are often included as part of the PCB manufacturing process to validate various design and fabrication parameters. For example, coupons often include PCB traces designed with specific impedance (e.g., 50Q, 75Q) to verify the manufacturer’s ability to meet impedance specifications. Coupons can include single-ended traces, differential pairs, or other controlled-impedance structures. They provide a standard area for testing signal integrity, making it easier to correlate manufacturing outcomes with design requirements. Coupons are separate from the main circuit, ensuring that TDR testing does not interfere with or damage other functional parts of the PCB. Coupons generally include specific test points or pads to facilitate connection of TDR probes or measurement equipment.(0010] Thus, coupons allow the measurement of the characteristic impedance of PCB traces in a controlled and repeatable manner to ensure compliance with design specifications and identify variations caused by factors such as material inconsistencies, trace geometry, or process deviations. Coupons serve as a quality control check during the PCB manufacturing process, ensuring that each production batch meets required electrical properties. Coupons help isolate manufacturing issues (e.g., improper etching, dielectric thickness variations) without the need to test the entire PCB and they validate that the PCB stack-up, including materials and layer alignment, adheres to the design specifications. During testing, TDR equipment is connected to the coupon, and the reflections are analyzed to determine electrical performance and locate any impedance mismatches.(0011] In practice, TDR testing is performed on coupons as well as PCB transmission lines that form part of the circuit on a PCB. Generally speaking, the device under test (e.g., coupon, PCB transmission line of actual circuit, other transmission line) is referred to herein as a “test target.” Data from TDR testing systems relating to a test target may be compared to PCB layout files to identify design features causing reflections (e.g., vias, connectors, trace width changes). These findings are used to refine future designs or address manufacturing issues. TDR measurements also are commonly compared with simulation results to validate a PCB model, and discrepancies may reveal issues like material inconsistencies or unexpected geometries. Additionally, TDR measurements are useful in some instances to align impedance measurements with industry standards and confirm that the PCB meets customer or projectspecific impedance requirements.|0012] Thus, conventional TDR testing systems provide an effective way to verify, troubleshoot, and optimize controlled-impedance PCB designs by testing signal traces on test targets for impedance control, detect open or short circuits, and identify defects like voids,Attorney Docket No.: BRLN-009W001 cracks, or poor solder connections. By maintaining proper test setups, analyzing waveforms thoroughly, and integrating TDR insights into design and manufacturing workflows, a PCB designer can ensure high signal integrity and robust performance in their PCBs.

[0013] Beyond controlled-impedance testing of PCB designs, TDR testing systems are versatile tools used to assess electrical properties and identify faults in a variety of conductive and dielectric materials. Other examples of components often tested using TDR systems include: cables, wires and wire harnesses to assess impedance uniformity, detect faults (opens, shorts, kinks), and measure cable lengths; various connectors and Interfaces to verify impedance continuity and ensure proper signal transmission through connectors; antennas to measure feedline impedance and match to ensure efficient power transfer; transmission lines of various form factors more generally, to assess the integrity of high-frequency signal transmission, e.g., on stripline, microstrip, waveguide and coaxial structures; underground utilities to locate and diagnose faults in buried cables or pipelines; power distribution systems to detect faults in busbars, power planes, and grounding systems; and semiconductor packages to test interconnects and traces within integrated circuit packages for impedance and connectivity.

[0014] Several reputable companies manufacture and supply TDR testing equipment. These companies serve industries ranging from electronics and telecommunications to aerospace and automotive. Examples of some providers of TDR testing equipment include Tektronix (TDR- enabled oscilloscopes and probes like the DSA8300 series for signal integrity analysis, PCB testing, and cable diagnostics), Keysight Technologies (formerly Agilent Technologies; high- precision TDR solutions integrated into vector network analyzers (VNAs) and oscilloscopes like the Infmiium series for high-speed digital design, differential pair testing, and impedance characterization), Rohde & Schwarz (TDR and vector network analysis for high-frequency applications such as signal integrity, cable testing, and RF component analysis), Teledyne LeCroy (WaveExpert and LabMaster series oscilloscopes with TDR options for differential signal integrity, high-speed serial testing, and PCB diagnostics), Fluke Networks (DSX Cable Analyser series for field testing of cables and network infrastructure), Anritsu (MT 1000 A Network Master Pro and MS202x series portable and benchtop TDR solutions for telecommunications and aerospace), Mohr Test and Measurement (CT 100 series precision TDR instruments specifically for aerospace and high-reliability applications, e.g., fault analysis in wire harnesses, connectors, and PCB traces), Omicron Lab (Bode 100 for educational andAttorney Docket No.: BRLN-009W001 small-scale industrial applicions, basic signal integrity testing and impedance analysis), Picotest, and ZMetrix (ST-Series systems for PCB testing applications).SUMMARY(0016] The Inventors have recognized and appreciated that conventional TDR testing systems can reliably measure transmission line impedances down to approximately 10 ohms, but that accuracy and sensitivity generally decrease at lower impedances. More specifically, conventional TDR testing systems generally are designed with a specific dynamic range to accommodate typical impedances found in transmission lines (often between 25 Q and 100 Q for controlled-impedance systems). The reflection coefficient T for low impedances approaches -1, meaning that most of the incident signal reflects back with little energy transmitted. This can make accurate measurements of very low impedances challenging. Additionally, at very low impedances, the signal-to-noise ratio (SNR) can degrade, especially in less sensitive instruments. Moreover, a TDR pulse with a longer rise time might not distinguish very low impedances accurately due to reduced resolution.(0017] Accordingly, the lowest impedance that can be accurately measured by conventional TDR testing equipment depends on multiple factors, including the capabilities of the TDR instrument, the dynamic range of the measurement system, and the quality of the signal injection and reflection detection circuitry. The Inventors have recognized and appreciated that conventional TDR equipment is not adequate for significantly low impedances (e.g., below 10 ohms, also referred to herein as “ultra-low” impedance).(0018] In view of the foregoing, various inventive concepts disclosed herein relate to a time domain reflectometry (TDR) controlled-impedance testing system including one or more testing channels (to couple a test signal to a test target) having an impedance of less than 10 ohms, more preferably less than 5 ohms, and even more preferably approximately or equal to 2 ohms or less.(0019] In example implementations, a TDR controlled-impedance testing system according to the inventive concepts disclosed herein includes a printed circuit board (PCB) including a transmission line (e.g., microstrip, stripline, coplanar waveguide) constituting at least a portion of a testing channel. In one aspect, the transmission line includes one or more “ultra -wide” traces. By way of non-limiting example, an ultra-wide trace may be formed on one or more conductor layers of a multilayer PCB stack-up (e.g., four layers, six layers, or more than six layers), to implement transmission lines having a significantly low characteristic impedance.Attorney Docket No.: BRLN-009W001The range of frequencies over which a transmission line according to the concepts disclosed herein maintains a significantly low characteristic impedance generally is over the radio frequency (RF) signal range from approximately 3 kHZ to 300 GHz, and more specifically over a range of frequencies from approximately 100 kHz to 1 GHz.|0020| In non-limiting example implementations, PCBs for TDR controlled-impedance testing systems including significantly low impedance transmission lines according to the concepts disclosed herein are fabricated using conventional FR4 dielectric materials (e.g., core and prepreg for multilayered implementations) and using one (1) ounce per square foot copper for conductive layers (e.g., so as to benefit from the ubiquitous availability and use of FR4 and industry-standard copper foils). In other examples, specialized dielectric materials such as Rogers laminates or hydrocarbon ceramics, PTFE-based materials such as Taconic or Arion, or Isola may be employed for the PCB transmission line. Regardless of the choice of dielectric materials, however, in various example implementations an ultra-wide trace (e.g., used in an ultra-low impedance PCB transmission line) may have a width on the order of at least 200 mils (5 millimeters), or on the order of at least 300 mils (7.6 millimeters), or on the order of at least 400 mils (10.2 millimeters), or on the order of at least 500 mils (12.7 millimeters), or on the order of at least 800 mils (approximately 20 millimeters), and may be as wide as approximately 1200 mils (approximately 30 millimeters).|00211 In some examples, the ultra-low impedance PCB transmission line may be implemented on a multilayer PCB stack-up, wherein the stack-up includes four layers, six layers, or more than six layers. In one example, an ultra-low impedance PCB transmission line may include one ultra-wide trace on one layer of the stack-up and at least one return plane on another layer of the stack-up to form the transmission line. In another example, an ultra-low impedance PCB transmission line may include two or more ultra-wide traces (including one trace on a first inner layer of the stack-up, and another trace on a second inner layer of the stack-up) that are electrically coupled together (e.g., by one or more vias). The two (or more) ultra-wide traces function in tandem with at least one return plane on another layer of the stack -up adjacent to the inner layer(s) to form the transmission line. In various aspects, employing two or more ultra-wide traces on respective inner layers of the stack-up to form the transmission line allows for a balanced stack-up including an even number of layers, and also provides for increased current conducting capability of the transmission line while at the same time using industry standard one ounce per square foot copper foil for respective layers.Attorney Docket No.: BRLN-009W001

[0022] In some aspects, to implement an ultra-wide trace using conventional PCB software tools (e.g, KiCAD, Eagle, or Altium Designer), a PCB designer needs to particularly specify the ultra-wide trace not as a trace but rather as a plane, as the conventional PCB software tools generally limit trace widths to a maximum of 250 mils (6.35 millimeters). To this end, the PCB designer instead uses the PCB software tool to specify an ultra-wide trace by outlining a plane having particular dimensions based at least in part on a target characteristic impedance, the copper thickness, the distance of the plane / ultra-wide trace from a ground plane or a ground trace, and the dielectric constant of the PCB insulating material (e.g., core, prepreg or other specialty dielectric material) between the plane / ultra-wide trace and the ground plane / ground trace. The PCB software tool then creates a copper flood based on the specified outline of the plane. Accordingly, an ultra-wide trace according to the concepts disclosed herein advantageously exploits attributes of a copper flood (e.g., including the particular clearances around traces, pads, or other conductive features that are in or traverse the area designated by the designer for the plane, as specified by corresponding design rules for copper floods). Additionally, according to yet another aspect, the PCB designer may specify one or more additional planes on one or more layers of the PCB, in addition to those serving as an ultrawide trace, and thereby use copper floods in these additional planes to balance the copper distribution from layer-to-layer. Such a layer-to-layer balancing of copper distribution in the multilayer stack-up improves impedance consistency, PCB manufacturability, and durability (e.g., prevent warping of the PCB).

[0023] It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the inventive subject matter disclosed herein. It should also be appreciated that terminology explicitly employed herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in theAttorney Docket No.: BRLN-009W001 drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and / or structurally similar elements).

[0025] FIG. 1 shows a block diagram of a time domain reflectometry (TDR) system according to one example inventive implementation.

[0026] FIG. 2 shows a block diagram of a strobe-pulse generator in the TDR system shown in FIG. 1, according to one example inventive implementation.

[0027] FIG. 3 shows a more detailed schematic of the step generator and the sampling gate of the TDR system shown in FIG. 1, implemented in an integrated fashion with at least a portion of the testing channel according to one inventive example implementation.

[0028] FIG. 4 shows a cross-sectional view of a multilayer PCB including an ultra-wide impedance-controlled conductive (e.g., copper) trace on a first layer and a return conductor on a second layer to constitute at least a portion of an ultra-low impedance PCB radio frequency (RF) transmission line according to one inventive example implementation that can be employed in the TDR system shown in FIGS. 1-3.

[0029] FIG. 5 shows a top-down view of the multilayer PCB of FIG. 4, illustrating the ultrawide impedance-controlled trace on the first layer (in black) superimposed on the return conductor on the second layer (in gray) to constitute at least a portion of the ultra-low impedance PCB radio frequency (RF) transmission line.

[0030] FIG. 6 illustrates a cross-sectional view of another example of a multilayer PCB comprising a six -layer stack-up, in which multiple ultra-wide impedance-controlled traces are formed, together with multiple return conductors, to provide a modified stripline ultra-low impedance PCB RF transmission line according to inventive example implementations.

[0031] FIG. 7 shows a Gerber file for a top soldermask of a testing channel of a TDR system according to one inventive example implementation based on the multilevel PCB employing the six-layer stack-up shown in FIG. 6.

[0032] FIG. 8 shows a Gerber file for layer 1 ( / . / ) of the example testing channel based on the multilevel PCB employing the six -layer stack-up shown in FIG. 6.

[0033] FIG. 9 shows a Gerber file for layer 2 (Z2) of the example testing channel based on the multilevel PCB employing the six -layer stack-up shown in FIG. 6.Attorney Docket No.: BRLN-009W001

[0034] FIG. 10 shows a Gerber file for layer 3 ( / J) of the example testing channel based on the multilevel PCB employing the six-layer stack-up shown in FIG. 6, wherein L3 includes a first ultra-wide trace according to some of the inventive concepts disclosed herein.

[0035] FIG. 11 shows a Gerber file for layer 4 ( / .- / ) of the example testing channel based on the multilevel PCB employing the six-layer stack-up shown in FIG. 6, wherein L4 includes a second ultra-wide trace according to some of the inventive concepts disclosed herein.

[0036] FIG. 12 shows a Gerber file for layer 5 (7.5) of the example testing channel of the multilevel PCB employing the six -layer stack-up shown in FIG. 6.

[0037] FIG. 13 shows a Gerber file for layer 6 (76) of the example testing channel of the multilevel PCB employing the six -layer stack-up shown in FIG. 6.

[0038] FIG. 14 shows a Gerber file for drill holes for vias that pass through all levels of the example testing channel based on the multilevel PCB employing the six-layer stack-up shown in FIG. 6.

[0039] FIG. 15 shows a Gerber file for drill holes for blind vias that pass through only some of the levels of the of the example testing channel based on the multilevel PCB employing the six-layer stack-up shown in FIG. 6.

[0040] FIG. 16 shows a fabrication drawing for the example testing channel based on the multilevel PCB employing the six -layer stack-up shown in FIG. 6.DETAILED DESCRIPTION

[0041] Following below are more detailed descriptions of various concepts related to, and embodiments of, time domain reflectometry (TDR) controlled-impedance testing systems and associated methods for significantly low impedance applications. It should be appreciated that various inventive concepts as introduced herein and accompanying drawings may be implemented in multiple ways. Examples of specific implementations and applications are provided primarily for illustrative purposes so as to enable those skilled in the art to practice the implementations and alternatives apparent to those skilled in the art.

[0042] The figures and example implementations described herein are not meant to limit the scope of the present implementations to a single embodiment. Other implementations are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the disclosed example implementations may be partially or fully implemented using known components, in some instances only those portions of suchAttorney Docket No.: BRLN-009W001 known components that are necessary for an understanding of the present implementations are described, and detailed descriptions of other portions of such known components are omitted so as not to obscure the present implementations.

[0043] In the discussion herein, various examples of time domain reflectometry and printed circuit board concepts and elements are provided, wherein a given example or set of examples showcases one or more features of an implementation for significantly low impedance applications and / or a related fabrication method. It should be appreciated that one or more features discussed in connection with a given example may be employed in other examples of printed circuit boards and associated fabrication methods according to the present disclosure, such that the various features disclosed herein may be readily combined in multiple ways according to the present disclosure (provided that respective features are not mutually inconsistent).

[0044] Certain dimensions and features (e.g., of printed circuit boards) according to the present disclosure are described herein using the terms “approximately,” “about,” “substantially,” and / or “similar.” As used herein, the terms “approximately,” “about,” “substantially,” and / or “similar” indicates that each of the described dimensions or features is not a strict boundary or parameter and does not exclude functionally similar variations. Unless context or the description indicates otherwise, the use of the terms “approximately,” “about,” “substantially,” and / or “similar” in connection with a numerical parameter indicates that the numerical parameter includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit.

[0045] FIG. 1 shows a block diagram of one example implementation of a time domain reflectometry (TDR) system 200 according to the inventive concepts disclosed herein. In the system 200 shown in FIG. 1, a clock 206 may include a crystal oscillator to provide a system clock signal 207 for other components of the RF circuitry of the system. The clock signal 207 is divided into two clock signal channels by a resistive 6dB power splitter 208. A first clock signal 230 is applied to a strobe-pulse generator 210, which in turn provides a first pulse 226A and a second pulse 226B that is complimentary to the first pulse (i.e., 180 degrees out of phase with the first pulse). The strobe-pulse generator 210 is discussed further below in connection with FIG. 2. The first pulse 226A and the second pulse 226B generated by the strobe-pulse generator 210 are applied to a sampling gate 216. As discussed further below in connectionAttorney Docket No.: BRLN-009W001 with FIG. 3, the first pulse and the second pulse have a full-width at half-maximum (FWHM) that is sufficiently short so as to effectively trigger the sampling gate 216.(0046] With reference again to FIG. 1, a second clock signal 231 is applied to a delay module 212, which is controlled by a microcontroller 220 to delay (time-shift) the second clock signal 231 so as to provide an adjusted clock signal 224. This adjusted clock signal 224 is then used to trigger a step generator 214, which ultimately provides a test signal 225 as an output of the TDR system 200. More specifically, the test signal 225 propagates through the sampling gate 216 and then along a testing channel 202 which generally includes, or is constituted by, a probe 203 that applies the test signal 225 to the test target 204 (also referred to as a “device under test” or simply DUT).(0047] The testing channel 202 (which may include the probe 203) generally is implemented as a transmission line along which the test signal 225 propagates. According to the inventive concepts disclosed herein, the testing channel 202 is configured such that a characteristic impedance of the testing channel is less than 10 ohms. In some example implementations, the testing channel is configured such that its characteristic impedance is approximately, equal to, or less than 5 ohms, and in other example implementations the testing channel is configured such that its characteristic impedance is approximately, equal to, or less than 2 ohms. As shown in FIG. 1 (and as discussed further below in connection with FIGS 4, 5 and 6), in some example implementations at least a portion of the testing channel 202 includes an ultra-low characteristic impedance PCB RF transmission line 130 that employs one or more ultra-wide impedance controlled traces 120A, as discussed in PCT Application Serial No. PCT / US25 / 58954, filed December 10, 2025, entitled “Printed Circuit Boards Including Impedance-Controlled Traces for Significantly Low Impedance Applications and Methods for Fabricating Same,” which is hereby incorporated herein by reference in its entirety. Furthermore, one or more of the step generator 214 or the sampling gate 216 also may employ one or more ultra-wide impedance- controlled traces 120A or ultra-low characteristic impedance transmission lines 130. By employing one or more testing channels having respective characteristic impedances of less than 10 ohms (and corresponding internal impedance-matched circuity such as the step generator 214 and the sampling gate 216), the TDR system 100 shown in FIG. 1 is particularly configured to facilitate useful and accurate measurements relating to test targets 204 which themselves have an ultra-low characteristic impedance of less than 10 ohms.(0048] In the system of FIG. 1, based at least in part on the material properties and configuration of the test target 204, the test signal 225 applied to the test target 204 (via theAttorney Docket No.: BRLN-009W001 testing channel 202) gives rise to a reflected signal that is superimposed on the test signal 225, such that a combined signal 205 ultimately is carried by the testing channel 202. This combined signal 205 is acquired by the sampling gate 216 (discussed further below in connection with FIG. 3) to provide an analog sampled output signal 228 from the sampling gate 216. The analog sampled output signal 228 is converted into digital values by an analog-digital converter 218, which is triggered and read out by the microcontroller 220. In one aspect, the microcontroller 220 also buffers the digital values and passes them to a computer 222 for high level data processing and display. In some implementations, at least a portion of the computer 222 may be constituted by a digital oscilloscope to display representations of various signals.

[0049] FIG. 2 shows a block diagram of the strobe-pulse generator 210 of FIG. 1 according to one example implementation. In the example shown in FIG. 2, the first clock signal 230 is applied to fast frequency divider (e.g., which may be implemented as a monolithc microwave integrated circuit or MMC), which in turn generates a square-wave signal with off-on steps having significantly short rise-times (e.g., on the order of approximately 50 picoseconds). The square-wave signal is then shaped via a broadband amplifier that increases the pulse amplitude (and also isolates the fast-frequency divider from the subsequent circuitry). In some examples, the amplifier may followed by an attenuator, which suppresses multiple reflections that may arise due to any impedance mismatches which may be present in the signal chain involving the TDR system circuitry, the testing channel 202 and the test target 204 (as shown in FIG. 1). Subsequently, the steps of the square wave signal are transformed into pulses using clipping lines. A high-speed differential driver then outputs complementary strobe pulses with sufficiently high amplitudes, which trigger the sampling gate 216.

[0050] Returning for the moment to FIG. 1, the delay module 212 that receives the second clock signal 231 and provides the adjusted clock signal 224 to trigger the step generator 214 may be implemented in some examples using cascaded delay lines with binary staggered time delays. An arrangement of n switched delay lines with binary cascaded lengths provides N = 2” equidistant time delays. In one implementation, each of the n switched delay lines may be selectively added or removed from the cascade via one or more switches (e.g., RF switches) controlled by the microcontroller 220. In one non-limiting example, n = seven delay lines may be employed, respectively having lengths of 10, 20, 40, 80, 160, 320, 640 picoseconds, so as to provide for a range of delays up to 1.27 nanoseconds with a spacing of 10 picoseconds (yielding 128 selectable delays).Attorney Docket No.: BRLN-009W001|005l] FIG. 3 shows a more detailed schematic of a non-limiting example of the step generator 214 and the sampling gate 216 implemented in an integrated fashion with at least a portion of the testing channel 202. As discussed above in connection with FIG. 1, the test signal 225 provided by the step generator 214 gives rise to a reflected signal (from the test target 204 or DUT) that is superimposed on the test signal 225, such that a combined signal 205 ultimately is carried by the testing channel 202. This combined signal 205 is acquired by the sampling gate 216 to provide an analog sampled output signal 228 from the sampling gate 216.(0052] In FIG. 3, the step generator 214 may generate the test signal 225 as a step signal using a fast-switching MMIC frequency divider or high-speed logic components. In one non-limiting example, the test signal 225 generated by the step generator 213 may have a rise time of less than 100 picoseconds and a repetition frequency of 5MHz. To adjust the amplitude of the test signal 225, the step generator 214 optionally may include one or more amplifiers or attenuators (not shown in FIG. 3); in some instances, one or more such amplifiers or attenuators may be adjustable under the control of the microcontroller 220. In one aspect, the step generator 214 is coupled to the testing channel 202; accordingly, some portion of the circuitry of the step generator 214 may include an ultra-low impedance PCB RF transmission line 130 to facilitate impedance-matched coupling to the testing channel 202. In FIG. 3, the test signal 225 propagates along a portion of the testing channel 202, which in this example is integrated with the sampling gate 216, towards the probe 203 that is coupled to the test target (not shown in FIG. 3). As noted above, the test signal 225 is reflected from the test target to form the combined signal 205, which is then “sampled” by the respective components of the sampling gate 216.

[0053] As shown in FIG. 3, in one non-limiting example the sampling gate 216 may be configured as a multiple-diode travelling wave sampling system in which relatively smaller sections of transmission lines are selectively isolated, as described for example in U.S. Patent No. 3,629,731, which is hereby incorporated by reference herein in its entirety.

[0054] More specifically, in the arrangement shown in the example of FIG. 3, the sampling gate 216 includes an upper branch 216A and a lower branch 216B, wherein each branch includes multiple diodes 234 (e.g., a total of six diodes are shown in FIG. 3, three for each branch). The diodes 234 interconnect transmission line sections 236 having respective lengths Ls. In one example implementation, as shown in FIG. 3, one or more of the transmission line sections 236 may be implemented as an ultra-low characteristic impedance PCB RF transmission line 130 that employs one or more ultra-wide impedance controlled traces 120AAttorney Docket No.: BRLN-009W001(e.g., as discussed in PCT Application Serial No. PCT / US25 / 58954, incorporated by reference above).(0055] In the arrangement of FIG. 3, the diodes in the respective branches 216A and 216B become conductive while the leading edges of the complementary strobe pulses 226A and 226B simultaneously travel across the upper and lower branches of the sampling gate towards a portion of the testing channel 202. While the diodes stay conductive, a part of the combined signal 205 propagates along the upper and lower branches 216A and 216B. The trailing edges of the strobe pulses 226A and 226B successively close the diodes 234; as a result, respective transmission line sections 236 become successively isolated, and a part of the combined signal 205 is thereby “trapped” on an isolated section. A length Lsof respective transmission line sections 236 defines, at least in part, a sampling duration and hence a resolution bandwidth of the sampling gate 216.(0056] In FIG. 3, resistors 238 coupled to transmission line sections 236 allow a “trapped” portion of the combined signal to charge a holding capacitor 232 during the sampling duration and thus store a voltage so as to provide the sampled analog output signal 228. While not shown explicitly in FIG. 3, the output signal 228 may be pre-amplified in an operational amplifier prior to analog to digital conversion (by the analog-to-digital converter 218 shown in FIG. 1). In one non-limiting example, the sequential sampling arrangement shown in FIG. 3 is configured to sample the combined signal 205 with a time resolution on the order of 10 picoseconds around the steepest ascent of the test signal 224. Various discrete time shifts between the strobe pulses 226A and 226B and the combined signal 205 are achieved by controlling the delay module 212, as discussed above, so to sample the combined signal 205 and provide the sampled analog output signal 228 at well-defined times to facilitate data processing. With reference again to FIG. 1, the digital output of the analog-to-digital converter 218 may be stored in the microcontroller 220 and transferred to the computer 222 for data- processing and for displaying the results.(0057] FIG. 4 shows a cross-sectional view of a multilayer PCB 100 including an ultra-wide impedance controlled conductive (e.g., copper) trace 120 according to one inventive example implementation that can be employed in a TDR system as described above in connection with FIGS. 1-3. In the illustration of FIG. 4, the cross-sectional view is taken along ay-z plane of the multilayer PCB (where the z axis represents a height or thickness dimension of the multilayer PCB). Generally speaking, in the various figures, the position along the x-axis of a multilayer PCB at which a given cross-sectional view is taken may not strictly correspond toAttorney Docket No.: BRLN-009W001 any one specific PCB design example discussed later in this disclosure; rather, respective cross-sectional views are provided to conceptually illustrate constituent elements of the multilayer architecture germane to the inventive subject matter disclosed herein.

[0058] FIG. 4 shows an example of a multilayer PCB having a stack-up 110 including four conductive layers (designated generically in the figure by LI, L2, L3 and L4). It should be appreciated, however, that the various inventive concepts disclosed herein similarly apply to PCBs with only two conductive layers, as well as multilayer PCBs having a stack-up of greater than four layers (e.g., as discussed further below in connection with FIG. 12). In the various figures, conductive layers of a stack-up generally are shown in solid white, whereas electrically-insulating materials between conductive layers generally are shown with grayscale cross-hatching (e.g., darker gray-scale cross-hatching for core, lighter gray-scale crosshatching for prepreg). Also, for purposes of this disclosure, respective conductive layers of a given stack-up may be referred to herein for convenience as “copper layers” or simply “layers;” however, it should be appreciated that the various concepts disclosed herein may be implemented with conductive layers employing copper or other materials (e.g., aluminum, gold, silver, nickel, tin, lead, carbon). Additionally, when referring to respective layers and electrically-insulating material of a given stack-up, the use of ordinal adjectives may not necessarily correspond to generic layer designations (e.g., such as LI, L2, L3, and L4) shown in the various figures; instead, ordinal adjectives generally refer to the sequential order in which a given layer or electrically-insulating material of a stack-up is introduced in the following discussion.

[0059] As shown in FIG. 4, the stack-up 110 of the multilayer PCB 100 in this example includes a first electrically insulating material 124 (e.g., “core”) and a first layer 112 (Z2) (e.g., comprising first copper), wherein the first layer 112 and the first electrically -insulating material 124 are contiguous. A first ultra-wide impedance-controlled trace 120A is formed in the first layer 112. In one inventive aspect, the ultra-wide trace 120A has a width 122 in a range of from approximately or equal to 200 mils (or 5 millimeters) to approximately or equal to 1200 mils (or 30 millimeters). As noted earlier, this range for the width 122 of the ultra-wide trace 120A is an order (or multiple orders) of magnitude wider than the width of a conventional impedance-controlled trace (i.e., 5-20 mils / 0.13-0.5 mm wide for conventional traces); given this width 122, at the time of this disclosure, the ultra-wide trace 120A would not be considered as an impedance-controlled trace in the conventional parlance of PCB designers. Accordingly, the ultra- wide impedance-controlled trace 120 A constitutes a novel PCB design element.Attorney Docket No.: BRLN-009W001

[0060] As also shown in FIG. 4, the ultra-wide trace 120A has a trace thickness 118. In implementations employing copper for conductive layers, in one example the trace thickness 118 of an ultra-wide copper trace is at least 0.5 ounces per square foot (i.e., at least 0.67 to 0.7 mils of copper) and less than 2.0 ounces per square foot (i.e., less than 2.7 to 2.8 mils of copper). Accordingly, while in one aspect the ultra-wide trace 120A is significantly wider than a conventional impedance-controlled trace, in another aspect it may be thinner than conductive elements typically employed for high-current DC or near-DC power distribution applications on a PCB (which typically employ at least 2.0 ounce per square foot or greater of copper and are often disposed on an outer layer of a PCB to effectively dissipate heat). The Inventors have also recognized and appreciated that, in consideration of RF signals being carried by the ultrawide trace 120, there is not necessarily a need for relatively thicker copper; the skin effect arising from RF signals often limits the depth of current being carried by the ultra-wide trace to less than (and in some instance significantly less than) the thickness of the trace.|00611 In FIG. 4, the multiplayer PCB 100 also includes a first return conductor 126 formed in a second layer 114 of the stack-up (e.g., comprising second copper). As shown in FIG. 4, at least a portion of the first electrically-insulating material 124 of the stack-up (e.g., the core) is disposed between the ultra-wide trace 120A and the return conductor 126. In such an arrangement, the ultra-wide trace 120 A and the return conductor 126 constitute at least a portion of a PCB radio frequency (RF) transmission line 130. A characteristic impedance of the PCB RF transmission line 130 is based at least in part on the width 122 of the ultra-wide trace 120A, the thickness 118 of the ultra-wide trace 120A, a first dielectric constant (En) 132A of the first electrically-insulating material 124, and a first thickness 134A of the first electrically-insulating material 124. f0062| In one inventive aspect, one or more of the width 122 of the ultra-wide impedance- controlled trace 120A, the thickness 118 of the ultra-wide trace 120A, the first dielectric constant 132A of the first electrically-insulating material 124 or the first thickness 134A of the first electrically-insulating material is selected such that the characteristic impedance of the PCB RF transmission line 130 is less than or equal to 10 ohms. In other inventive aspects, one or more of the foregoing parameters may be selected such that the characteristic impedance of the PCB RF transmission line 130 is less than or equal to 5 ohms, or less than or equal to 2 ohms. As also noted earlier, at the time of this disclosure, conventional PCB manufacturers would not consider designing or building a controlled-impedance PCB with the characteristic impedances contemplated herein (e.g., 10 ohms or less). Moreover, multiple examples ofAttorney Docket No.: BRLN-009W001 conventional PCB transmission line impedance calculators (e.g., available online from various sources) provide non-sensical answers for characteristic impedance (e.g., a negative characteristic impedance) when provided with ultra-wide impedance-controlled trace widths for transmission line conductors in the ranges contemplated herein (e.g., 5 millimeters to 30 millimeters).

[0063] In the example of FIG. 4, the first layer 112 in which the ultra-wide trace 120A is implemented and the second layer 114 in which the return conductor 126 is implemented are “neighboring” layers of the stack-up 110 (e.g., there is only one intervening electrically- insulating material 124). It should be appreciated, however, that an ultra-wide trace and a return conductor constituting at least a portion of a PCB transmission line need not necessarily be implemented on neighboring layers of the stack-up.

[0064] FIG. 5 shows a top-down view (i.e., in the x-y plane) of at least a portion the multilayer PCB of FIG. 4, illustrating the ultra-wide impedance-controlled trace 120 A formed in the first layer (shown in FIG. 5 in black), superimposed on the return conductor 128 formed in the second layer (shown in FIG. 5 in gray) to constitute at least a portion of the ultra-low impedance PCB radio frequency (RF) transmission line 130. It should be appreciated that the top-down view of FIG. 5 is created using respective Gerber files for one example implementation of the first layer (shown in black) and the second layer (shown in gray); accordingly, other layers of the PCB stack-up shown in FIG. 4 are not reflected in FIG. 5. As an exemplary frame of reference, the cross-sectional view of FIG. 4 is taken along the dashed line A-A shown in FIG. 5. From the perspective of the x-y plane, the significant width 122 of the ultra-wide trace 120A vis a vis the return conductor 128 may be readily appreciated.

[0065] FIG. 6 illustrates a cross-sectional view of another example of a multilayer PCB 100-1 according to the inventive concepts disclosed herein. The multiplayer PCB 100-1 of FIG. 6 comprises a stack-up 110 having six conductive layers (designated generically in the figure by LI, L2, L3, L4, L5 and 1.6), in which multiple ultra-wide impedance-controlled traces 120 A and 120B are formed, together with two return conductors 126 and 144, to provide a modified stripline ultra-low impedance PCB RF transmission line 130.

[0066] In the following discussion of FIG. 6, ordinal adjectives for respective layers of the stack-up 110 build upon the previous description above of implementation examples involving four-layer stack-ups 110. Accordingly, whereas the first layer 112 of the four-layer stack-up shown in FIGS. 4 corresponds to the generic level designation L2 of the four-layer stack-up,Attorney Docket No.: BRLN-009W001 the first layer 112 of the six-layer stack-up shown in FIG. 6 (in which the first ultra-wide trace 120A is formed) instead corresponds to the generic level designation L4 in the six-layer stack- up. Similarly, the second layer 114 corresponds to the generic level designation L5 in the six- layer stack up (as opposed to generic level designation L3 in the four-layer stack-up), the third layer 142 corresponds to the generic level designation L2 in the six-layer stack-up (as opposed to the generic level designation LI in the four-layer stack-up), and the fourth layer 116 corresponds to the generic level designation L6 in the six-layer stack-up (as opposed to the generic level designation L4 in the four-layer stack-up). Respective elements that appear in the various examples of a four-layer stack-up discussed above and that also appear in the six- level stack-up shown in FIG. 6 are designated with the same reference numbers.

[0067] With reference now to FIG. 6, and building upon what has been already described above in connection with FIG. 4, the six-level stackup shown in FIG. 6 further includes a fifth layer 148 (e.g., comprising fifth copper), and a fourth electrically-insulating material 150 at least partially disposed between the fifth layer 148 and the first layer 112. As can be seen in FIG. 6, the multilayer PCB 100-1 further comprises a second ultra-wide impedance-controlled copper trace 120B formed in the fifth layer 148 of the stack-up. Accordingly, the PCB RF transmission line 130 comprises the first ultra-wide trace 120A, the second ultra-wide trace 120B, the first return conductor 126, and the second return conductor 148. In the example depicted in FIG. 6, the second ultra- wide trace 120B has the same width 122 as the first ultrawide trace 120A (and the same thickness 118 as the first ultra-wide trace 120A).

[0068] In the configuration shown in FIG. 6, the characteristic impedance of the PCB RF transmission line 130 is based at least in part on the width 122 of the first ultra-wide trace 120A and the second ultra-wide trace 120B, the thickness 118 of the first ultra-wide trace, the first dielectric constant 132A of the first electrically-insulating material 124, the first thickness 134A of the first electrically-insulating material, the third dielectric constant 132C of the third electrically-insulating material 146, the third thickness 134C of the third electrically-insulating material, a fourth dielectric constant 164 of the fourth electrically-insulating material, and a fourth thickness 166 of the fourth electrically-insulating material. In one aspect, one or more of the foregoing parameters is selected such that the characteristic impedance of the PCB RF transmission line 130 is less than or equal to 10 ohms (or less than or equal to 5 ohms, or less than or equal to 2 ohms).

[0069] In the six-layer stack-up 110 shown in FIG. 6, the respective return conductors 126 and 144 are electrically interconnected by one or more second vias 152. Notably, in theAttorney Docket No.: BRLN-009W001 configuration shown in FIG. 6, the respective ultra-wide traces 120 A and 120B are electrically interconnected by one or more first vias 154. In FIG. 6 the fourth layer 116 constitutes a first outer layer of the stack-up and comprises the first contact portion 156A coupled to at least the first via 154 to facilitate electrical connection to the first ultra-wide trace 120A and the second ultra-wide trace 120B. In some examples the first contact portion 156A may be an annular first contact portion to facilitate the electrical connection to the first and second ultra-wide traces. FIG. 6 also shows a bottom soldermask 172, in which a first opening 174 is made to allow access to the first contact portion 156A.

[0070] In FIG. 6, the stack-up 110 further comprises a sixth layer 158 (e.g., comprising sixth copper), and a fifth electrically-insulating material 160 at least partially disposed between the sixth layer 158 and the third layer 142. The sixth layer constitutes a second outer layer of the stack-up 110 and comprises at least the second contact portion 156B. As can be seen in FIG. 6, the second contact portion 156B is coupled to the second via 152 to facilitate electrical connection to the first return conductor 126 and the second return conductor 144. FIG. 6 also shows a top soldermask 176, in which a second opening 178 is made to allow access to the second contact portion 156A.

[0071] Although multiple salient aspects of the discussion above involve ultra-wide impedance-controlled traces and / or ultra-low characteristic impedance PCB transmission lines, the Inventors have recognized and appreciated that the modified stripline transmission line configuration shown in FIG. 6 provides multiple novel advantages, irrespective of the width of respective traces and range of characteristic impedance.

[0072] For example, the design of a transmission line using a six-layer stack-up, with two inner layers of the stack-up electrically coupled together as the “signal” conductors of the transmission line, allows for a “dielectrically-balanced” implementation. The Inventors have recognized and appreciated that a six-layer stack-up provides for a dielectrically-balanced transmission line design. More specifically, in one example implementation, the electrically- insulating material 124, between the first trace 120A (a first “signal” conductor) and the first return conductor 126, as well as the electrically-insulating material 146 between the second trace 120B (a second “signal” conductor) and the second return conductor 144, both may be core and have the same dielectric constant (i.e., Eri = En). The thickness and dielectric constant of core is relatively more stable and predictable during the fabrication process, thus arguably leading to more predictable outcomes in target characteristic impedance. Also, the symmetrical arrangement of core as the dielectric material between each signal conductor andAttorney Docket No.: BRLN-009W001 a corresponding return conductor arguably provides for a more symmetric current flow in the respective return conductors. Additionally, in one example, the electrically-insulating material 164 between the first trace 120A (the first “signal” conductor) and the second trace 120B (the second “signal” conductor) may be prepreg. Even though the dielectric constant and / or thickness of this prepreg may vary to some extent during fabrication, arguably any such variation would have an attenuated affect on the resulting characteristic impedance of the transmission line (as the first signal conductor and the second signal conductor are electrically interconnected). Thus, the dielectrically-balanced design of FIG. 6 may not only facilitate a more balanced current flow in the respective conductors, but may further facilitate a more predictable characteristic impedance (across multiple manufacturing runs).

[0073] Another prospective advantage of the six-layer stack-up shown in FIG. 6 for a modified stripline transmission line design involving two signal conductors relates to increased currentcarrying capability. In some examples, the increased current-carrying capability relates, at least in part, to the well-known “skin effect” arising from RF signals carried on the transmission line. As known in the relevant arts, the “skin effect” is an alternating-current (AC) phenomenon where, at relatively higher frequencies, current concentrates near a conductor's surface rather than in the center of the conductor. This occurs because the changing magnetic field induces opposing currents (eddy currents) inside the conductor, thereby increasing resistance and power loss, especially at higher frequencies - essentially, the conductor behaves as if it has a smaller cross-section.

[0074] In the configuration shown in FIG. 6 in which there are two signal conductors electrically coupled together (i.e., the trace 120A and the trace 120B), current in the trace 120A will in some instances be concentrated along the bottom surface of the trace (i.e., facing the first return conductor 126), but generally not along the top surface of the trace 120 A (which faces the other signal trace 120B). Similarly, current in the trace 120B will be concentrated along the top surface of the trace (i.e., facing the second return conductor 144), but generally not along the bottom surface of the trace 120B (which faces the other signal trace 120A). Accordingly, it may be appreciated from the foregoing that the respective signal conductors in the configuration of FIG. 6 (i.e., the traces 120A and 120B) each may carry on the order of half of the current that would otherwise be carried on both the top and bottom surfaces of a single signal trace in a conventional stripline configuration.

[0075] Thus, for at least the foregoing reasons, it may be appreciated that the modified stripline transmission line configuration shown in FIG. 6 (e.g., involving two electrically-connectedAttorney Docket No.: BRLN-009W001 signal traces on respective inner layers of a multilayer stack-up) provides multiple novel advantages, irrespective of the specific width of the respective traces serving as signal conductors (i.e., even if the width of the traces falls within a conventional range of impedance- controlled traces on the order of 5-20 mils), and irrespective of the characteristic impedance of the transmission line (i.e., even if the characteristic impedance falls within a conventional range of 25 ohms or above). Of course, it may be appreciated from the disclosure herein that these and other possible advantages may be provided in example implementations involving ultra-wide impedance controlled traces and / or ultra-low characteristic impedance transmission lines. It should further be appreciated that although the example of a modified stripline transmission line involving two signal conductors was shown in FIG. 6 using a six-layer stack- up, a similar configuration of two electrically-connected signal conductors on respective inner layers of a stack-up, surrounded by respective return conductors, similarly may be implemented in a four-layer stack-up, or a stack-up having more than six layers.

[0076] With reference again to FIG. 1, based on the six-layer stack-up 110 of the multilayer PCB 100-1 shown in FIG. 6, an illustrative non -limiting example of a testing channel 202 for the TDR system 200 may be effectively implemented that includes an ultra-low impedance PCB RF transmission line 130 having two ultra-wide impedance controlled traces 120A and 120B. In one aspect, such a testing channel 202 may be implemented with a probe 203 that is particularly configured to engage with a test target 204 (DUT) having a circular or annular electrical connection. However, it should be appreciated that various examples of testing channels 202 employing one or more ultra-low impedance PCB RF transmission lines 130 having one or more ultra-wide impedance-controlled traces may have a variety of probe configurations to accommodate different types of test targets 204 (e.g., impedance-controlled traces on PCB boards, cables, wires and wire harnesses, various connectors and Interfaces, antennas, transmission lines of various form factors, underground utilities, power distribution systems, and semiconductor packages).

[0077] Following below are brief descriptions of respective figures that provide an overview of the respective layers of a six-layer stack-up to implement a test channel based on an ultralow impedance PCB RF transmission line employing two ultra-wide impedance-controlled traces on respective layers of the stack-up.

[0078] FIG. 7 shows a Gerber file for a top soldermask of a testing channel of a TDR system according to one inventive example implementation based on the multilevel PCB employing the six-layer stack-up shown in FIG. 6.Attorney Docket No.: BRLN-009W001

[0079] FIG. 8 shows a Gerber file for layer 1 (LI) of the example testing channel based on the multilevel PCB employing the six -layer stack-up shown in FIG. 6.(0080] FIG. 9 shows a Gerber file for layer 2 (L2) of the example testing channel based on the multilevel PCB employing the six -layer stack-up shown in FIG. 6.

[0081] FIG. 10 shows a Gerber file for layer 3 (L3) of the example testing channel based on the multilevel PCB employing the six-layer stack-up shown in FIG. 6, wherein L3 includes a first ultra-wide trace according to some of the inventive concepts disclosed herein.

[0082] FIG. 11 shows a Gerber file for layer 4 (L4) of the example testing channel based on the multilevel PCB employing the six-layer stack-up shown in FIG. 6, wherein L4 includes a second ultra-wide trace according to some of the inventive concepts disclosed herein.

[0083] FIG. 12 shows a Gerber file for layer 5 (L5) of the example testing channel of the multilevel PCB employing the six -layer stack-up shown in FIG. 6.

[0084] FIG. 13 shows a Gerber file for layer 6 (L6) of the example testing channel of the multilevel PCB employing the six -layer stack-up shown in FIG. 6.

[0085] FIG. 14 shows a Gerber file for drill holes for vias that pass through all levels of the example testing channel based on the multilevel PCB employing the six-layer stack-up shown in FIG. 6.

[0086] FIG. 15 shows a Gerber file for drill holes for blind vias that pass through only some of the levels of the of the example testing channel based on the multilevel PCB employing the six-layer stack-up shown in FIG. 6.

[0087] FIG. 16 shows a fabrication drawing for the example testing channel based on the multilevel PCB employing the six -layer stack-up shown in FIG. 6.CONCLUSION

[0088] All parameters, dimensions, materials, and configurations described herein are meant to be example and the actual parameters, dimensions, materials, and / or configurations may in some instances depend upon the specific application or applications for which the inventive teachings is / are used. It is to be understood that the foregoing embodiments are presented primarily by way of example and that inventive embodiments may be practiced otherwise than as specifically described. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein.Attorney Docket No.: BRLN-009W001

[0089] In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure. Other substitutions, modifications, changes, and omissions may be made in the design, operating conditions and arrangement of respective elements of the example implementations without departing from the scope of the present disclosure. The use of a numerical range does not preclude equivalents that fall outside the range that fulfill the same function, in the same way, to produce the same result.

[0090] The above-described embodiments can be implemented in multiple ways. For example, embodiments may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on a suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

[0091] Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electrical device.

[0092] Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible format.

[0093] Such computers may be interconnected by one or more networks in a suitable form, including a local area network or a wide area network, such as an enterprise network, an intelligent network (IN) or the Internet. Such networks may be based on a suitable technology, may operate according to a suitable protocol, and may include wireless networks, wired networks or fiber optic networks.

[0094] The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems orAttorney Docket No.: BRLN-009W001 platforms. Additionally, such software may be written using any of a number of suitable programming languages and / or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine. Some implementations may specifically employ one or more of a particular operating system or platform and a particular programming language and / or scripting tool to facilitate execution.

[0095] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0096] All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.

[0097] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0098] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0099] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0100] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, butAttorney Docket No.: BRLN-009W001 also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e., “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.[0101 j As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.[0102| In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

Attorney Docket No.: BRLN-009W001CLAIMS1. A time domain reflectometry (TDR) controlled-impedance testing system (200), comprising: a signal generator (214) to provide at least one test signal (225); at least one testing channel (202) to couple the at least one test signal to a test target (204); and a sampling gate (216) to sample a combined signal (205) including the test signal and a reflected signal from the test target, wherein the at least one testing channel is configured to have a characteristic impedance of less than 10 ohms.

2. The TDR testing system of claim 1, wherein the at least one testing channel is configured to have an impedance of approximately, equal to, or less than 5 ohms.

3. The TDR testing system of claim 1, wherein the at least one testing channel is configured to have an impedance of approximately, equal to, or less than 2 ohms.

4. The TDR system of claim 1, wherein the at least one testing channel includes an ultralow impedance printed circuit board (PCB) radio frequency (RF) transmission line (130) having the characteristic impedance of less than 10 ohms.

5. The TDR system of claim 4, wherein: the ultra-low impedance PCB RF transmission line includes at least one ultra-wide impedance controlled trace (120 A); and a width of the at least one ultra-wide impedance controlled trace is at least 5 millimeters or 200 mils.

6. The TDR system of claim 1, wherein the signal generator and the sampling gate are impedance-matched to the at least one testing channel.

7. The TDR system of claim 1, wherein the sampling gate includes at least a first portion of the at least one testing channel.Attorney Docket No.: BRLN-009W0018. The TDR system of claim 7, wherein the first portion of the at least one testing channel includes a first ultra-low impedance printed circuit board (PCB) radio frequency (RF) transmission line (130) having the characteristic impedance of less than 10 ohms.

9. The TDR system of claim 8, wherein: the sampling gate comprises a plurality of transmission line segments 236 interconnected by a plurality of diodes 234; the first portion of the at least one testing channel includes the plurality of transmission line segments; and at least one transmission line segment of the plurality of transmission line segments includes the first ultra-low impedance PCB RF transmission line.

10. The TDR system of claim 9, wherein the signal generator includes a second ultra-low impedance PCB RF transmission line having the characteristic impedance of less than 10 ohms.

11. A time domain reflectometry (TDR) controlled-impedance testing system, comprising: at least one testing channel to couple at least one test signal to a test target, the at least one testing channel having an impedance of less than 10 ohms.

12. The TDR testing system of claim 11, wherein the at least one testing channel has an impedance of approximately, equal to, or less than 5 ohms.

13. The TDR testing system of claim 11, wherein the at least one testing channel has an impedance of approximately, equal to, or less than 2 ohms.

14. The TDR testing system of any of claims 11 to 13, wherein the impedance of the at least one testing channel is substantially constant over a range of frequencies up to approximately or equal to 7 GHz.Attorney Docket No.: BRLN-009W00115. The TDR testing system of any of claims 11 to 13, wherein the impedance of the at least one testing channel is substantially constant over a range of frequencies up to approximately or equal to 20 GHz.

16. The TDR testing system of any of claims 11 to 13, wherein the impedance of the at least one testing channel is substantially constant over a range of frequencies over a range of frequencies from approximately 100 kHz to 1 GHz.

17. The TDR system of any of claims 11 to 16, further comprising at least one printed circuit board (PCB) including at least one transmission line constituting at least a portion of the at least one testing channel.

18. The TDR system of claim 17, wherein the at least one transmission line is a microstrip transmission line.

19. The TDR system of claim 17, wherein the at least one transmission line is a stripline transmission line.

20. The TDR system of claim 17, wherein the at least one transmission line is a coplanar waveguide transmission line.

21. The TDR system of any of claims 17 to 20, wherein the at least one transmission line includes at least one ultra-wide trace.

22. The TDR system of claim 21, wherein the ultra-wide trace has a width of at least 300 mils or at least 7.62 millimeters.

23. The TDR system of claim 21, wherein the ultra- wide trace has a width of at least 400 mils or at least 10.16 millimeters.

24. The TDR system of claim 21, wherein the ultra-wide trace has a width of at least 500 mils or at least 12.7 millimeters.

25. The TDR system of claim 21, wherein the ultra- wide trace has a width of at least 800 mils or 20.3 millimeters.Attorney Docket No.: BRLN-009W00126. The TDR system of any of claims 21 to 25, wherein: the ultra-wide trace is an ultra-wide copper trace; and the ultra-wide copper trace has a thickness of 1 ounce per square foot or approximately 1.37 mils.

27. The TDR system of any of claims 17 to 26, wherein: the printed circuit board includes an electrically insulating base material; and the electrically insulating base material comprises FR4.

28. The TDR system of claim 27, wherein at least some of the electrically insulating base material comprises prepreg.

29. The TDR system of any of claims 17 to 26, wherein: the printed circuit board includes an electrically insulating base material; and the electrically insulating base material comprises only FR4.

30. The TDR system of any of claims 17 to 29, wherein the printed circuit board is a multilayer printed circuit board comprising a stack-up.

31. The TDR system of claim 30, wherein the stack-up of the multilayer printed circuit board includes at least six layers.

32. The TDR system of claim 30 or claim 31, wherein the multilayer printed circuit board comprises: a first inner layer including a first ultra-wide trace; a second inner layer adjacent to the first inner layer, the second inner layer including a second ultra-wide trace electrically coupled to the first ultra-wide trace on the first inner layer; and a third layer adjacent to the first inner layer, the third layer including a first return plane, wherein the first ultra-wide trace, the second ultra-wide trace and the first return plane form the at least one transmission line.Attorney Docket No.: BRLN-009W00133. The TDR system of any of claims 30 to 32, wherein the at least one transmission line includes an annular portion on at least one outer layer of the stack-up to facilitate electrical connection to the at least one transmission line.

34. The TDR system of claim 33, further comprising a plurality of blind vias electrically connecting the annular portion and at least one conductor of the at least one transmission line on at least one inner layer of the stack-up.

35. A time domain reflectometry (TDR) controlled-impedance testing system, comprising: at least one printed circuit board (PCB) to provide at least one testing channel to couple at least one test signal to a test target, the at least one PCB comprising: at least one ultra-wide impedance-controlled trace having a width of at least 200 mils or at least 5 millimeters; and at least one return plane, wherein the at least one ultra-wide trace and the at least one return plane constitute at least a portion of a low impedance transmission line having an impedance of less than 10 ohms.

36. The TDR testing system of claim 35, wherein the low impedance transmission line has an impedance of approximately, equal to, or less than 5 ohms.

37. The TDR testing system of claim 35, wherein the low impedance transmission line has an impedance of approximately, equal to, or less than 2 ohms.

38. The TDR testing system of any of claims 35 to 37, wherein the impedance of the low impedance transmission line is substantially constant over a range of frequencies up to approximately or equal to 7 GHz.

39. The TDR testing system of any of claims 35 to 37, wherein the impedance of the low impedance transmission line is substantially constant over a range of frequencies up to approximately or equal to 20 GHz.Attorney Docket No.: BRLN-009W00140. The TDR testing system of any of claims 35 to 37, wherein the impedance of the low impedance transmission line is substantially constant over a range of frequencies from approximately 100 kHz to 1 GHz.

41. The TDR system of any of claims 35 to 40, wherein the at least one transmission line is a microstrip transmission line.

42. The TDR system of any of claims 35 to 40, wherein the at least one transmission line is a stripline transmission line.

43. The TDR system of any of claims 35 to 40, wherein the at least one transmission line is a coplanar waveguide transmission line.

44. The TDR system of any of claims 35 to 43, wherein the ultra-wide trace has a width of at least 400 mils or at least 10.16 millimeters.

45. The TDR system of any of claims 35 to 43, wherein the ultra- wide trace has a width of at least 500 mils or at least 12.7 millimeters.

46. The TDR system of any of claims 35 to 43, wherein the ultra-wide trace has a width of at least 800 mils or 20.3 millimeters.

47. The TDR system of any of claims 35 to 46, wherein: the ultra-wide trace is an ultra-wide copper trace; and the ultra-wide copper trace has a thickness of 1 ounce per square foot or approximately 1.37 mils.

48. The TDR system of any of claims 35 to 47, wherein: the printed circuit board includes an electrically insulating base material; and the electrically insulating base material comprises FR4.

49. The TDR system of claim 48, wherein at least some of the electrically insulating base material comprises prepreg.

50. The TDR system of any of claims 35 to 49, wherein:Attorney Docket No.: BRLN-009W001 the printed circuit board includes an electrically insulating base material; and the electrically insulating base material comprises only FR4.

51. The TDR system of any of claims 35 to 50, wherein the printed circuit board is a multilayer printed circuit board comprising a stack-up.

52. The TDR system of claim 51, wherein the stack-up of the multilayer printed circuit board includes at least six layers.

53. The TDR system of claim 51 or claim 52, wherein the multilayer printed circuit board comprises: a first inner layer including a first ultra-wide trace; a second inner layer adjacent to the first inner layer, the second inner layer including a second ultra-wide trace electrically coupled to the first ultra-wide trace on the first inner layer; and a third layer adjacent to the first inner layer, the third layer including a first return plane, wherein the first ultra-wide trace, the second ultra-wide trace and the first return plane form the low impedance transmission line.

54. The TDR system of any of claims 51 to 53, wherein the low impedance transmission line includes an annular portion on at least one outer layer of the stack-up to facilitate electrical connection to the low impedance transmission line.

55. The TDR system of claim 54, further comprising a plurality of blind vias electrically connecting the annular portion and at least one conductor of the low impedance transmission line on at least one inner layer of the stack-up.

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