Transformer-type differential series resonant cavity, differential series resonant oscillator, chip and device

Abstract

Disclosed in the present invention are a transformer-type differential series resonant cavity, a differential series resonant oscillator, a chip and a device. The resonant cavity comprises: a two-port transformer and a variable capacitor module, wherein the two-port transformer contains an inductor LP1, an inductor LP2, an inductor LS1 and an inductor LS2 which are coupled to each other; the variable capacitor module comprises a variable capacitor CP and a variable capacitor CS; one end of the inductor LP1 is connected to a first port, and the other end thereof is connected to the variable capacitor CP; one end of the inductor LP2 is connected to a second port, and the other end thereof is connected to the variable capacitor CP; one end of the inductor LS1 and one end of the inductor LS2 are respectively connected to a third port and a fourth port, and the other end of the inductor LS1 and the other end of the inductor LS2 are connected to each other; two ends of the variable capacitor CS are respectively connected to the third port and the fourth port; and the frequencies of a plurality of poles of a voltage gain function AV are set to be equal, such that AV at a zero phase is increased. The present invention solves the problem of it being impossible for a series resonant oscillator to realize a pure differential output in a current pure CMOS process.

Description

Transformer-type differential series resonant cavity, differential series resonant oscillator, chip and device Technical Field

[0001] This invention relates to a local oscillator generation circuit for mixing in wireless communication systems, and more particularly to a transformer-type differential series resonant cavity, a differential series resonant oscillator, a chip, and a device. Background Technology

[0002] In high-speed wireless and wired communications, as well as high-speed digital-to-analog (DAC) / analog-to-digital (ADC) systems, ultra-low phase noise voltage-controlled oscillators (VCOs) are often required. According to Leeson's formula, the phase noise of a VCO can be reduced by increasing the cavity voltage or decreasing the cavity inductance. However, the maximum voltage across the cavity is limited by manufacturing processes, and excessively reducing the inductance degrades the cavity's quality factor. Therefore, it is difficult to further reduce the phase noise of traditional VCOs. Multi-core VCOs are another solution for reducing phase noise; however, when ultra-low phase noise is required, this solution faces challenges such as large on-chip area, severe inter-core mismatch, and complex power supply networks.

[0003] In recent years, series resonant voltage-controlled oscillators (VCOs) have been proven to achieve ultra-low phase noise in single-core architectures. To achieve series resonance, the first existing technology uses an inverter to drive a series resonant cavity composed of an inductor and a capacitor connected in series. The voltage across the capacitor in the resonant cavity is extracted and applied to the input of the next-stage inverter. Finally, a combination of four inverters and a series resonant cavity is cascaded together to form a series resonant oscillator, achieving quadrature signal output. However, this technology requires four discrete inductors, resulting in a large chip area.

[0004] The second prior art solution, based on the first prior art solution, replaces the inductor in the series resonant cavity with a transformer. The primary winding of the transformer consists of a capacitor connected in series with the transformer's primary inductor, while the secondary winding consists of a capacitor connected in parallel with the transformer's secondary inductor. The inverter output drives the primary winding, and the voltage at the transformer's secondary winding is applied to the input of the next-stage inverter. Finally, a combination of four inverters and a transformer-type series resonant cavity is cascaded together to form a series resonant oscillator, achieving quadrature signal output. However, this solution suffers from mode ambiguity, meaning there are two different oscillation frequencies. Furthermore, both the first and second prior art solutions can only achieve quadrature output, not pure differential output.

[0005] The third existing technical solution uses a series resonant cavity composed of an inductor and a capacitor connected in series. The series resonant cavity is placed at the source of the cross-coupled transistor to realize a differential series resonant oscillator. Although this solution can achieve differential output, the differential structure topology has not yet been realized on pure CMOS process and requires an additional bias inductor, which occupies a large chip area. Summary of the Invention

[0006] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a transformer-type differential series resonant cavity, differential series resonant oscillator, chip and device based on pole aggregation technology.

[0007] The first technical solution adopted in this invention is:

[0008] A transformer-type differential series resonant cavity includes a two-port transformer and a variable capacitor module. The two-port transformer contains inductors L that are coupled in pairs. P1 Inductor L P2 and inductor L S1 Inductor L S2 The variable capacitor module includes a variable capacitor C. P and variable capacitor C S ;

[0009] The inductor L P1 The terminal with the same name is connected to the first port, and the terminal with the different name is connected to the variable capacitor C. P The inductor L P2 The opposite-named terminal is connected to the second port, and the same-named terminal is connected to the variable capacitor C. P ;

[0010] The inductor L S1 heteronym terminals and inductor L S2 The terminals with the same name are connected to the third and fourth ports respectively, and the inductor L S1 The same terminal and inductor L S2 The opposite terminals are connected to each other; the variable capacitor C S The two ends are connected to the third port and the fourth port respectively;

[0011] The voltage gain function A of the transformer-type differential series resonant cavity V The multiple pole frequencies are set to be equal, so that A at zero phase... V Increase.

[0012] Furthermore, the variable capacitor C P Includes a first switched capacitor array and a variable capacitor C VP1 and variable capacitor C VP2 The first switched capacitor array is connected to inductors L at both ends. P1 and inductor LP2 The other end; the variable capacitor C VP1 and variable capacitor C VP2 One end is connected to the control voltage V TUNEP The variable capacitor C VP1 and variable capacitor C VP2 The other end is connected to both ends of the first switched capacitor array;

[0013] The variable capacitor C S Includes a second switched capacitor array and a variable capacitor C VS1 and variable capacitor C VS2 The two ends of the second switched capacitor array are respectively connected to inductors L. S1 and inductor L S2 One end; the variable capacitor C VS1 and variable capacitor C VS2 One end is connected to the control voltage V TUNES The variable capacitor C VS1 and variable capacitor C VS2 The other end is connected to both ends of the second switched capacitor array.

[0014] Furthermore, the variable capacitor C P Includes a first switched capacitor array and a variable capacitor C VP1 and variable capacitor C VP2 The first switched capacitor array is connected to inductors L at both ends. P1 and inductor L P2 The other end; the variable capacitor C VP1 and variable capacitor C VP2 One end is connected to the control voltage V TUNEP The variable capacitor C VP1 and variable capacitor C VP2 The other end is connected to both ends of the first switched capacitor array;

[0015] The variable capacitor C S It includes a second switched capacitor array, with inductors L connected to both ends of the second switched capacitor array. S1 and inductor L S2 One end.

[0016] Furthermore, both the first and second switched capacitor arrays are NMOS-based switched capacitor arrays, and the switched capacitor arrays include multiple switched capacitor units.

[0017] The switched capacitor unit includes transistor M. N Resistance R B1 Resistance R B2 Switched capacitor CU1 Switched capacitor C U2 The third inverter, the fourth inverter, and the fifth inverter;

[0018] The switched capacitor C U1 One end is connected to transistor M N The drain of the capacitor, the switched capacitor C U1 The other end is connected to one end of the switched capacitor array;

[0019] The switched capacitor C U2 One end is connected to transistor M N The source of the switched capacitor C U2 The other end is connected to the other end of the switched capacitor array;

[0020] The resistor R B1 One end is connected to transistor M N The drain of the resistor R B2 One end is connected to transistor M N The source; the enable signal EN is applied to transistor M after passing through the third and fourth inverters in sequence. N The gate; the enable signal EN, after passing through the fifth inverter, is applied to resistor R. B1 The other end and resistor R B2 The other end.

[0021] Furthermore, both the first and second switched capacitor arrays are switched capacitor arrays based on complementary switches, and the switched capacitor array includes multiple switched capacitor units.

[0022] The switched capacitor unit includes transistor M. P Transistor M N Resistance R B1 Resistance R B2 Switched capacitor C U1 Switched capacitor C U2 The third inverter, the fourth inverter, and the fifth inverter;

[0023] The transistor M P The drain and transistor M N The drains of the transistors are connected, and the connection point is denoted as point A; the transistor M P The source and transistor M N The source poles are connected, and the connection point is denoted as point B;

[0024] The switched capacitor C U1 One end is connected to point A, and the switched capacitor is connected to point C. U1 The other end is connected to one end of the switched capacitor array;

[0025] The switched capacitor C U2One end is connected to point B, and the switched capacitor is connected to point C. U2 The other end is connected to the other end of the switched capacitor array;

[0026] The resistor R B1 One end of the resistor R is connected to point A. B2 Connect one end to point B;

[0027] The enable signal EN is applied to transistor M after passing through the third inverter. P The gate of the transistor is activated, and the enable signal EN is applied to transistor M after passing through the third and fourth inverters in sequence. N The gate; the enable signal EN, after passing through the fifth inverter, is applied to resistor R. B1 The other end and resistor R B2 The other end.

[0028] The second technical solution adopted in this invention is:

[0029] A differential series resonant oscillator includes a differential driver and a transformer-type differential series resonant cavity as described above;

[0030] The differential output terminal of the differential driver is connected to the first and second ports of the transformer-type differential series resonant cavity; the differential input terminal of the differential driver is connected to the third and fourth ports of the transformer-type differential series resonant cavity.

[0031] Furthermore, the differential driver includes two inverters with identical structures and two capacitors C. B1 C B2 The input terminal of the differential driver is connected to capacitor C. B1 C B2 One end, capacitor C B1 C B2 The other end is connected to the input terminals of two inverters; the output terminals of the two inverters serve as the output terminals of the differential driver.

[0032] The inverter consists of an NMOS transistor, a PMOS transistor, and a resistor R. FB The inverter is composed of two transistors whose gates are connected together as the input and two transistors whose drains are connected together as the output. A resistor R... FB The two ends are connected to the input and output terminals of the inverter, respectively; the source of the NMOS transistor is connected to ground, and the source of the PMOS transistor is connected to the power supply.

[0033] Furthermore, the differential driver includes two inverters with identical structures and two capacitors C. B1 C B2 The input terminal of the differential driver is connected to capacitor C. B1 C B2One end, capacitor C B1 C B2 The other end is connected to the input terminals of two inverters; the output terminals of the two inverters serve as the output terminals of the differential driver.

[0034] The inverter consists of a first NMOS transistor, a second NMOS transistor, and a resistor R. B The inverter is composed of two transistors whose gates are connected together as the input terminal, and the source of the first NMOS transistor and the drain of the second NMOS transistor connected together as the output terminal. A resistor R... B One end is connected to the input of the inverter, and the other end is connected to the power supply; the drain of the first NMOS transistor is connected to the power supply, and the source of the second NMOS transistor is connected to ground.

[0035] Furthermore, the differential driver includes two inverters with identical structures; the input and output terminals of the two inverters are respectively connected to the input and output terminals of the differential driver.

[0036] The inverter is composed of an NMOS transistor and a PMOS transistor. The gates of the two transistors are connected to form the input terminal of the inverter, and the drains of the two transistors are connected to form the output terminal of the inverter. The source of the NMOS transistor is connected to ground, and the source of the PMOS transistor is connected to the power supply.

[0037] In the transformer-type differential series resonant cavity, the inductor L S1 and inductor L S2 One end is connected to the external bias voltage V B Connected, bias voltage V B Through inductor L S1 and inductor L S2 The voltage reaches the input terminal of the inverter and serves as the bias voltage for the inverter.

[0038] Furthermore, the differential driver includes two inverters with identical structures; the input and output terminals of the two inverters are respectively connected to the input and output terminals of the differential driver.

[0039] The inverter is composed of a first NMOS transistor and a second NMOS transistor. The gates of the two transistors are connected to form the input terminal of the inverter, and the source and drain of the first NMOS transistor are connected to form the output terminal of the inverter. The drain of the first NMOS transistor is connected to the power supply, and the source of the second NMOS transistor is connected to ground.

[0040] In the transformer-type differential series resonant cavity, the inductor L S1 and inductor L S2 One end is connected to the external bias voltage V B Connected, bias voltage VB Through inductor L S1 and inductor L S2 The voltage reaches the input terminal of the inverter and serves as the bias voltage for the inverter.

[0041] The third technical solution adopted in this invention is:

[0042] A chip includes a differential series resonant oscillator as described above, and a method for implementing the method described above.

[0043] The fourth technical solution adopted in this invention is:

[0044] A communication device comprising a chip as described above.

[0045] The beneficial effects of this invention are: by constructing a transformer-type differential series resonant cavity and using pole-gathering technology, this invention enables the series resonant oscillator to achieve differential operation. It is the first oscillator to achieve differential series resonance on pure CMOS technology, which solves the mode ambiguity problem of transformer-type series resonant oscillators and avoids the large area problem caused by additional bias inductors. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 is a schematic diagram of the transformer-type differential series resonant cavity of the present invention;

[0048] Figure 2 is a schematic diagram of the differential series resonant oscillator of the present invention;

[0049] Figure 3 is a circuit diagram of the differential series resonant oscillator provided in Embodiment 1 of the present invention;

[0050] Figure 4 is a schematic diagram of the two-port transformer T1 in an embodiment of the present invention;

[0051] Figure 5 is a structural diagram of a switched capacitor array based on complementary switches provided in an embodiment of the present invention;

[0052] Figure 6 shows the test results of the tuning range of the differential series resonant oscillator provided in Embodiment 1 of the present invention;

[0053] Figure 7 is a phase noise test curve of the differential series resonant oscillator provided in Embodiment 1 of the present invention at 7.762 GHz;

[0054] Figure 8 is a phase noise test curve of the differential series resonant oscillator provided in Embodiment 1 of the present invention at 9.122 GHz;

[0055] Figure 9 is a phase noise test diagram of the differential series resonant oscillator provided in Embodiment 1 of the present invention at 1MHz and 10MHz frequency offsets at various frequency points;

[0056] Figure 10 is a test diagram of the FoM value of the differential series resonant oscillator provided in Embodiment 1 of the present invention at frequency offsets of 1MHz and 10MHz at various frequency points;

[0057] Figure 11 is a circuit structure diagram of the differential series resonant oscillator provided in Embodiment 2 of the present invention;

[0058] Figure 12 is a circuit diagram of the differential series resonant oscillator provided in Embodiment 3 of the present invention;

[0059] Figure 13 is a circuit structure diagram of the differential series resonant oscillator provided in Embodiment 4 of the present invention;

[0060] Figure 14 is a circuit structure diagram of the differential series resonant oscillator provided in Embodiment 5 of the present invention;

[0061] Figure 15 is a circuit diagram of the differential series resonant oscillator provided in Embodiment 6 of the present invention. Detailed Implementation

[0062] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0063] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0064] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0065] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0066] In summary, the purpose of this invention is to solve the following technical problems: 1) solving the problem that series resonant oscillators on current pure CMOS processes cannot achieve pure differential output; 2) solving the mode ambiguity problem existing in traditional transformer-type series resonant oscillators; 3) solving the problem that traditional series resonant oscillators occupy a large chip area; 4) solving the problem that the bias resistor of the switched capacitor array circuit in traditional oscillators contributes a large phase noise.

[0067] To address technical problems 1)-3), this invention provides a differential series resonant oscillator employing transformer aggregation technology, which achieves pure differential output on a pure CMOS process. Furthermore, by adjusting the voltage gain function A of the transformer-type series resonant cavity... V By setting the two pole frequencies to be close and using a small transformer magnetic coupling coefficient k, the two peaks of Av converge at the zero-phase point, improving the gain at the zero-phase point of Av. This enhances the performance of the transformer-type series resonant oscillator in differential operation, thus achieving a high-performance pure differential series resonant oscillator. Since the transformer-type series resonant cavity has only one unique zero-phase point, the proposed transformer-type differential series resonant oscillator avoids the mode ambiguity problem of previous transformer-type quadrature series resonant oscillators.

[0068] To address technical problem 4), this invention provides a switched capacitor array circuit employing complementary switches. By simultaneously using NMOS and PMOS transistors as switches, the phase noise introduced by the bias resistors in the switched capacitor array through modulation of the parasitic capacitances of the NMOS and PMOS transistors cancels each other out, thereby reducing the total phase noise contributed by the bias resistors.

[0069] The following detailed description is provided in conjunction with the accompanying drawings and specific embodiments.

[0070] Example 1

[0071] As shown in Figures 1, 2, and 3, the circuit structure of the differential series resonant oscillator provided in this embodiment is as follows:

[0072] The drain and gate terminals of NMOS transistor M1 (M3) are connected to the drain and gate terminals of PMOS transistor M2 (M4), and the resistor R is connected to the gate terminal. FB1 (R FB2 A line is connected between the drain and gate of M1 and M2 (M3 and M4). The sources of M1 and M3 are interconnected and grounded, while the sources of M2 and M4 are interconnected and connected to the power supply V. DD By C P1 C P2 and SW P The two ends of the five-bit switched capacitor array and the varactor C V1 C V2 The two ends are connected, and the variable capacitance tube C v1 C v2 The common terminal is connected to the voltage control signal V. TUNE Inductor L P1 (L P2 ) Connected across the drains of M1 and M2 (M3, M4) and C P1 C V1 (C P2 C V2 Between ) . By C S1 C S2 and SW S The two ends of the five-bit switched capacitor array and the inductor L S1 L S2 The two ends are connected, and the inductor L S1 and L S2 They are directly connected. Capacitor C B1 (C B2 ) connected across the gates of M1, M2 (M3, M4) and C S1 L S1 (C S2 L S2 Between. The gate of transistor M5 (M6) is connected to the drain of M1, M2 (M3, M4), and the output V of the oscillator is... out+ and V out- The drains of transistors M5 and M6 are connected to the ground respectively, and the sources of M5 and M6 are grounded.

[0073] It should be noted that the switched capacitor array used in this embodiment is a five-bit switched capacitor array, but it is not limited to five bits. Different bit values ​​of switched capacitor arrays can be selected according to actual needs.

[0074] As an optional implementation method, L P1 L P2 and L S1 L S2The two-port transformer T1, along with the power supply and ground wires, is shown in Figure 4. The interface sequence is ①②③④⑤⑥⑦⑧. ① and ② correspond to L... S2 The positive electrode and L S1 The negative electrode, ③ and ⑤ correspond to L respectively. P1 The positive and negative electrodes, ④ and ⑥ correspond to L respectively. P2 The negative and positive terminals, ⑦ and ⑧, correspond to the power supply and ground wires, respectively. The inductance L in transformer T1... P1 L P2 and L S1 L S2 Mutually coupled, where L P1 (L P2 ) and L S1 (L S2 ) is a strong coupling with a turns ratio of 1:2.

[0075] As an optional implementation, the switched capacitor array in this embodiment is a complementary switching type switched capacitor array, including multiple switched capacitor units, as shown in Figure 5. The specific circuit structure of the switched capacitor unit is as follows: NMOS transistor M N and PMOS transistor M P The drain and source are connected to each other, and the switched capacitor C U1 and bias resistor R B1 (Switched capacitor C) U2 and bias resistor R B2 Connect to M N and M P The drain (source) of the capacitor, the switched capacitor C U1 (C U2 The other end is connected to a differential series resonant oscillator circuit. The enable signal EN of the switched capacitor array is applied to transistor M after passing through an inverter. P The gate, after passing through another inverter, is loaded onto transistor M. N Gate. The EN signal, after passing through another inverter, is applied to the bias resistor R. B1 and R B2 The other end.

[0076] The working principle of the oscillator will be explained in detail below.

[0077] 1) Working principle of a fully differential, low-phase-noise series resonant voltage-controlled oscillator

[0078] Referring to Figure 3, NMOS transistor M1 (M3), PMOS transistor M2 (M4), and feedback resistor R FB1 (R FB2 This forms a self-biased inverter, providing negative resistance to the oscillator and maintaining oscillation. DD Provides the required power supply voltage for the circuit, with DC current from VDD Initially, the current flows through M2 and M1 (M4 and M3), eventually converging to ground. The inverter outputs (drains of M1, M2, M3, and M4) are driven by L. P1 L P2 L S1 L S2 C P1 C P2 C V1 C V2 C S1 C S2 The transformer-type series resonant cavity, when configured, produces an inverter output voltage close to a square wave. Due to the low input impedance of the series resonant cavity, a large current flows into it, and a significant amount of energy is stored in the inductor and capacitor, resulting in ultra-low phase noise. Because this transformer-type series resonant cavity provides a large voltage gain, C... S1 C S2 L S1 L S2 There is a large voltage swing at both ends (①②). To ensure that the voltage swing does not exceed the maximum value of the process limit after entering the gates of transistors M1, M2, M3, and M4, a capacitor C is added. B1 C B2 For C S1 C S2 L S1 L S2 The voltage swing at both ends (①②) is divided.

[0079] By C P1 C P2 and SW P A five-bit switched capacitor array composed of C S1 C S2 and SW S A five-bit switched capacitor array is used for coarse tuning of the oscillation frequency. This is achieved by changing the varactor capacitor C. V1 C V2 Control voltage V TUNE This enables continuous frequency tuning.

[0080] Pole-focused polymerization technology adjusts the capacitance C P1 C P2 C S1 C S2 To achieve this, C P1 C P2 C V1 C V2 L P1 L P2 The corresponding pole frequency, and C S1 C S2L S1 L S2 After the corresponding pole frequencies are adjusted to be equal, the two voltage gain resonant peaks of the transformer-type series resonant cavity converge, increasing the voltage gain at the zero-phase point and improving C. S1 C S2 L S1 L S2 The voltage swing at both ends (①②) and the energy they store reduce the phase noise of the oscillator.

[0081] By adjusting the magnetic coupling coefficient k of the transformer, the input impedance of the transformer-type series resonant cavity can be flexibly adjusted, thereby achieving flexible control over power consumption and phase noise. When the magnetic coupling coefficient k is increased, the input impedance of the transformer-type series resonant cavity increases, the oscillator power consumption decreases, and the phase noise increases; when the magnetic coupling coefficient k is decreased, the input impedance of the transformer-type series resonant cavity increases, the oscillator power consumption increases, and the phase noise decreases.

[0082] 2) Control principle of complementary switch-capacitor array

[0083] When the enable signal EN is high, transistor M N When the gate voltage is high, transistor M P The gate is low, and M P and M N When both the drain and gate of transistor M are at low level, transistor M... N and M P The voltage between the gate and source is greater than the threshold voltage, M N and M P Both are conducting, at this time capacitor C U1 and C U2 All of these are applied to the differential series resonant oscillator, increasing the equivalent capacitance of the resonant cavity and lowering its resonant frequency; when the enable signal EN is low, transistor M... N When the gate voltage is low, transistor M P The gate is high, and M P and M N When both the drain and gate of transistor M are at high level, transistor M... N and M P The voltage between the gate and source is less than the threshold voltage, M N and M P Both are cut off, at which point capacitor C... U1 and C U2 By not loading it into the differential series resonant oscillator, the equivalent capacitance of the resonant cavity in the differential series resonant oscillator is reduced, thereby increasing the resonant frequency of the resonant cavity.

[0084] Additionally, when the enable signal EN is low, transistor M... N and M P Parasitic capacitance and capacitance C U1 and C U2 The transistor M is connected in series and loaded into a differential series resonant oscillator. N and M P The parasitic capacitance is related to the drain and source voltages. At this time, the bias resistor R... B1 and R B2 Resistance thermal noise modulation, changing transistor M N and M P The parasitic capacitance of the transistor causes a change in the equivalent capacitance of the resonant cavity of the differential series resonant oscillator, resulting in changes in the oscillation frequency and the phase of the output signal. This is due to the parasitic capacitance of transistor M. N and M P Parasitic capacitance changes inversely with voltage, therefore the bias resistor R B1 and R B2 Resistance thermal noise modulation transistor M N and M P The introduced phase noises are opposite and cancel each other out; therefore, the switched capacitor array of the complementary switch in this invention is biased against the resistor R. B1 and R B2 It is not sensitive to noise.

[0085] Specifically, the tuning range of this embodiment is 7.65–9.135 GHz, and the tuning range test curve is shown in Figure 6. Figures 7 and 8 show the phase noise test results curves at oscillation frequencies of 7.65 GHz and 9.135 GHz, respectively. Figure 9 shows the phase noise at each frequency point at frequency offsets of 1 MHz and 10 MHz, where the phase noise at 1 MHz frequency offset is -130.5 to -132 dBc / Hz, and the phase noise at 10 MHz frequency offset is -150.5 to -153 dBc / Hz. The power consumption of this embodiment is 159–164.5 mW, and the FoM values ​​at 1 MHz and 10 MHz frequency offsets are 186.4–189 dBc / Hz and 186.5–190 dBc / Hz, respectively, as shown in Figure 10. In summary, this embodiment realizes an ultra-low phase noise, compact differential series resonant voltage-controlled oscillator.

[0086] Based on the above, the differential series resonant oscillator of this embodiment has at least the following advantages and beneficial effects compared to the prior art:

[0087] (1) This invention proposes a fully differential series resonant oscillator that can achieve pure differential output under pure CMOS process, solves the mode ambiguity problem of traditional transformer series resonant oscillators, occupies less chip area, has a wider tuning range, and has flexible and controllable power consumption and phase noise.

[0088] (2) This invention proposes a complementary switching type switched capacitor array, which solves the problem of large noise contribution of bias resistor in traditional switched capacitor arrays.

[0089] Example 2

[0090] As shown in Figure 11, the main difference between the differential series resonant oscillator provided in this embodiment and the oscillator in Embodiment 1 is that the transformer-type series resonant cavity is composed of an inductor L. P1 L P2 L S1 L S2 and capacitor C P1 C P2 C S1 C S2 C VP1 C VP2 C VS1 C VS2 Composition, the oscillator is connected to port V TUNEP and V TUNES Controlling the variable capacitor C VP1 C VP2 C VS1 C VS2 The capacitance value is adjusted to change the resonant frequency of the differential series resonant cavity, thereby achieving continuous tuning. For example, during continuous tuning, the control voltage V... TUNEP Follow V TUNES The change in frequency ensures that the frequencies of the two poles in the proposed differential series resonant cavity change synchronously, thereby reducing the change in circuit performance during continuous tuning.

[0091] The differential series resonant oscillator of this embodiment can achieve the same function and beneficial effects as the oscillator of Embodiment 1.

[0092] Example 3

[0093] As shown in Figure 12, the main difference between the differential series resonant oscillator provided in this embodiment and the oscillator in Embodiment 1 is that the inverter is a non-self-biased inverter, and the active drive section consists of transistors M1, M2, M3, M4 and a bias resistor R. B1 R B2 Composition, external bias voltage V B Through bias resistor R B1 R B2DC bias is applied to the gates of transistors M1, M2, M3, and M4. Similar to Example 1, the transformer-type series resonant cavity is still composed of inductor L. P1 L P2 L S1 L S2 and capacitor C P1 C P2 C S1 C S2 C V1 C V2 composition.

[0094] The differential series resonant oscillator of this embodiment can achieve the same function and beneficial effects as the oscillator of Embodiment 1.

[0095] Example 4

[0096] As shown in Figure 13, the main difference between the differential series resonant oscillator provided in this embodiment and the oscillator in Embodiment 1 is that the active driving section consists of NMOS transistors M1, M2, M3, and M4 and a bias resistor R. B1 R B2 R B3 R B4 Composition. NMOS transistors M1 and M2 (M3 and M4) constitute an all-NMOS inverter, and the input terminals of M1 and M2 (M3 and M4) are connected to voltage divider capacitors C. B1 C B2 (C B3 C B4 V connected to the differential series resonant cavity SN V SP (V SP V SN Terminal ) The power supply voltage passes through the bias resistor R. B1 R B2 R B3 R B4 Bias voltages are provided to the gates of transistors M1, M2, M3, and M4. Similar to Example 1, the transformer-type series resonant cavity is still composed of inductor L. P1 L P2 L S1 L S2 and capacitor C P1 C P2 C S1 C S2 C V1 C V2 composition.

[0097] The differential series resonant oscillator of this embodiment can achieve the same function and beneficial effects as the oscillator of Embodiment 1.

[0098] Example 5

[0099] As shown in Figure 14, the main difference between the differential series resonant oscillator provided in this embodiment and the oscillator in Embodiment 1 is that the active driving section consists of transistors M1, M2, M3, and M4, with their gates directly connected to the differential series resonant cavity. The transistor gate bias voltage V... B The inductor LS1 and LS2 are tapped at their center points to the gates of transistors M1, M2, M3, and M4. Similar to Example 1, the transformer-type series resonant cavity is still composed of inductor L... P1 L P2 L S1 L S2 and capacitor C P1 C P2 C S1 C S2 C V1 C V2 composition.

[0100] The differential series resonant oscillator of this embodiment can achieve the same function and beneficial effects as the oscillator of Embodiment 1.

[0101] Example 6

[0102] As shown in Figure 15, the main difference between the differential series resonant oscillator provided in this embodiment and the oscillator in Embodiment 1 is that the inductor L P1 L P2 L S1 L S2 There is magnetic coupling between each pair of elements, and the magnetic coupling coefficient is k. 21 k 31 k 41 k 32 k 42 k 43 Similar to Example 1, the transformer-type series resonant cavity is still composed of an inductor L. P1 L P2 L S1 L S2 and capacitor C P1 C P2 C S1 C S2 C V1 C V2 The active drive section is composed of transistors M1, M2, M3, and M4.

[0103] The differential series resonant oscillator of this embodiment can achieve the same function and beneficial effects as the oscillator of Embodiment 1.

[0104] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0105] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made based on the essence of the content of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A transformer-type differential series resonant cavity, characterized in that, It includes a two-port transformer and a variable capacitor module, the two-port transformer containing mutually coupled inductors L P1 Inductor L P2 and inductor L S1 Inductor L S2 The variable capacitor module includes a variable capacitor C. P and variable capacitor C S ; The inductor L P1 One end is connected to the first port, and the other end is connected to the variable capacitor C. P One end of the inductor L; P2 One end is connected to the second port, and the other end is connected to the variable capacitor C. P The other end; The inductor L S1 and inductor L S2 One end is connected to the third and fourth ports respectively, and the inductor L S1 and inductor L S2 The other end is connected to the other end; the variable capacitor C S The two ends are connected to the third port and the fourth port respectively; The voltage gain function A of the transformer-type differential series resonant cavity V The multiple pole frequencies are set to be equal, so that A at zero phase... V Increase.

2. The transformer-type differential series resonant cavity according to claim 1, characterized in that, The variable capacitor C P Includes a first switched capacitor array and a variable capacitor C VP1 and variable capacitor C VP2 The first switched capacitor array is connected to inductors L at both ends. P1 and inductor L P2 The other end; the variable capacitor C VP1 and variable capacitor C VP2 One end is connected to the control voltage V TUNEP The variable capacitor C VP1 and variable capacitor C VP2 The other end is connected to both ends of the first switched capacitor array; The variable capacitor C S Includes a second switched capacitor array and a variable capacitor C VS1 and variable capacitor C VS2 The two ends of the second switched capacitor array are respectively connected to inductors L. S1 and inductor L S2 One end; the variable capacitor C VS1 and variable capacitor C VS2 One end is connected to the control voltage V TUNES The variable capacitor C VS1 and variable capacitor C VS2 The other end is connected to both ends of the second switched capacitor array.

3. The transformer-type differential series resonant cavity according to claim 1, characterized in that, The variable capacitor C P Includes a first switched capacitor array and a variable capacitor C VP1 and variable capacitor C VP2 The first switched capacitor array is connected to inductors L at both ends. P1 and inductor L P2 The other end; the variable capacitor C VP1 and variable capacitor C VP2 One end is connected to the control voltage V TUNEP The variable capacitor C VP1 and variable capacitor C VP2 The other end is connected to both ends of the first switched capacitor array; The variable capacitor C S It includes a second switched capacitor array, with inductors L connected to both ends of the second switched capacitor array. S1 and inductor L S2 One end.

4. A transformer-type differential series resonant cavity according to claim 2 or 3, characterized in that, Both the first and second switched capacitor arrays are NMOS-based switched capacitor arrays, and each switched capacitor array includes multiple switched capacitor units. The switched capacitor unit includes transistor M. N Resistance R B1 Resistance R B2 Switched capacitor C U1 Switched capacitor C U2 The third inverter, the fourth inverter, and the fifth inverter; The switched capacitor C U1 One end is connected to transistor M N The drain of the capacitor, the switched capacitor C U1 The other end is connected to one end of the switched capacitor array; The switched capacitor C U2 One end is connected to transistor M N The source of the switched capacitor C U2 The other end is connected to the other end of the switched capacitor array; The resistor R B1 One end is connected to transistor M N The drain of the resistor R B2 One end is connected to transistor M N The source pole; The enable signal EN is applied to transistor M after passing through the third and fourth inverters in sequence. N The gate; the enable signal EN, after passing through the fifth inverter, is applied to resistor R. B1 The other end and resistor R B2 The other end.

5. A transformer-type differential series resonant cavity according to claim 2 or 3, characterized in that, Both the first and second switched capacitor arrays are switched capacitor arrays based on complementary switches, and the switched capacitor array includes multiple switched capacitor units. The switched capacitor unit includes transistor M. P Transistor M N Resistance R B1 Resistance R B2 Switched capacitor C U1 Switched capacitor C U2 The third inverter, the fourth inverter, and the fifth inverter; The transistor M P The drain and transistor M N The drains of the transistors are connected, and the connection point is denoted as point A; the transistor M P The source and transistor M N The source poles are connected, and the connection point is denoted as point B; The switched capacitor C U1 One end is connected to point A, and the switched capacitor is connected to point C. U1 The other end is connected to one end of the switched capacitor array; The switched capacitor C U2 One end is connected to point B, and the switched capacitor is connected to point C. U2 The other end is connected to the other end of the switched capacitor array; The resistor R B1 One end of the resistor R is connected to point A. B2 Connect one end to point B; The enable signal EN is applied to transistor M after passing through the third inverter. P The gate of the transistor is activated, and the enable signal EN is applied to transistor M after passing through the third and fourth inverters in sequence. N The gate; the enable signal EN, after passing through the fifth inverter, is applied to resistor R. B1 The other end and resistor R B2 The other end.

6. A differential series resonant oscillator, characterized in that, Includes a differential driver and a transformer-type differential series resonant cavity as described in any one of claims 1-5; The differential output terminal of the differential driver is connected to the first and second ports of the transformer-type differential series resonant cavity; the differential input terminal of the differential driver is connected to the third and fourth ports of the transformer-type differential series resonant cavity.

7. The differential series resonant oscillator according to claim 6, characterized in that, The differential driver includes two inverters with identical structures and two capacitors C. B1 C B2 The input terminals of the differential driver are respectively connected to capacitor C. B1 C B2 One end, capacitor C B1 C B2 The other end is connected to the input terminals of two inverters respectively; the output terminals of the two inverters serve as the output terminals of the differential driver. The inverter consists of an NMOS transistor, a PMOS transistor, and a resistor R. FB The inverter is composed of two transistors whose gates are connected together as the input and two transistors whose drains are connected together as the output. A resistor R... FB The two ends are connected to the input and output terminals of the inverter, respectively; the source of the NMOS transistor is connected to ground, and the source of the PMOS transistor is connected to the power supply.

8. The differential series resonant oscillator according to claim 6, characterized in that, The differential driver includes two inverters with identical structures and two capacitors C. B1 C B2 The input terminals of the differential driver are respectively connected to capacitor C. B1 C B2 One end, capacitor C B1 C B2 The other end is connected to the input terminals of two inverters respectively; the output terminals of the two inverters serve as the output terminals of the differential driver. The inverter consists of a first NMOS transistor, a second NMOS transistor, and a resistor R. B The inverter is composed of two transistors whose gates are connected together as the input terminal, and the source of the first NMOS transistor and the drain of the second NMOS transistor connected together as the output terminal. A resistor R... B One end is connected to the input of the inverter, and the other end is connected to the power supply; the drain of the first NMOS transistor is connected to the power supply, and the source of the second NMOS transistor is connected to ground.

9. The differential series resonant oscillator according to claim 6, characterized in that, The differential driver includes two inverters with identical structures; the input and output terminals of the two inverters are respectively connected to the input and output terminals of the differential driver. The inverter is composed of an NMOS transistor and a PMOS transistor. The gates of the two transistors are connected to form the input terminal of the inverter, and the drains of the two transistors are connected to form the output terminal of the inverter. The source of the NMOS transistor is connected to ground, and the source of the PMOS transistor is connected to the power supply. In the transformer-type differential series resonant cavity, the inductor L S1 and inductor L S2 One end is connected to the external bias voltage V B Connected, bias voltage V B Through inductor L S1 and inductor L S2 The voltage reaches the input terminal of the inverter and serves as the bias voltage for the inverter.

10. The differential series resonant oscillator according to claim 6, characterized in that, The differential driver includes two inverters with identical structures; the input and output terminals of the two inverters are respectively connected to the input and output terminals of the differential driver. The inverter is composed of a first NMOS transistor and a second NMOS transistor. The gates of the two transistors are connected to form the input terminal of the inverter, and the source and drain of the first NMOS transistor are connected to form the output terminal of the inverter. The drain of the first NMOS transistor is connected to the power supply, and the source of the second NMOS transistor is connected to ground. In the transformer-type differential series resonant cavity, the inductor L S1 and inductor L S2 One end is connected to the external bias voltage V B Connected, bias voltage V B Through inductor L S1 and inductor L S2 The voltage reaches the input terminal of the inverter and serves as the bias voltage for the inverter.

11. A chip, characterized in that, Includes a differential series resonant oscillator as described in any one of claims 7-10.

12. A communication device, characterized in that, The communication device includes the chip as described in claim 11.

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