Quantum circuit generation method and quantum circuit generation device

Abstract

A quantum error correction code circuit in which an intermediate number of ancilla qubits compared with the prior art are used is to be obtained, while taking real machine restrictions into consideration. For this purpose, a quantum circuit generation device according to the disclosed invention includes a circuit search unit and a control unit. The circuit search unit selects a swap gate or a cnot gate according to the information acquisition status of ancilla qubits. The control unit adds, to a quantum circuit list, the quantum circuit selected by the circuit search unit, as well as a measurement gate when an ancilla qubit for which the acquisition of information necessary for eigenvalue measurement has been completed is obtained.

Description

Quantum circuit generation method and quantum circuit generation apparatus

[0001] The disclosed technology relates to a technique for searching for the quantum circuits necessary for error correction when implementing quantum error correction codes on a quantum computer, taking into account the definition of the code and the connectivity between qubits within the computer.

[0002] In recent years, the practical application of quantum computing, a computational method different from conventional computation performed on computers (i.e., classical computation), has been progressing. In classical computation, calculations are performed using bit values ​​of 0 and 1, but in quantum computing, calculations are performed using qubits that can take values ​​called superpositions of these two. As a result, it is known that quantum computing can efficiently perform calculations even for problems that would take an enormous amount of time to solve using classical computation. Figure 1 schematically shows quantum computing. The "input" is a quantum mechanical state (quantum state). A quantum state can be represented as a vector. The "operation" is the transformation of the quantum state. This is performed using the action and measurement of a unitary matrix on the state vector. The "output" is the quantum state after the operation, or a value obtained from the quantum state after the operation.

[0003] Quantum bits are susceptible to influences (errors) from the surrounding environment, including thermal noise, which can cause the computation state to become unintended during the execution of a quantum computation. Figure 2 schematically illustrates the occurrence of errors in quantum computation. The larger the number of qubits used in the operation, and the deeper the circuit (the more stages of computation), the less likely it is that the desired output will be obtained. Therefore, computation methods protected from noise (errors) are necessary.

[0004] In response to the above problems, the concept of quantum error correction, a technique for reducing the impact of errors, has been proposed, and various types of codes have been proposed to date. The error correction flow is schematically shown in Fig. 3. Quantum error correction consists of the following three steps. [Step 1] Embed the information of the quantum bit to be protected from errors into a plurality of quantum bits. The embedding method is sometimes called a "code". The quantum bits where the information is embedded are called "data quantum bits". [Step 2] Periodically detect that an error has occurred. For detection, another quantum bit is used in addition to the data quantum bits. This is called an auxiliary quantum bit. [Step 3] Correct the error based on the error detection information.

[0005] Normally, in order to perform error detection, an auxiliary quantum bit is placed near the data quantum bits, and a quantum gate is applied between them. By doing so, the auxiliary quantum bit acquires information on the presence or absence of an error, and by measuring the auxiliary quantum bit, information on the error that has occurred in the data quantum bits is obtained. In order to perform this error detection at high speed, n-k auxiliary quantum bits are often used (Non-Patent Document 1). Fig. 4(a) shows an error detection quantum circuit in the case of n = 3 and k = 1. The number of auxiliary quantum bits is n-k = 2. The total number of quantum bits used is n+(n-k)=2n-k = 5. The number of circuit stages is 3.

[0006] Also, a technique for performing error detection using only one auxiliary quantum bit has been proposed in the case of a repetition code when the data quantum bits are arranged on a circumference or a surface code on a square lattice (Non-Patent Document 2). Fig. 4(b) shows an error detection quantum circuit in the case of n = 3. The number of quantum bits used is n + 1 = 4, but the number of circuit stages is 7.

[0007] AG Fowler et al., "Surface codes: Towards practical large-scale quantum computation", Phys. Rev. A 86, 032324, 2012.AV Antipov, et al., "Realizing a class of stabilizer quantum error correction codes using a single ancilla and circular connectivity", Phys. Rev. A 107, 032403, 2023.

[0008] The larger the code distance, the higher the error tolerance, and the larger the number of data qubits, the greater the code distance. In the case of Non-Patent Document 1, the total number of qubits required to implement the code is n + (nk) = (2n-k), and a large-scale quantum computer is required to implement a code with a large code distance. The more auxiliary qubits there are, the shorter the time required for error detection. In the method of Non-Patent Document 2, which uses only one auxiliary qubit, error detection takes a long time. As a result, there is a risk that errors will accumulate compared to the aforementioned method, and the accuracy of error correction may decrease, potentially preventing the code from performing to its full potential. The disclosed technology provides a quantum error correction code circuit using an intermediate number of auxiliary qubits, taking into account the constraints of the actual hardware.

[0009] To solve the above problems, a quantum circuit generation device according to the disclosed technology is a device that generates a quantum circuit for detecting an error in each data qubit using one or more auxiliary qubits for a group of data qubits generated by a stabilizer code, and includes a circuit search unit. The error detection of each data qubit is performed by measuring the eigenvalue of the generator of the stabilizer code, and the eigenvalue measurement is performed by obtaining information on all the data qubits corresponding to the generator. Let G be a graph representing the arrangement and coupling of the data qubit group and the auxiliary qubits with vertices and edges. When there is an auxiliary qubit for which information acquisition necessary for eigenvalue measurement has not been completed and all the data qubits sharing an edge with the auxiliary qubit have completed information acquisition, the circuit search unit adds a swap gate that exchanges and moves the positions of the auxiliary qubit and the data qubit on the graph G. Also, when there is an auxiliary qubit for which information acquisition necessary for eigenvalue measurement has not been completed and there is a data qubit that shares an edge with the auxiliary qubit and has not acquired information, the circuit search unit adds a cnot gate with the data qubit as the control qubit and the auxiliary qubit as the target qubit. Further, when an auxiliary qubit for which information acquisition necessary for eigenvalue measurement has been completed is obtained, the circuit search unit adds a measurement gate.

[0010] According to the disclosed technology, for a specific actual machine (number of qubits N, qubit arrangement G) and code, the following parameters can be changed to generate an error detection circuit. [Code distance] It is related to the number n of data qubits, and usually, a larger code distance and a larger number of data qubits mean better error tolerance. [Number of auxiliary qubits] Usually, the more auxiliary qubits n d there are, the shorter the time required for error detection, and as a result, the performance of the code tends to improve. a

[0011] N = n d + n a Under the constraint, it is possible to search for the combination that exhibits the best performance.

[0012] Diagram schematically showing quantum computing. Diagram schematically showing the occurrence of errors in quantum computing. Diagram schematically showing an error correction flow. Diagram explaining an error detection quantum circuit according to the prior art. Diagram showing a parity measurement circuit for a Z-type / X-type stabilizer. Diagram explaining the effect of a swap gate. Diagram explaining that two-qubit gates cannot act on the same qubit simultaneously. Diagram explaining the positioning of the disclosed technology in quantum computing. Functional block diagram of an error detection quantum circuit generation device and a flowchart explaining its operation. Detailed flowchart of a quantum circuit search process. Diagram explaining four situations that an auxiliary qubit can take. Diagram explaining the definition of a parity check transition matrix. Diagram explaining the initial value of a parity check transition matrix. Diagram explaining the update rule of a parity check transition matrix when a swap gate is applied. Diagram explaining the update rule of a parity check transition matrix when a cnot gate is applied. Diagram explaining the update rule of a parity check transition matrix when an auxiliary qubit is measured. Diagram showing an example of the functional configuration of a computer.

[0013] First, the technology underlying the disclosed technology will be explained, then the positioning of the disclosed technology in quantum computing will be explained, and then the embodiments will be explained.

[0014] [Underlying Technology] <Stabilizer Code> The [n,k,d] stabilizer code C is defined by specifying a commuting subgroup of the n-qubit Pauli group P n and a group S that does not contain -I. "I" means the identity matrix for n qubits. In the case of the [n,k,d] stabilizer code, the set S G :={g1,g2,…,g m'} consisting of m':=(n-k) generators that generate S is specified, and S=<S G > is determined. <S G > means the group generated from the set S G . The state to be protected from errors is |Ψ>=g iEmbed into a state that satisfies |Ψ>. To perform error correction using this sign, measure the eigenvalues ​​for these m' generators (Reference 1: MA Nielsen and IL Chuang, "Quantum Computation and Quantum Information", Cambridge University Press, 2000). Since the eigenvalues ​​of these operators are ±1, if there are no errors, the measurement result corresponding to eigenvalue 1 is obtained. Here, g i The results obtained when measuring the eigenvalues ​​are s i Let ∈{0,1} be written as s i When = 0, the result corresponds to an eigenvalue of 1, s i When the value is 1, the result corresponds to the eigenvalue -1. This measurement result is called the syndrome value, and the measurement used to obtain the syndrome value is specifically called a parity measurement.

[0015] <CSS Code> The set of generators S that defines the stabilizer code C. G If the elements consist only of Pauli Z operators or only of Pauli X operators, this code is called a Calderbank-Shor-Steane (CSS) code. The respective types of stabilizers are called Z-type stabilizers and X-type stabilizers, respectively. Therefore, a CSS code C is defined by the following set of stabilizers. Here g i (X) ,g j (z) These are generators consisting only of Pauli X and Pauli Z operators, respectively, where m := m' / 2.

[0016] <Measurement of Parity of CSS Codes> Note that the parity measurement of CSS codes can be performed independently for each type of parity, such as first measuring all X-type parity, then measuring all Z-type parity. Therefore, it is sufficient to obtain circuits that perform each type of parity measurement. Furthermore, if an algorithm for obtaining one type of circuit is given, obtaining the other type of circuit can be done by swapping the target and control in the cnot gate and replacing the basis for measuring the auxiliary qubits with an appropriate X or Z.

[0017] <Parity Measurement Circuit> For parity measurement to obtain syndrome values, a circuit consisting of cnot gates is used. Figure 5(a) shows the parity measurement circuit for a Z-type stabilizer, specifically the circuit for measuring the generators Z1 and Z2. The circuit operation is briefly explained below. (1) Initialize the auxiliary qubit to |0>. (2) Apply the cnot gate to the data qubit as the control bit and the auxiliary qubit as the target bit. (3) Measure the Z of the auxiliary qubit.

[0018] Figure 5(b) shows the parity measurement circuit for an X-type stabilizer, specifically the circuit for measuring the generator X1X2. The circuit operation is briefly explained below: (1) Initialize the auxiliary qubit to |+>. (2) Apply the CNOTT gate, using the data qubit as the target bit and the auxiliary qubit as the control bit. (3) Measure the X of the auxiliary qubit.

[0019] <Implementation of Quantum Computers and Codes> On actual quantum computers, there are limitations on the quantum gates that can be operated, depending on the implementation method. For example, in cases where qubits are arranged on the vertices of a square lattice, it may not be possible to operate a two-qubit gate between non-adjacent qubits (Figure 6(a)). In other words, the gates that can be operated are determined according to the graph G representing the arrangement of qubits.

[0020] By using a swap gate, it becomes possible to apply a two-qubit gate even to qubits in configurations where a two-qubit gate cannot be directly applied, as described above (Figure 6(b)).

[0021] Furthermore, a two-qubit gate cannot act on the same qubit simultaneously (Figure 7). However, it is possible to act on them consecutively, not simultaneously.

[0022] The above is a description of the prerequisite technology.

[0023] [Position of Disclosure Technology in Quantum Computing] The position of disclosure technology in quantum computing will be explained using Figure 8. The quantum computer 80 is assumed to include a physical qubit unit 801, a control unit 802, and an error correction unit 803. The control unit 802 embeds a quantum state into the physical qubit using a predetermined error correction code (step S801). The control unit 802 performs operations on the data qubit by manipulating a quantum gate (step S802). The error correction unit 803 detects an error in the data qubit after the operation (step S803). The error correction unit 803 corrects the error in the data qubit in which an error was detected. Steps S802 to S804 are repeated as needed. Finally, the control unit 802 observes the data qubit to obtain the calculation result (step S805).

[0024] The error detection quantum circuit generation device 81 related to the disclosed technology has an error correction unit 803 that generates a quantum circuit for performing the error detection step S803.

[0025] The embodiments of the disclosed technology will be described in detail below. Components with the same function will be numbered identically, and redundant explanations will be omitted.

[0026] [First Embodiment] Figure 9(a) is a functional block diagram showing an example of the configuration of an error detection quantum circuit generation device 81 according to the first embodiment. The error detection quantum circuit generation device 81 comprises an input unit 811, a control unit 812, a circuit search unit 813, and an output unit 814. Figure 9(b) is a flowchart illustrating an example of the operation of the error detection quantum circuit generation device 81. The following explanation will use Figure 9.

[0027] <Input> The input unit 811 obtains the CSS code C and the graph G=(V,E) (step S901). C is defined by equation (1). V is the set of vertices, and E is the set of edges. Data qubits and auxiliary qubits are defined on each vertex v∈V, and this arrangement is given. The number of data qubits is n, and the number of auxiliary qubits is n. a Let n+n a = (number of elements in V). Each data qubit is labeled d. i (i=1,2,…,n) Each auxiliary qubit is labeled a i (i=1,2,…,n a Assign a label to V. Note that this label can be defined when defining the sign and is generally independent of the V label. At this time, specify whether to perform an X-type or Z-type parity measurement.

[0028] The first embodiment provides a quantum circuit that performs parity measurements on all specified X-type and Z-type stabilizer generators under the above input. However, the gates and operations that can be used in the quantum circuit are limited to the following three types: (1) X measurement or Z measurement of an auxiliary qubit (2) 2-qubit cnot gate (3) 2-qubit swap gate Note that for qubits located at vertices u,v ∈ V, a 2-qubit gate operation is only possible if the edge between u and v is at E.

[0029] The control unit initializes the parity check progress matrix M(t), the stabilizer generator list L(t), and the quantum circuit list C (step S902). In the initial state, C has zero quantum circuits. The initial state L(0) of L(t) is when all stabilizer generators are listed. The parity check progress matrix M(t) manages the progress of information acquisition (parity check) of the auxiliary qubits and the positions of the data qubits and auxiliary qubits in the graph G, and its details will be described later.

[0030] The circuit search unit 813 searches for the quantum circuit necessary for error detection (step S903). Figure 10 shows the detailed flow of the quantum circuit search, and Figure 11 shows the four possible situations (cases 1 to 4) for the auxiliary qubit.

[0031] The circuit search unit 813 classifies the status of the auxiliary qubits (Figure 10, step S1001). Each auxiliary qubit at each update is classified into one of the following four statuses.

[0032] (Case 1) Case 1 is when the auxiliary qubit 1102 has already acquired information from some data qubit (for example, 1101 in Figure 11), has not been subjected to a gate operation, and is one of the data qubits sharing an edge that constitutes the same generator as the operator from which information has already been acquired (for a stabilizer whose information has not yet been fully acquired), and is not a checked operator. Assume that the data qubit 1111 is a data qubit that has information that the auxiliary qubit 1102 of interest has not yet fully recovered. In this case, the circuit search unit 813 selects a cnot gate with data qubit 1111 as the control bit in order to acquire information from data qubit 1111 (process 1) (step S1011).

[0033] (Case 2) Case 2 is the case where the auxiliary qubit 1102 has already acquired information from some data qubit (for example, 1101 in Figure 11), has not been subjected to a gate operation, and among the data qubits sharing an edge, there is no data qubit that "does not exist" as it is not a checked operator and whose generator is not yet fully checked, and among the qubits that share an unmatched edge, there is a data qubit (not limited to data) whose distance difference before and after the swap becomes 0 or greater (the distance decreases before and after the swap). Assume that the data qubit 1121 is a data qubit that has information that the auxiliary qubit 1102 of interest has not yet fully recovered. In this case, the circuit search unit 813 selects a swap gate to exchange the auxiliary qubit 1102 and the data qubit 1122 in order to bring the auxiliary qubit 1102 closer to the data qubit 1121 (process 2) (step S1012).

[0034] (Case 3) Case 3 is when the auxiliary qubit 1102 has not acquired information from any data qubit (qubit with the same pattern as 1101), has not been subjected to a gate operation, and there is an operator that constitutes a generator from which no operator has yet acquired information among the data qubits that share an edge. Suppose that data qubit 1131 is a data qubit that corresponds to an operator that constitutes a generator from which no operator has yet acquired information. In this case, the circuit search unit 813 selects a cnot gate with data qubit 1131 as the control bit in order to acquire information from data qubit 1131 (process 3) (step S1013).

[0035] (Case 4) Case 4 is the case where there are no auxiliary qubits corresponding to cases 1 to 3. In this case, none of the auxiliary qubits have acquired information about any of the operators that make up the unchecked stabilizer generator. In this case, the circuit search unit 813 selects a swap gate that exchanges auxiliary qubit 1102 and data qubit 1142 in order to reduce the distance between the auxiliary qubit (let's call it 1102) and the data qubit 1141 before and after the swap (process 4) for the auxiliary qubit (let's call it 1102) that is closest to the data qubit (let's call it 1141) that makes up the operator that makes up the generator for which no operator has acquired information (step S1014).

[0036] Return to Figure 9. The control unit 812 adds the quantum circuit obtained in step 903 to list C (step S904). The control unit 812 updates M(t) (step S905). The rules for updating M(t) will be described later. Based on M(t), the control unit 812 checks for the presence of an auxiliary qubit that has all the information necessary for measuring the eigenvalue of the generator. If an auxiliary qubit with all the necessary information is found, it adds a circuit to list C for measuring the auxiliary qubit and detecting an error. It also adds a circuit to list C for initializing the auxiliary qubit (step S906). Note that the auxiliary qubits that have finished checking the generator are initialized and made reusable. The control unit 812 updates L(t) by removing the generators that have completed the check (step S907).

[0037] The control unit 812 checks whether the number of elements in L(t) is zero or not. If it is zero (Yes in step S908), the output unit 811 outputs the quantum circuit C (step S909). If it is not zero (No in step S908), the process returns to step S903 and continues the search for the quantum circuit.

[0038] [Parity Check Transition Matrix] <Definition> The parity check transition matrix M(t) is explained below. M(t) is as shown in Figure 12 (n+n a (+1) × (n+n a Defined as a )-dimensional matrix. Label d i The data qubits have information in column i, label aj The information of the auxiliary qubits is listed in column n+j. The bottom row contains the position p on the graph of the data qubit in column i. i , the position p on the graph of the n+j series of auxiliary qubits n+j It is assumed that the following is included. Also, the last line is excluded (n+n a ) × (n + n a For the 3D matrix portion, all diagonal elements are assumed to be 1, all elements of the upper right block matrix are assumed to be 0, and all elements except the diagonal terms of the upper left and lower right blocks are assumed to be 0.

[0039] <Initialization> Let M(0) be the initial parity check progression matrix. As shown in Figure 13(a), the components of the lower left block of M(0) are set to 0. Each column component of the bottom row reflects the initial arrangement of each qubit. Figure 13(b) shows n=3, n a An example of the initial parity check transition matrix when = 1 is shown. Figure 13(c) shows n=3, n a An example of the relationship between graph G and the qubit positions when = 1 is shown. Since the data qubit d1 and the auxiliary qubit a1 do not share an edge, a CNOTT gate cannot be applied to them.

[0040] <Update Rules> Matching X(t) at each time step:={e1(t),…,e l Suppose (t) and the 2-qubit gate operation in its matching are given. Here e i (t)∈E, X(t)⊆E, and any e i (t),e j For (t)∈X(t), e i (t)∩e j X(t) is the set of edges such that (t) = φ (empty set). Although the algorithm in the disclosure technique does not explicitly construct X(t), it does not select gates that act on the same qubit at the same time, so it is equivalent to selecting a gate from such a matching at each time. The elements in X(t) to which the cnot gate and swap gate are applied are defined by the following equation.

[0041] (Update rules when applying a swap gate) A swap of qubits includes swaps between data qubits, between auxiliary qubits, and between data qubits and auxiliary qubits. (p i ,p j ) (i,j=1,2,…,n), (p n+i ,p n+j ) (i,j=1,2,…,n a ), (p i ,p n+j ) (i=1,2,…,nj=1,2,…,n a For )∈X(t), swap the corresponding elements in the bottom row. Figure 14(a) shows p i and p n+j This shows the swap. Figure 14(b) shows an example where p2 and p4 in the last row of the matrix in Figure 13(b) are swapped. This corresponds to swapping the data qubit d2, which was at graph position p2, with the auxiliary qubit a1, which was at graph position p4, as shown in Figure 14(c). As a result of this operation, the data qubit d1 and the auxiliary qubit a1 share an edge, so a CNOTT gate can be applied to them.

[0042] (Update rules when applying the cnot gate) With parity measurement of a Z-type stabilizer in mind, in the case of the cnot gate, the first argument of (*,*) is the control and the second argument is the target. In the case of X-type measurement, simply swap the roles of control and target. Follow the explanation of the swap gate above for p i Assume that is in the (n+j)th column. As shown in Figure 15(a), (p k ,p i When a cnot gate is applied to )∈X(t), the last row is p k In the column, the last row is p i Place a 1 in the row where there is a 1 in the column. In other words, the "1"s from row 1 to column n on row (n+j) are labeled a j The auxiliary qubit is labeled d i This indicates that information about the data qubits has been obtained. k The first argument is the data qubit, p iNote that the second argument is an auxiliary qubit. Figure 15(c) shows the result of applying cnot with d1 at graph position p1 as the control bit and a1 at graph position p2 as the target bit. Figure 15(b) shows the result of placing a 1 in the row where there is a 1 in the column where the last row is p2, within the column where the last row is p1.

[0043] (Update rule when measuring auxiliary qubits) Label a j When measuring the auxiliary qubit with , the component in the (n+j)th column of the (n+j) rows remains 1, while all other components are set to 0 (Figure 16). This corresponds to label a j This means initializing the information acquisition status using the auxiliary qubits that have this property.

[0044] The above is a description of the first embodiment.

[0045] [Supplement: Regarding termination] The number of Pauli operators contained in L(t) is counted, allowing for duplication, n P Next, count the number of parity values ​​obtained by each auxiliary qubit, and write n' p This is written as follows. However, here we will only aggregate if all Pauli operators for which each auxiliary qubit obtains parity are included in one or more generators in L(t). Using these, This is defined as follows: At t=0, N {unchecked} Since this is the number of Pauli operators in L(t), with duplicates allowed, it is greater than 0.

[0046] Furthermore, for each auxiliary qubit, we select one stabilizer generator from L(t) that contains the most Pauli operators for which that auxiliary qubit has parity. If there are multiple such generators, we select one according to a specific rule, such as the generator closest to the beginning of the list when L(t) is considered as a one-dimensional list. We then enumerate the Pauli operators contained in this generator for which the auxiliary qubit under consideration has not achieved parity, and calculate the sum of the graph distances between the corresponding data qubit and the auxiliary qubit. We then sum these distances over all auxiliary qubits to obtain d {total} This is how it is defined.

[0047] In the following, the disclosed technology performs syndrome measurements on all stabilizer generators within a finite time and then stops, that is, within a finite time N {unchecked} We will show that this equals 0.

[0048] First, for an auxiliary qubit that has not yet acquired parity to acquire parity, it must be determined as case 3 at a certain time. Therefore, note that from the definition of case 3, the situation in which multiple auxiliary qubits simultaneously acquire parity of Pauli operators contained in the same stabilizer generator does not occur. Below, we consider N when case 1, 2, or 3 is selected at each time step. {unchecked} ,d {total} We will observe how it changes.

[0049] If an auxiliary qubit corresponding to case 1 exists, parity is obtained one or more times, so N {unchecked} This decreases. Here, if the auxiliary qubit has fully acquired the parity of the generator, the projection measurement will update the corresponding generator in L(t) and the corresponding row in M(t), but this operation is N {unchecked} Note that you should not change the value of [this variable].

[0050] If an auxiliary qubit corresponding to case 3 exists, parity is obtained at least once, resulting in N {unchecked} It decreases. Also, at the time immediately after case 3 is selected, there is always one or more auxiliary qubits that correspond to either case 1 or 2. If there are auxiliary qubits that correspond to case 2, the swap gate is executed and d {total} This decreases. In particular, even if there are no auxiliary qubits corresponding to cases 1 and 3 in the processing of each time step, as long as there is an auxiliary qubit corresponding to case 2, d {total} As the number of cases decreases, it can be seen that an auxiliary qubit corresponding to case 1 or 3 will appear after a finite amount of time. Therefore, if an auxiliary qubit corresponding to case 1, 2, or 3 exists at each time step, then N {unchecked} d {total} It can be seen that it decreases monotonically.

[0051] Next, consider the case where none of the processes in cases 1, 2, and 3 are performed. In this case, the process in case 4 results in one or more pairs of generators and auxiliary qubits such that the distance on the graph between the Pauli operator constituting the stabilizer generator in L(t) and the auxiliary qubit decreases before and after the process. Therefore, if this process is repeated, an auxiliary qubit corresponding to case 3 will inevitably appear after a finite amount of time.

[0052] Therefore, the sequence of events—the occurrence of case 3, the occurrence of cases 1, 2, and 3, and the occurrence of case 4—is repeated, and within a finite amount of time, N {unchecked} This indicates that the result is 0, meaning the disclosed technology performs syndrome measurements on all stabilizer generators and then stops.

[0053] [Programs, Recording Media] The functions realized by the components described herein may be implemented in a circuitry or processing circuitry, including a general-purpose processor, an application-specific processor, an integrated circuit, an ASIC (Application Specific Integrated Circuit), a CPU (a Central Processing Unit), conventional circuits, and / or a combination thereof, programmed to realize the functions described herein. A processor includes transistors and other circuits and is considered a circuitry or processing circuitry. A processor may be a programmed processor that executes a program stored in memory.

[0054] In this specification, circuitry, unit, and means are hardware programmed to perform or execute the functions described herein. Such hardware may be any hardware disclosed herein, or any hardware known to be programmed to perform or execute the functions described herein.

[0055] If the hardware is a processor that is considered to be a type of circuitry, then the circuitry, means, or unit is a combination of hardware and software used to constitute the hardware and / or processor.

[0056] The various processes described above can be carried out by loading a program that executes each step of the above method into the recording unit 2020 of the computer 2000 shown in Figure 17, and then causing the control unit 2010, input unit 2030, output unit 2040, display unit 2050, etc. to operate.

[0057] The program describing this process can be recorded on a computer-readable recording medium. Any computer-readable recording medium can be used, such as a magnetic recording device, optical disc, magneto-optical recording medium, or semiconductor memory.

[0058] Furthermore, this program may be distributed, for example, by selling, transferring, or lending portable recording media such as DVDs or CD-ROMs on which the program is recorded. Alternatively, the program may be stored in the storage device of a server computer and distributed by transferring the program from the server computer to other computers via a network.

[0059] A computer executing such a program may, for example, first store the program, either recorded on a portable storage medium or transferred from a server computer, in its own memory. Then, when processing is to be executed, the computer reads the program stored in its memory and executes the processing according to the read program. Alternatively, the computer may directly read the program from the portable storage medium and execute the processing according to that program, or it may sequentially execute the processing according to the received program each time a program is transferred to it from a server computer. Furthermore, the processing may be executed using a so-called ASP (Application Service Provider) type service, where the processing function is realized only by issuing execution instructions and obtaining results, without transferring the program from the server computer to this computer.In addition, the processing may be executed using a so-called SaaS (Software as a Service) type service, where a part of the server computer is made available to the user along with the program. Furthermore, the aforementioned programs include information used for processing by electronic computers that is equivalent to a program (data, etc., that is not a direct instruction to the computer but has the property of defining the computer's processing).

[0060] Furthermore, although the above explanation assumes that the device is configured by executing a predetermined program on a computer, at least a part of these processes may be implemented in hardware.

Claims

1. A method for generating a quantum circuit that detects errors in a data qubit group generated by a stabilizer code using one or more auxiliary qubits, wherein the error detection of each data qubit is performed by measuring the eigenvalue of the generator of the stabilizer code, the eigenvalue measurement is performed by acquiring information on all data qubits corresponding to the generator, and a graph G is formed by vertices and edges representing the arrangement and coupling of the data qubit group and the auxiliary qubits, if there is an auxiliary qubit for which the acquisition of information necessary for eigenvalue measurement has not been completed, and all data qubits that share an edge with the auxiliary qubit have had their information acquired, a swap gate is added to move the position of the auxiliary qubit and the position of the data qubit on the graph G by swapping them, if there is an auxiliary qubit for which the acquisition of information necessary for eigenvalue measurement has not been completed, and there is a data qubit that shares an edge with the auxiliary qubit for which information has not been acquired, a cnot gate is added with the data qubit as the control qubit and the auxiliary qubit as the target qubit, A quantum circuit generation method for adding a measurement gate when an auxiliary qubit has been obtained that has completed acquiring the information necessary for eigenvalue measurement.

2. A quantum circuit generation method according to claim 1, wherein the exchange of the position of the auxiliary qubit and the position of the data qubit brings the auxiliary qubit closer to the data qubit that has not acquired information.

3. The quantum circuit generation method according to claim 1, wherein the progress of information acquisition of the auxiliary quantum bits and the positions in the graph G of the auxiliary quantum bits are managed by a parity check progress matrix, the number of data quantum bits is n, and the label of the data quantum bits is d i (i = 1, 2,..., n), the number of auxiliary quantum bits is n a , the label of the auxiliary quantum bits is a j (j = 1, 2,..., n a ), when this is the case, the parity check progress matrix is a matrix of (n + n a +1) rows and (n + n a ) columns, the information of the data quantum bit with label d i is described in the i-th column, the information of the auxiliary quantum bit with label a j is described in the (n + j)-th column, and the positions of the data quantum bits and the auxiliary quantum bits on the graph are described in the (n + n a +1)-th row. A quantum circuit generation method 4. A device for generating a quantum circuit that detects errors in each data qubit using one or more auxiliary qubits for a group of data qubits generated by a stabilizer code, wherein the error detection of each data qubit is performed by measuring the eigenvalue of the generator of the stabilizer code, the eigenvalue measurement is performed by acquiring information on all data qubits corresponding to the generator, and the circuit search unit searches for swap gates and cnot gates, with a graph G representing the arrangement and coupling of the group of data qubits and the auxiliary qubits as vertices and edges, and a control unit adds the measurement gate to the quantum circuit list when the quantum circuit search unit has found and an auxiliary qubit for which the acquisition of information necessary for eigenvalue measurement has been completed is obtained, wherein the circuit search unit selects a swap gate that moves the auxiliary qubit and the data qubit on the graph G by exchanging their positions, if there is an auxiliary qubit for which the acquisition of information necessary for eigenvalue measurement has not been completed, and all data qubits that share an edge with the auxiliary qubit have had their information acquired. A quantum circuit generator that selects a cnot gate in which the data qubit is a control qubit and the auxiliary qubit is a target qubit, when there is an auxiliary qubit from which information necessary for eigenvalue measurement has not been acquired, and there is a data qubit that shares an edge with the auxiliary qubit from which information has not been acquired.

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