Quantum circuit control incorporating programmable digital pattern generator

Abstract

A novel and useful apparatus and method of programmable control of quantum operations with error correction used to control analog circuits necessary for controlling qubits in a QDA. In order to facilitate software development, a system is provided where lower-level patterns can be composed into higher-level patterns referred to as "characters." The order of character processing and the content of characters is user programmable. A three-level pattern generator architecture is used to decompose programmable "characters" into qubit control signal transitions. The highest level of abstraction in the circuit is L2 character memory and associated control logic which stores characters in linked lists. An L1 layer of parallel state machines consumes and plays out characters consisting of a set of states over time as output patterns. A L0 layer maps outputs from L1 to qubit control signals where the pattern chosen for a qubit can be altered based on qubit measurement outputs.

Description

[0001] 12485.0117

[0002] QUANTUM CIRCUIT CONTROL INCORPORATING PROGRAMMABLE DIGITAL PATTERN GENERATOR

[0003] REFERENCE TO PRIORITY APPLICATION

[0004] This application claims the benefit of U.S. Provisional Application No. 63 / 734,652, filed December 16, 2024, entitled “Quantum Circuit Control Incorporating Programmable Digital Pattern Generator” incorporated herein by reference in its entirety.

[0005] FIELD OF THE DISCLOSURE

[0006] The subject matter disclosed herein relates to the field of quantum computing and more particularly relates to a system and method of programmable control of qubits and quantum operations in a quantum dot array.

[0007] BACKGROUND OF THE INVENTION

[0008] Quantum computing holds the promise of solving certain classes of problems that are intractable for classical computers, including factorization of large numbers, simulation of quantum mechanical systems, optimization problems, and machine learning tasks. Practical realization of this promise, however, requires the construction of quantum processors comprising large numbers of physical qubits that can be initialized, manipulated, and measured with extremely high fidelity while maintaining sufficiently long coherence times. Qubits, however, require accurate and fast timing control that cannot be fixed at circuit design time.

[0009] It is thus desirable to have a programmable solution for controlling qubits in a quantum dot array that addresses the challenges of accurate and fast timing control, response to measurement results, and scalability. Qubits require accurate and fast timing control that cannot be fixed at circuit design time. Qubit control can consist of operations such as calibration, measurement, and correction. Qubit control may need to respond to measurement results in a timely manner. The speed of corrections and the number of signals under control do not make this problem suitable for control via standard components such as CPUs. 12485.0117

[0010] SUMMARY OF THE INVENTION

[0011] The present invention is a novel and useful apparatus and method of programmable control of quantum operations with error correction incorporating digital logic circuits that are used to control the analog circuits necessary for controlling qubits in the quantum dot array. In order to facilitate software development, a system is provided where lower-level patterns can be composed into higher-level patterns referred to as “characters.” The order of character processing and the content of characters is user programmable.

[0012] In one example embodiment, a three-level pattern generator architecture is used to decompose programmable “characters” into qubit control signal transitions. The highest level of abstraction in the circuit is a character memory and associated control logic known as “L2” or “L2 layer”. The L2 layer stores characters in one or more linked lists. Characters are loaded automatically to the next lower level of the pattern generator based on “next address” information stored within the characters. A sufficiently wide memory channel is provided along with alternating buffers to ensure an uninterrupted supply of characters under normal conditions. Note that the L2 layer can output multiple characters in parallel.

[0013] The next lower level of abstraction is known as “LI” or LI layer”. At this layer, characters are consumed and played out over time as patterns. In one embodiment, characters consist of a set of states. Each state comprises: (1) an opcode controlling state transitions, (2) a cycle count to control state exit, and (3) a set of output bits to control signals in the quantum dot array (QDA). The LI layer contains parallel state machines to consume multiple characters and generate multiple output patterns in parallel.

[0014] The lowest level of abstraction in the circuit is known as “L0” or “L0 layer”. At this level, outputs from LI are mapped to a plurality of qubit control signals. The LI pattern chosen for a given qubit can be altered based on measurement outputs.

[0015] Several advantages of the pattern generator include: (1) qubit control patterns can be composed in the field rather than being fixed in hardware; (2) qubit control patterns can be composed of individual “characters” which can represent elements of qubit control; (3) software can then create abstraction layers to allow compiling of user-defined patterns to run on this circuit; (4) this solution can accommodate patterns and sequences not yet defined, and can be manipulated in real time to respond to environmental changes; (5) qubit control patterns can respond to qubit measurements in real time; and (6) large numbers of qubit control signals can be controlled at once.

[0016] There is thus provided in accordance with the invention, a programmable digital pattern generator for use in a quantum computer having a plurality of qubits, comprising memory for 12485.0117 storing a plurality of linked lists of characters, each character comprising a plurality of state machine entries, each state machine entry comprising pattern output encoding, a plurality of parallel state machines for progressing through each character and generating corresponding pattern outputs, and an expansion circuit for expanding pattern output encoding to analog output signals for controlling individual qubits in a quantum dot array.

[0017] There is also provided in accordance with the invention, a quantum computing machine, comprising a classical computing core, a quantum computing core comprising a plurality of qubit arranged in a quantum dot array, and a programmable digital pattern generator operative to generate pattern outputs of time-sequenced control pulses to control said plurality of qubits in accordance with one or more user-programmable sequences composed of characters each comprising multiple states, whereby a plurality of parallel state machines are adapted to progress through the states in each character and generate said time-sequenced control pulses.

[0018] There is further provided in accordance with the invention, a method of controlling a plurality of qubits in a quantum dot array of a quantum computer, the method comprising programming a plurality of characters into a character memory, each character comprising a sequence of states, each state defining pattern output control bits, arranging said characters into one or more linked-list sequences using next-address pointers, continuously supplying said characters from the character memory to a plurality of parallel state machines, generating, via said parallel state machines, a plurality of independent time-based patterns simultaneously, mapping, on a per-qubit basis, a selected one of said independent time-based patterns to each qubit’s control signals, and dynamically altering, in real time and in response to measurement results from one or more qubits, which of said independent time-based patterns is mapped to any given qubit.

[0019] 12485.0117

[0020] BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention is explained in further detail in the following exemplary embodiments and with reference to the figures, where identical or similar elements may be partly indicated by the same or similar reference numerals, and the features of various exemplary embodiments being combinable. It should be expressly understood that the drawings are included for illustrative purposes and do not represent the scope of the present system. It is to be understood that the figures may not be drawn to scale. Further, the relation between objects in a figure may not be to scale and may have a reverse relationship as to size. In the accompanying drawings, like reference numbers in different drawings may designate identical or similar elements, portions of similar elements and / or elements with similar functionality. The present system is explained in further detail, and by way of example, with reference to the accompanying drawings which show features of various exemplary embodiments that may be combinable and / or severable wherein:

[0022] Fig. 1 is a high level block diagram illustrating a first example quantum computer system constructed in accordance with the present invention;

[0023] Fig. 2 is a high level block diagram illustrating an example pattern generator coupled to a host and QDA;

[0024] Fig. 3 is a diagram illustrating an example interface between the pattern generator and multiple analog configuration targets;

[0025] Fig. 4 is a diagram illustrating an example register structure in the analog configuration target in more detail;

[0026] Fig. 5 is a diagram illustrating an example multi-layer architecture of the pattern generator constructed in accordance with the present invention;

[0027] Fig. 6 is a diagram illustrating the contents of an example linked list character in more detail;

[0028] Fig. 7 is a diagram illustrating an example L2 linked list layer circuit in more detail;

[0029] Figs. 8A and 8B is a diagram illustrating a first example LI state machine layer circuit in more detail;

[0030] Figs. 8Cis a diagram illustrating a second example LI state machine layer circuit in more detail;

[0031] Fig. 9 is a diagram illustrating an example L0 DAC control layer circuit in more detail;

[0032] Figs. 10A, 10B, and 10C is a timing diagram illustrating example timing and waveforms for pattern generation and control signals; and

[0033] Fig. 11 is a flow diagram illustrating an example pattern generator operating sequence. 12485.0117

[0034] DETAILED DESCRIPTION

[0035] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be understood by those skilled in the art, however, that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

[0036] Among those benefits and improvements that have been disclosed, other objects and advantages of this invention will become apparent from the following description taken in conjunction with the accompanying figures. Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the invention that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention which are intended to be illustrative, and not restrictive.

[0037] The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

[0038] The figures constitute a part of this specification and include illustrative embodiments of the present invention and illustrate various objects and features thereof. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. In addition, any measurements, specifications and the like shown in the figures are intended to be illustrative, and not restrictive. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

[0039] Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention. 12485.0117

[0040] Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method. Any reference in the specification to a system should be applied mutatis mutandis to a method that may be executed by the system.

[0041] Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The phrases “in one embodiment,” “in an example embodiment,” and “in some embodiments” as used herein do not necessarily refer to the same embodiment s), though it may. Furthermore, the phrases “in another embodiment,” “in an alternative embodiment,” and “in some other embodiments” as used herein do not necessarily refer to a different embodiment, although it may. Thus, as described below, various embodiments of the invention may be readily combined, without departing from the scope or spirit of the invention.

[0042] In addition, as used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and / or,” unless the context clearly dictates otherwise. The term “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. In addition, throughout the specification, the meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

[0043] Quantum Computer Architecture

[0044] A high-level block diagram illustrating a first example quantum computer system constructed in accordance with the present invention is shown in Figure 1. The quantum computer, generally referenced 10, comprises a conventional (i.e. not a quantum circuit) external support unit 12, software unit 20, cryostat unit 36, quantum processing unit 38, clock generation units 33, 35, and one or more communication busses between the blocks. The external support unit 12 comprises operating system (OS) 18 coupled to communication network 76 such as LAN, WAN, PAN, etc., decision logic 16, and calibration block 14. Software unit 20 comprises control block 22 and digital signal processor (DSP) 24 blocks in communication with the OS 18, calibration engine / data block 26, and application programming interface (API) 28.

[0045] Quantum processing unit 38 comprises a plurality of quantum core circuits 60, high speed interface 58, detectors / samplers / output buffers 62, quantum error correction (QEC) 64, digital block 66, analog block 68, correlated data sampler (CDS) 70 coupled to one or more analog to digital converters (ADCs) 74 as well as one or more digital to analog converters (DACs, not shown), clock / divider / pulse generator circuit 42 coupled to the output of clock generator 35 which comprises high frequency (HF) generator 34. The quantum processing unit 12485.0117

[0046] 38 further comprises serial peripheral interface (SPI) low speed interface 44, cryostat software block 46, microcode 48, command decoder 50, software stack 52, memory 54, and pattern generator 56. The clock generator 33 comprises low frequency (LF) generator 30 and power amplifier (PA) 32, the output of which is input to the quantum processing unit (QPU) 38. Clock generator 33 also functions to aid in controlling the spin of the quantum particles in the quantum cores 60.

[0047] The cryostat unit 36 is the mechanical system that cools the QPU down to cryogenic temperatures. Typically, it is made from metal and it can be fashioned to function as a cavity resonator 72. It is controlled by cooling unit control 40 via the external support unit 12. The cooling unit control 40 functions to set and regulate the temperature of the cryostat unit 36. By configuring the metal cavity appropriately, it is made to resonate at a desired frequency. A clock is then driven via a power amplifier which is used to drive the resonator which creates a magnetic field. This magnetic field can function as an auxiliary magnetic field to aid in controlling one or more quantum structures in the quantum core.

[0048] The external support unit / software units may comprise any suitable computing device or platform such as an FPGA / SoC board. In one embodiment, it comprises one or more general purpose CPU cores and optionally one or more special purpose cores (e.g., DSP core, floating point, etc.) that that interact with the software stack that drives the hardware, i.e. the QPU. The one or more general purpose cores execute general purpose opcodes while the special purpose cores execute functions specific to their purpose. Main memory comprises dynamic random access memory (DRAM) or extended data out (EDO) memory, or other types of memory such as ROM, static RAM, flash, and non-volatile static random access memory (NV SRAM), bubble memory, etc. The OS may comprise any suitable OS capable of running on the external support unit and software units, e.g., Windows, MacOS, Linux, QNX, NetBSD, etc. The software stack includes the API, the calibration and management of the data, and all the necessary controls to operate the external support unit itself.

[0049] The clock generated by the high frequency clock generator 35 is input to the clock divider 42 that functions to generate the signals that drive the QPU. Low frequency clock signals are also input to and used by the QPU. A slow serial / parallel interface (SPI) 44 functions to handle the control signals to configure the quantum operation in the QPU. The high speed interface 58 is used to pump data from the classic computer, i.e. the external support unit, to the QPU. The data that the QPU operates on is provided by the external support unit.

[0050] Non-volatile memory may include various removable / non-removable, volatile / nonvolatile computer storage media, such as hard disk drives that reads from or writes 12485.0117 to non-removable, nonvolatile magnetic media, a magnetic disk drive that reads from or writes to a removable, nonvolatile magnetic disk, an optical disk drive that reads from or writes to a removable, nonvolatile optical disk such as a CD ROM or other optical media. Other removable / non-removable, volatile / nonvolatile computer storage media that can be used in the exemplary operating environment include, but are not limited to, magnetic tape cassettes, flash memory cards, digital versatile disks, digital video tape, solid state RAM, solid state ROM, and the like.

[0051] The computer may operate in a networked environment via connections to one or more remote computers. The remote computer may comprise a personal computer (PC), server, router, network PC, peer device or other common network node, or another quantum computer, and typically includes many or all of the elements described supra. Such networking environments are commonplace in offices, enterprise-wide computer networks, intranets and the Internet.

[0052] When used in a LAN networking environment, the computer is connected to the LAN via network interface 76. When used in a WAN networking environment, the computer includes a modem or other means for establishing communications over the WAN, such as the Internet. The modem, which may be internal or external, is connected to the system bus via user input interface, or other appropriate mechanism.

[0053] Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++, C# or the like, conventional procedural programming languages, such as the “C” programming language, and functional programming languages such as Python, MATLAB, Prolog and Lisp, machine code, assembler or any other suitable programming languages.

[0054] Also shown in Figure 1 is the optional data feedback loop between the quantum processing unit 38 and the external support unit 12 provided by the partial quantum data read out. The quantum state is stored in the qubits of the one or more quantum cores 60. The detectors 62 function to measure / collapse / detect some of the qubits and provide a measured signal through appropriate buffering to the output ADC block 74. The resulting digitized signal is sent to the decision logic block 16 of the external support unit 12 which functions to reinject the read out data back into the quantum state through the high speed interface 58 and quantum initialization circuits. In an alternative embodiment, the output of the ADC is fed back to the input of the QPU. 12485.0117

[0055] In one embodiment, quantum error correction (QEC) is performed via QEC block 64 to ensure no errors corrupt the read out data that is reinjected into the overall quantum state. Errors may occur in quantum circuits due to noise or inaccuracies similarly to classic circuits. Periodic partial reading of the quantum state function to refresh all the qubits in time such that they maintain their accuracy for relatively long time intervals and allow the complex computations required by a quantum computing machine.

[0056] It is appreciated that the architecture disclosed herein can be implemented in numerous types of quantum computing machines. Examples include semiconductor quantum computers, superconducting quantum computers, magnetic resonance quantum computers, optical quantum computers, etc. Further, the qubits used by the quantum computers can have any nature, including charge qubits, spin qubits, hybrid spin-charge qubits, etc.

[0057] In one embodiment, the quantum structure disclosed herein is operative to process a single particle at a time. In this case, the particle can be in a state of quantum superposition, i.e. distributed between two or more locations or charge qdots. In an alternative embodiment, the quantum structure processes two or more particles at the same time that have related spins. In such a structure, the entanglement between two or more particles could be realized. Complex quantum computations can be realized with such a quantum interaction gate / structure or circuit.

[0058] In alternative embodiments, the quantum structure processes (1) two or more particles at the same time having opposite spin, or (2) two or more particles having opposite spins but in different or alternate operation cycles at different times. In the latter embodiment, detection is performed for each spin type separately.

[0059] Pattern Generator Circuit and Operation

[0060] A high level block diagram illustrating an example pattern generator coupled to a host and QDA is shown in Figure 2. The example system comprises a pattern generator circuit 82 in communication with a host or upper layer control and memory 80 (e.g., DRAM) and a quantum dot array (QDA) 84. In operation, the host 80 provides character data 86 and configuration 88 to the pattern generator and receives status information 90 therefrom. The character data is processed to generate a plurality of qubit control signals 92 that are output to the QDA 84. One or more qubit measurements 94 from the QDA are decoded via decoder 98 to generate qubit decisions 96 that are fed back to the pattern generator. The pattern generator provides programmable control of quantum operations with error correction utilizing digital logic circuits for controlling the analog circuits that control qubits in the quantum dot array. 12485.0117

[0061] The pattern generator is configured to process high level characters comprising lower level patterns.

[0062] A diagram illustrating an example pattern generator coupled to multiple analog configuration targets is shown in Figure 3. The example system, generally referenced 100, comprises pattern generator 101 and analog configuration registers 106 coupled to system bus 108, data / select interface (I / F) 102, configuration I / F 107 and a plurality of analog configuration target blocks 103, DACs 104, and qubits 105.

[0063] A diagram illustrating an example analog configuration target in more detail is shown in Figure 4. In one embodiment, the analog configuration targets comprise low level patterns used to directly control the qubits in the QDA. They comprise a plurality of values 120 for upper DACs including a DAC value 122, phase rise value 124, phase fall value 126, and precharge value 128. They also comprise a plurality of values 130 for lower DACs including a DAC value 132, phase rise value 134, phase fall value 136, and precharge value 138. A detector block 140 is also provided that includes a detector value 142 generated from the QDA output.

[0064] A diagram illustrating the layers of an example pattern generator in accordance with the present invention is shown in Figure 5. The circuit, generally referenced 150, comprises pattern generator block 152 coupled to host 154, memory 156, and QDA 174. In one embodiment, the pattern generator comprises three layers, L2 linked list layer 158, LI state machine layer 160, and L0 DAC control layer 162.

[0065] In this example, a three-level pattern generator architecture is used to decompose programmable “characters” received from the host into qubit control signal transitions. The highest level of abstraction in the circuit is a character memory and associated control logic known as “L2” or “L2 layer” 158. The L2 layer stores characters in one or more linked lists made up of character entries 164. Characters are loaded automatically to the next lower level of the pattern generator based on “next address” information 165 stored within the characters. A sufficiently wide memory channel is provided along with alternating buffers to ensure an uninterrupted supply of characters under normal conditions. Note that the L2 layer can output multiple characters in parallel.

[0066] The next lower level of abstraction is known as “LI” or LI layer” 160 which contains multiple parallel state machines to consume multiple characters and generate multiple output patterns in parallel. At this layer, characters 166 are consumed and played out over time as patterns. In one embodiment, characters consist of a set of states. Each state comprises: (1) an opcode controlling state transitions, (2) a cycle count to control state exit, and (3) a set of output bits to control signals in the quantum dot array (QDA). 12485.0117

[0067] The lowest level of abstraction in the circuit is known as “L0” or “L0 layer” 162. At this level, pattern outputs 170 from LI layer are mapped via DAC signal generator block 168 to a plurality of DAC control signals 172 used to control the qubits in the QDA. The LI pattern chosen for a given qubit can be altered based on measurement outputs. One or more measurements from the QDA are converted to digital values 182 via ADC 176. A decoder 178 generates qubit decisions 180 from raw ADC qubit measurements 182. Note that the decoder 178 may comprise any suitable logic circuit, e.g., FPGA, etc., and may be implemented internal to or external of the pattern generator.

[0068] As described supra, the L2 layer processes words stored in linked lists in local memory. Words comprise a set of characters where the size is given by the number of entries in the linked list. A table defining a 256-bit linked list entry is presented in Table 1 below.

[0069] Table 1 : Linked List 256-bit Entry

[0070] Bits Field

[0071] [255 : 248] Next Linked List-Pattern 3

[0072] [247:240] Next Linked List-Pattern 2

[0073] [239:232] Next Linked List-Pattern 1

[0074] [231 :224] Next Linked List-Pattern 0

[0075] [223 :0] Characters output to LI (7 x 32-bits)

[0076] Note that in one embodiment, a Next Address of OxFF terminates the linked list for that pattern.

[0077] A diagram illustrating the contents of an example linked list character in more detail is shown in Figure 6. In one embodiment, the character 164 comprises eight 32-bit values seven of which are states and one of which includes four next addresses 336, one for each of the four state machines in LI layer. Each 32-bit state entry comprises a 4-bit state opcode 330, 8-bit state opcode argument 332, and a 20 bit state output 334.

[0078] The number of signals needed to be controlled in order to control the qubits in the QDA is quite large and includes two classifications. One is signals from the pattern generator circuit that drives select lines (e.g., 2 bits / DAC) into the analog configuration targets, derived from the 20-bit state output field. The scope includes the analog configuration targets to generate 10-bit values which is the full bit resolution to the DACs. In one example, 10-bit precision is needed in order to control the DACs themselves, but efficiency can be achieved by realizing that only a finite number (e.g., three) of distinct levels are needed for any given operation on a qubit. Thus, the pattern generator uses preconfigured patterns efficiently. 12485.0117

[0079] In addition, the pattern generator is programmable since it is not known before manufacturing exactly what a pattern is going to look like. Over time, understanding of the patterns is likely to change, and patterns will need to achieve different things, e.g., calibration, measurement, maintenance of qubits, error correction, or experimental use where the pattern generator is used to do individual experiments on qubits and it is desired to receive feedback information. Thus, the system is designed to be flexible and programmable. Currently, off-the- shelf components having this level of programmability are not available.

[0080] Note that the rate of updates of these patterns is quite fast. In one example embodiment, the system clock runs at 200 MHz, and at each clock cycle, all of the values that control the qubits are updated, which means qubits can be controlled to within 5 ns resolution. This is sufficient for most uses, except where higher accuracy is needed in phase control, which is handled via the analog configuration targets as well. One of 32 phases is selected from a divide counter, e.g., a Johnson counter with 32 phases. Thus, the pattern generator provides phase selection for the main clock. Note further that the pattern generator does not need to operate at very high resolution and accuracy, e.g., multiplied by 32. For the rise or fall of this clock, one of the 32 phases is selected depending on the optimum phase for clock rise and fall.

[0081] With the particular phase selected, the pattern generator looks up a value in the analog configuration targets. That selects a particular phase of the clock, and that is the clock that propagates out to the DACs. Another feature of the present invention is that patterns respond relatively quickly to measurement output. Thus, if it is detected that a correction mechanism is required on a qubit, it is performed relatively instantly. In the case of 5 ns resolution, for example, if a bit flip or phase flip is detected as necessary to correct for an error, every clock edge can respond to the error or correction instruction. It is appreciated that this cannot be performed with a CPU or similar off-the-shelf processor.

[0082] In one embodiment, all of the values for every control bit are written into a large memory, and then the pattern generator plays out these patterns from memory. This results, however, in a very large memory that is impractical to support. The number of signals per qubit tile dictates the bandwidth required from the digital domain to the analog domain. Storing the pattern in memory and playing it out has the disadvantage that the size of the memory grows too quickly to make it feasible. One approach is to have the pattern generator control each of the bits individually without taking advantage of efficiencies, thus requiring over 1350 signals. A memory is required that can be read out once per clock cycle. To change these at 5 ns resolutions requires a new set of 1350 signals every 5 ns. A microsecond of calculation thus equates to 263 kb per microsecond. 12485.0117

[0083] Rather than send all the bits to the analog circuit configuration targets, registers are provided where preconfigured values are written to the analog configuration targets, and then the lines are selected. For example, the circuit may request the middle value or the top value or whatever is needed. A programmable interface to the analog configuration targets is provided. This provides a solution to the physical design issue, i.e. the number of signals from a physical design point of view is large challenge. Thus, rather than send all the values raw from the digital to the analog domain, a smaller configuration interface is used to program the analog circuity. This also means that if the number of registers or the layout of registers changes, it is not necessary to change the interface itself. Configuration data can be re-addressed similar to an addressing system where an address space is created within the analog portion. The digital circuit writes, for example, two registers, and if the circuit in the analog portion is modified, the digital side does not need modification, and it is not necessary to change the interface. From an engineering point of view, this makes it easier to disassociate one from the other where a change to something on one side (analog or digital) does not require a change on the other side.

[0084] In one embodiment, the registers reside inside the configuration targets. They have the full resolution required to address the DACs and can be programmed across the programmable interface. When creating patterns, only the addresses are required to be sent as opposed to sending the full data width.

[0085] In one embodiment, despite using only three distinct values, the values may need to be updated. A calibration step can be performed where updated values are determined. Those values get programmed in and they typically do not change during a particular experiment or series of experiments. So, for example, during qubit initialization or similar operation, those values are expected to be static for a relatively long time duration.

[0086] For one experiment, for example, one particular pattern is exercised from the pattern generator, and during that pattern, these values are static. In some cases, information may be fed back from the qubits that is used to adjust some of the patterns in real time. Within the lifetime of a single pattern, however, it is generally be anticipated that the related programmed values are static.

[0087] In one embodiment, there are three DAC value levels. There are thus three phase rise selects and three phase fall selects. Each of those is the full 10 bits that the DAC needs. So at some point, those 10 bits are written into the register, but this is performed only once. This would be part of the setup / calibration or part of the system programming. Thus, during programming of the system, these registers are written to with one or more patterns from the pattern generator. At that point, the pattern is “played,” and the programming may be updated 12485.0117 on the fly. Typically, the pattern generator will play out, and once complete, it can move on to perform something else, which may include reprogramming some of the registers or reprogramming the pattern and then “playing” the pattern(s) again.

[0088] Once launched, the pattern generator and related circuitry can perform tasks autonomously, including things like waiting for events or waiting periods of time or responding to measurement outputs. The pattern generator can perform these things and generate an interrupt signal to declare a task complete and readiness to perform another task, e.g., reconfigure itself, etc.

[0089] It is noted that the key functionality of the system resides in the pattern generator, which has a read and write interface that can be programmed via a plurality of registers along with a phase selection mechanism. Circuitry is provided to avoid timing issues related to gating the clock. Considering 32 phases of a very fast clock, it is preferred not to generate any glitching on the clock that is fed to the DACs. Logic is included that uses selective edges of the slower clock to choose a safe place to turn on and off the fast clock so as not to create glitching.

[0090] One level of efficiency that can be taken advantage of is that not all of the DAC patterns are independent. In other words, it is not necessary to control every DAC independently all the time. DACs can be ganged together in groups. This is built into the pattern generator architecture itself where, in one embodiment, the pattern generator includes three levels: L0, LI, L2. The lowest level L0 includes the connectivity related to the DACs.

[0091] When generating patterns, there is one of four patterns to generate at any one time which correspond to the four state machines in LI layer. For example, one pattern may be an initialization pattern, one a bit flip, one a phase flip, and one that includes both a bit flip and phase flip. This is an example of the parallelism built into the system. The generated patterns are distributed to DACs, and ultimately a group of DACs that represent a qubit, which can change based on the architecture of the qubit. In one example, different qubit architecture tiles are used, with each tile having its own qubit architecture. A DAC represented in one tile can be different from another. A connectivity map is used for a particular tile to know what the relationship is between a qubit and a DAC. For example, performing initialization on a qubit, the pattern generator may perform one or more atomics working on a qubit. The connectivity level L0 represents a qubit and a corresponding set of DACs. The pattern generator determines the input to the DACs at any given point in time. In one embodiment, the pattern generator is collocated with the quantum circuitry on the same chip.

[0092] In higher level layers LI and L2, a pattern gets created which consumes time. For example, the system waits a certain amount of time before changing the output signal. The 12485.0117 pattern generator controls the timing. The L0 layer controls the patterns and directs them to the DACs or other places they need to be input to. If a particular qubit needs a different pattern to correct it, it is the L0 layer logic that considers the decoded measurement data and based on that chooses which of the patterns to direct to the qubit. In one embodiment, up to four patterns can be generated at a time with multiple qubits in the quantum dot array. The pattern generator functions to decide which pattern to write to which qubit. Signal connectivity includes multiple signals (i.e. wire, trace, etc.) for only a particular number of qubits depending on the tile.

[0093] As the number of qubits increases, the number of required signals increases linearly. The number of qubits a single pattern generator controls is typically finite. A particular tile, for example, will “x” number of qubits, which corresponds to “y” number of DACs. This dictates the number of pattern generator circuits required to control the qubits. For example, considering four tiles, one pattern generator circuit can control 17 qubits. It is appreciated that the pattern generator can be adapted accordingly to control any number of qubits.

[0094] The general architecture of the pattern generator is constructed to be able to handle modifications. The different levels of abstraction described here dictate the type of activity level and the actual patterns to be generated. One or more state machines are used to control all of the outputs needed to be sent to the L0 connectivity level. Different opcodes like a CPU are provided to decide how to progress between different states to create looping. States can be jumped, timing is controlled, state duration is controlled, etc.

[0095] In one embodiment, multiple states are bundled into characters, with each character representing some meaningful portion of a pattern. A character is created to implement a piece of a pattern. Ultimately, a pattern becomes a word or a set of words where it is composed with characters and then provided to the next processing level. The pattern generator then feeds these characters into respective state machines in a particular order and “plays” them out through the system. With all the different levels of complexity, it is broken down in such a way that when software is capable of composing these patterns, it is done in a way that the abstraction of the hardware itself represents something meaningful. This creates a system that can compose these patterns, which are useful in providing a more intuitive way to control the qubits than having to resort to the low-level components of the pattern generator.

[0096] Note that some of the signals are used only by that particular level itself. There is, for example, a signal for sampling the output to the measurement system which is not distributed to the qubits. Within the state machines themselves are several functions performed within the state machine itself and then other functions that are performed to the qubits. 12485.0117

[0097] In one embodiment, functionality of the pattern generator is divided into three levels or layers: L2 layer comprising the word layer of linked lists in local memory storing multiple characters; LI layer comprising character layer of multiple state machines to generate characters; and L0 layer comprising the connection to direct patterns to individual qubits.

[0098] In one embodiment, local memory is used to enable deterministic operation of the pattern generator. Note that it is not desirable to fetch data from a system with variable latency for the anticipated application of the system. Character memory of 256 bits has been found sufficient to store an entire character such that several state machines can digest a full character at a time.

[0099] L2 Linked List Layer

[0100] Each of the three processing layers will be now be described in more detail. A diagram illustrating an example L2 linked list layer circuit in more detail is shown in Figure 7. The L2 linked list layer, generally referenced 190, comprises memory read / write 194 to and from system bus 192, character linked list memory 196 which in this example is 32x256 with each row comprising a character as described supra in connection with Figure 6, linked list read circuit 198 including buffer selection 200 and next character decode 202, character buffer 204 including buffer write pointers 206, ping pong buffers 208, and buffer read pointers 210, configuration / status 212 coupled to the system bus 192, and L2 control and state machine 214 including idle 216, priming 218, and active 220 modes.

[0101] The function of the L2 layer is to seamlessly serve characters to each pattern state machine in LI. Each L2 linked list entry contains a character and an address pointing to the next L2 linked list entry. As the LI layer consumes characters, L2 linked list entries are following until a termination entry is found. Each L2 linked list entry has an independent next entry for each LI pattern.

[0102] Characters are stored in memory 196 and read out by the linked list read circuit 198 to the character buffer 204 where they are written to ping pong (double) buffers 208. Characters are written to one half of the buffer via buffer write pointers 206 while the other half is read out via buffer read pointers 210. In this example, four character lines 230 are output to the LI layer while handshaking lines 232 from the LI layer are input to the character buffer circuit.

[0103] Several interrupt signals are generated by the L2 layer and output to the host including a 4-bit termination interrupt indicating that a pattern has been terminated, underflow interrupt indicating that more characters can be written to the memory, and a ‘done’ interrupt indicating 12485.0117 a pattern has finished. In addition, a 4-bit active signal is generated indicating which of the four simultaneous patterns are active at a point in time.

[0104] In the example pattern generator disclosed herein, there are four linked lists (LLs) in L2 with a 1 : 1 mapping between these four inked lists and the state machines. It is appreciated that the pattern generator can be implemented with more or less linked lists and corresponding state machines in accordance with the particular implementation.

[0105] In operation, each linked list (LL) starts at the start address given by the configuration register. The character at this address gets loaded into the buffer 204 corresponding to the linked list (0 for LLO, 1 for LL1, 2 for LL2, etc.). The next address for each linked list is recorded. For each linked list, the buffers are filled until the ping and pong locations for each buffer are full. At this point, pattern generation is ready to begin.

[0106] As the four state machines in LI layer, described in more detail infra, consume characters they signal this to L2 via CHAR DONE signals. On each clock cycle L2 checks each buffer in turn to see if it has an empty location. If it does, it reads the next location for that buffer and loads in the character. In one embodiment, it can only do one read from the linked list per cycle so if there are multiple buffers that require new chars they will be serviced in turn over multiple cycles.

[0107] Pseudo code examples for priming of the buffers, servicing the buffers, and output of the buffers to LI layer are presented below.

[0108] Pseudo code 1 : Priming the buffers for LLindex in 0, 1,2,3: if pattern_enable[LLindex]: buffer[LLindex][ping] = LinkedList[LLStartAddr[LLindex]].char nextfLL] = LinkedList[LLStartAddr[LL].next] buffer[LL][pong] = LinkedList[next[LL]].char nextfLL] = LinkedList[next[LL]].next buffer_write_pointer[LLindex] = ping buffer read pointer[LLindex] = ping

[0109] _ Pseudo code 2: Servicing the buffers _ for LLindex in 0, 1,2,3: if pattern enablefLLindex]: if buffer not full [LLindex] : buffer[LLindex][ping] = LinkedList[LLStartAddr[LLindex]].char next[LL] = LinkedList[LLStartAddr[LL].next] buffer_write_pointer[LLindex] = swap_write_pointer(LLindex) wait for next clock cycle # can only do one LinkedList read per cycle 12485.0117

[0110] Pseudo code 3: Output buffers to LI Layer for LLindex in 0, 1,2,3: if pattern_enable[LLindex]: if char_done[LLindex]: buffer_read_pointer[LLindex] = swap_read_pointer(LLindex) charfLLindex] = buff er [LLindex] [buff er read pointer]

[0111] LI State Machine Layer

[0112] A diagram illustrating a first example LI state machine layer circuit in more detail is shown in Figures 8A and 8B. The LI state machine layer, generally referenced 240, comprises four state machine circuits 244, state machine 0 through 3. Each state machine block receives characters 230 from L2 layer and outputs a character done signal 232. Each state machine generates a 20-bit state output 256 and function and trace interrupts 258, 260, respectively, that are output to the L0 layer. Configuration and status information 242 are communicated over the system bus 192.

[0113] As each character is input and processed, the flow for each state machine begins with initializing the state to 0 (step 244) and setting the count to state. count (step 246. The clock count is decremented (step 247) based on decoding of the opcodes and as long as the count has not reached 0 (step 248), the state remains constant. Once the count has decremented to zero, the next state is computed (step 250). This is performed by checking the opcode and implementing the instructions in accordance with the case statement shown. If the next state equals 7 or the next opcode is EXIT (step 252), character processing is complete (step 254) and processing returns to step 244. Otherwise, processing returns to step 246 to process the next opcode.

[0114] In operation, the LI layer processes characters in a state machine and generates pattern outputs. In one embodiment, a character has 7x32-bit locations with one location used by L2 link layer control. This functionality is duplicated for each pattern required (e.g., initialization, bit flip, etc.). Characters are formed by a series of entries which both encode the output and also the progression through the character. There are multiple opcodes for character progression including, for example, INCR (increment), WAIT, LOOP, etc.

[0115] To maintain pattern progression seamless, a pair of ping / pong buffers in L2 are used. One is loaded while the other generates output. To ensure no underflow, the loading of characters into LI layer is preferably faster than the progress through the pattern. A single character location entry is shown in Table 2 below. 12485.0117

[0116] Table 2: Single character location entry

[0117] [31 :28] [27:20] [19:0]

[0118] Opcode Opcode Argument Output

[0119] Note that each entry comprises a 4-bit opcode, 8-bit opcode argument, and 20-bit output field which is passed to LO layer. An example set of 11 opcodes and associated opcode arguments are provided below in

[0120] Table 3.

[0121] Table 3: Opcodes and Opcode Arguments

[0122] Opcode [31 :28] Value Description Opcode Argument [27:20]

[0123] INCR 0 Increment state 27:20 Cycle count

[0124] HALT 1 Halt execution 27:20 Cycle count

[0125] EXIT 2 Exit character 27:20 Cycle count

[0126] JUMP 3 Jump to state 27:25 Jump state; 24:20 Cycle count

[0127] LOOP 4 Loop to state 27:25 Loop state; 24:20 Loop count

[0128] SYNC 5 Wait for sync pulse 27:26 Sync Sei; 25:20 Cycle count

[0129] WAIT 6 Wait for event 27:20 Cycle count

[0130] IRQF 7 Generate functional interrupt 27:20 Cycle count

[0131] TRCE 8 Record trace value 25:23 Trace Slot; 23:20 Trace value

[0132] IRQT 9 Generate trace interrupt 27:20 Cycle count

[0133] INCL 10 Increment state long 27:20 Cycle count « 8 Example output bits for the 20-bit output field is shown below in Table 4.

[0134] Table 4: Output Bits

[0135] Output [19:0] MSB LSB # Bits Description

[0136] DAC Value Sei 4 0 5 DAC values via L0 Stage 1 and DAC mapping

[0137] Phase Rise Sei 6 5 2 Phase rise select to DACs via DAC mapping

[0138] Phase Fall Sei 8 7 2 Phase fall select to DACs via DAC mapping

[0139] Precharge Sei 9 9 1 Always from Pattern 0 (1 -bit precharge)

[0140] Sample Enable 10 10 1 Always from Pattern 0 (1 -bit ready signal)

[0141] Detector Bus 18 11 8 Always from Pattern 0 ( 1 -bit dig-ana meas.)

[0142] Sync Output 19 19 1 Always from Pattern 0 to GPIO pins

[0143] Example values used for the detector bus from the QDA to the pattern generator is shown below in Table 5 below. 12485.0117

[0144] Table 5: Detector Bus _ _ _ _ _ d2A det s4

[0145] A diagram illustrating a second example LI state machine layer circuit in more detail is shown in Figure 8C. To aid in understanding the operation of the pattern generator, an alternative view of the pattern generator is shown having the same functionality of the circuit of Figure 8A. This second LI state machine layer circuit 241 comprises, for example, four state machines 0 through 3 306 with each state machine comprising a memory 290 for storing at least one character including seven states SO through S6, each including opcode 303 and output 305 fields, multiplexer 292, state trace logic 308, control block 294 that implements the state machine logic and which includes state transition timer 296, next state decoder 298, and current state 300.

[0146] In operation, characters 302 are passed to the LI state machine layer which functions to process them and generate patterns for the L0 DAC control layer for distribution to the analog circuitry. The LI layer characters 302 contain opcodes which control the sequence of character processing. Each of the state entries in the LI character 290 contains an output field 305 to control the outputs for that particular entry. The state machine control logic 294 generates an appropriate select signal for multiplexer 292 to steer the output field of one of the seven states to the state. output 310. A character done signal 304 is also generated that is fed back to the L2 layer to indicate when processing of a character is complete and to forward the next character in the linked list. Each state machine 306 has an associated input character, character done, and state output signals. It is noted that the functionality of the circuit of Figure 8B is exactly the same as that of Figure 8 A.

[0147] L0 DAC Control Layer

[0148] A diagram illustrating an example L0 DAC control layer circuit in more detail is shown in Figure 9. The L0 DAC control layer, generally referenced 270, comprises a configuration / status register and related circuit 272 in communication with the system bus 192, Four DAC output expand circuits 274, each associated with one of the patterns / state machines, a plurality of multiplexers 278 operative to generate N DAC control signals 280 that are output 12485.0117 to the QDA. The selects for the multiplexers is generated by the qubit to DAC mapping circuit 284 which receives the qubit decisions 180 output of the decoder 178 (Figure 5) based on the ADC raw measurements from the qubits in the QDA.

[0149] Thus, the LI output field is passed to the L0 layer to control the driving of signals to analog. Note that some bits from the LI output field are passed directly to analog pins, while other bits are input to multiplexers 278 under control of qubit measurement decisions to control qubit correction patterns. In the case of DAC values to analog LI layer outputs, a bus is used as an index into a stage 1 table (not shown) in the L0 layer.

[0150] As described supra, the L0 layer controls the hardware muxing output signals from LI layer to individual qubits. Control of the muxing is from QNN / LUT outputs 180. In one embodiment, the output signals represent decisions based on qubit outputs. Expansion of the reduced width DAC select values to full values is performed in this layer.

[0151] Example control outputs from the L0 layer are shown below in Table 6.

[0152] Table 6: L0 Outputs

[0153] Output Name Width Description pg dac value sel 96x2 DAC value select to analog configuration target; 2-bits per DAC+ pg_dac_phase_rise_sel 96x2 Phase rise select to analog configuration target; 2-bits per DAC+ pg_dac_phase_fall_sel 96x2 Phase fall select to analog configuration target; 2-bits per DAC+ pg_precharge_sel 1 Precharge clock select to analog pg detector 8 Detector control bus (same used for all detectors) pg_sync_out 1 Sync output to GPIO qnn_sample_en 1 Sample measurements at QNN lut sample en 1 Sample measurements at LUT

[0154] Note that depending on the particular DAC mapping, not all DACs are actively driven at the same time.

[0155] A timing diagram illustrating the clock and data signals of an example pattern generator circuit is shown in Figures 10A, 10B, and 10C. These figures show the timing waveforms for the various clock, data, and control signals for the pattern generator from start of a pattern to the end of the pattern for the example of four patterns running in parallel.

[0156] A flow diagram illustrating an example pattern generator operating sequence is shown in Figure 11. The operating sequence of the pattern generator 152 (Figure 5) begins with enabling and initializing the pattern generator (step 320). Characters are then loaded into the L2 layer character memory (step 322). The state addresses for each used linked list is then 12485.0117 programmed or configured appropriately (step 324). Note that in operation, not all the linked lists (i.e. state machines) may be used all the time. Considering the example of four patterns / state machines presented herein, it is possible that one, two, or three of the four linked lists (i.e. patterns) are active. The number of linked list active at any one time is dependent on the activity of the QDA. The used that are in use are then activated (step 326). A soft reset is then performed on the L2 layer and character processing proceeds (step 328).

[0157] The pattern generator described supra have several advantages including: (1) qubit control patterns are composed in the field rather than being fixed in hardware; (2) qubit control patterns are composed of individual “characters” which can represent elements of qubit control; (3) software is used to create abstraction layers to allow compiling of user defined patterns to run on the circuit; (4) the circuit is able to accommodate patterns and sequences not yet defined, and can be manipulated in real time to respond to environmental changes; (5) qubit control patterns respond to qubit measurements in real time; and (6) large numbers of qubit control signals can be controlled simultaneously.

[0158] In one embodiment, the pattern generator is adapted to be integrated within the same hybrid classical / quantum device as the qubits. In addition, the pattern generator circuit is suitable for integration within the cryostat and is able to function at cryogenic temperatures of less than one Kelvin. This capability provides an advantage in terms of latency, bandwidth and signal connectivity compared with prior art systems that perform qubit control outside the cryostat. Typically, connections from outside the cryostat are very limited in number and carry a high penalty as they conduct heat in and out of the cryostat chamber. Further, external connections require signals to be driven much further distances thus consuming additional power. It is noted that in systems with a sufficient number of qubits to perform practical quantum computing it will not be physically possible to provide sufficient connectivity to implement qubit control externally.

[0159] Those skilled in the art will recognize that the boundaries between logic and circuit blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.

[0160] Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other 12485.0117 such that the desired functionality is achieved, irrespective of architectures or intermediary components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.

[0161] Furthermore, those skilled in the art will recognize that boundaries between the above described operations are merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

[0162] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0163] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first,” “second,” etc. are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

[0164] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form 12485.0117 disclosed. As numerous modifications and changes will readily occur to those skilled in the art, it is intended that the invention not be limited to the limited number of embodiments described herein. Accordingly, it will be appreciated that all suitable variations, modifications and equivalents may be resorted to, falling within the spirit and scope of the present invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

12485.0117CLAIMS1. A programmable digital pattern generator for use in a quantum computer having a plurality of qubits, comprising: memory for storing a plurality of linked lists of characters, each character comprising a plurality of state machine entries, each state machine entry comprising pattern output encoding; a plurality of parallel state machines for progressing through each character and generating corresponding pattern outputs; and an expansion circuit for expanding pattern output encoding to analog output signals for controlling individual qubits in a quantum dot array.

2. The programmable digital pattern generator according to claim 1, wherein said characters stored in said memory are user-composable, enabling arbitrary qubit control sequences.

3. The programmable digital pattern generator according to claim 1, wherein said pattern generator is configured to operate autonomously after being launched, including waiting for events, waiting for specified time periods, and responding to measurement outputs.

4. The programmable digital pattern generator according to claim 1, wherein said expansion circuit comprises connectivity mapping that gangs groups of digital to analog converter (DAC) circuits together thereby reducing the number of independently controlled signals.

5. A quantum computing machine, comprising: a classical computing core; a quantum computing core comprising a plurality of qubit arranged in a quantum dot array; and a programmable digital pattern generator operative to generate pattern outputs of time- sequenced control pulses to control said plurality of qubits in accordance with one or more user-programmable sequences composed of characters each comprising multiple states, whereby a plurality of parallel state machines are adapted to progress through the states in each character and generate said time- sequenced control pulses.12485.01176. The quantum computing machine according to claim 5, wherein said pattern generator is configured to alter, in real time and in response to qubit measurement results, which pattern output is applied to any given qubit.

7. The quantum computing machine according to claim 5, wherein said pattern generator comprises a character memory configured to store a linked list of characters and control logic configured to automatically supply a next character using next-address information stored with each character, each character comprising a plurality of state machine entries, each state machine entry comprising pattern output encoding.

8. The quantum computing machine according to claim 5, wherein said pattern generator comprises a plurality of parallel state machines configured to consume characters and to generate a plurality of output patterns simultaneously, each character comprising a plurality of states, each state including an opcode controlling state transition, a cycle count controlling state duration, and a set of output bits.

9. The quantum computing machine according to claim 5, wherein each state machine is configured to generate a pattern output adapted to perform a particular qubit operation.

10. The quantum computing machine according to claim 5, wherein said qubit operation is selected from the group consisting of initialization, bit flip, phase flip, combined bit flip and phase flip, phase rise, phase fall, calibration, measurement, maintenance, error correction, and experimental.

11. The quantum computing machine according to claim 5, wherein said pattern generator comprises an expansion circuit configured to map outputs from states to qubit control signals and to conditionally select, on a per-qubit basis and in response to real-time measurement outputs, which of a plurality of simultaneously generated patterns is routed to each qubit.

12. The quantum computing machine according to claim 5, further comprising a plurality of analog configuration targets containing registers that store a plurality of preprogrammed voltage levels, wherein the pattern generator generates select signals that choose among said pre-programmed voltage levels rather than transmitting fullresolution data every clock cycle.12485.011713. The quantum computing machine according to claim 5, further comprising phaseselection circuitry configured to select one of a plurality of phases of a clock for rise and fall edges at digital to analog converters (DACs) controlling each qubit.

14. The quantum computing machine according to claim 5, further comprising a configuration interface adapted to program full resolution analog values in one or more configuration targets that are read out to qubits and associated digital to analog converters (DACs), where pattern outputs comprise one or more select lines used to address said configuration targets.

15. A method of controlling a plurality of qubits in a quantum dot array of a quantum computer, the method comprising: programming a plurality of characters into a character memory, each character comprising a sequence of states, each state defining pattern output control bits; arranging said characters into one or more linked-list sequences using next-address pointers; continuously supplying said characters from the character memory to a plurality of parallel state machines; generating, via said parallel state machines, a plurality of independent time-based patterns simultaneously; mapping, on a per-qubit basis, a selected one of said independent time-based patterns to each qubit’s control signals; and dynamically altering, in real time and in response to measurement results from one or more qubits, which of said independent time-based patterns is mapped to any given qubit.

16. The method according to claim 15, further comprising composing lower-level patterns into higher-level characters and higher-level characters into sequences, thereby enabling software abstraction layers and compilation of user-defined quantum operations into hardware-executable patterns.

17. The method according to claim 15, wherein said mapping includes ganging groups of control lines for multiple digital to analog converters (DACs) to reduce routing and bandwidth requirements.12485.011718. The method according to claim 15, further comprising autonomously executing a launched sequence, including waiting for one or more external events or measurement triggers, and issuing an interrupt to a classical computing core upon sequence completion to allow launch of a new sequence.

19. The method according to claim 15, wherein said characters stored in said memory are user-composable, enabling arbitrary qubit control sequences.

20. The method according to claim 15, wherein said plurality of parallel state machines consume characters and generate a plurality of output patterns simultaneously with each state including an opcode that controls state transition, a cycle count controlling state duration, and a set of output bits.

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