Optical semiconductor element and method for manufacturing optical semiconductor element

Abstract

Provided are: an optical semiconductor element in which increases in dark current are rare even under high temperature and high humidity conditions, and in which an electrode and an optical filter are in contact; and a method manufacturing for the same. An optical semiconductor element (1) according to the present disclosure comprises an electrode (80) and an optical filter (90) of which at least a portion is in contact with the electrode (80). The optical filter (90) includes a dielectric multilayer film, has, on the uppermost layer of the optical filter (90), a protective film (91) containing SiO2 or Si3N4, and is characterized by having, between the uppermost layer and the protective film (91), an intermediate layer which is observed to be darker than the uppermost layer and the protective film (91) in a cross-sectional TEM image.

Description

Optical semiconductor device and method for manufacturing an optical semiconductor device

[0001] This invention relates to an optical semiconductor device and a method for manufacturing an optical semiconductor device.

[0002] Optical semiconductor devices have traditionally been used in various applications such as communications and sensing. Multilayer film technology has been developed to allow for the selection of light-receiving wavelengths.

[0003] For example, Patent Document 1 discloses a photodetector for optical communication, and in Patent Document 1, in order to selectively receive light in the 1,300 nm band and the 1,550 nm band, a filter (SiO₂) is placed on the top surface of the chip. ２ / SiN / Al ２ O ３ Techniques for forming multilayer films (such as those mentioned above) are disclosed. The same document also proposes electrically isolating the semiconductor stacked portion at the boundary of adjacent filters by etching.

[0004] Furthermore, Patent Document 2 describes a technology relating to a photodetector in which the ultraviolet region is cut off by a multilayer film filter. In the same document, on the incident surface of the semiconductor chip, an optical filter of dielectric multilayer film is formed across the p-n junction on its upper surface. Furthermore, Patent Document 3 describes a technology relating to Si and SiO ２ A photodetector has been proposed that reflects wavelengths other than a specific range using a multilayer film. Furthermore, Patent Document 4 proposes a specific optical filter that reduces only some of the harmful light in the emission spectrum emitted by a light-emitting element.

[0005] Japanese Patent Publication No. 11-54785, Japanese Patent Publication No. 2004-119678, Japanese Patent Publication No. 2002-33503, Japanese Patent Publication No. 2024-132415

[0006] In recent years, sensors using light-emitting elements and light-receiving elements that emit light at specific wavelengths have been widely developed as sensing technologies for acquiring information about objects such as people. For such sensor applications, there has been a growing demand for optical semiconductor elements that include light-receiving elements with optical filters to block information other than the specific wavelength, and light-emitting elements that emit only the specific wavelength.

[0007] In order to enhance the blocking effect for wavelengths other than a specific wavelength, it is necessary to provide an optical filter without any gaps on the main surface side where light is received or emitted. However, when the optical filter is in contact with the electrode, it has been found that the leakage current (i.e., dark current) of the optical semiconductor device tends to increase significantly when used or stored under high-temperature and high-humidity conditions. Therefore, an object of the present invention is to provide an optical semiconductor device in which the electrode and the optical filter are in contact and the increase in dark current is small even under high-temperature and high-humidity conditions, and a method for manufacturing the same.

[0008] The inventors of the present invention have intensively studied means for solving the above problems. As described above, when the optical filter is in contact with the electrode, the dark current of the optical semiconductor device tends to increase significantly when used or stored under high-temperature and high-humidity conditions. While solving such reliability problems, it is necessary to fabricate an optical semiconductor device with an optical filter that covers the entire upper surface of the optical semiconductor device, which is the surface for receiving light or extracting light, or straddles the side surface of the layer having a light-receiving portion or a light-emitting portion and can cover the entire light-receiving area of the optical semiconductor device. The inventors of the present invention have found that forming a protective film on the uppermost layer of the optical filter and forming an intermediate layer between the uppermost layer of the optical filter and the protective film can lead to suppression of the increase in dark current. That is, the main configuration of the present invention is as follows.

[0009] (1) An optical semiconductor device comprising an electrode and an optical filter that is in contact with at least a part of the electrode, wherein the optical filter includes a dielectric multilayer film, and there is a SiO ２ or Si ３ N ４ - containing protective film on the uppermost layer of the optical filter, and an intermediate layer that is observed darker than the uppermost layer and the protective film in a cross-sectional TEM image is provided between the uppermost layer and the protective film.

[0010] (2) The optical semiconductor device according to (1) above, wherein the optical filter is a laminate including a Si layer and a SiO ２ layer, and the uppermost layer is a SiO ２ layer.

[0011] (3) The intermediate layer is SiO with oxygen defects ２Or the optical semiconductor device described in (1) above, which includes SiON.

[0012] (4) The optical semiconductor element according to (1) above, wherein the thickness of the protective film is an integer multiple of the value obtained by dividing the light-receiving wavelength or light-emitting wavelength of the optical semiconductor element by twice the refractive index of the protective film.

[0013] (5) The optical semiconductor element according to (1) or (2) above, wherein the optical filter has an opening that exposes a part of the electrode, and the side surface of the opening is covered by the protective film.

[0014] (6) An electrode formation step of forming electrodes on an optical semiconductor element; an optical filter formation step of forming an optical filter including a dielectric multilayer film so as to be in contact with the electrodes; and a SiO2 film on the uppermost layer of the optical filter. ２ or Si ３ N ４ A method for manufacturing an optical semiconductor device, comprising: a protective film formation step of forming a protective film including; wherein the optical filter formation step uses a sputtering method; the protective film formation step uses a plasma CVD method; and in the protective film formation step, an intermediate layer is formed between the uppermost layer and the protective film, which is observed to be darker than the uppermost layer and the protective film in a cross-sectional TEM image.

[0015] (7) The optical filter comprises a Si layer and SiO ２ It includes a laminate of layers, the uppermost layer being SiO ２ A method for manufacturing the optical semiconductor device described in (6) above, which is a layer.

[0016] (8) The intermediate layer is SiO with oxygen vacancies ２ A method for manufacturing an optical semiconductor device as described in (6) above, which also includes SiON.

[0017] (9) The method for manufacturing an optical semiconductor element as described in (6) above, wherein the thickness of the protective film is an integer multiple of the value obtained by dividing the light-receiving wavelength or emission wavelength of the optical semiconductor element by twice the refractive index of the protective film.

[0018] (10) The method for manufacturing an optical semiconductor element according to (6) above, wherein the optical filter forming step includes a step of forming an opening that exposes a part of the electrode, and the third step covers the side surface of the opening with the protective film.

[0019] (11) The optical semiconductor device according to (1), wherein the optical semiconductor device is a photodetector having a photodetector layer made of an InGaAs layer, the dark current when a reverse bias voltage of 5V is applied immediately after the fabrication of the optical semiconductor device is 0.185nA or less, and the rate of change of the dark current after 24 hours of high-speed accelerated lifetime testing is 3.5 times or less.

[0020] (12) An optical semiconductor element comprising an electrode and an optical filter in contact with at least a portion of the electrode, wherein the optical filter includes a dielectric multilayer film and the uppermost layer of the optical filter has SiO ２ or Si ３ N ４ The optical filter has a protective film containing a Si layer and SiO ２ The SiO includes a laminate of layers, and the SiO after 24 hours of high-speed accelerated lifetime testing. ２ The average D concentration within the layer is 1.5 × 10⁻⁶ ２１ atom / cm ３ The following are optical semiconductor devices.

[0021] (13) An electrode formation step in which an electrode is formed on a photo-semiconductor device, and a Si layer and SiO in contact with the electrode. ２ An optical filter forming step in which an optical filter including a dielectric multilayer film of layers is formed, and SiO is placed on the uppermost layer of the optical filter ２ or Si ３ N ４ The process includes a protective film formation step in which a protective film containing is formed, wherein the optical filter formation step uses a sputtering method, and the protective film formation step uses a plasma CVD method, and the SiO after 24 hours of high-speed accelerated lifetime testing. ２ The average D concentration within the layer is 1.5 × 10⁻⁶ ２１ atom / cm ３ A method for manufacturing an optical semiconductor device, characterized by the following:

[0022] According to the present invention, it is possible to provide an optical semiconductor element in which an electrode and an optical filter are in contact, and a method for manufacturing the optical semiconductor element, in which the dark current does not increase even under high temperature and high humidity conditions.

[0023] This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 1. This is a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 1. Here, the cross-sectional view in Figure 2A is a schematic cross-sectional view when the semiconductor photodetector Figure 2B is cut along the dotted line. This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 2A. This is a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 2B. Here, the cross-sectional view in Figure 3A is a schematic cross-sectional view when the semiconductor photodetector Figure 3B is cut along the dotted line. This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 3A. This is a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 3B. Here, the cross-sectional view in Figure 4A is a schematic cross-sectional view when the semiconductor photodetector Figure 4B is cut along the dotted line. Figure 4A is followed by a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. Figure 4B is followed by a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. Here, the cross-sectional view of Figure 5A is a schematic cross-sectional view when the semiconductor photodetector Figure 5B is cut along the dotted line. Figure 5A is followed by a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. Figure 5B is followed by a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. Here, the cross-sectional view of Figure 6A is a schematic cross-sectional view when the semiconductor photodetector Figure 6B is cut along the dotted line. Figure 6A is followed by a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. Figure 6B is followed by a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. Here, the cross-sectional view of Figure 7A is a schematic cross-sectional view when the semiconductor photodetector Figure 7B is cut along the dotted line. Figure 7A is followed by a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. This is a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 7B.Here, the cross-sectional view in Figure 8A is a schematic cross-sectional view of the semiconductor photodetector Figure 8B when it is cut along the dotted line. Following Figures 8A and 8B, this is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. This is a STEM image of Example 1, including the boundary between the 22nd and 23rd layers of the optical filter, and the boundary between the 23rd layer of the optical filter and the protective film. This is a magnified TEM image of section A in Figure 10A (boundary between the 23rd layer of the optical filter and the protective film). This is a STEM image of Example 3, including the boundary between the 22nd and 23rd layers of the optical filter, and the boundary between the 23rd layer of the optical filter and the protective film. This is a magnified TEM image of section A in Figure 11A (boundary between the 23rd layer of the optical filter and the protective film). This is a STEM image of Comparative Example 2, including the boundary between the 22nd and 23rd layers of the optical filter, and the boundary between the 23rd layer of the optical filter and the protective film (continuation of the optical filter). This is a magnified TEM image of section A in Figure 12A (the boundary between the 23rd layer of the optical filter and the protective film (continuation of the optical filter)). This is a STEM image of Comparative Example 3, including the boundary between the 22nd and 23rd layers of the optical filter, and the boundary between the 23rd layer of the optical filter and the protective film. This is a magnified TEM image of section A in Figure 13A (the boundary between the 23rd layer of the optical filter and the protective film). This is a top view of the measurement jig for measuring the resistivity of the fabricated semiconductor photodetector. This is a side view of the measurement jig for measuring the resistivity of the fabricated semiconductor photodetector.

[0024] Prior to describing the circumstances of the embodiments according to the present invention, the following points will be explained in advance.

[0025] In this specification, when "InGaAs" is simply written without specifying the elemental composition ratio, it means that the total ratio of Group III elements In (indium) and Ga (gallium) to Group V element As (arsenic) is 1:1, and the ratio of Group III elements In to Ga can represent any compound. ｘ Ga （１－ｘ）When expressed in terms of As, it is preferable that 0 < x < 1. However, "InGaAs" may contain 5% or less Al (molar concentration, the same applies hereafter) relative to the total of In and Ga. It may also contain up to 5% P (phosphorus) and Sb (antimony) relative to As. Furthermore, when simply expressed as "InP", the composition ratio of Group III and Group V elements can be measured by photoluminescence measurement and X-ray diffraction measurement, etc.

[0026] Furthermore, in this specification, a layer that functions electrically as p-type is referred to as a p-type semiconductor layer (sometimes called a "p-type layer"), and a layer that functions electrically as n-type is referred to as an n-type semiconductor ("n-type layer"). On the other hand, in cases where specific impurities such as Si, Zn, and S are not intentionally added, it will be treated as "i-type" or "undoped" in this specification.

[0027] In this specification, the resistivity of an optical filter after protective film formation is measured using a two-terminal method. The measurement method used in this specification will be described in detail below. Figure 14 shows a top view of the measurement method using the two-terminal method, and Figure 15 shows a side view thereof. First, an optical filter 90 and a protective film 91 are formed on an insulating quartz glass substrate (made of synthetic quartz, 400 μm thick, not shown) in the same manner as the method of lamination on a semiconductor laminate described later. Then, the quartz glass substrate is scribed and cut together with the optical filter 90, which has the protective film 91 in a strip shape with a width L. After that, an Au wire 5 (diameter 20 μm) is brought into contact with the sides of the quartz glass substrate at both ends of the width L, and Ag paste 6 is applied to the entire surface including the sides of the quartz glass substrate and the sides of the optical filter 90 and protective film 91 so as to enclose the Au wire 5. The paste is then heat-treated at 70°C for 2 hours to cure, and a resistivity measurement sample with two electrodes spaced L apart is obtained. Here, the cross-sectional area S of the optical filter 90 and protective film 91 in contact with the electrode (Ag paste 6) is calculated from the length of the strip of the optical filter 90 (for example, 1000 μm) and the thickness of the optical filter 90 and protective film 91. Then, as shown in Figure 14, an insulating glass plate 3 and an external connection terminal 7 are placed on the glass epoxy substrate 2, and the Au wire 5 is bonded to the glass plate 3 using an insulating adhesive 4, thereby suspending a strip-shaped resistivity measurement sample in the air using the Au wire 5, as shown in Figure 15. The Au wire 5 is connected to the external connection terminal 7, and a Source Measure Unit (SMU) is connected to the external connection terminal 7 to pass current and measure the V-I curve, and the resistance R of the optical filter 90 is calculated from its slope, and the resistance R (Ω), width L (μm), and cross-sectional area S (μm) are calculated. ２ The resistivity ρ = R × S / L (Ω・μm) is calculated from the value of ). The width L can be, for example, 200 μm. The method for measuring the resistivity of only the optical filter 90 without a protective film is the same.

[0028] In this specification, the light-receiving wavelength of a semiconductor photodetector is determined by spectral sensitivity spectroscopy. In the embodiments described later, a spectral sensitivity spectroscopy device (model number: CARY7000) manufactured by Agilent Technologies was used.

[0029] In this specification, the conditions for the High Accelerated Stress Test (HAST) on the chip are 130°C, 85% RH humidity, and 2 atmospheres for 24 hours. The bias voltage is 0V. Furthermore, the extent to which water ingress is prevented is determined by performing a special HAST test as described below, and H is determined by SIMS (secondary ion mass spectrometry) analysis. ２ The presence or absence of O infiltration was quantitatively confirmed.

[0030] First, the water supplied to the HAST tank is "ultrapure water (H ２ O) is not "heavy water (D ２ Use "O" (deuterium). Next, perform SIMS depth analysis on the optical filter after HAST to quantify (average calculation) the "D (deuterium)" element concentration and compare it between each sample. If the total film thickness of the optical filter is 4 μm or less, perform SIMS depth analysis on the entire filter; if it exceeds 4 μm, perform SIMS depth analysis on the range from the outermost surface of the optical filter to 4 μm and calculate the average value. Similarly, evaluate the "H" element concentration and compare the "D / H" ratio. The "H" element is thought to be due to the "H" element (e.g., hydrogen or water) that was originally present in the optical filter, while the "D" element is thought to be an element that entered from the outside by HAST. Since "D" is a stable isotope, it is assumed that there is no exchange between "D" and "H". Therefore, if the "D / H" value after HAST is large, the HAST test will result in D ２ This indicates that a large amount of oxygen (O) has entered the system.

[0031] In this specification, the presence or absence of an intermediate layer is determined by acquiring STEM (scanning transmission electron microscope) and TEM (transmission electron microscope) images and visually confirming whether there is a layer region that appears darker than the surrounding area using cross-sectional TEM. For example, a Hitachi HD2700 can be used with an acceleration voltage of 200 kV, and the STEM image can be a ZC (Z-contrast image). If an intermediate layer exists, its width can also be measured by acquiring a TEM image. The magnification of the STEM image can be set to, for example, 130,000x, and the TEM image can be imaged at a magnification greater than or equal to the magnification of the STEM image. In the TEM image, the scattering of transmitted electrons increases as the electron density of the sample increases, in other words, as the atomic number increases, and the image becomes darker. Furthermore, the scattering is weaker and the image becomes brighter as the sample is composed of lighter elements. ２ or Si ３ N ４ The intermediate layer, which is observed to be darker than its surroundings, is expected to be in a state closer to Si than its surroundings. For example, SiO ２ SiO with oxygen vacancies that is closer to Si ２ It is thought that it will be observed to be faint. Similarly, SiO ２ SiONs with oxygen vacancies closer to Si are thought to appear fainter.

[0032] The embodiments of each invention will be described below with reference to the drawings. In addition, for the sake of clarity, the aspect ratios of the substrate and each layer in each drawing are exaggerated from the actual ratios. Furthermore, the correspondence between each schematic cross-sectional view and the top view does not always coincide due to dimensional constraints, and the ratios are changed in cases where it becomes difficult to distinguish them.

[0033] (First Embodiment) In the first embodiment, we will first describe the optical semiconductor element as a semiconductor photodetector 1.

[0034] ―Method for Manufacturing a Semiconductor Photodetector― The method for manufacturing a semiconductor photodetector according to the present invention includes at least an electrode formation step, an optical filter formation step, and a protective film formation step. Referring to Figures 1 to 9, the method for manufacturing a semiconductor photodetector 1 according to an embodiment of the present invention, including optional steps, includes a first step (semiconductor laminate formation step), a second step (contact region formation step), a third step (diffusion prevention layer formation step), a fourth step (Zn diffusion step), a fifth step (dielectric layer formation step), a sixth step (electrode formation step), a seventh step (optical filter formation step), an eighth step (protective film formation step), and a ninth step (backside electrode formation step), and a piecemaking step (not shown). In addition, in Figures 1 to 9, Figures 2A, 2B, etc., are shown as follows: Figure 2B is a top view of the semiconductor photodetector 1 under construction, and Figure 2A is a cross-sectional view taken at a cross-section perpendicular to the dotted line in Figure 2B. Hereafter, when simply referred to as Figure 2, etc., it refers to both Figure 2A and Figure 2B. The details of each step will be described below. Note that steps 1 through 9 are processes performed on a substrate where numerous elements, not individualized into separate pieces, are arranged; however, Figures 1 through 9 represent a typical element area on the substrate.

[0035] In the first step, a plurality of compound semiconductor layers, each containing at least a light-receiving layer 20, are stacked on a substrate 10 to form a semiconductor laminate 11. The semiconductor laminate 11 may also include a window layer 30 and a contact layer 40 (Figure 1). In the second step, a predetermined pattern is formed on the contact layer 40 (Figure 2). In the third step, a diffusion prevention layer 50 is formed to create an opening pattern for the Zn diffusion region, which will be described later (Figure 3). In the fourth step, the diffusion prevention layer 50 is used as a mask to diffuse p-type impurities from the surface side of the window layer 30 and the contact layer 40 (Figure 4). The contact layer 40 becomes a p-type contact layer 61, and the interface between the region where the p-type impurities of the semiconductor layer have diffused (p-type region 62) and the p-type impurity non-diffusing region in the light-receiving layer 20 becomes a light-receiving portion 63 (Figure 4A). In the fifth step, a dielectric layer 70 is formed over the entire surface, and a pattern is formed to expose the p-type contact layer 61 (Figure 5A). In the sixth step (electrode formation step), a frame-shaped electrode 81 is formed on the p-type contact layer 61 so as to surround the light-receiving portion 63 fabricated above and to be spaced apart from the outer circumference of the semiconductor laminate 11, and a pad electrode 82 is formed to connect to a part of the frame-shaped electrode 81. The frame-shaped electrode 81 and the pad electrode 82 together are referred to as the upper electrode 80 (Figure 6). In the seventh step (optical filter formation step), an optical filter 90 is formed so as to be in contact with at least a part of the upper electrode 80 formed in the sixth step. The optical filter 90 includes a dielectric multilayer film. The optical filter 90 may cover the entire surface of the semiconductor laminate 11 and the frame-shaped electrode 81, except for the upper surface of the pad electrode 82 (Figure 7). In the eighth step (protective film formation step), SiO is applied to the uppermost layer of the optical filter 90 formed in the seventh step. ２ or Si ３ N ４ A protective film 91 containing is formed. The protective film 91 may be formed on the side surface of the optical filter 90 (Figure 8). The ninth step is to grind the back surface of the substrate 10 and form a back surface electrode 100 on the back surface of the substrate 10 for electrical conductivity (Figure 9). The tenth step is a framing step, which is not shown.

[0036] <First Step> As described above, the first step is to form a semiconductor laminate 11 by stacking a plurality of compound semiconductor layers, each containing at least a light-receiving layer 20, on a substrate 10 (Figure 1). As the substrate 10, a growth substrate such as GaAs, InP, or InAs can be used, and an InP growth substrate is preferred. When a growth substrate is used, an n-type substrate is preferred. For the sake of explanation, an embodiment in which an n-type InP growth substrate 10 is used as the substrate 10 will be described below. The n-type InP growth substrate 10 can be one that is generally available, and its thickness should be sufficient to physically support the semiconductor laminate 11 and optical filter 90, which will be described later.

[0037] In the first step, a light-receiving layer 20, a window layer 30, and a contact layer 40 may be deposited on the n-type InP growth substrate 10 in this order. The light-receiving layer 20 is preferably an InGaAs layer. The light-receiving layer 20 may be undoped or n-type, but the average n-type impurity concentration determined by SIMS analysis is 2.5 × 10⁻⁶. １４ / cm ３ The above 1.0 x 10 １５ / cm ３ It is preferable to dope in the following manner: 3.0 × 10 １４ / cm ３ The above 9.5 x 10 １４ / cm ３It is more preferable to dope the material as follows: At least one n-type impurity is selected from Si, Ge, Sn, Pb, S, Se, and Te, with Si or Ge being preferred. The thickness of the light-receiving layer 20 is preferably 1.0 μm or more and 5.0 μm or less, and more preferably 2.0 μm or more and 4.0 μm or less. The window layer 30 can be an n-type InP layer, and the contact layer 40 can be an undoped InGaAs layer. The thickness of the window layer 30 is preferably 500 nm or more and 2.0 μm or less. The thickness of the contact layer 40 is preferably 50 nm or more and 200 nm or less, and more preferably 70 nm or more and 150 nm or less. A buffer layer may be provided between the n-type InP growth substrate 10 and the light-receiving layer 20 to eliminate lattice mismatch. The light-receiving layer 20, the window layer 30, the contact layer 40, and any other optional layers together are referred to as a semiconductor laminate 11. The total film thickness of the substrate 10 and the semiconductor laminate 11 is preferably 500 μm or less, and more preferably 400 μm or less. In addition to the layers mentioned above, a first buffer layer, a second buffer layer, or a first contact layer may be formed.

[0038] Here, each of the semiconductor layers described above can be formed by epitaxial growth, for example, by known thin-film growth methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or sputtering. For example, trimethylindium (TMIn) can be used as the In source, trimethylgallium (TMGa) as the Ga source, and arsine (AsH) as the As source. ３ By using these raw material gases in a predetermined mixing ratio and growing them in the vapor phase using a carrier gas, each layer can be formed to a desired thickness depending on the growth time. If each layer is to be dopanted to a p-type or n-type, a dopant source gas may be used as desired.

[0039] <Second Step> The second step, as described above, is the step of forming a predetermined pattern on the contact layer 40 (Figure 2). By forming a resist pattern on the surface of the contact layer 40, etching the openings, and peeling off the resist, a predetermined pattern can be formed on the contact layer 40. When the contact layer 40 is an InGaAs layer, although not limited to this, the etching solution may be, for example, H ２ SO ４ : H ２ O ２ : H ２ A ratio of O = 1:1:7 can be used. Figure 2B is a top view of Figure 2, but the contact layer 40 does not necessarily have to be closed as a frame, and although it is rectangular except for the opening in Figure 2B, it may be circular or the like. The width of the contact layer 40 is preferably 5 nm to 20 nm, and more preferably 8 nm to 15 nm (see reference numeral 40 in Figure 2B). If it is narrower than this range, sufficient current will not flow to the light-receiving part described later, and if it is wider than this range, the amount of light reaching the light-receiving part will be small. In addition, the size of the inner circumference of the contact layer 40 can be set appropriately depending on the application. For each application, it is preferable to design it so that sufficient current flows to the light-receiving part described later.

[0040] <Third Step> The third step, as described above, is the step of forming the diffusion prevention layer 50. That is, it is the step of forming the diffusion prevention layer 50 on a part of the surface of the window layer 30 including the contact layer 40 on the upper surface of Figure 2A (Figure 3). The diffusion prevention layer 50 is SiO ２ , SiON etc. may also be used, ３ N ４ It is preferable that the film thickness of the diffusion prevention layer 50 is the same as the film thickness of the contact layer 40. The film thickness of the diffusion prevention layer 50 is preferably 50 nm to 200 nm, and more preferably 70 nm to 150 nm. The diffusion prevention layer 50 can be formed, for example, by plasma CVD (Chemical Vapor Deposition). After that, a resist pattern can be formed on the diffusion prevention layer 50, the openings can be etched, and the resist can be peeled off to form a diffusion prevention layer 50 with a predetermined pattern. Si ３ N ４The etching solution is BHF (ultra-high purity buffered hydrofluoric acid). The diffusion prevention layer 50 is preferably formed on the outside of the contact layer 40. The formed diffusion prevention layer 50 can be used as a mask during the diffusion of p-type impurities in the fourth step.

[0041] <Fourth Step> As described above, the fourth step is a step in which p-type impurities are diffused from the contact layer 40 and window layer 30 to the light-receiving layer 20, using the mask opening not covered by the diffusion prevention layer 50 as the entry point for diffusion. For example, Zn can be used as the p-type impurity. Since Zn is not easily diffused into the diffusion prevention layer 50 formed in the third step described above, it can be diffused using the MOCVD method from the mask opening not covered by the diffusion prevention layer 50 (window layer 30 and contact layer 40 in Figure 3B). In terms of the diffusion distance in the depth direction, it is preferable to adjust the conditions so that Zn diffuses to a depth of 0.1 μm to 0.5 μm from the interface between the window layer 30 and the light-receiving layer 20 toward the light-receiving layer 20. By diffusing Zn, the contact layer 40 becomes a p-type contact layer 61, and a part of the window layer 30 and the light-receiving layer 20 is p-type. The interface between the region where p-type impurities have diffused in the semiconductor layer (p-type region 62) and the non-diffusing region of p-type impurities within the light-receiving layer 20 is defined as the light-receiving portion 63 (Figure 4A). This allows for the formation of a semiconductor laminate 11 having the light-receiving portion 63 on the n-type InP growth substrate 10. The p-type contact layer 61, the p-type region 62, and the light-receiving portion 63 together constitute the Zn diffusion region 60. Here, the size of the inner circumference of the Zn diffusion region, excluding the pad electrode portion 82 described later, can be set appropriately according to the application. Lateral diffusion of Zn after entering through the opening is possible, but for the sake of explanation, when viewed from above (Figure 4B), the p-type region 62 (light-receiving portion 63) is described as being approximately the same region as the mask opening of the diffusion prevention layer 50 used as a mask during p-type impurity diffusion.

[0042] <Step 5> As described above, Step 5 is the step of forming the dielectric layer 70. That is, the dielectric layer 70 is deposited on the surface including the diffusion prevention layer 50, the p-type region 62, and the p-type contact layer 61 formed in Step 4 (Figure 5). The dielectric layer 70 is made of the same Si as the diffusion prevention layer 50. ３ N ４It is preferable that SiO ２ Alternatively, it may be SiON or the like. The thickness of the dielectric layer 70 may be the same as the thickness of the diffusion prevention layer 50, but it is preferable that it be thicker than the diffusion prevention layer 50. The dielectric layer 70 can be formed, for example, by plasma CVD (Chemical Vapor Deposition). After that, a resist pattern can be formed on the dielectric layer 70, the openings can be etched, and the resist can be peeled off to form a dielectric layer 70 with a predetermined pattern. Si ３ N ４ The etching solution is BHF. When a dielectric layer 70 of a predetermined pattern is formed and the p-type contact layer 61 is exposed, the width of the opening of the p-type contact layer 61 is preferably 3 μm or more and 10 μm or less, and more preferably 5 μm or more and 8 μm or less (see reference numeral 61 in Figure 5). Furthermore, it is preferable that the p-type contact layer 61 is located in the center of the width of the contact layer 40 formed in the second step. The protective layer 50 is left intact, and the outer periphery is Si ３ N ４ It is preferable that the diffusion prevention layer extends to the edge of the semiconductor layer (Figure 5). In this embodiment, the dielectric layer 70 is formed while the diffusion prevention layer 50 remains, but the diffusion prevention layer 50 may be removed after the fourth step before forming the dielectric layer 70.

[0043] <Step 6> As described above, Step 6 is an electrode formation step in which the upper electrode 80 (frame electrode 81 and pad electrode 82) is formed (Figure 6). In the example shown in Figure 6, since there is a p-type region 63 on the main surface side that receives light, the frame electrode 81 is formed on the p-type contact layer 61, and the pad electrode 82 is formed on a part of the dielectric layer 70 so as to be electrically connected to the frame electrode 81 with a size that allows bonding with the outside. Here, when the light-receiving element 1 is viewed from above from the optical filter side, the frame electrode 81 may cast a shadow and reduce the amount of light reaching the light-receiving part 63, so it is preferable to place it near the outer circumference of the light-receiving part 63. Also, in order to prevent leakage current from traveling along the end face of the element, it is preferable to form the frame electrode 81 so as to be spaced away from the outer circumference of the semiconductor laminate 11. The distance of the frame electrode 81 from the outer circumference of the semiconductor laminate 11 is preferably 25 μm or more and 100 μm or less, and more preferably 30 μm or more and 70 μm or less. Furthermore, similar to the frame-shaped electrode 81, it is preferable that the pad electrode 82 be positioned inward so as to be spaced apart from the outer circumference of the semiconductor laminate 11. The shape of the frame-shaped electrode 81 depends on the shape of the contact layer 40 formed earlier, and the outer and inner shapes can be any shape, such as rectangular or circular. The pad electrode 82 is formed so as to be connected to a part of the frame-shaped electrode 81 (Figure 6B). The frame-shaped electrode 81 and the pad electrode 82 may be formed by vapor deposition or sputtering, but it is preferable to form them using EB metal vapor deposition. A predetermined resist pattern (electrode pattern) is formed on the dielectric layer 70 and the p-type contact layer 61, and the dielectric layer 70 at the opening is etched. A metal layer for conductivity is formed by vapor deposition, and the resist is swollen to remove metal other than the electrode pattern, thereby forming the frame-shaped electrode 81 and the pad electrode 82. The frame-shaped electrode 81 and the pad electrode 82 can be formed from, for example, Ti, Pt, Au, etc. It is preferable that the frame-shaped electrode 81 and the pad electrode 82 are of the same height. The film thickness (or total film thickness) of the frame electrode 81 and the pad electrode 82 is not particularly limited. In the top view of Figure 6, the width of the frame electrode 81 and the diameter of the pad electrode 82 can be adjusted as appropriate depending on the application. The first to sixth steps described above are an example of a manufacturing method for obtaining a photodetector having electrodes on its top surface, and can be modified as appropriate within the range of a manufacturing method that can obtain a photodetector having electrodes on its top surface.

[0044] <Step 7> As described above, Step 7 is an optical filter formation step in which an optical filter 90 is formed that is in contact with at least a portion of the upper electrode 80 formed in Step 6 (Figure 7). In this embodiment, the optical filter 90 is formed on the entire surface of the frame electrode 81 and the dielectric layer 70 (on the semiconductor laminate 11), excluding the external connection surface of the pad electrode 82. As shown in Figure 7A, the optical filter 90 is in contact with the upper electrode 80 (frame electrode 81 and pad electrode 82). The optical filter 90 includes a dielectric multilayer film and is formed using the sputtering method. Before forming the optical filter 90, a resist pattern is placed in advance, and a lift-off method is used to remove the resist along with a portion of the optical filter on the resist after film formation to form a predetermined opening in the optical filter 90. Alternatively, after forming the optical filter 90, a resist pattern is formed on the optical filter 90, the pad electrode 82 portion is etched, and the resist is peeled off to form an optical filter 90 having a predetermined opening. These are examples of steps in the optical filter formation step to form an opening that exposes a portion of the upper electrode 80. Since a portion of the surface of the pad electrode 82 is not covered by the optical filter 90 and is required to be exposed to allow for electrical wiring to the outside, the surface of the pad electrode 82 exposed by the opening of the optical filter 90 is called the external connection surface of the pad electrode 82. The reason why the above step is included in the optical filter formation process is to form an external connection surface of the pad electrode 82 that allows for electrical wiring to the outside of the semiconductor photodetector 1.

[0045] The optical filter 90 has a dielectric multilayer film consisting of a Si layer and SiO ２ Preferably, it includes a laminate of layers, and the uppermost layer of the optical filter 90 is SiO ２ It is preferable that it be a layer. SiO ２ It is more preferable that the oxygen flow rate during layer formation be 100 sccm or more and 500 sccm or less, and even more preferable that the oxygen flow rate be 100 sccm or more and 300 sccm or less. Si layer and SiO ２ Dielectric multilayer films may be formed from laminates of high refractive index, medium refractive index, and low refractive index using layers of different materials. Si layer and SiO２ When forming the optical filter 90 which includes a laminated structure of layers, the resistivity of the optical filter 90 is 3.0 × 10⁻⁶ １２ It is preferable to form it to be Ωμm or larger, 3.8 × 10 １２ It is more preferable that the thickness be Ωμm or greater. The film thickness of the optical filter 90 is preferably 2500 nm to 3500 nm, and more preferably 2800 nm to 3300 nm.

[0046] The deposition rate depends on the power input to the sputtering target and the gas flow rate (Ar, O) used in the sputtering method. ２ By changing (such as H), it is possible to adjust the resistivity range within a desired range. If it is possible to adjust the resistivity to obtain the desired resistivity, a deposition method such as ion beam-assisted deposition may be used. After that, a resist pattern is formed on the optical filter 90, the pad electrode 82 portion is etched, and the resist is peeled off to form an optical filter 90 with a predetermined pattern. The aperture diameter of the optical filter 90 is arbitrary as it depends on the method of connection to the outside of the pad electrode 82, but it is preferably 120 μm or less (Figure 7B).

[0047] <Step 8> As mentioned above, in Step 8, SiO is applied to the top layer of the optical filter 90 formed in Step 7. ２ or Si ３ N ４This is a protective film forming step of forming a protective film 91 (Fig. 8). The protective film 91 is formed using the plasma CVD method. Here, when forming the protective film 91, it is preferable to form it using a plasma CVD apparatus different from the apparatus for forming the optical filter 90. For example, after forming the optical filter 90 by the sputtering method, it may be taken out from the film forming apparatus once and then put into the plasma CVD film forming apparatus to form the protective film 91 using the plasma CVD method. It is preferable to also cover the side surface of the opening of the optical filter 90 formed in the seventh step with the protective film 91 (Fig. 8A). In the protective film forming step of the eighth step, between the uppermost layer of the optical filter 90 and the protective film 91, conditions such as the plasma generation conditions and the raw material gas flow rate are adjusted so that an intermediate layer that is observed darker than the uppermost layer of the optical filter 90 and the protective film 91 in the cross-sectional TEM image is formed. The intermediate layer formed here is presumed to contain SiO ２ or SiON with oxygen defects. The film thickness of the intermediate layer is preferably 5 nm or more and 30 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0048] The film thickness of the protective film 91 is preferably an integral multiple (within an error of 5%) of the value obtained by dividing the light receiving wavelength of the semiconductor light receiving element 1 by twice the refractive index of the protective film 91 in order to expect the effect of improving the output. For example, when the light receiving wavelength of the semiconductor light receiving element 1 is λ １ and the refractive index of the protective film 91 is n １ , the film thickness of the protective film 91 can be expressed as k × (λ １ / 2n １ ) (k is an integer of 1 or more). The material of the protective film 91 is preferably SiO ２ or Si ３ N ４ , but other materials may also be used. The film thickness of the protective film 91 is not particularly limited as long as the received light reaches the light receiving portion 63.

[0049] <Step 9> As described above, Step 9 is the step of forming a back electrode on the back surface of the substrate 10 for electrical conduction (Figure 9). The back surface of the substrate 10 may be ground before forming the back electrode, and the thickness of the substrate 10 after grinding is preferably 80 μm or more and 300 μm or less, and more preferably 200 μm or less. Also, the overall thickness of the element including the substrate 10 and the semiconductor laminate 11 is preferably 100 μm or more and 350 μm or less, and more preferably 150 μm or more and 280 μm or less. After grinding the substrate 10, the back surface of the substrate 10 is cleaned and the back electrode 100 can be formed by metal deposition or sputtering. For example, the back electrode 100 can be an alloy containing Au. The film thickness (total film thickness) of the back electrode 100 is not limited, but is preferably, for example, 500 nm or more and 1000 nm or less.

[0050] <Step 10> Step 10, as mentioned above, is the individualization step, although it is not shown in the diagram. The semiconductor photodetector 1 fabricated in Figure 9 is individualized into chips using a laser dicer. Individualization may be performed by cutting from the optical filter to the substrate as shown in Figure 9, or by cutting partway and using scribing or breaking in combination. In addition, if a mesa formation step is added between steps 5 and 9, and the semiconductor layer including the photodetector layer is partially removed along the planned cutting line in the individualization step by dry etching or the like, then in the individualization step, only the remaining part including the substrate needs to be cut.

[0051] In the first embodiment described above, an intermediate layer is formed between the uppermost layer of the optical filter 90 and the protective film 91 by performing a protective film formation step after the optical filter formation step. This makes it possible to manufacture a semiconductor photodetector 1 in which the upper electrode 80 and the optical filter 90 are in contact, yet the dark current does not increase even under high temperature and high humidity conditions. The embodiments of the manufacturing method according to the present invention are not limited to the above embodiment, and for example, the following modifications may be applied, or these may be combined.

[0052] (Modification 1) As modification 1 of the first embodiment described above, a different type of light-receiving part is given. In the first embodiment described above, the light-receiving part 63 is a PIN junction or PN junction by Zn diffusion, but the light-receiving part 63 is a PIN junction or PN junction by doping during epitaxial growth instead of by Zn diffusion. The amount of doping may also be adjusted to become an APD (avalanche photodiode) type. In addition, in the first embodiment, an InGaAs-based light-receiving element using an n-type InP growth substrate 10 was described as an example, but in the present invention, the dark current that can be suppressed by the presence of the intermediate layer is considered to be the current in the path from the top electrode 80 through the optical filter 90 along the side of the element to the back electrode 100. In other words, since it is not due to the current flowing inside the element, the effects of the invention may be achieved regardless of the type of substrate 10 and semiconductor laminate 11. Depending on the type of substrate 10 and the light-receiving center wavelength, each layer constituting the semiconductor laminate 11 may be appropriately selected from a III-V semiconductor layer consisting of one or more elements selected from the group III elements Al, Ga, and In, and one or more elements selected from the group V elements N, As, P, and Sb.

[0053] (Modification 2) As a second modification of the first embodiment described above, a diffusion prevention layer 50 and dielectric layer 70 with different ranges are given. In the first embodiment described above, the diffusion prevention layer 50 and dielectric layer 70 are formed up to the edge of the semiconductor photodetector 1, but these layers do not have to be formed up to the edge of the semiconductor photodetector 1. The diffusion prevention layer 50 and dielectric layer 70 are not formed at the edge of the semiconductor photodetector 1, and instead an optical filter 90 or protective film 91 may be formed.

[0054] (Modification Example 3) As described in Japanese Patent Application No. 2024-073142 filed by the inventors of the present invention, after forming the dielectric layer 70 described above, a bonding layer may be formed on the p-type electrode and the dielectric layer, and a support substrate may be bonded through the bonding layer. Examples of the support substrate include a Si substrate, a Ge substrate, a compound semiconductor substrate, a metal substrate (such as Cu-Mo, Mo, etc.), or a ceramic substrate (such as an AlN sintered body, etc.). In this case, since the InP growth substrate is etched and removed, the frame electrode, the pad electrode, and the optical filter and the protective film are formed on the side where the InP growth substrate has been removed.

[0055] - Semiconductor Light-Receiving Element - Next, the semiconductor light-receiving element 1 described in the first embodiment obtained through at least the electrode formation process, the optical filter formation process, and the protective film formation process described above will be described. As shown in FIG. 9, this semiconductor light-receiving element 1 includes an upper surface electrode 80 (frame electrode 81 and pad electrode 82) and an optical filter 90 that is at least partially in contact with the upper surface electrode 80. The optical filter 90 has an opening that exposes a part of the upper surface electrode 80 in order to enable electrical wiring with the outside. It is preferable that the side surface of the opening is covered with a protective film 91. The optical filter 90 includes a dielectric multilayer film. As the dielectric multilayer film included in the optical filter 90, it preferably includes a laminate of Si layers and SiO ２ layers, and the uppermost layer of the optical filter 90 is preferably a SiO ２ layer. A laminate of high refractive index, medium refractive index, and low refractive index layers may be included using layers of a material different from the Si layer and the SiO ２ layer. When forming the optical filter 90 including the laminate of Si layers and SiO ２ layers, the initial resistivity of the optical filter 90 after forming the protective film 91 is preferably 3.0×10 １２ Ωμm or more, and more preferably 3.8×10 １２ Ωμm or more. And the resistivity after the HAST test for 24 hours at 130°C, humidity 85%RH, and 2 atmospheres is preferably 9.0×10 １１ Ωμm or more. Also, the ratio (change rate %) of the difference between the resistivity after the HAST test and the initial resistivity of the optical filter 90 to the initial resistivity is preferably 90% or less, and more preferably 50% or less.

[0056] The semiconductor photodetector 1 has SiO on top of the top layer of the optical filter 90. ２ or Si ３ N ４ A protective film 91 containing is provided. Preferably, the thickness of the protective film 91 is an integer multiple (within 5% error) of the value obtained by dividing the light-receiving wavelength of the semiconductor photodetector 1 by twice the refractive index of the protective film 91. For example, if the light-receiving wavelength of the semiconductor photodetector 1 is λ １ The refractive index of the protective film 91 is n １ In this case, the thickness of the protective film 91 is k × (λ １ / 2n １ It can be expressed as (where k is an integer greater than or equal to 1).

[0057] The semiconductor photodetector 1 has an intermediate layer between the top layer of the optical filter 90 and the protective film 91, which is observed to be darker than the top layer of the optical filter 90 and the protective film 91 in the cross-sectional TEM image. The intermediate layer formed here is SiO with oxygen vacancies. ２ Or it is presumed to contain SiO. HAST testing shows a tendency for the resistivity of the optical filter 90 to decrease and the dark current (reverse current) to increase, but when a protective film 91 is formed on the optical filter 90 while the intermediate layer of the present invention is observed, the decrease in the resistivity of the optical filter 90 after the formation of the protective film 91 can be suppressed, as can the increase in the dark current. And the SiO of the optical filter 90 ２ When the concentrations of hydrogen (H) and deuterium (D) in the layer and Si layer are measured using SIMS analysis, if the protective film is formed in a state where the intermediate layer of the present invention is observed, the increase in deuterium (D) entering from the outside is suppressed by HAST testing. Therefore, it is considered that the intermediate layer has a significant effect in preventing water intrusion.

[0058] When the semiconductor photodetector 1 is a photodetector having a photodetector layer made of an InGaAs layer as exemplified in the first embodiment, the dark current when a reverse bias voltage of 5V is applied is 0.185nA or less, preferably 0.184nA or less, and more preferably 0.183nA or less. Furthermore, the rate of change of the dark current after 24 hours of high-speed accelerated life testing is 3.5 times or less, and preferably 3.4 times or less.

[0059] The semiconductor photodetector 1 preferably has a photodetector peak wavelength (the wavelength at which the intensity in the photosensitivity spectrum is maximum) of 800 nm to 2500 nm, more preferably 850 nm to 2000 nm, and even more preferably 900 nm to 1700 nm. The photodetector layer 20 is preferably an InGaAs layer. The full width at half maximum of the peak in the photosensitivity spectrum is preferably, for example, 50 nm to 200 nm.

[0060] As detailed in the examples, it was experimentally confirmed that the semiconductor photodetector 1 provided with the intermediate layer described above does not experience an increase in dark current under high temperature and high humidity conditions, even when the electrodes and optical filter are in contact.

[0061] (Second Embodiment) In the second embodiment, in the seventh step of the method for manufacturing a semiconductor photodetector, the optical filter 90 is made of a Si layer and SiO ２ It includes a dielectric layer film in layers. Also, the top layer of the optical filter 90 is SiO ２ It is preferable that it be a layer. Furthermore, after forming the protective film 91 in the eighth step, the SiO of the optical filter 90 after 24 hours of high-speed accelerated life testing ２ The average D concentration within the layer is 1.5 × 10⁻⁶ ２１ atom / cm ３ The following applies. Except as described above, the method for manufacturing the semiconductor photodetector is the same as in the first embodiment. The semiconductor photodetector 1 manufactured according to the second embodiment will be described. The optical filter 90 consists of a Si layer and SiO ２ It includes a stack of layers. The top layer is SiO ２ It is preferable that it be a layer. Furthermore, the SiO of the optical filter 90 after 24 hours of high-speed accelerated life testing. ２ The average D concentration within the layer is 1.5 × 10⁻⁶ ２１ atom / cm ３ The semiconductor photodetector is identical to that in the first embodiment, except as follows. The second embodiment also provides the same effects as the first embodiment. SiO of the optical filter 90 after 24 hours of high-speed accelerated life testing. ２ The average D concentration within the layer is 9.9 × 10⁻⁶. ２０ atom / cm ３It is more preferable that the following conditions apply: 4.0 × 10 ２０ atom / cm ３ It is even more preferable that the following conditions are met: The lower limit is not particularly limited, but the minimum resolution in SIMS is 2.0 × 10⁻¹⁶. １８ atom / cm ３ Therefore, for example, 2.0 × 10 １８ atom / cm ３ That concludes the report. Furthermore, the average D concentration in the Si layer of the optical filter 90 after 24 hours of high-speed accelerated life testing was 1.0 × 10⁻⁶. ２０ atom / cm ３ Preferably, it is 5.0 × 10 １９ atom / cm ３ The following is more preferable:

[0062] (Third Embodiment) The present disclosure is also applicable to semiconductor light-emitting elements, which are optical semiconductor elements, and it is also possible to make the semiconductor light-emitting element 1 equipped with an optical filter 90 that transmits or reflects a specific wavelength range. A semiconductor light-emitting element according to the third embodiment of the present invention will be described. For example, by replacing the light-receiving layer 20 in the first embodiment with an active layer, the optical semiconductor element of the present invention can be used as a semiconductor light-emitting element, and a semiconductor light-emitting element with a small dark current (also called reverse current) even under high temperature and high humidity conditions can be realized. That is, the semiconductor light-emitting element according to the second embodiment is an optical semiconductor light-emitting element comprising an electrode and an optical filter in contact with at least a part of the electrode, wherein the optical filter includes a dielectric multilayer film, and the uppermost layer of the optical filter is SiO ２ or Si ３ N ４ The semiconductor light-emitting element has a protective film containing a certain material, and between the uppermost layer and the protective film, there is an intermediate layer which appears darker than the uppermost layer and the protective film in a cross-sectional TEM image. The semiconductor light-emitting element may have an n-type semiconductor layer, an active layer, and a p-type semiconductor layer between the substrate and the optical filter in this order.

[0063] In the method for manufacturing a semiconductor light-emitting element, in the first step described above, a plurality of compound semiconductor layers, each containing at least an active layer, are stacked on a substrate 10 to form a semiconductor laminate 11. If the semiconductor laminate 11 in the first step has a p-type semiconductor layer and an n-type semiconductor layer, the p-type impurity diffusion in the fourth step described above may be omitted.

[0064] The present invention will be described in more detail below using examples, but the present invention is not limited in any way to the following examples. Reference numerals refer to Figures 1 to 9.

[0065] 3-inch n-type InP growth substrate 10 (thickness: 350 μm, S-doped, carrier density: 2 × 10) ８ / cm ３ On top of that, using the MOCVD method, an undoped InP buffer layer (film thickness 0.5 μm) and a tracely Si-doped InP layer were created. ０．５３ Ga ０．４７ As light-receiving layer 20 (film thickness: 3.0 μm, average Si concentration 9 × 10⁻¹⁶ by SIMS analysis) １４ / cm ３ (Carrier density too low to measure), n-type InP window layer 30 (film thickness: 1.0 μm, Si doped, carrier density: 8 × 10) １５ / cm ３ ), and undoped In ０．５３ Ga ０．４７ As contact layers 40 (film thickness: 0.1 μm) were sequentially deposited to form a semiconductor laminate 11. This is shown in Figure 1.

[0066] A pattern as shown in Figure 2 was formed on the undoped InGaAs contact layer 40. This pattern formation involved forming a resist pattern and etching the openings (etched areas). H was used as the etching solution for InGaAs. ２ SO ４ : H ２ O ２ : H ２A solution with an O content of 1:1:7 was used. Next, it was allowed to stand for 30 seconds, washed with ultrapure water, and dried. After that, the resist was removed by washing. As shown in Figure 2B, the InGaAs contact layer 40 was not a complete frame shape when viewed from above, but rather an open frame shape for the pad electrode 82 described later. The width of the InGaAs contact layer 40 was 11 μm. When the InGaAs contact 40 was considered as a closed rectangle, the inner circumference size of the rectangle was 396 μm × 396 μm, and the outer circumference size was 418 μm × 418 μm.

[0067] Next, by plasma CVD, Si is placed on the n-type InP window layer 30, including the InGaAs contact layer 40 of the undoped layer on which the above pattern was formed. ３ N ４ A diffusion-preventing layer 50 (thickness: 100 nm) consisting of the above was deposited. ３ N ４ A resist pattern was formed on the diffusion prevention layer 50, and the openings were etched. Si ３ N ４ BHF solution was used as the etching solution for the diffusion prevention layer 50, and it was allowed to stand for 3 minutes and 30 seconds, then washed with ultrapure water and dried. After that, the resist was removed by washing. In this way, the diffusion prevention layer 50 shown in Figure 3 was formed.

[0068] By supplying a Zn source gas while heating using the MOCVD method, Zn was diffused in the depth direction of the n-type InP window layer 30 and the undoped InGaAs contact layer 40. Zn was diffused from the interface between the undoped InGaAs contact layer 40 and the n-type InP window layer 30 and the undoped InGaAs light-receiving layer 20 to a region up to 300 nm towards the undoped InGaAs light-receiving layer 20. DEZn (diethylzinc) was used as the Zn source. Since a p-type region can be formed by Zn diffusion, the InGaAs contact layer 40 after Zn diffusion becomes a p-type InGaAs contact layer 61, the portion of the n-type InP window layer 30 and part of the undoped InGaAs light-receiving layer 20 where Zn has diffused and become p-type is a p-type region 62, and the interface with the p-type region 62 within the undoped InGaAs light-receiving layer 20 is the light-receiving portion 63. The average Zn concentration in the thickness direction in the p-type region 62 of the n-type InP window layer 30 is 5.0 × 10⁻¹⁴. １８ / cm ３ Furthermore, the size of the Zn diffusion region 60, excluding the area near the pad electrode 82, was 422 μm × 422 μm.

[0069] By plasma CVD, Si ３ N ４ A dielectric layer 70 (thickness: 177 nm) made of the above was deposited. ３ N ４ A resist pattern was formed on the dielectric layer 70, and the openings were etched. ３ N ４ A BHF solution was used as the etching solution for the dielectric layer 70, and after standing for 6 minutes, it was washed with ultrapure water and dried. The resist was then removed by washing. In this way, the dielectric layer 70 shown in Figure 5 was formed. The width of the p-type contact layer 61 was 7 nm. The p-type contact layer 61 was located in the center of the undoped contact layer 40 formed in Figure 2. In Figure 5, except for the portion of the p-type contact layer 61 exposed on the surface, the material is Si ３ N ４ It is covered with a dielectric layer 70 (Figure 5B).

[0070] A frame-shaped electrode 81 and a pad electrode 82, as shown in Figure 6, were formed on the surface of Figure 5. For electrode pattern formation, a resist pattern was first formed, and the electrode formation area was etched. Ti (film thickness: 30 nm) / Pt (film thickness: 50 nm) / Au (film thickness: 1000 nm) were deposited by EB metal deposition. Next, excess metal and resist were removed by lift-off, forming the electrode pattern shown in Figure 6. The width of the frame-shaped electrode 81 was 20 μm, and the distance from the outer circumference of the semiconductor laminate 11 was 40 μm. The diameter of the pad electrode 82 was 105 μm. The inner circumference of the frame-shaped electrode 81, excluding the pad electrode 82, was 390 μm × 390 μm. Similarly, the outer circumference of the frame-shaped electrode 81, excluding the pad electrode 82, was 430 μm × 430 μm. The frame-shaped electrode 81 and the pad electrode 82 were combined to form the top electrode 80.

[0071] Except for the opening for the pad electrode 82 to connect to the outside, Si ３ N ４ An optical filter 90 was formed to cover the entire surface of the dielectric layer 70 and the frame-shaped electrode 81. For the optical filter 90, first a resist pattern was formed on the region that would become the external connection surface on the pad electrode 82, and the Si layer (amorphous silicon layer) and SiO formed the optical filter 90. ２ A dielectric multilayer film consisting of layers was formed by sputtering. In the sputtering apparatus, Si was used as the target, the TS distance was set to 110 mm, Ar gas was flowed at a flow rate of 300 sccm, the pressure was set to 0.6 Pa, and the discharge power was set to 9 kW. ２ During layer formation, oxygen was flowed at 200 sccm. The specific structure and film formation conditions of the examples and comparative examples of the optical filter 90 will be described later. Next, the excess dielectric multilayer film and resist on the external connection surface of the pad electrode 82 were removed by lift-off, and an optical filter 90 having an opening as shown in Figure 7 was formed. The opening diameter was 85 μm. Except for the opening of the pad electrode 82, the optical filter 90 was in contact with the upper electrode 80 (frame electrode 81 and pad electrode 82).

[0072] As shown in Figure 8, SiO is placed on the top layer of the optical filter 90. ２ or Si ３ N４ A protective film 91 containing the material was formed. First, a protective film 91 was formed on the entire surface of the optical filter 90, including the opening shown in Figure 8, using the plasma CVD method. At this time, the sides of the opening of the optical filter 90 were also covered with the protective film 91. The specific structure and film formation conditions of the examples and comparative examples of the protective film 91 will be described later. After that, a resist pattern was formed on the formed protective film 91, and the protective film 91 was etched to expose the bottom of the opening and the external connection surface of the pad electrode 82. BHF solution was used as the etching solution for the protective film 91. After that, it was washed with ultrapure water and dried. Finally, the resist was removed by washing. In this way, a protective film 91 as shown in Figure 8 was formed.

[0073] The deposition conditions were adjusted so that an intermediate layer was formed between the uppermost layer of the optical filter 90 and the protective film 91, which appeared darker than the optical filter and protective film 91 in a cross-sectional TEM. The specific conditions for the examples and comparative examples will be described later.

[0074] The back surface of the growth substrate 10 was ground to achieve an overall thickness of 150 μm. Furthermore, as shown in Figure 9, a back surface electrode 100 containing Au was formed on the back surface of the growth substrate 10.

[0075] Finally, the fabricated semiconductor photodetector 1 was separated into individual chips using a laser dicer.

[0076] Table 1 shows the layer structure of the optical filter 90 in Examples 1-4 and Comparative Examples 1-3. The layer structure of the optical filter 90 is the same in Examples 1-4 and Comparative Examples 1-3. Table 2 shows the layer structure of the protective film 91 in Examples 1-4 and Comparative Examples 1-3, respectively. In Table 2, p-CVD represents plasma CVD. In Examples 1-4, after forming the 23rd layer of the optical filter 90, the element was removed from the deposition apparatus, the excess dielectric layer and resist were removed by lift-off to expose a part of the pad electrode 82, and then the element was placed in a p-CVD deposition apparatus to form the protective film 91 by plasma CVD. The SiO2 film thickness of the protective film 91 in Examples 1, Comparative Example 2, and Comparative Example 3: 390 nm corresponds to the light-receiving wavelength λ １ = 1130 nm, the refractive index of the protective film 91 is n １ = 1.459, k × (λ) when k = 1１ / 2n １ It was set based on the value of ).

[0077]

[0078] ＊ Comparative Example 2 involves depositing a 390 nm thick SiO2 film after the 23rd layer of the optical filter 90, without removing the element from the deposition apparatus (without exposing it to the atmosphere). ２ This has been added. For convenience, it is referred to as a protective film 91, but in reality it is an extension of the optical filter 90. ＊＊ In Comparative Example 3, after forming the 23rd layer of the optical filter 90, the element was temporarily removed from the deposition apparatus (opened to the atmosphere), the excess dielectric layer and resist were removed by lift-off to expose the pad electrode 82, and then the element was put back into the deposition apparatus to form the protective film 91 by sputtering.

[0079] Figures 10A, 11A, 12A, and 13A each show SEM images including the boundary between the 22nd and 23rd layers of the optical filter 90, and the boundary between the 23rd layer of the optical filter 90 and the protective film 91, for each of Example 1, Example 3, Comparative Example 2, and Comparative Example 3. Figures 10B, 11B, 12B, and 13B each show enlarged TEM images of section A (the boundary between the 23rd layer of the optical filter 90 and the protective film 91) for each of Figures 10A (Example 1), 11A (Example 3), 12A (Comparative Example 2), and 13A (Comparative Example 3). The thick arrows in Figures 10B, 11B, 12B, and 13B indicate the boundary between the 23rd layer of the optical filter 90 and the protective film 91.

[0080] ​Table 3 shows the presence or absence of an intermediate layer between the 23rd layer of the optical filter 90 and the protective film 91, and, if an intermediate layer exists, its approximate width, for each of Examples 1 to 4 and Comparative Examples 1 to 3. Here, TEM images were obtained for Examples 1 and 3 and Comparative Examples 2 and 3, so the presence or absence of an intermediate layer and its width were directly confirmed. However, for Examples 2 and 4, TEM images were not obtained, so the presence or absence of an intermediate layer was not directly confirmed. Therefore, since Example 2 was manufactured under the same conditions as Example 1, and Example 4 was manufactured under the same conditions as Example 2, it is assumed that the results regarding the presence or absence of an intermediate layer are similar for each. In Comparative Example 1, since the protective film 91 was not formed in the first place, it is natural to assume that no intermediate layer was formed.

[0081]

[0082] From the conditions for the protective film 91 in Table 2 and the results in Table 3, it can be seen that when the protective film 91 is formed by plasma CVD after the optical filter 90 is formed, an intermediate layer is formed. Also, the material of the protective film 91 is SiO ２ Is it Si? ３ N ４ Regardless of whether it is Si, an intermediate layer is formed, ３ N ４ A comparison between Example 1 and Example 3 shows that the width of the intermediate layer is thicker when using [the specified material]. In Comparative Example 3, SiO was used as the material for the protective film 91. ２ Although the system is used and the system is vented to the atmosphere before forming the protective film 91, an intermediate layer is not formed. From this, it can be said that in order to form an intermediate layer, it is important to use plasma CVD as the film deposition method rather than sputtering as the film deposition method for the protective film 91, among the material, deposition method, and film thickness.

[0083] Tables 4 and 5 show the degree of water penetration into the optical filter 90 when the protective film 91 was formed in Examples 1-4 and Comparative Examples 1-3, using SIMS analysis. SIMS analysis was performed in the depth direction from the protective film surface at the center of the chip when viewed from above. Table 4 shows all SiO in the optical filter 90 ２Table 5 shows the average hydrogen (H) and deuterium (D) concentrations for all Si layers of the optical filter 90. Here, the initial average H (or D) concentration refers to the average H (or D) concentration immediately after fabrication of the photodetector.

[0084] ( * The minimum resolution of element D concentration in this SIMS analysis is 2.0 × 10⁻⁶. １８ atom / cm ３ That is the case.

[0085] ( * The minimum resolution of element D concentration in this SIMS analysis is 2.0 × 10⁻⁶. １８ atom / cm ３ That is the case.

[0086] Table 4 SiO ２ From the layers and the Si layer in Table 5, the SiO of the optical filter 90 after 24 hours of the high-speed accelerated lifetime test (HAST) in the example is ２ The average D concentration within the layer is 1.5 × 10⁻⁶ ２１ atom / cm ３ The following is true, and the average D concentration in the Si layer is 1.0 × 10⁻⁶. ２０ atom / cm ３The results were as follows: The average D concentration increased from the initial average D concentration in Examples 1 to 4 compared with Comparative Examples 1 to 3. Also, the D / H ratio after 24 hours of HAST was significantly smaller in Examples 1 to 4 compared with Comparative Examples 1 to 3. Since the element "D" entered from the outside through HAST, it is thought that this resulted in the formation of an intermediate layer, which prevented water from diffusing into the optical filter 90. Furthermore, Examples 1 and 2 in Table 4 had higher average D concentrations and higher D / H ratios after 24 hours of HAST than Examples 3 and 4. Comparing Examples 1 and 2 in Tables 4 and 5, it can be seen that Example 1 had a smaller average D concentration and D / H ratio after 24 hours of HAST. This indicates that even with the same protective film 91, a thicker film thickness reduces water diffusion into the optical filter 90. The same can be said for the comparison between Examples 3 and 4. Also, the material of the protective film 91 in Examples 1 and 2 is SiO ２ In contrast, the material of the protective film 91 in Examples 3 and 4 is Si ３ N ４ This is Si ３ N ４ is SiO ２ Compared to that, Si has a lower rate of water penetration or reactivity with water. ３ N ４ When this is used, the protective film 91 itself functions as a layer that prevents water from entering, and it is thought that this increases the effect of preventing the aforementioned water from diffusing. As a result, the SiO of the optical filter 90 after 24 hours of the High-Speed ​​Accelerated Life Test (HAST) ２ The average D concentration within the layer is 1.5 × 10⁻⁶ ２１ atom / cm ３ It can be seen that the effects of the present invention can be obtained by forming a protective film 91 on the optical filter 90 as follows.

[0087] Table 6 shows the dark current flowing through the chip (semiconductor light-emitting element 1) when 5V was applied to Examples 1-4 and Comparative Examples 1-3. Here, the initial Ir(0) in Table 6 represents the dark current immediately after chip fabrication. From Table 6, it can be seen that the initial Ir(0) for Examples 1-4 is all 0.185 nA or less, and the dark current change rate is 3.5 times (350%) or less. It can be seen that if an intermediate layer is present as in the examples, the increase in dark current can be suppressed even under high temperature and high humidity conditions. Furthermore, even after a 24-hour HAST test, SiO ２ The average D concentration within the layer is 1.5 × 10⁻⁶ ２１ atom / cm ３ The following conditions demonstrate that the increase in dark current can be suppressed even under high temperature and high humidity conditions.

[0088]

[0089] Table 7 shows the results of measuring the resistivity using the same optical filter 90 as in Comparative Example 1, and the same optical filter 90 and protective film 91 as in Examples 1-4 and Comparative Examples 2-3. The resistivity measurement method in Table 7 is as described above, using a synthetic quartz substrate (resistivity 1.4 × 10⁻⁶). １４ An optical filter 90 and (except for Comparative Example 1) a protective film 91 were deposited on a Ωμm (400μm thickness) film, and small pieces measuring L200μm x 1000μm were cut out to form electrodes as described above to prepare samples for resistivity measurement. Volume resistivity was measured using the two-terminal method by connecting Au wires as shown in Figures 14 and 15. The measurement temperature was 25°C, and measurements were taken using a Keithley Source Measure Unit (SMU). After holding the samples for 24 hours under the same conditions as the HAST test described above (130°C, 85% RH humidity, 2 atm), the resistivity was measured again. The rate of change (ρ(24) - ρ(0)) / ρ(0) between the initial resistivity ρ(0) and the resistivity ρ(24) after the 24-hour HAST test was smaller for Examples 1 to 4 than for Comparative Examples 1 to 3. This indicates that the resistivity of the optical filter 90 of the semiconductor light-emitting element 1 in Examples 1 to 4 was maintained at a higher level even after the 24-hour HAST test compared to the elements in Comparative Examples 1 to 3. Based on these results, it can be considered that the change in dark current in the chip is influenced by the change in the resistivity of the optical filter 90 due to moisture.

[0090] ( ＊ The upper limit of this resistivity measurement is 1.4 × 10⁻⁶. １４ The resistance is Ωμm. (Measurement is not possible for resistance values ​​higher than the measured value of the base synthetic quartz substrate.)

[0091] From the above results, it was confirmed that the semiconductor photodetector fabricated to have the intermediate layer of the present invention suppresses the increase in dark current even under high temperature and high humidity conditions compared to the comparative example. Furthermore, the SiO2 after a 24-hour HAST test ２ The average D concentration within the layer is 1.5 × 10⁻⁶ ２１ atom / cm ３ Under the following conditions, it was confirmed that the increase in dark current was suppressed even under high temperature and high humidity compared to the comparative example.

[0092] 1. Semiconductor photodetector 2. Glass epoxy substrate 3. Glass plate 4. Adhesive 5. Au wire 6. Ag paste 7. External connection terminal 10. Substrate 11. Semiconductor laminate 20. Photodetector layer 30. Window layer 40. Contact layer 50. Diffusion prevention layer 60. Zn diffusion region 61. p-type contact layer 62. p-type diffusion region 63. Photodetector 70. Dielectric layer 80. Top electrode 81. Frame electrode 82. Pad electrode 90. Optical filter 91. Protective film 100. Back electrode

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