Automatic illumination control device for wafer pin-hole inspection, and illumination control method

Abstract

The present invention relates to an automatic illumination control device for wafer pin-hole inspection, and an illumination control method, in which an illumination value for wafer pin-hole inspection may be automatically set by using a resistivity value recognized through an identification code provided on a wafer. The automatic illumination control device for wafer pin-hole inspection comprises: a collection unit that collects information about a wafer; a recognition unit that recognizes a resistivity value of the wafer from the wafer information collected by the collection unit; and a control unit that controls an illumination unit to output an illumination value corresponding to the resistivity value of the wafer recognized by the recognition unit. Therefore, productivity can be improved.

Description

Automatic illuminance control device and illuminance control method for wafer defect inspection

[0001] The present invention relates to an apparatus and method for automatically controlling illumination for inspecting defects (pin-holes) in a wafer, and more particularly to an automatic illumination control apparatus and method for wafer defect inspection that can automatically set an illumination value for wafer defect inspection using a resistivity value recognized through an identification code provided on the wafer.

[0002] Generally, semiconductor devices are manufactured by performing various unit processes on a silicon wafer used as a semiconductor wafer to form an electrical circuit containing electrical components on the silicon wafer.

[0003] In addition, identification marks, such as wafer management numbers, are marked on the front or back of the wafer using a laser or the like for wafer production management and data management. These wafer markings can be recognized by a wafer marking recognition device, and by recognizing the markings on the wafer before or after the process, wafer management, including production management, can be efficiently executed.

[0004] A wafer marking recognition device as described above may include an optical character reader (OCR) for recognizing markings, and may be provided with a notch detection sensor for detecting a notch cut in the shape of a 'v' or 'u' on the edge of the wafer.

[0005] According to semiconductor standards, the wafer identification code consists of a total of 18 digits. Generally, the first 8 digits can be used arbitrarily by the manufacturer, and the last 10 digits represent prescribed information.

[0006] Meanwhile, as the integration density of semiconductor devices increases, the yield and reliability of these devices are significantly affected by the quality of the wafers on which they are fabricated. Wafer quality is determined by the number of defects generated throughout the entire process of wafering, which involves fabricating the wafer during crystal growth.

[0007] These wafer defects can be classified into crystal defects occurring during ingot growth and defects caused by external contaminants. Among these, external contaminants such as dust are easily removed by etching or cleaning processes; however, crystal defects such as COP (Crystal Originated Particles), FPD (Flow Pattern Defect), OiSF (Oxygen-induced Stacking Fault), BMD (Bulk Micro Defect), and LDP (Large Dislocation Pit) remain unremoved by cleaning processes and affect the yield and quality of semiconductor devices; therefore, their occurrence must be suppressed during the wafer fabrication process. Accordingly, verifying and inspecting the precise distribution and density of these defects prior to implementing semiconductor devices on the wafer is crucial for yield management.

[0008] In other words, wafers used in the manufacture of semiconductor devices are prepared by thinly slicing silicon ingots; during the growth of the ingot, impurities are mixed in due to the high growth temperature, and oxygen from the quartz crucible 10 7 ~10 8They coexist in atom / cm³ single crystals. During the growth of these ingots, voids or crystal defects caused by silicon atoms, such as those resulting from rotational speed or oxygen levels, can lead to the formation of air pockets. These air pockets are transferred directly to the wafers sliced ​​from the ingot. Wafers containing defects such as air pockets are mostly discarded. Furthermore, wafers are subjected to thermal or physical stress during multiple processes. At this time, if even minor defects such as cracks are present on the wafer, new cracks may develop or semiconductor device products may fail due to thermal or physical stress during the process, potentially leading to a decrease in yield.

[0009] A wafer defect inspection device for inspecting defects on the surface or inside of a wafer as described above is known. In such an inspection device, for example, light is irradiated from one side of the wafer and an image of the wafer is taken from the other side, and the wafer defects are inspected by performing image analysis processing on the captured image.

[0010] The defects of the wafer may include pinholes existing on or inside the wafer, as well as hole defects (through-holes) that completely penetrate the wafer in the thickness direction.

[0011] In addition, the wafer defect inspection device is usually operated in cassette units as a receiving container, and 10 to 25 wafers of various types with different resistivity ranges are received in one cassette.

[0012] The above wafer defect inspection device typically utilizes a highly sensitive camera with a wide camera sensor dynamic range based on light source transmittance. Consequently, if the wafer contains through-holes, strong light passes through them. In this case, the strong light causes smearing in the highly sensitive camera, making it impossible to accurately detect defects.

[0013] An example of such technology is disclosed in the following patent documents 1 to 3, etc.

[0014] For example, Patent Document 1 (Republic of Korea Registered Patent Publication No. 10-0902408, registered June 4, 2009) discloses a wafer marking recognition device comprising: a loading stage rotatably installed to mount a wafer having a specific marking for identification and a notch formed therein; a notch detection sensor disposed above the loading stage to detect the notch of the wafer; an optical character reader (OCR) disposed above the loading stage to recognize the marking marked on the wafer; and a buffer stage that is vertically movable relative to the loading stage to move the wafer upward and unload it from the loading stage, and is capable of reciprocating along a horizontal direction relative to the loading stage to separate the raised wafer from a sensor detection area below the notch detection sensor.

[0015] In addition, Patent Document 2 (Republic of Korea Registered Patent Publication No. 10-2525814, registered on April 21, 2023) discloses a method and system for improving the detection and classification of defects-of-interest (DOI) on a semiconductor wafer, comprising the steps of: providing a certain amount of illumination light generated by an illumination source to a vertically stacked structure disposed on a substrate; collecting light from the vertically stacked structure in response to the amount of illumination light; causing the illumination source to change the spectral range of the illumination light; causing the illumination aperture subsystem to change the shape of the illumination light provided to the substrate; causing the illumination polarization subsystem to change the polarization of the illumination light provided to the substrate; detecting the amount of light collected at each of the plurality of different depths on a detector; generating a three-dimensional image of the inspected volume; determining the presence of defects within the inspected volume based on the three-dimensional image; and classifying the defects as defects of interest based on the three-dimensional image.

[0016] Meanwhile, Patent Document 3 (Korean Published Patent Application No. 2002-0006061, published on January 19, 2002) discloses a method for displaying a semiconductor wafer identification code, comprising the steps of defining a series of codes corresponding to the specifications of a semiconductor wafer and displaying said codes on one surface of said semiconductor wafer, wherein said codes include a series of characters or numbers representing the grade and use of the semiconductor wafer, the year of production, a fuller serial number, a single crystal ingot serial number, a position in the single crystal ingot, a serial number of the semiconductor wafer, and the name of the manufacturer.

[0017] Patent Document 1, as described above, discloses a technology for recognizing markings indicated on a wafer, but does not disclose a configuration for recognizing resistivity values ​​for automatic illuminance setting.

[0018] In addition, the above-mentioned patent document 2 discloses a technology for acquiring a series of images at multiple different wafer depths and generating a three-dimensional image of a thick semiconductor structure from the series of images, but it does not disclose a technology for checking resistivity values ​​to find the optimal illumination of a backlight for wafer inspection and utilizing the resistivity values ​​included in the wafer's unique identification code.

[0019] Meanwhile, the above-mentioned patent document 3 discloses a technology for defining and displaying on a wafer the contents of identification codes representing various information such as the grade, serial number, and production year of a wafer for the convenience of the user, but the above-mentioned patent document 3 also does not disclose a configuration for recognizing resistivity values ​​for automatic illuminance setting.

[0020] In addition, in the conventional technology described above, when a new wafer is introduced into the pin-hole inspection equipment, the process of finding the optimal illumination level by gradually increasing the backlight illumination level from a low level to a high level is performed. Therefore, in the case of wafers with low resistivity, the process must be performed in several steps, which resulted in a long tact time.

[0021] The objective of the present invention is to solve the problems described above by providing an automatic illuminance control device and an illuminance control method for wafer defect inspection that can automatically set an illuminance value for wafer defect inspection using a resistivity value recognized through a wafer identification code (ID).

[0022] Another objective of the present invention is to provide an automatic illumination control device and an illumination control method for wafer defect inspection that can realize improved throughput by automatically setting the light source illumination due to differences in dopant content by wafer type, thereby reducing the setting time.

[0023] Another objective of the present invention is to provide an automatic illumination control device and an illumination control method for wafer defect inspection that can improve productivity by shortening the tact time.

[0024] To achieve the above objective, the automatic illumination control device for wafer defect inspection according to the present invention is characterized by comprising: a collection unit for collecting information about a wafer; a recognition unit for recognizing the resistivity value of the wafer from the wafer information collected by the collection unit; and a control unit for controlling a lighting unit to output an illumination value corresponding to the resistivity value of the wafer recognized by the recognition unit.

[0025] In addition, the automatic illumination control device for wafer defect inspection according to the present invention is characterized by further including a judgment unit that checks whether an image acquired from a camera is within a gray level value range according to the illumination value.

[0026] In addition, the automatic illuminance control device for wafer defect inspection according to the present invention is characterized by further including a storage unit that stores information regarding an illuminance value corresponding to a resistivity value of the wafer.

[0027] In addition, the automatic illumination control device for wafer defect inspection according to the present invention further comprises a setting unit that automatically resets the illumination value according to the information stored in the storage unit when the judgment result of the judgment unit deviates from the error range of the gray level.

[0028] In addition, the automatic illumination control device for wafer defect inspection according to the present invention is characterized in that the collection unit includes an optical character reader (OCR) that identifies a wafer ID provided on the wafer.

[0029] In addition, in the automatic illumination control device for wafer defect inspection according to the present invention, the optical character reader is characterized by being mounted on any one of a wafer defect measuring device, a wafer load module, a wafer transfer module, and a wafer edge area inspection module.

[0030] In addition, the automatic illumination control device for wafer defect inspection according to the present invention is characterized in that the collection unit includes a barcode reader that recognizes a barcode provided in a FOUP (Front Opening Unified Pod).

[0031] In addition, in the automatic illumination control device for wafer defect inspection according to the present invention, the collection unit is characterized by collecting information about the wafer from a system storing information about the wafer, classifying it into DSP (Double Side Polished) and SSP (Single Side Polished).

[0032] In addition, to achieve the above objective, the automatic illumination control method for wafer defect inspection according to the present invention is characterized by comprising: (a) a step of collecting information about a wafer; (b) a step of recognizing the resistivity value of the wafer from the wafer information collected in step (a); (c) a step of outputting an illumination value corresponding to the resistivity value of the wafer recognized in step (b) to a lighting unit; and (d) a step of acquiring an image of the surface of the wafer according to the illumination value output in step (c).

[0033] In addition, the automatic illumination control method for wafer defect inspection according to the present invention is characterized by further including the step of (e) automatically resetting the illumination value when the image obtained in step (d) deviates from the error range of the gray level.

[0034] As described above, according to the automatic illuminance control device and illuminance control method for wafer defect inspection of the present invention, by providing a collection unit for collecting information about a wafer and a recognition unit for recognizing the resistivity value of the wafer, and by controlling a lighting unit with an illuminance value corresponding to the resistivity value of the wafer, the illuminance of the light source is automatically set, thereby achieving the effect of realizing improved productivity (throughput).

[0035] In addition, according to the automatic illuminance control device and illuminance control method for wafer defect inspection of the present invention, the effect of further improving productivity by shortening the tact time is also obtained.

[0036] FIG. 1 is a block diagram of a wafer defect measurement system applied to the present invention,

[0037] FIG. 2 is a configuration diagram of the wafer defect measurement system shown in FIG. 1,

[0038] FIG. 3 is a front perspective view of a first wafer defect measuring device and a second wafer defect measuring device as a twin stage applied to the present invention,

[0039] FIG. 4 is a rear perspective view of a first wafer defect measuring device and a second wafer defect measuring device as a twin stage applied to the present invention,

[0040] FIG. 5 is a front perspective view of the first wafer defect measuring device shown in FIG. 3,

[0041] FIG. 6 is a rear perspective view of the first wafer defect measuring device shown in FIG. 3,

[0042] FIG. 7 is a block diagram showing the configuration of an automatic illumination control device for wafer defect inspection according to the present invention.

[0043] FIG. 8 is a perspective view of a wafer edge region inspection module applied to the present invention,

[0044] FIG. 9 is a drawing for explaining an example of a wafer ID applied to the present invention,

[0045] FIG. 10 is a flowchart illustrating an automatic illumination control process for wafer defect inspection according to the present invention.

[0046] The above and other objects and novel features of the present invention will become more apparent from the description in this specification and the accompanying drawings.

[0047] In the description of the present invention, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Furthermore, since the size and thickness of each component shown in the description and drawings of the present invention are depicted arbitrarily for convenience of explanation, the present invention is not necessarily limited to what is depicted.

[0048] Additionally, the terms “part,” “module,” or “part” used herein may perform at least one function or operation and may be implemented as hardware or software consisting of mechanical or electrical / electronic configurations, or as a combination of hardware and software; and, excluding the “part,” “module,” or “part” that need to be implemented in specific hardware, the plurality of “parts,” “modules,” or “parts” may be integrated into at least one module and implemented by at least one processor.

[0049] Meanwhile, the term "wafer" as used herein generally refers to a substrate formed of semiconductor or non-semiconductor materials, non-limiting examples of semiconductor materials include single-crystal silicon, gallium arsenide, and indium phosphide, and such substrates can be typically processed in semiconductor manufacturing facilities, and the substrate may be made of glass, sapphire, or other insulating materials, and "notch" refers to a cutout in a semiconductor wafer that specifies the direction to indicate the crystal orientation.

[0050] Additionally, as used herein, "left-right direction and front-back direction" refers to the X-axis and Y-axis directions as directions parallel to the surface on which the wafer is mounted, and "up-down direction" refers to the Z-axis direction as a direction perpendicular to the horizontal direction formed by the X-axis and Y-axis, and "wafer defect" may include defects such as cracks, defects, or damage in the edge region of the wafer, defects on the surface of the wafer, etc., and "wafer defect measurement" may include inspection of the wafer edge region, detection of the wafer surface and detection of defect depth, measurement of the type of defect, size of the defect, depth of the defect, and defect image.

[0051] The configuration of a wafer defect measurement system to which the automatic illuminance control device and illuminance control method for wafer defect inspection according to the present invention are applied is described with reference to the drawings.

[0052] FIG. 1 is a block diagram of a wafer defect measurement system applied to the present invention, and FIG. 2 is a configuration diagram of the wafer defect measurement system shown in FIG. 1. That is, the automatic illuminance control device and illuminance control method for wafer defect inspection according to the present invention can shorten the tact time by applying a wafer defect measurement system as shown in FIG. 1 and FIG. 2 and automatically setting the illuminance value for wafer defect inspection using the resistivity value recognized through the wafer identification code.

[0053] The wafer defect measurement system illustrated in FIGS. 1 and 2 may include a first wafer defect measurement device (100) and a second wafer defect measurement device (100'), a wafer load module (200) provided for inspection and storage of wafers, a wafer transfer module (300) that transfers a wafer (W) of the wafer load module by a single robot arm (310), a wafer edge area inspection module (400) that inspects the edge area of ​​the wafer (W) transferred by the single robot arm (310), and a control module (500) that controls an illuminance value according to the recognition of a wafer identification code and each device and module of the wafer defect measurement system.

[0054] Accordingly, the wafer defect measurement system described above can sequentially perform control of the roughness value for defect inspection of the wafer (W), inspection of the wafer edge region, detection of the wafer surface and defect depth, and measurement of the type of defect, size of the defect, depth of the defect, and defect image. That is, for convenience of explanation, FIG. 2 shows the state in which the wafer (W) is seated on each of the first wafer defect measurement device (100), the second wafer defect measurement device (100'), the wafer load module (200), and the wafer edge region inspection module (400).

[0055] The first wafer defect measuring device (100), the second wafer defect measuring device (100'), the wafer load module (200), and the wafer edge area inspection module (400) may be located within the stroke area of ​​a single robot arm (310) of the wafer transfer module (300). That is, the main body of the wafer transfer module (300) may be movable left and right within the system along a rail (320), and the single robot arm (310) provided on the main body may be movable up and down on the main body and may be movable left and right, forward and backward within the stroke area.

[0056] The first wafer defect measuring device (100) and the second wafer defect measuring device (100') are described with reference to FIGS. 3 and FIGS. 4.

[0057] FIG. 3 is a front perspective view of a first wafer defect measuring device and a second wafer defect measuring device as a twin stage applied to the present invention, and FIG. 4 is a rear perspective view of a first wafer defect measuring device and a second wafer defect measuring device as a twin stage applied to the present invention.

[0058] As shown in FIGS. 3 and 4, the first wafer defect measuring device (100) and the second wafer defect measuring device (100') can simultaneously or sequentially measure defects in the first wafer (1) and the second wafer (1') as substrates transported by a single robot arm (310).

[0059] Meanwhile, the expressions ‘first’ and ‘second’ may be used for the respective identical components of the first wafer defect measuring device (100) and the second wafer defect measuring device (100’). That is, the first wafer defect measuring device (100) may include a first main body (10) and a first gantry (20) as a structure for installing a measuring device such as a camera on the first main body (10), and the second wafer defect measuring device (100’) may include a second main body (10’) and a second gantry (20’) as a structure on the second main body (10’).

[0060] Additionally, as illustrated in FIGS. 2 to 4, the first wafer defect measuring device (100) may include a first surface detection module (110) for detecting the surface condition of the first wafer (1) and a first defect depth detection module (120) for detecting the defect depth of the first wafer (1), and the second wafer defect measuring device (100') may include a second surface detection module (110') for detecting the surface condition of the second wafer (1') and a second defect depth detection module (120') for detecting the defect depth of the second wafer (1').

[0061] The first body (10) and the second body (10') may be provided, for example, as aluminum plates, and may be provided to be in contact with each other on the same plane as shown in FIGS. 2 to 4. That is, the first body (10) and the second body (10') may be provided as twin stages.

[0062] As shown in FIGS. 3 and 4, the first gantry (20) and the second gantry (20') are provided in the shape of first and second support plates on each of the respective sides of the first main body (10) and the second main body (10'), and can be formed as an upper plate connecting the upper portions of the first and second support plates. That is, the first gantry (20) and the second gantry (20') can be provided in a roughly "C" shape when viewed in a planar view from above.

[0063] A square-shaped bracket (21) for a first line camera is coupled to the interior of the upper plate of the first gantry (20), and a bracket (22) for a first Z-axis drive camera is coupled to the side of the bracket (21) for the first line camera, and a first surface detection module (110) for detecting the surface condition of the first wafer (1) is mounted inside the bracket (21) for the first line camera, and a first defect depth detection module (120) for detecting the defect depth of the first wafer (1) can be mounted on the bracket (22) for the first Z-axis drive camera.

[0064] Additionally, a square-shaped bracket (21') for a second line camera is coupled to the interior of the upper plate of the second gantry (20'), and a bracket (22') for a second Z-axis drive camera is coupled to the side of the bracket (21') for the second line camera. A second surface detection module (110') for detecting the surface condition of the second wafer (1') is mounted inside the bracket (21') for the second line camera, and a second defect depth detection module (120') for detecting the defect depth of the second wafer (1') can be mounted on the bracket (22') for the second Z-axis drive camera. Furthermore, as shown in FIGS. 3 and 4, the first gantry (20) and the second gantry (20') can be arranged to be in contact with each other.

[0065] As described above, in a wafer defect measurement system equipped with a twin stage according to the present invention, a surface detection module (110, 110') for detecting the surface condition of a wafer (W, 1, 1') and a defect depth detection module (120, 120') for detecting the defect depth of a wafer (1, 1') are arranged parallel to each other along the X-axis as shown in FIG. 3 and FIG. 4, thereby enabling a reduction in the footprint, which is the space occupied by the equipment of the twin stage.

[0066] The specific structures of the first wafer defect measuring device (100) and the second wafer defect measuring device (100') described above will be explained with reference to FIGS. 5 and 6.

[0067] FIG. 5 is a front perspective view of the first wafer defect measuring device shown in FIG. 3, and FIG. 6 is a rear perspective view of the first wafer defect measuring device shown in FIG. 3.

[0068] Also, since the first wafer defect measuring device (100) and the second wafer defect measuring device (100') are configured identically, as shown in FIGS. 5 and 6, only the configuration of the first wafer defect measuring device (100) is described for convenience of explanation, but the same configuration can be applied to the configuration of the second wafer defect measuring device (100').

[0069] As shown in FIGS. 5 and 6, a first gantry (20) in the shape of a 'C' is provided in the first body (10) of the first wafer defect measuring device (100), a first main table (30) movable along the Y-axis is provided on the upper part of the first body (10), and a first sub table (40) movable along the X-axis is provided on the upper part of the first main table (30).

[0070] Additionally, the first sub-table (40) is equipped with a first screen plate (50) formed in a roughly circular shape to block light that may be applied from the outside of the first wafer (1) during inspection of the first wafer (1), and a plurality of first wafer supports (60) that support the first wafer (1) along the periphery of the first screen plate (50) may be equipped.

[0071] On both sides of the first main body (10), a first linear servo (70) and a first LM guide (71) are provided in a structure that supports the first main table (30) inside the space between the first and second support plates of the first gantry (20) so that the first main table (30) can be moved along the Y-axis. That is, the first linear servo (70) is provided to drive the first main table (30) along the Y-axis, and the first LM guide (71) is provided to support the first main table (30) that can be moved along the Y-axis. That is, a first linear servo (70) and a first LM guide (71) are mounted on both sides of the first main body (10), and a first main table (30) is mounted on the upper part of the first linear servo (70) and the first LM guide (71) so as to be movable along the Y-axis, and a second linear servo (70') and a second LM guide (71') are mounted on both sides of the second main body (10'), and a second main table (30') is mounted on the upper part of the second linear servo (70) and the second LM guide (71') so as to be movable along the Y-axis.

[0072] As described above, in the wafer defect measurement system equipped with a twin stage applied to the present invention, the first main table (30) is supported by a first linear servo (70) and a first LM guide (71) at the bottom of the first main table (30) so that the first main table (30) can move along the Y-axis inside the first gantry (20), and the second main table (30') is supported by a second linear servo (70') and a second LM guide (71') at the bottom of the second main table (30') so that the second main table (30') can move along the Y-axis inside the second gantry (20'), thereby allowing the size of the first wafer defect measurement device (100) and the second wafer defect measurement device (100') to be reduced.

[0073] As shown in FIG. 6, the first sub-table (40) is configured to be movable along the X-axis by being driven by a first servo actuator (80), and the first servo actuator (80) can be operated by being coupled to a first clean cable carrier (81) used as a pneumatic tube and wire passage.

[0074] The first screen plate (50) may be configured to be movable up and down on the first sub-table (40) by means of a first up-down cylinder (90) that can be operated by pneumatic or hydraulic pressure. Accordingly, the first screen plate (50) may be configured to be movable up and down inside a plurality of first wafer supports (60) to block light that may be applied from the outside during the inspection process of the first wafer (1). To this end, a cutout for the movement of the first screen plate (50) may be provided inside the plurality of first wafer supports (60).

[0075] As shown in FIGS. 5 and 6, the plurality of first wafer supports (60) are arranged in a structure with three of them spaced at 120-degree intervals, but are not limited thereto and may be arranged in four or more depending on the type of wafer.

[0076] The first surface detection module (110) is provided for surface inspection to check the size, position, dimensions of the wafer and whether there are microcracks, pinholes, stains (foreign substances), etc. on the surface or back of the wafer, and as shown in FIGS. 5 and 6, it may include a first line camera control unit (111), three first line scan cameras (112), a first lens (113) for the line scan cameras, a first line camera illumination unit (114), and a line illumination unit (115) composed of near-infrared (NIR) light.

[0077] That is, the first surface detection module (110) can detect defects such as foreign substances, cracks, scratches, and pinholes present on the surface or inside of the first wafer (1) by using transmitted light that passes through the first wafer (1), for example, infrared light of 1050 nm to 1100 nm, to acquire an image through three first line scan cameras (112) in which imaging elements are arranged in a strip shape, and can inspect the through-hole of the first wafer (1) by irradiating visible light that does not pass through the wafer, for example, visible light in the wavelength range of 400 nm to 700 nm, toward the first wafer (1), acquiring an image of the first wafer (1) using a through-hole camera on the other side of the first wafer (1), and determining whether light is transmitted, and can re-determine whether there is a defect by re-acquiring an image of the defect through a review camera at the defect location detected through the first line scan camera (112). In addition, the size of the line lighting unit (115) can be reduced by applying a halogen lamp or an LED lamp to the first surface detection module (110).

[0078] The first defect depth detection module (120) includes a depth detection camera and a first depth measurement lighting unit (121) for detecting the location of a defect (hereinafter referred to as "depth") relative to the thickness of the wafer detected through the first surface detection module (110). The depth detection camera is designed to have a focal depth relatively smaller than the thickness of the wafer, so that it can accurately measure defects of size 1㎛ to 3000㎛ present in the wafer. That is, the first defect depth detection module (120) can automatically locate the surface of the wafer (1) and detect the location of the defect in the wafer (1) by taking 30 shots at intervals of 25㎛ in the depth direction, for example.

[0079] As illustrated in FIGS. 1 and 2, the wafer load module (200) may include an inspection load section (210) and a storage load section (220), each having a wafer receiving container and a load port for receiving and stacking each wafer (W) in a vertical direction. That is, in the inspection load section (210), an inspection wafer receiving container, on which a plurality of wafers, for example 25 wafers (W), to be inspected in the wafer defect measurement system applied to the present invention are placed, may be mounted on the first load port, and in the storage load section (220), a storage wafer receiving container, on which a plurality of wafers, for example 25 wafers, whose inspection of wafers (W) has been completed according to the present invention are placed, may be mounted on the second load port. For example, a FOUP (Front Opening Unified Pod) transported from an OHT (Overhead Hoist Transport) may be used as the wafer receiving container.

[0080] The wafer transfer module (300) is equipped with a robot arm (310) that is mounted on the inspection load portion (210) of the wafer load module (200) to load and unload the wafer (W) to be inspected to the wafer edge region inspection module (400), the first wafer defect measuring device (100), and the second wafer defect measuring device (100'). The robot arm (310) may be provided with an edge grip portion for holding the wafer or a vacuum suction portion such as a vacuum chuck.

[0081] The robot arm (310) is provided with multiple joints and can be extended in a horizontal direction and can move left and right or forward and backward within a single robot driving stroke range. That is, since the centerline of the first wafer defect measuring device (100), the centerline of the second wafer defect measuring device (100'), the centerline of the inspection load section (210), and the centerline of the storage load section (220) are within the robot driving stroke range of the wafer transfer module (300), wafer handling within the entire system is possible by the wafer transfer module (300), thereby achieving minimization of the inspection stage.

[0082] Next, an example of the configuration of an automatic illumination control device for wafer defect inspection according to the present invention will be described with reference to the drawings.

[0083] FIG. 7 is a block diagram showing the configuration of an automatic illumination control device for wafer defect inspection according to the present invention.

[0084] The automatic illumination control device for wafer defect inspection according to the present invention may include a control module (500), and as illustrated in FIG. 7, the control module (500) may include a collection unit (510) for collecting information about a wafer (W), a recognition unit (520) for recognizing the resistivity value of the wafer from the wafer information collected by the collection unit (510), a control unit (530) for controlling a lighting unit to output an illumination value corresponding to the resistivity value of the wafer recognized by the recognition unit (520), a judgment unit (540) for checking whether an image acquired from a camera is within a gray level value range according to the illumination value, a storage unit (550) for storing information about the illumination value corresponding to the resistivity value of the wafer, and a setting unit (560) for automatically resetting the illumination value according to the information stored in the storage unit (550) when the judgment result from the judgment unit (540) deviates from the error range of the gray level.

[0085] The above collection unit (510) may be provided in the wafer edge region inspection module (400) as shown in FIG. 8. FIG. 8 is a perspective view of the wafer edge region inspection module applied to the present invention.

[0086] The wafer edge region inspection module (400) is a device for inspecting the edge region of a wafer to inspect defects such as cracks, defects, or damage in the edge region of a semiconductor wafer (W) and to align a notch (N), as shown in FIG. 8, and may include a vacuum suction unit (410) provided on a base (401) and equipped with a vacuum chuck that vacuum suctions the wafer in a non-contact state, a support (420) that supports the wafer (W), a wafer mounting position inspection unit (430) equipped with a camera for recognizing the mounting position of the wafer (W), a rotating unit that rotates the vacuum suction unit (410) that vacuum suctions the wafer to continuously inspect the edge region of the wafer (W), and an edge inspection line scan unit provided on the same plane as the wafer (W) and inspecting the edge region and notch (N) position of the wafer that is rotated by the rotating unit.

[0087] The above vacuum adsorption unit (410) may include, for example, a vacuum chuck exposed at the top of the base (401) for vacuum adsorbing a wafer (W), and an air supply unit for exhausting and sucking air to vacuum adsorb the wafer (W) to the vacuum chuck.

[0088] In addition, the base (401) may be provided with a structure in which an X-axis driving unit for moving the vacuum chuck in the X direction, a Y-axis driving unit for moving the vacuum chuck in the Y direction, and a Z-axis driving unit for moving the vacuum chuck in the Z direction are sequentially stacked.

[0089] The above support (420) is provided to temporarily hold a wafer that is loaded and unloaded in correspondence with the diameter of the wafer (W). That is, the support (420) is provided at 120-degree intervals and consists of three support members having a roughly "C" shape, and the edge portion of the wafer is placed on the upper edge portion of these three support members. By providing the support (420) with three "C" shaped support members, it is possible to easily enter and exit the vacuum chuck without obstruction of the support members, and the wafer can be stably held only at the edge portion of the wafer.

[0090] A wafer ID may be provided at the lower portion near the notch (N) formed on the wafer (W), as shown in FIG. 9. FIG. 9 is a drawing for explaining an example of a wafer ID applied to the present invention.

[0091] Figure 9 shows an example of a Wafer ID (SEMI-M13), where the wafer ID is "7G087354WA15.581G3". In the wafer ID, "7G087354" represents Identification, "WA" represents Vendor, "15.5" represents Resistivity, "8" represents Dopant, "1" represents Crystal Orientation, and "G3" represents Check Characters. That is, the wafer ID in Figure 9, which is shown as an example of the present invention, indicates that the resistivity is 15.5 Ω cm.

[0092] Meanwhile, FIG. 8 shows an example in which an optical character reader (OCR, 440) is applied as a collection unit (510) to identify a wafer ID provided on a wafer (W). That is, the optical character reader (440) is mounted on the lower part of the wafer (W) on one side of the wafer edge area inspection module (400) to collect a wafer ID as shown in FIG. 9.

[0093] Additionally, in FIG. 8, the optical character reader (440) is shown separated from the base (401), but this is for convenience of explanation and may be fixed to one side of the base (401), such as the wafer mounting position inspection unit (430). In the above description, an example is shown in which the optical character reader (440) is provided in the wafer edge area inspection module (400) as a collection unit (510), but it is not limited thereto and may be provided in the wafer defect measuring device (100, 100'), wafer load module (200), and wafer transfer module (300).

[0094] In addition, the above collection unit (510) can collect wafer information from a barcode reader that recognizes a barcode provided in the FOUP (Front Opening Unified Pod).

[0095] Meanwhile, the above-mentioned collection unit (510) may also collect information about the wafer by setting it so that the wafer is classified into DSP (Double Side Polished) / SSP (Single Side Polished) and inspected according to the recipe setting from a separate system in which information about the wafer is stored. That is, even if the resistivity values ​​of the DSP / SSP wafers are the same, the gray level at the same illuminance value differs slightly due to reasons such as light refraction and scattering, so the above-mentioned collection unit (510) can collect wafer information by distinguishing between DSP / SSP wafers.

[0096] The above recognition unit (520) recognizes the resistivity (resistivity value) from the wafer information (Wafer ID) as illustrated in FIG. 9, which is collected by the collection unit (510). That is, it recognizes the resistivity value of the corresponding wafer as 15.5 Ω cm in the "15.5" portion, which is the resistivity area.

[0097] The control unit (530) can control a line camera lighting unit and / or a line lighting unit as a lighting unit to output an illuminance value corresponding to the resistivity value of the wafer recognized by the recognition unit (520). Such control can be executed according to the correlation between the resistivity value of the wafer and the illuminance value stored in the storage unit (550).

[0098] Generally, there are differences in the dopant content depending on the type of wafer, and as the dopant content increases, the resistivity and light transmittance decrease. Table 1 below shows an example of resistivity values ​​according to the type of wafer.

[0099] Wafer Type Resistivity (Ω㎝) P-1~30 P0.03~1 P+0.01~0.03 P++0.005~0.01 P+++< 0.005

[0100] Meanwhile, the judgment unit (540) checks whether the image acquired from the line scan camera is within the gray level value range according to the illuminance value as described above, and if the judgment result of the judgment unit (540) is outside the gray level error range, the setting unit (560) can automatically reset the illuminance value according to the information stored in the storage unit (550).

[0101] In addition, although the configurations of the recognition unit (520), control unit (530), judgment unit (540), and setting unit (560) were described separately in the above description, they are not limited thereto and can be executed continuously by a program configured with a microprocessor or the like provided in the control module (500). Also, the storage unit (550) may be composed of semiconductor memory such as RAM or ROM and may be configured to operate by a program.

[0102] Next, an automatic illumination control method for wafer defect inspection according to the present invention will be described with reference to FIG. 10. FIG. 10 is a flowchart illustrating the automatic illumination control process for wafer defect inspection according to the present invention.

[0103] In order to perform automatic illumination control for wafer defect inspection according to the present invention, first, information about the wafer is collected from the collection unit (510) for the wafer for wafer defect inspection (S10). The wafer information collection in step S10 can be performed by identifying the wafer ID provided on the wafer with an optical character reader (440), recognizing the barcode provided on the FOUP (Front Opening Unified Pod), and from a system in which information about the wafer is stored.

[0104] In the wafer information collected in step S10, the recognition unit (520) recognizes the resistivity value of the wafer (S20), and the control unit (530) outputs an illuminance value corresponding to the resistivity value of the wafer recognized in step S20 to the line camera lighting unit and / or line lighting unit (S30). The output of the illuminance value in step S30 can be executed according to the correlation between the resistivity value of the wafer and the illuminance value stored in the storage unit (550).

[0105] Next, the line scan camera can acquire an image of the surface of the wafer according to the illuminance value output in step S30 (S40).

[0106] Regarding the image obtained in step S40 above, the judgment unit (540) determines whether it is within the error range of the gray level (S50), and if the image obtained in step S50 above exceeds the error range of the gray level, the setting unit (560) automatically resets the illuminance value by referring to the resistivity value stored in the storage unit (550) as described above (S60).

[0107] Based on the resetting of the illuminance value in step S60, proceed to step S30 and repeat the process described above. Meanwhile, if the image acquired in step S50 is within the error range of the gray level, the automatic illuminance control process for the wafer is terminated, and proceed to step S10 for the newly loaded wafer for defect inspection to execute the process described above.

[0108] Although the invention made by the inventors has been specifically described according to the above embodiments, the invention is not limited to the above embodiments and can be modified in various ways without departing from the gist thereof.

[0109] Productivity can be improved by using the automatic illumination control device and illumination control method for wafer defect inspection according to the present invention.

Claims

1. A collection unit that collects information about a wafer, A recognition unit that recognizes the resistivity value of a wafer from wafer information collected by the above-mentioned collection unit, An automatic illumination control device for wafer defect inspection, characterized by including a control unit that controls a lighting unit to output an illumination value corresponding to the resistivity value of the wafer recognized by the recognition unit.

2. In Paragraph 1, An automatic illumination control device for wafer defect inspection, characterized by further including a judgment unit that checks whether an image acquired from a camera is within a gray level value range according to the above illumination value.

3. In Paragraph 2, An automatic illuminance control device for wafer defect inspection, characterized by further including a storage unit that stores information regarding an illuminance value corresponding to a resistivity value of the wafer.

4. In Paragraph 3, An automatic illuminance control device for wafer defect inspection, characterized by further including a setting unit that automatically resets the illuminance value according to information stored in the storage unit when the judgment result of the judgment unit exceeds the error range of the gray level.

5. In Paragraph 1, An automatic illumination control device for wafer defect inspection, characterized in that the above-mentioned collection unit includes an optical character reader (OCR) that identifies a wafer ID provided on the wafer.

6. In Paragraph 5, An automatic illumination control device for wafer defect inspection, characterized in that the above optical character reader is mounted on any one of a wafer defect measuring device, a wafer load module, a wafer transfer module, and a wafer edge area inspection module.

7. In Paragraph 1, An automatic illumination control device for wafer defect inspection, characterized in that the above-mentioned collection unit includes a barcode reader that recognizes a barcode provided in a FOUP (Front Opening Unified Pod).

8. In Paragraph 1, An automatic illumination control device for wafer defect inspection, characterized in that the above-mentioned collection unit collects information about the wafer by classifying it into DSP (Double Side Polished) and SSP (Single Side Polished) from a system storing information about the wafer. 9.(a) Step of collecting information about the wafer, (b) a step of recognizing the resistivity value of the wafer from the wafer information collected in step (a) above, (c) a step of outputting an illuminance value corresponding to the resistivity value of the wafer recognized in step (b) above to a lighting unit, (d) A step of acquiring an image of the surface of a wafer according to the illuminance value output in step (c) above, characterized by an automatic illuminance control method for wafer defect inspection.

10. In Paragraph 9, (e) A method for automatic illumination control for wafer defect inspection, characterized by further including a step of automatically resetting the illumination value when the image obtained in step (d) is outside the gray level error range.

11. In Paragraph 9, An automatic illumination control method for wafer defect inspection, characterized in that the wafer information collection in step (a) above is performed by identifying a wafer ID provided on the wafer using an optical character reader (OCR).

12. In Paragraph 11, An automatic illumination control method for wafer defect inspection, characterized in that the optical character reader is mounted on any one of a wafer defect measuring device, a wafer load module, a wafer transfer module, and a wafer edge area inspection module to identify the wafer ID.

13. In Paragraph 11, An automatic illumination control method for wafer defect inspection, characterized in that the wafer information collection in step (a) above is executed by recognizing a barcode provided on a FOUP (Front Opening Unified Pod).

14. In Paragraph 11, An automatic illumination control method for wafer defect inspection, characterized in that the wafer information collection in step (a) above is collected by classifying it into DSP (Double Side Polished) and SSP (Single Side Polished) from a system storing information about the wafer.

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