Circuit board

Abstract

A circuit board comprising: a first build-up structure; and a second build-up structure disposed on the first build-up structure, wherein the second build-up structure includes a lower build-up structure and an upper build-up structure disposed on the lower build-up structure and having a smaller horizontal width than the lower build-up structure, and the upper build-up structure comprises, in a lower portion thereof, a stepped portion recessed in the horizontal direction.

Description

circuit board

[0001] This embodiment relates to a circuit board.

[0002]

[0003] Recently, technologies related to electronic products such as AI and servers have been progressing toward multi-functionality and high speed. To respond to this trend, high-layer and large-area circuit board technologies are also developing rapidly to keep pace with the fast-advancing semiconductor chip manufacturing technology.

[0004] Furthermore, regarding mobile products such as smartphones and tablets, the thickness of circuit boards applied to miniaturize finished electronic products is also decreasing, and technologies related to multilayer circuit boards, which configure more circuit layers within a circuit board of the same thickness, are being actively researched. In addition, as the pitch of semiconductor chips narrows and the size of chips increases, chiplet technology for separating semiconductor chips by function is being researched. Moreover, technologies for connecting separated chiplets on circuit boards are being actively researched. Furthermore, by connecting semiconductor chips with different functions on circuit boards, technologies regarding the connection relationship between circuit boards and semiconductor chips are being actively researched, such as the circuit board connecting semiconductor chips to one another, which was previously considered only from the perspective of conventional semiconductor packaging.

[0005] Recent requirements for printed circuit boards are closely linked to the increasing speed and density in the electronics industry market. To meet these demands, many challenges must be addressed, including the miniaturization of circuits, superior electrical characteristics, high reliability, high-speed signal transmission structures, and enhanced functionality.

[0006] In particular, efficient heat dissipation is becoming a very important issue to improve product reliability and prevent malfunctions in sets such as mobile phones, servers, and networks that are becoming faster, consume high power, and simultaneously become denser and smaller. High heat generation temperatures of semiconductor chips are a significant cause of errors such as malfunctions and freezes in the sets.

[0007] To lower the temperature of these semiconductor chips, the technology applied to products so far involves installing a heat sink over the semiconductor chip that generates high heat or operating a cooling fan to forcibly exhaust the high heat generated by the chip.

[0008]

[0009] The present invention provides a circuit board capable of high multilayer and large area, and capable of improving heat dissipation efficiency.

[0010]

[0011] A circuit board according to the present embodiment comprises a first build-up structure; and a second build-up structure disposed on the first build-up structure, wherein the second build-up structure comprises a lower build-up structure and an upper build-up structure disposed on the lower build-up structure and having a horizontal width smaller than the horizontal width of the lower build-up structure, and the upper build-up structure is provided at the bottom and includes a stepped portion that is concave along the horizontal direction.

[0012] It includes an insulating layer disposed in the above-mentioned step portion, and the insulating layer may be a material different from the material constituting the second build-up structure.

[0013] The first build-up structure may include a first bonding portion protruding toward the second build-up structure on its upper surface, and the second build-up structure may include a second bonding portion protruding toward the first build-up structure on its lower surface.

[0014] The vertical length of the first bonding part and the vertical length of the second bonding part may be the same.

[0015] The vertical length between the upper surface of the first bonding part and the upper surface of the first build-up structure may be the same as the vertical length between the lower surface of the second bonding part and the lower surface of the second build-up structure.

[0016] The gap between the upper surface of the first bonding part and the lower surface of the second bonding part may be located at the center of the vertical length between the upper surface of the first build-up structure and the lower surface of the second build-up structure.

[0017] It may include a connecting part disposed in the spaced-apart space between the upper surface of the first bonding part and the lower surface of the second bonding part.

[0018] The vertical length of the first bonding part and the vertical length of the second bonding part may be different from each other.

[0019] The upper build-up structure includes a core layer and an insulating layer disposed on the core layer, and the step portion may be disposed below the core layer.

[0020] The insulating layer may include an extension protruding outwardly from the side of the core layer of the upper build-up structure.

[0021]

[0022] Through this embodiment, a placement space for semiconductor chips is formed through a cavity, which has the advantage of securing a wide placement space for multiple electronic components and semiconductor chips within the circuit board.

[0023] In addition, there is an advantage in that heat dissipation efficiency can be improved by implementing a heat dissipation structure in the horizontal and vertical directions through heat dissipation members.

[0024]

[0025] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0026] FIGS. 2 to 4 are drawings for explaining the process of forming a cavity in a circuit board according to an embodiment of the present invention.

[0027] FIGS. 5 and 6 are drawings for explaining various shapes of heat dissipation vias according to embodiments of the present invention.

[0028] FIGS. 7 and 8 are drawings illustrating modified examples of a circuit board structure in which a release film is separated within a trench according to an embodiment of the present invention.

[0029] FIG. 9 is a drawing illustrating another modified example of a structure for forming a step portion within a circuit board according to an embodiment of the present invention.

[0030] FIGS. 10 to 12 are drawings for explaining the process of forming a step portion within a circuit board according to FIG. 9.

[0031] FIG. 13 is a drawing illustrating a modified example of the combined structure of a first build-up structure and a second build-up structure according to an embodiment of the present invention.

[0032] FIG. 14 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0033]

[0034] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0035] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0036] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0037] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, shall be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it shall be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it shall not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0038] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0039] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0040] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0041] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0042] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0043] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0044] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0045] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0046] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0047] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0048] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0049] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 to 4 are drawings for explaining the process of forming a cavity within a circuit board according to an embodiment of the present invention, FIG. 5 and 6 are drawings for explaining various shapes of heat dissipation vias according to an embodiment of the present invention, and FIG. 7 and 8 are drawings illustrating modified examples of a circuit board structure in which a release film is separated within a trench according to an embodiment of the present invention.

[0050] Referring to FIGS. 1 to 6, a circuit board (10) according to an embodiment of the present invention may include a first build-up structure (100) and a second build-up structure (200).

[0051] The first build-up structure (100) may be placed below the second build-up structure (200). The first build-up structure (100) may include a plurality of insulating layers, a plurality of wiring portions, and a plurality of via portions.

[0052] A plurality of insulating layers of the first build-up structure (100) may include a first insulating layer (101), a second insulating layer (102) disposed on the first insulating layer (101), and a third insulating layer (103) disposed on the second insulating layer (102). The first to third insulating layers (101, 102, 103) may be arranged in a vertical direction.

[0053] The first to third insulating layers (101, 102, 103) may each be any insulating material, such as photocurable and / or thermosetting materials. As thermosetting insulating materials, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used as an example, and a prepreg (PPG) containing glass fibers within a resin may be used. Additionally, the resins mentioned above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. When the first to third insulating layers (101, 102, 103) are photocurable insulators, the first to third insulating layers (101, 102, 103) may each be a PID (Photo Imageable Dielectric).

[0054] At least some of the insulating layers among the plurality of insulating layers of the first build-up structure (100) may have a material different from that of other insulating layers. For example, the first insulating layer (101) and the second insulating layer (102) may each be a prepreg (PPG) containing glass fibers in a resin. Accordingly, at the bottom of the first build-up structure (100), the strength of the circuit board (10) is reinforced by the material characteristics of the first insulating layer (101) and the second insulating layer (102), thereby minimizing bending.

[0055] The third insulating layer (103) may be a PID (Photo Imageable Dielectric) or an ABF (Ajinomoto Build-up Film). A fine pattern of wiring for electrical connection with the second build-up structure (200) or a plurality of electronic elements (500, 600) to be described later can be easily implemented on the surface of the first build-up structure (100).

[0056] The third insulating layer (103) may include a resin and a filler disposed within the resin, and the filler of the third insulating layer (103) may have a smaller particle size than the filler in the first insulating layer (101) and the second insulating layer (102).

[0057] The number of stacked insulating layers of the first build-up structure (100) described above is exemplary, and the first build-up structure (100) may have more or fewer insulating layers arranged in the vertical direction.

[0058] The circuit board (10) may include a first protection layer (190). The first protection layer (190) may be disposed on the lower surface of the third insulating layer (103). When a semiconductor device is disposed on the surface of the first build-up structure (100) using a material such as solder, the first protection layer (190) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent the problem of external contaminants penetrating into the build-up structure and reducing reliability. Each of the first protection layers (190) may be a solder resist.

[0059] The first build-up structure (100) may include a circuit pattern for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The circuit pattern may include a plurality of wiring portions and a plurality of via portions.

[0060] A plurality of wiring sections may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring sections is embedded within a plurality of insulating layers or protective layers and exposed to the outside from the surface. A wiring section may also be referred to as a metal layer. Furthermore, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a wiring section being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which wiring sections are disposed on the first surface and the second surface of some of the insulating layers, respectively, and wiring sections are disposed on only the first surface or the second surface of other parts of the plurality of insulating layers.

[0061] A plurality of wiring sections of the first build-up structure (100) may include a first wiring section (111) disposed on the lower surface of the first insulating layer (101), a second wiring section (112) disposed on the first insulating layer (101), a third wiring section (113) disposed on the second insulating layer (102), and a fourth wiring section (114) disposed on the third insulating layer (103). The second wiring section (112) may be embedded on the first insulating layer (101). The third wiring section (113) may be embedded on the second insulating layer (102). The fourth wiring section (114) may be embedded on the third insulating layer (103). The second to fourth wiring sections (112, 113, 114) can each be implemented on the upper surface of the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103) using an ETS (Embedded Technology Substrate) method.

[0062] After forming the second wiring section (112) and the third wiring section (113) on the first insulating layer (101) and the second insulating layer (102), respectively, the upper surface of the second insulating layer (102) may be polished before forming the third insulating layer (103) on the second insulating layer (102). A polished surface may be placed on the upper surface of the second insulating layer (102). In this case, the surface of the third wiring section (113) may be polished together with the polishing. Accordingly, the vertical thickness of the second wiring section (112) and the third wiring section (113) placed on the first insulating layer (101) and the second insulating layer (102) may be smaller than the vertical thickness of the fourth wiring section (114) placed on the third insulating layer (103). Accordingly, the bonding portion (170) described later can be stably supported through the relatively thick fourth wiring portion (114), and there is an advantage of achieving a fine pitch through the second wiring portion (112) and the third wiring portion (113) within the first insulating layer (101) and the second insulating layer (102), and reducing the vertical thickness.

[0063] A wiring portion (116) for electrical connection with an electronic element (500, 600) may be disposed on the third insulating layer (103), and the wiring portion (116) may be named a pad portion in that it is coupled with the electronic element (500, 600). The pad portion (116) may include a first pad portion coupled with the first electronic element (500) and a second pad portion coupled with the second electronic element (600). The first pad portion and the second pad portion may each be arranged to overlap horizontally with the fourth wiring portion (114). The first electronic element (500) and the second electronic element (600) each include a pad (510, 610) coupled with the pad portion (116), and the pad (510, 610) may be soldered on the pad portion (116). The first electronic element (500) and the second electronic element (600) each have a height shorter than the vertical separation distance between the first build-up structure (100) and the second build-up structure (200) based on the vertical direction, and can be coupled on the first build-up structure (100).

[0064] In this case, a molding part (300) is disposed between the first build-up structure (100) and the second build-up structure (200), and a plurality of electronic elements (500, 600) can be embedded within the molding part (300). The molding part (300) has a vertical height equal to the vertical separation distance between the first build-up structure (100) and the second build-up structure (200), and can be disposed such that its side forms a plane with the side of the first build-up structure (100) and the side of the second build-up structure (200). Through the molding part (300), the connection between the plurality of electronic elements (500, 600) and the first build-up structure (100) can be firmly maintained.

[0065] The via may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via may be disposed within the via hole.

[0066] A plurality of vias of the first build-up structure (100) may include a first via (121) penetrating at least a portion of the first insulating layer (101), a second via (122) penetrating at least a portion of the second insulating layer (102), and a third via (123) penetrating at least a portion of the third insulating layer (103).

[0067] The first via (121) can electrically connect the first wiring section (111) and the second wiring section (112). The second via (122) can electrically connect the second wiring section (112) and the third wiring section (113). The third via (123) can electrically connect the third wiring section (113) and the fourth wiring section (114).

[0068] The first to third via sections (121, 122, 123) may each have a shape in which the horizontal width increases as it faces the second build-up structure (200). The vertical thickness of the third insulating layer (103) may be smaller than the vertical thickness of the first insulating layer (101) and / or the second insulating layer (102), and accordingly, the vertical length of the third via section (123) may be shorter than the vertical length of the first via section (121) and / or the second via section (122). Accordingly, the signal transmission length through the third via section (123) can be reduced.

[0069] The second build-up structure (200) can be placed on the first build-up structure (100).

[0070] The second build-up structure (200) may include a lower build-up structure (210) and an upper build-up structure (230). The lower build-up structure (210) and the upper build-up structure (230) may be arranged in a vertical direction. The lower build-up structure (210) may be placed on the first build-up structure (100). The upper build-up structure (230) may be placed on the lower build-up structure (210). The horizontal width of the upper build-up structure (230) may be smaller than the horizontal width of the lower build-up structure (210). Accordingly, a cavity (700) may be formed on the lower build-up structure (210). One area of ​​the lower build-up structure (210) may overlap vertically with the cavity (700), and another area of ​​the lower build-up structure (210) may overlap vertically with the upper build-up structure (230). A semiconductor chip (900, see FIG. 14) to be described later may be placed in the cavity (700).

[0071] The second build-up structure (200) may include a plurality of insulating layers, a plurality of wiring portions, and a plurality of via portions.

[0072] A plurality of insulating layers of the second build-up structure (200) may include a fourth insulating layer (211), a core layer (231) disposed on the fourth insulating layer (211), and a sixth insulating layer (232) disposed on the core layer (231). The fourth to sixth insulating layers (211, 231, 232) may be arranged in a vertical direction. The fourth insulating layer (211) may form a lower build-up structure (210). The core layer (231) and the sixth insulating layer (232) may form an upper build-up structure (230). Accordingly, the horizontal width of the fourth insulating layer (211) may be longer than the horizontal width of the core layer (231) and the sixth insulating layer (232), respectively.

[0073] The fourth to sixth insulating layers (211, 231, 232) may each be any insulating material, such as photocurable and / or thermosetting materials. As thermosetting insulating materials, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used as an example, and a prepreg (PPG) containing glass fibers within a resin may be used. Additionally, the resins mentioned above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. When the 4th to 6th insulating layers (211, 231, 232) are photocurable insulators, the 4th to 6th insulating layers (211, 231, 232) may each be a PID (Photo Imageable Dielectric).

[0074] The vertical length of the core layer (231) positioned in the vertical center may be longer than the vertical length of the fourth insulating layer (211) and / or the vertical length of the sixth insulating layer (232). Accordingly, bending of the second build-up structure (200) through the core layer (231) can be minimized.

[0075] The number of stacked insulating layers of the aforementioned second build-up structure (200) is exemplary, and the second build-up structure (200) may have more or fewer insulating layers arranged in the vertical direction.

[0076] The circuit board (10) may include a second protection layer (291) and a third protection layer (296). The second protection layer (291) may be placed on the lower surface of the fourth insulating layer (211). The second protection layer (291) may be placed between the first build-up structure (100) and the second build-up structure (200). The third protection layer (296) may be placed on the upper surface of the sixth insulating layer (232). When a semiconductor device is placed on the surface of the second build-up structure (200) using a material such as solder, the second protection layer (291) and the third protection layer (296) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent external contaminants from penetrating into the build-up structure and reducing reliability. The second protection layer (291) and the third protection layer (296) may each be solder resist.

[0077] The second build-up structure (200) may include a circuit pattern for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The circuit pattern may include a plurality of wiring portions and a plurality of via portions.

[0078] A plurality of wiring sections of the second build-up structure (200) may include a fifth wiring section (221) disposed on the lower surface of the fourth insulating layer (211), a sixth wiring section (222) disposed on the fourth insulating layer (211), a seventh wiring section (not shown) disposed on the core layer (231), and an eighth wiring section (not shown) disposed on the sixth insulating layer (232). The sixth wiring section (222), the seventh wiring section, and the eighth wiring section may each be embedded on the fourth insulating layer (211), the core layer (231), and the sixth insulating layer (232). The sixth to eighth wiring sections (222) may each be implemented on the upper surface of the fourth insulating layer (211), the core layer (231), and the sixth insulating layer (232) using an ETS (Embedded Technology Substrate) method.

[0079] The via portion of the second build-up structure (200) may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via portion may be disposed within the via hole.

[0080] A plurality of vias of the second build-up structure (200) may include a fourth via (224) penetrating at least a portion of the fourth insulating layer (211), a fifth via (not shown) penetrating at least a portion of the core layer (231), and a sixth via (not shown) penetrating at least a portion of the sixth insulating layer (232).

[0081] The fourth via (224) can electrically connect the fifth wiring section (221) and the sixth wiring section (222). The fifth via can electrically connect the sixth wiring section (222) and the seventh wiring section. The sixth via can electrically connect the seventh wiring section and the eighth wiring section.

[0082] The fourth to sixth via sections (224) may each have a shape in which the horizontal width increases as it faces the first build-up structure (100). The vertical thickness of the core layer (231) may be greater than the vertical thickness of the fourth insulating layer (211) and the sixth insulating layer (232). Accordingly, the vertical length of the fifth via section may be longer than the vertical length of the fourth via section (224) and the vertical length of the sixth via section.

[0083] The second build-up structure (200) may include a stepped portion. The stepped portion may be positioned on the side of the second build-up structure (200). The stepped portion may be an area where a part of the side of the second build-up structure (200) is stepped in a horizontal direction with respect to another part.

[0084] The stepped portion may include a trench (239). The trench (239) may be positioned at the bottom of the upper build-up structure (230). The trench (239) may be positioned in the connection area between the upper build-up structure (230) and the lower build-up structure (210). The trench (239) may be positioned on the side of the upper build-up structure (230) facing the cavity (700). The trench (239) may have a concave groove shape along the horizontal direction.

[0085] Referring to FIGS. 2 through 4, the trench (239) can be formed by the process of forming the cavity (700). Specifically, the process of forming the cavity (700) may include the process of removing the separation portion (650), which is the area for forming the cavity (700), from the upper structure (230A) after the release film (800) is placed between the upper structure (230A) and the lower build-up structure (210). Here, the separation portion (650) is an area of ​​the upper structure (230A) corresponding to the area for forming the cavity (700), and may be an area of ​​the upper structure (230A) excluding the upper build-up structure (230).

[0086] As illustrated in FIG. 3, the separation portion (650) can be removed through a slit-shaped separation area (236) formed between the separation portion (650) and the upper build-up structure (230). The separation area (236) may be an area where one portion of the upper build-up structure (230) has been removed by etching. The separation area (236) may be a through-hole shape penetrating from the upper surface to the lower surface of the upper build-up structure (230). During the removal process of the separation portion (650), a portion of the release film (800) is removed together with the separation portion (650), and the remaining portion may remain between the upper build-up structure (230) and the lower build-up structure (210) as illustrated in FIG. 4.

[0087] Accordingly, at the bottom of the upper build-up structure (230), a portion of the release film (800) may be placed in the trench (239) along with the trench (239). Here, the portion of the release film (800) placed in the trench (239) may be named an insulating layer (260). Since the insulating layer (260) corresponds to the release film (800), the material of the insulating layer (260) may be different from the material constituting the second build-up structure (200). The material of the insulating layer (260) may be different from the material constituting the core layer (231).

[0088] Due to the difference in hardening degree and rigidity between the core layer (231) and a plurality of insulating layers constituting the second build-up structure (200) and the release film (800), at least a portion of the insulating layer (260) placed in the trench (239) may protrude outward from the side of the core layer (231). In this case, the area protruding from the side of the core layer (231) in the insulating layer (260) may be named as an extension (262). Accordingly, the bonding strength between the lower build-up structure (210) and the upper build-up structure (230) may be further increased by increasing the contact area between the lower build-up structure (210) and the upper build-up structure (230) through the extension (262).

[0089] However, this is not limited to this, and the side of the insulating layer (260) placed in the trench (239) may be arranged to form a plane with the side of the core layer (231). Additionally, the insulating layer (260) may be omitted, in which case, as shown in FIGS. 7 and 8, only the groove-shaped trench (239), which is the separation area of ​​the release film (800), may be placed on the side of the core layer (231). As shown in FIGS. 7 and 8, when the insulating layer (260) is omitted due to the separation of the release film (800) from the trench (239), the stepped portion may have a groove shape that is concave inward compared to other areas. Accordingly, a sufficient horizontal separation distance between the side of the second build-up structure (200) and the semiconductor chip (900, see FIG. 14) can be secured, so that short circuits in the electrical connection area can be easily prevented.

[0090] According to the above structure, a cavity (700), which is a placement area for a semiconductor chip (900), can be formed on the lower build-up structure (210) so as to be aligned with a set area, and the semiconductor chip (900) placed in the cavity (700) can be placed so as to overlap horizontally with a heat dissipation member (250) to be described later.

[0091] FIG. 9 is a drawing illustrating another modified example of a structure for forming a step portion within a circuit board according to an embodiment of the present invention, and FIGS. 10 to 12 are drawings for explaining the process of forming a step portion within a circuit board according to FIG. 9.

[0092] Referring to FIG. 9, the second build-up structure (200) may include a stepped portion. The stepped portion may be positioned on the side of the second build-up structure (200). The stepped portion may be an area where a portion of the side of the second build-up structure (200) is stepped horizontally from another portion. In this variant, the aforementioned trench may be omitted, and the stepped portion may include a protrusion (265) in which a portion of the side of the upper build-up structure (230) protrudes horizontally more than another area. The protrusion (265) may be positioned in the connection area between the upper build-up structure (230) and the lower build-up structure (210). The protrusion (265) may be positioned on the lower part of the upper build-up structure (230). The protrusion (265) may be made of the same material as the core layer (231) constituting the second build-up structure (200).

[0093] Referring to FIGS. 10 to 12, the protrusion (265) can be formed by the process of forming the cavity (700). The process of forming the cavity (700) may include, as shown in FIG. 10, the removal of the separation portion (650), which is the area for forming the cavity (700), from the upper structure (230A) after the release film (800) is placed between the upper structure (230A) and the lower build-up structure (210). Here, the separation portion (650) is an area of ​​the upper structure (230A) corresponding to the area for forming the cavity (700), and may be an area of ​​the upper structure (230A) excluding the upper build-up structure (230).

[0094] As illustrated in FIG. 11, the separation portion (650) can be removed through a slit-shaped separation area (236) formed between the separation portion (650) and the upper build-up structure (230). The separation area (236) may be an area where one portion of the upper build-up structure (230) has been removed by etching. The separation area (236) may be a through-hole shape penetrating from the upper surface to the lower surface of the upper build-up structure (230). A portion of the separation area (236) may be positioned to overlap vertically with the release film (800), and another portion may be positioned to overlap vertically with the protrusion (265). That is, as a portion of the core layer (231) is removed during the formation process of the separation area (236), the protrusion (265) remains at the lower side of the core layer (231) and may overlap vertically with the separation area (236).

[0095] Afterwards, as illustrated in FIG. 12, during the removal process of the separation part (650), the release film (800) is separated from the side of the protrusion (265) together with the separation part (650), and the protrusion (265) can be positioned between the upper build-up structure (230) and the lower build-up structure (210).

[0096] Referring again to FIG. 1, the first build-up structure (100) and the second build-up structure (200) can be electrically and physically joined by a plurality of bonding parts (228, 170).

[0097] The first build-up structure (100) may include a first bonding portion (170) protruding toward the second build-up structure (200) on its upper surface. The first bonding portion (170) may have a metal post shape. The first bonding portion (170) may have a shape protruding upward from the upper surface of the fourth wiring portion (114). The horizontal width of the first bonding portion (170) may be shorter than the horizontal width of the fourth wiring portion (114). At least a portion of the first bonding portion (170) may be arranged to overlap horizontally with the first electronic element (500) and the second electronic element (600).

[0098] The second build-up structure (200) may include a second bonding portion (228) protruding toward the first build-up structure (100) on its lower surface. The second bonding portion (228) may have a metal post shape. The second bonding portion (228) may have a shape protruding downward from the lower surface of the fifth wiring portion (221). The horizontal width of the second bonding portion (228) may be shorter than the horizontal width of the fifth wiring portion (221). The horizontal width of the second bonding portion (228) may be the same as the horizontal width of the first bonding portion (170). The second bonding portion (228) and the first bonding portion (170) may each be provided in multiple numbers and arranged to overlap each other in a vertical direction. The second bonding portion (228) may be arranged such that at least a portion overlaps the first electronic element (500) and the second electronic element (600) in a horizontal direction.

[0099] Between the first bonding part (170) and the second bonding part (228), a connecting part (410) that electrically and physically connects the first bonding part (170) and the second bonding part (228) may be disposed. The connecting part (410) has a circular or elliptical ball shape and may be an area formed by soldering between the first bonding part (170) and the second bonding part (228).

[0100] The first bonding part (170), the second bonding part (228), and the connecting part (410) can be embedded within the aforementioned molding part (300), and accordingly, the connection between the first build-up structure (100) and the second build-up structure (200) can be firmly maintained.

[0101] The vertical length of the first bonding part (170) and the vertical length of the second bonding part (270) may be equal to each other. The vertical length (H1) between the upper surface of the first bonding part (170) and the upper surface of the first build-up structure (100) may be equal to the vertical length (H2) between the lower surface of the second bonding part (228) and the lower surface of the second build-up structure (200). The space between the upper surface of the first bonding part (170) and the lower surface of the second bonding part (228), that is, the placement space of the connecting part (410), may be located at the center of the vertical length between the upper surface of the first build-up structure (100) and the lower surface of the second build-up structure (200). The connecting part (410) may be arranged to overlap horizontally with a plurality of electronic elements (500, 600).

[0102] Accordingly, stress can be uniformly distributed in the electrical coupling area between multiple build-up structures, and since the space for arranging the first electronic element (500) and the second electronic element (600) is determined by the lengths of the multiple bonding parts (170, 228), there is ease in designing the circuit board (10).

[0103] As a variation, the vertical length of the first bonding part (170) and the vertical length of the second bonding part (228) may be different from each other. For example, the vertical length of the first bonding part (170) may be shorter than the vertical length of the second bonding part (228). Accordingly, the length of the second bonding part (228) positioned in the vertical direction is formed to be relatively short, so that the focusing process with the first bonding part (170) can be easily performed.

[0104] In another variation, the vertical length of the first bonding part (170) may be longer than the vertical length of the second bonding part (228). In this case, there is an advantage to the design that a space for arranging multiple electronic elements (500, 600) can be designed around the length of the second bonding part (228).

[0105] FIG. 13 is a drawing illustrating a modified example of a combined structure of a first build-up structure and a second build-up structure according to an embodiment of the present invention.

[0106] Referring to FIG. 13, a plurality of bonding portions may be omitted in the above-described embodiment. In this case, a connecting portion (460), which is an area formed by soldering, may be disposed between the first build-up structure (100) and the second build-up structure (200). The lower end of the connecting portion (460) may be in contact with the third wiring portion (113), and the upper end may be in contact with the fourth wiring portion (221). However, to reinforce the strength of the connecting portion (460) by increasing the vertical length of the connecting portion (460), a reinforcing portion (450) having a ball shape may be disposed in the center of the connecting portion (460). The reinforcing portion (460) may be formed of a metal material and may be embedded within the connecting portion (460).

[0107] The circuit board (10) may include a heat dissipation member (250). The heat dissipation member (250) may be placed in the second build-up structure (200). The heat dissipation member (250) may be placed within the upper build-up structure (230). The heat dissipation member (250) may be placed in the core layer (231). The core layer (231) may include a through hole (235) that penetrates from one side to the other side and is the placement area of ​​the heat dissipation member (250). The horizontal width of the through hole (235) may be greater than the horizontal width of the heat dissipation member (250). Accordingly, when the heat dissipation member (250) is coupled within the through hole (235), a molding area for embedding the heat dissipation member (250) within the through hole (235) may be placed.

[0108] The upper surface of the heat dissipation member (250) may be arranged to form a plane identical to the upper surface of the core layer (231), and the lower surface of the heat dissipation member (250) may be arranged to form a plane identical to the lower surface of the core layer (231). The upper surface of the heat dissipation member (250) may be in contact with the lower surface of the sixth insulating layer (232), and the lower surface of the heat dissipation member (250) may be in contact with the upper surface of the fourth insulating layer (211).

[0109] Heat generated by the operation of a plurality of electronic elements (500, 600) placed in the first build-up structure (100) can be efficiently dissipated through the heat dissipation member (250).

[0110] The second build-up structure (200) may include a plurality of heat dissipation vias connected to a heat dissipation member (250). The plurality of heat dissipation vias may include a first heat dissipation via (255) that penetrates at least a portion of the fourth insulating layer (211) and is connected to the lower surface of the heat dissipation member (250). The plurality of heat dissipation vias may include a second heat dissipation via (253) that penetrates at least a portion of the sixth insulating layer (232) and is connected to the upper surface of the heat dissipation member (250). A first metal layer (254) connected to the first heat dissipation via (255) may be disposed on the lower surface of the fourth insulating layer (211). A second metal layer (252) connected to the second heat dissipation via (253) may be disposed on the upper surface of the sixth insulating layer (232). The first metal layer (254) and the second metal layer (252) may have the shape of a metal plate having a predetermined thickness in the vertical direction. The horizontal width of each of the first metal layer (254) and the second metal layer (252) may be longer than the horizontal width of the heat dissipation member (250).

[0111] Accordingly, heat generated from a plurality of electronic elements (500, 600) or heat of the heat dissipation member (250) itself can be efficiently dispersed through a plurality of heat dissipation vias (255, 253) and a plurality of metal layers (254, 252), thereby improving heat dissipation efficiency.

[0112] As illustrated in FIG. 5, a plurality of heat dissipation vias (255, 253) may each have a circular cross-sectional shape. The first heat dissipation via (255) may have a shape in which the horizontal width gradually decreases as it faces the heat dissipation member (250). The second heat dissipation via (253) may have a shape in which the horizontal width gradually decreases as it faces the heat dissipation member (250). Accordingly, heat through the plurality of heat dissipation vias (255, 253) can be uniformly distributed in the upper build-up structure (230).

[0113] As a variation example, as shown in FIG. 6, a plurality of heat dissipation vias (255, 253) may each have a plate shape having a predetermined length in a first direction which is a horizontal direction. A plurality of heat dissipation vias (255, 253) may each be arranged along a second direction which is a horizontal direction and perpendicular to the first direction. A plurality of heat dissipation vias (255, 253) may each have regions with different lengths in the first direction. A plurality of heat dissipation vias (255, 253) may have a bar shape in cross-section. Accordingly, heat dissipation efficiency can be improved by increasing the surface area of ​​the plurality of heat dissipation vias (255, 253) themselves.

[0114] FIG. 14 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0115] Referring to FIG. 14, a semiconductor chip (900) may be disposed in a cavity (700) formed on a circuit board (10). For example, the semiconductor chip (900) may be a memory chip.

[0116] A semiconductor chip (900) may include a plurality of insulating layers (910), a wiring portion (920) disposed on the surface of each of the plurality of insulating layers (910), and a via portion (930) that connects the plurality of wiring portions (920) in a vertical direction and penetrates each of the plurality of insulating layers (910). A protective layer (990) may be disposed on the lower and upper surfaces of each of the plurality of insulating layers (910) to perform the function of preventing short circuits between solders.

[0117] Additionally, among the plurality of insulating layers (910), the lower surface of the insulating layer (910) facing the upper surface of the fourth insulating layer (211) constituting the lower build-up structure (210) may be exposed downward through a hole in the protective layer (990) and connected to the sixth wiring portion (222). The wiring portion of the semiconductor chip (990) may be soldered onto the sixth wiring portion (222).

[0118] A core (950) of a semiconductor chip (900) is disposed on a plurality of insulating layers (910), and the core (950) can be electrically connected to a wiring portion disposed on the plurality of insulating layers (910) through a wire (952). The core (950) can be disposed to overlap horizontally with a heat dissipation member (250).

[0119] A molding portion (980) is disposed on a plurality of insulating layers (910), and the core (950) can be embedded in the molding portion (980). Accordingly, the core (950) and the wire (952) can be firmly fixed on the plurality of insulating layers (910).

[0120] The semiconductor chip (900) may be spaced horizontally apart from the side of the upper build-up structure (230), but is not limited thereto, and the side of the semiconductor chip (900) may be connected to the side of the upper build-up structure (230) by the molding part (980).

[0121] Heat generated by the operation of the semiconductor chip (900) can be dissipated through the heat dissipation member (250).

[0122] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0123] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0124] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0125] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. First build-up structure; and It includes a second build-up structure disposed on the first build-up structure, and The second build-up structure comprises a lower build-up structure and an upper build-up structure disposed on the lower build-up structure and having a horizontal width smaller than the horizontal width of the lower build-up structure. The above upper build-up structure is provided at the bottom and is a circuit board including a concave step portion along the horizontal direction.

2. In Paragraph 1, It includes an insulating layer disposed on the above-mentioned stepped portion, and The above insulating layer is a circuit board that is a different material from the material constituting the second build-up structure.

3. In Paragraph 1, The first build-up structure includes a first bonding portion protruding toward the second build-up structure on its upper surface, and The above second build-up structure is a circuit board including a second bonding portion protruding toward the first build-up structure on the lower surface.

4. In Paragraph 3, A circuit board in which the vertical length of the first bonding part and the vertical length of the second bonding part are the same.

5. In Paragraph 4, A circuit board in which the vertical length between the upper surface of the first bonding part and the upper surface of the first build-up structure is the same as the vertical length between the lower surface of the second bonding part and the lower surface of the second build-up structure.

6. In Paragraph 4, The gap between the upper surface of the first bonding part and the lower surface of the second bonding part is a circuit board located at the center of the vertical length between the upper surface of the first build-up structure and the lower surface of the second build-up structure.

7. In Paragraph 6, A circuit board comprising a connecting portion disposed in the spaced-apart space between the upper surface of the first bonding portion and the lower surface of the second bonding portion.

8. In Paragraph 3, A circuit board in which the vertical length of the first bonding part and the vertical length of the second bonding part are different.

9. In Paragraph 2, The upper build-up structure comprises a core layer and an insulating layer disposed on the core layer, and The above step portion is a circuit board disposed below the core layer.

10. In Paragraph 9, The above insulating layer is a circuit board including an extension portion protruding outwardly from the side of the core layer of the upper build-up structure.

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