Low-power complementary metal-oxide semiconductor inverter
By configuring CMOS inverters with transistors having varying threshold voltages and oxide thicknesses, the issue of excessive current consumption is addressed, allowing stable operation in energy-constrained settings for low-power circuits.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- DONGGUK UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
- Filing Date
- 2025-12-18
- Publication Date
- 2026-06-25
AI Technical Summary
Conventional CMOS inverters experience large charge/discharge and short circuit currents due to simultaneous switching of PMOS and NMOS transistors, consuming excessive current during signal transitions.
Designing CMOS inverters with transistors having threshold voltages that differ in magnitude, connecting gates and sources of specific transistors to operate below or above threshold voltages, and using thick and thin oxide transistors to minimize current consumption.
The solution results in minimal current consumption, enabling stable logic signal processing with CMOS inverters even in energy-limited environments, suitable for low-power circuits in wireless sensor networks.
Smart Images
Figure KR2025022187_25062026_PF_FP_ABST
Abstract
Description
Low-power complementary metal-oxide-semiconductor inverter
[0001] The present invention relates to a Complementary Metal-Oxide Semiconductor (CMOS) inverter, and more specifically, to a low-power CMOS inverter.
[0002]
[0003] Ambient RF energy harvesters supply power to wireless sensor networks.
[0004] Generally, ambient RF energy harvesters can supply very little energy, less than tens of uJ.
[0005] The low-power circuit can operate by consuming very small currents at the pA level and receiving energy harvested by the ambient RF energy harvester.
[0006] Therefore, low-power circuits are receiving a lot of attention as wireless sensor network technology has recently advanced.
[0007] Among electronic circuits, a CMOS inverter inverts an input signal and outputs it. The CMOS inverter is the most basic gate that constitutes a digital integrated circuit.
[0008] Generally, a CMOS inverter consists of a PMOS transistor connected between the power supply and the output port, and an NMOS transistor connected between the output port and ground. Here, the PMOS transistor refers to a P-type metal-oxide-semiconductor transistor, and the NMOS transistor refers to an N-type metal-oxide-semiconductor transistor.
[0009] Generally, the input port of a CMOS inverter is connected in common to the gates of the PMOS transistor and the NMOS transistor so that the two transistors can be turned on simultaneously when the input signal is near the switching threshold of the transistors.
[0010] As a result, conventional CMOS inverters have a problem in that very large charge / discharge and short circuit currents flow during the short time when input / output signals cross each other.
[0011] To solve these problems, it is necessary to provide a low-power CMOS inverter that consumes very little current at all times.
[0012] The background technology of the present invention is disclosed in Korean Registered Patent No. 10-2034903.
[0013]
[0014] The present invention provides a low-power CMOS inverter that consumes very little current at all times.
[0015] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the present invention belongs from the description below.
[0016]
[0017] According to one aspect of the present invention, a low-power CMOS inverter is provided.
[0018] A low-power CMOS inverter according to one embodiment of the present invention includes a PMOS transistor and an NMOS transistor, wherein the PMOS transistor is connected between a power supply and an output port, the NMOS transistor is connected between an output port and ground, and the gate and source of either the PMOS transistor or the NMOS transistor are connected to each other so that it can operate in a region below a threshold voltage at all times.
[0019] Another low-power CMOS inverter according to one embodiment of the present invention comprises two NMOS transistors, wherein the two NMOS transistors comprise a third NMOS transistor and a fourth NMOS transistor, wherein the third NMOS transistor is connected between a power supply and an output port, and the fourth NMOS transistor is connected between an output port and ground, and wherein the gate, source, and body of the third NMOS transistor are connected to each other, and the input port is connected to the gate of the fourth NMOS transistor, and wherein the magnitude of the threshold voltage of the fourth NMOS transistor is relatively larger than the magnitude of the threshold voltage of the third NMOS transistor.
[0020] Another low-power CMOS inverter according to one embodiment of the present invention comprises two PMOS transistors, wherein the two PMOS transistors comprise a third PMOS transistor and a fourth PMOS transistor, wherein the third PMOS transistor is connected between a power source and an output port, the fourth PMOS transistor is connected between an output port and ground, the gate, source, and body of the fourth PMOS transistor are connected to each other, the input port is connected to the gate of the third PMOS transistor, and the magnitude of the threshold voltage of the third PMOS transistor is relatively larger than the magnitude of the threshold voltage of the fourth PMOS transistor.
[0021]
[0022] According to one embodiment of the present invention, the present invention can be used as one of the constituent blocks of a low-power circuit that operates by receiving very small energy of tens of uJ or less harvested by an ambient RF energy harvester without a separate battery.
[0023] According to one embodiment of the present invention, the present invention can be used as one of the constituent blocks of various low-power circuits by consuming very little current at all times.
[0024] The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the composition of the invention described in the description or claims of the present invention.
[0025]
[0026] FIGS. 1 to 4 are drawings for explaining a low-power CMOS inverter structure according to an embodiment of the present invention.
[0027] FIGS. 5 to 8 are drawings showing the results of simulating the input / output characteristics of a low-power CMOS inverter according to an embodiment of the present invention.
[0028] FIGS. 9 to 12 are drawings showing waveforms simulating input and output signals of a low-power CMOS inverter according to an embodiment of the present invention.
[0029]
[0030] The present invention is susceptible to various modifications and may have various embodiments; therefore, specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the present invention to specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. In describing the present invention, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may unnecessarily obscure the essence of the invention. Furthermore, singular expressions used in this specification and claims should generally be interpreted as meaning "one or more" unless otherwise stated.
[0031] Throughout the specification, when it is stated that a part is "connected (connected, in contact, combined)" with another part, this includes not only cases where they are "directly connected," but also cases where they are "indirectly connected" with other members interposed between them. Furthermore, when it is stated that a part "includes" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but rather allows for the inclusion of additional components.
[0032] The terms used herein are merely for describing specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “comprising” or “having” are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.
[0033] The present invention will be described below with reference to the attached drawings. However, the present invention may be implemented in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification have been given similar reference numerals.
[0034]
[0035] The present invention relates to a Complementary Metal-Oxide Semiconductor (CMOS) inverter.
[0036] FIGS. 1 to 4 are drawings for explaining a low-power CMOS inverter structure according to an embodiment of the present invention.
[0037] Referring to FIGS. 1 and 2, the low-power CMOS inverter includes a PMOS transistor and an NMOS transistor, wherein the PMOS transistor is connected between a power supply and an output port, the NMOS transistor is connected between an output port and ground, and the gate and source of either the PMOS transistor or the NMOS transistor are connected to each other so that it can operate in a region below a threshold voltage at all times.
[0038] For example, the PMOS transistor of a low-power CMOS inverter may be characterized in that its gate and source are connected to each other, its input port is connected to the gate of an NMOS transistor, and the magnitude of the threshold voltage of the NMOS transistor is relatively larger than the magnitude of the threshold voltage of the PMOS transistor.
[0039] For example, the NMOS transistor of a low-power CMOS inverter may be characterized in that its gate and source are connected to each other, its input port is connected to the gate of a PMOS transistor, and the threshold voltage of the PMOS transistor is relatively larger than the threshold voltage of the NMOS transistor.
[0040]
[0041] Referring to FIG. 1, a low-power CMOS inverter according to one embodiment of the present invention includes a first PMOS transistor (130) and a first NMOS transistor (140).
[0042] The first PMOS transistor (130) is connected between the power supply and the output port, and the first NMOS transistor (140) is connected between the output port and ground.
[0043] The first PMOS transistor (130) has its gate and source connected to each other, and its input port is connected to the gate of the first NMOS transistor (140).
[0044] The threshold voltage of the first NMOS transistor (140) is characterized by being relatively larger than the threshold voltage of the first PMOS transistor (130).
[0045] Referring to Fig. 1, is power supply voltage, is the input voltage and represents the output voltage.
[0046]
[0047] Referring to FIG. 2, another low-power CMOS inverter according to one embodiment of the present invention includes a second PMOS transistor (150) and a second NMOS transistor (160).
[0048] The second PMOS transistor (150) is connected between the power supply and the output port, and the second NMOS transistor (160) is connected between the output port and ground.
[0049] The second NMOS transistor (160) has its gate and source connected to each other, and its input port is connected to the gate of the second PMOS transistor (150).
[0050] The threshold voltage of the second PMOS transistor (150) is characterized by being relatively larger than the threshold voltage of the second NMOS transistor (160).
[0051] Referring to Fig. 2, is power supply voltage, is the input voltage and represents the output voltage.
[0052]
[0053] Referring to FIG. 3, another low-power CMOS inverter according to one embodiment of the present invention includes a third NMOS transistor (230) and a fourth NMOS transistor (240).
[0054] The third NMOS transistor (230) is connected between the power supply and the output port, and the fourth NMOS transistor (240) is connected between the output port and ground.
[0055] The gate, source, and body of the third NMOS transistor (230) are connected to each other, and the input port is connected to the gate of the fourth NMOS transistor (240).
[0056] At this time, the threshold voltage of the fourth NMOS transistor (240) is characterized by being relatively larger than the threshold voltage of the third NMOS transistor (230).
[0057] Referring to Fig. 3, is power supply voltage, is the input voltage and represents the output voltage.
[0058]
[0059] Referring to FIG. 4, another low-power CMOS inverter according to one embodiment of the present invention includes a third PMOS transistor (250) and a fourth PMOS transistor (260).
[0060] The third PMOS transistor (250) is connected between the power supply and the output port, and the fourth PMOS transistor (260) is connected between the output port and ground.
[0061] The gate, source, and body of the fourth PMOS transistor (260) are connected to each other, and the input port is connected to the gate of the third PMOS transistor (250).
[0062] At this time, the threshold voltage of the third PMOS transistor (250) is characterized by being relatively larger than the threshold voltage of the fourth PMOS transistor (260).
[0063] Referring to Fig. 4, is power supply voltage, is the input voltage and represents the output voltage.
[0064]
[0065] FIGS. 5 to 8 are drawings showing the results of simulating the input / output characteristics of a low-power CMOS inverter according to one embodiment of the present invention.
[0066] Figure 5 is the result of simulating the input / output characteristics of a low-power CMOS inverter according to one embodiment of the present invention shown in Figure 1.
[0067] Referring to Fig. 5, the horizontal axis represents the input voltage ( ), the vertical axis is the output voltage ( It means ).
[0068] The simulation of the present invention is the power supply voltage ( Apply 0.9V to ).
[0069] Referring to FIG. 5, the low-power CMOS inverter has an input voltage ( When this is lower than the switching point, much less current must flow into the first NMOS transistor (140) than the current that must flow into the first PMOS transistor (130) where the gate and source are connected.
[0070] To do so, the low-power CMOS inverter must be designed with devices in which the threshold voltage of the first NMOS transistor (140) has a value relatively larger than the threshold voltage of the first PMOS transistor (130).
[0071] For example, the first NMOS transistor (140) can be designed as a thick oxide transistor for an input / output circuit (I / O) with a high threshold voltage, and the first PMOS transistor (130) can be designed as a thin oxide transistor for a core with a low threshold voltage.
[0072] In addition, the switching point increases as the threshold voltage of the first NMOS transistor (140) increases, so there is an advantage that the switching point becomes more ideally close to half of the power supply voltage.
[0073]
[0074] Figure 6 is the result of simulating the input / output characteristics of another low-power CMOS inverter according to one embodiment of the present invention shown in Figure 2.
[0075] Referring to Fig. 6, the horizontal axis represents the input voltage ( ), the vertical axis is the output voltage ( It means ).
[0076] The simulation of the present invention is the power supply voltage ( ) Apply 0.9V.
[0077] Referring to Fig. 6, the low-power CMOS inverter has an input voltage ( When ) is higher than the switching point, much less current must flow into the second PMOS transistor (150) than the current that must flow into the second NMOS transistor (160) where the gate and source are connected.
[0078] To do so, the low-power CMOS inverter must be designed with devices in which the threshold voltage of the second PMOS transistor (150) has a value relatively larger than the threshold voltage of the second NMOS transistor (160).
[0079] For example, the second PMOS transistor (150) can be designed as a thick oxide transistor for an input / output circuit (I / O) with a high threshold voltage, and the second NMOS transistor (160) can be designed as a thin oxide transistor for a core with a low threshold voltage.
[0080] In addition, since the switching point is lower as the threshold voltage of the second PMOS transistor (150) increases, there is an advantage that the switching point becomes more ideally close to half of the power supply voltage.
[0081]
[0082] FIG. 7 is a diagram showing the results of simulating the input / output characteristics of another low-power CMOS inverter according to one embodiment of the present invention illustrated in FIG. 3.
[0083] Referring to Fig. 7, the horizontal axis of the simulation result graph is the input voltage ( ), the vertical axis is the output voltage ( It means ).
[0084] The simulation of the present invention is the power supply voltage ( Apply 1V to ).
[0085] A low-power CMOS inverter comprising two transistors (230, 240) according to one embodiment of the present invention has an input voltage ( When this is lower than the switching point, much less current must flow through the fourth NMOS transistor (240) than the current flowing through the third NMOS transistor (230) in which the gate, source, and body are connected to each other.
[0086] To do so, a low-power CMOS inverter including two transistors (230, 240) must be designed with devices in which the threshold voltage of the fourth NMOS transistor (240) has a value relatively larger than the threshold voltage of the third NMOS transistor (230).
[0087] For example, the fourth NMOS transistor (240) can be designed as a thick oxide transistor for an input / output circuit (I / O) with a high threshold voltage, and the third NMOS transistor (230) can be designed as a thin oxide transistor for a core with a low threshold voltage.
[0088] In addition, a low-power CMOS inverter including two transistors (230, 240) has the advantage that the switching point becomes higher as the threshold voltage of the fourth NMOS transistor (240) increases, so the switching point becomes more ideally close to half of the power supply voltage.
[0089]
[0090] FIG. 8 is a diagram showing the results of simulating the input / output characteristics of another low-power CMOS inverter according to one embodiment of the present invention illustrated in FIG. 4.
[0091] Referring to Fig. 8, the horizontal axis of the simulation result graph is the input voltage ( ), the vertical axis is the output voltage ( It means ).
[0092] The simulation of the present invention is the power supply voltage ( Apply 1V to ).
[0093] A low-power CMOS inverter comprising two transistors (250, 260) according to one embodiment of the present invention has an input voltage ( When ) is higher than the switching point, much less current must flow in the third PMOS transistor (250) than in the fourth PMOS transistor (260) in which the gate, source, and body are connected to each other.
[0094] To do so, a low-power CMOS inverter including two transistors (250, 260) must be designed with devices in which the threshold voltage of the third PMOS transistor (250) has a value relatively larger than the threshold voltage of the fourth PMOS transistor (260).
[0095] For example, the third PMOS transistor (250) can be designed as a thick oxide transistor for a high input / output circuit (I / O), and the fourth PMOS transistor (260) can be designed as a thin oxide transistor for a core with a low threshold voltage.
[0096] In addition, a low-power CMOS inverter including two transistors (250, 260) has the advantage that the switching point becomes lower as the threshold voltage of the third PMOS transistor (250) increases, so the switching point becomes more ideally close to half of the power supply voltage.
[0097]
[0098] FIGS. 9 to 12 are drawings showing waveforms simulating input and output signals of a low-power CMOS inverter according to an embodiment of the present invention.
[0099] FIG. 9 is a diagram of a waveform simulating the input / output signal of a low-power CMOS inverter according to one embodiment of the present invention shown in FIG. 1.
[0100] Referring to Fig. 9, the horizontal axis of the simulation graph is time, and the vertical axis is voltage, is the input voltage and represents the output voltage.
[0101] As confirmed in Figure 5, the input signal is inverted around a switching point of approximately 0.15V and output correctly.
[0102] At this time, the simulated maximum consumption current is 50 pA or less.
[0103]
[0104] FIG. 10 is a diagram of waveforms simulating input and output signals of another low-power CMOS inverter according to an embodiment of the present invention illustrated in FIG. 2.
[0105] Referring to Fig. 10, the horizontal axis of the simulation graph is time, and the vertical axis is voltage, is the input voltage and represents the output voltage.
[0106] As confirmed in Figure 6, the input signal is inverted around a switching point of approximately 0.7V and output correctly.
[0107] At this time, the simulated maximum consumption current is 50 pA or less.
[0108]
[0109] FIG. 11 is a diagram of waveforms simulating input and output signals of another low-power CMOS inverter according to one embodiment of the present invention shown in FIG. 3.
[0110] Referring to Fig. 11, the horizontal axis of the simulation graph is time, and the vertical axis is voltage, is the input voltage and represents the output voltage.
[0111] As confirmed in Fig. 7, the input signal is inverted around a switching point of approximately 0.3V and output correctly.
[0112] At this time, the simulated maximum consumption current is 50 pA or less.
[0113]
[0114] FIG. 12 is a diagram of waveforms simulating input and output signals of another low-power CMOS inverter according to one embodiment of the present invention shown in FIG. 4.
[0115] Referring to Fig. 12, the horizontal axis of the simulation graph is time, and the vertical axis is voltage, is the input voltage and represents the output voltage.
[0116] As confirmed in Fig. 8, the input signal is inverted around a switching point of approximately 0.7V and output correctly.
[0117] At this time, the simulated maximum consumption current is 50 pA or less.
[0118]
[0119] Although it has been described above that all components constituting an embodiment of the present invention are combined or operate as a single unit, the present invention is not necessarily limited to such an embodiment. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate.
[0120] The present invention has been described above with reference to its embodiments. Those skilled in the art will understand that the present invention may be embodied in modified forms without departing from the essential characteristics of the invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the invention is defined by the claims, not by the foregoing description, and all variations within the scope of the claims should be interpreted as being included in the invention.
[0121]
[0122] The modes for carrying out the invention are described together in the best mode for carrying out the invention above.
[0123]
[0124] The present invention relates to a low-power complementary metal-oxide semiconductor (CMOS) inverter, and more specifically, to a CMOS inverter that minimizes constant current consumption. Since stable logic signal processing is possible even in an environment with extremely limited energy sources, it can be used in various ways throughout the semiconductor and electronic circuit industries, thus having industrial applicability.
Claims
1. In a low-power CMOS inverter, Includes a first PMOS transistor and a first NMOS transistor, The first PMOS transistor is connected between the power supply and the output port, and The first NMOS transistor is connected between the output port and ground, and The first PMOS transistor has its gate and source connected to each other, and The input port is a low-power CMOS inverter connected to the gate of the first NMOS transistor.
2. In Paragraph 1, A low-power CMOS inverter characterized in that the magnitude of the threshold voltage of the first NMOS transistor is relatively larger than the magnitude of the threshold voltage of the first PMOS transistor.
3. In a low-power CMOS inverter, It includes a second PMOS transistor and a second NMOS transistor, The second PMOS transistor is connected between the power supply and the output port, and The second NMOS transistor is connected between the output port and ground, and The gate and source of the second NMOS transistor are connected to each other, and The input port is a low-power CMOS inverter connected to the gate of the second PMOS transistor.
4. In Paragraph 3, A low-power CMOS inverter characterized in that the magnitude of the threshold voltage of the second PMOS transistor is relatively larger than the magnitude of the threshold voltage of the second NMOS transistor.
5. In a low-power CMOS inverter, It includes two NMOS transistors, but, The two NMOS transistors mentioned above include a third NMOS transistor and a fourth NMOS transistor, and The above third NMOS transistor is connected between the power supply and the output port, and The above-mentioned fourth NMOS transistor is connected between the output port and ground, and The gate, source, and body of the third NMOS transistor are connected to each other, and The input port is a low-power CMOS inverter connected to the gate of the fourth NMOS transistor.
6. In Paragraph 5, A low-power CMOS inverter characterized in that the magnitude of the threshold voltage of the fourth NMOS transistor is relatively larger than the magnitude of the threshold voltage of the third NMOS transistor.
7. In a low-power CMOS inverter, It includes two PMOS transistors, The two PMOS transistors mentioned above include a third PMOS transistor and a fourth PMOS transistor, and The above third PMOS transistor is connected between the power supply and the output port, and The above-mentioned fourth PMOS transistor is connected between the output port and ground, and The gate, source, and body of the above-mentioned fourth PMOS transistor are connected to each other, and The input port is a low-power CMOS inverter connected to the gate of the third PMOS transistor.
8. In Paragraph 7, A low-power CMOS inverter characterized in that the magnitude of the threshold voltage of the third PMOS transistor is relatively larger than the magnitude of the threshold voltage of the fourth PMOS transistor.