Superconductive multilayer circuit boards for quantum computing systems

Abstract

In a general aspect, a multilayer board structure is used to mechanically support and electrically connect a quantum processing unit. In some aspects, a multilayer board structure includes a stack of printed circuit boards. Each printed circuit board in the stack includes a dielectric substrate, a copper layer on a surface of the dielectric substrate; and a superconductive layer electroplated on a surface of the copper layer such that the copper layer is sandwiched between the superconductive layer and the dielectric substrate.

Description

Attorney Docket No.: RIGET-133WO1Superconductive Multilayer Circuit Boards for Quantum Computing SystemsTECHNICAL FIELD

[0001] The following description relates to superconductive multilayer circuit boards for quantum computing systems.BACKGROUND

[0002] Quantum computers can perform computational tasks by storing and processing information within quantum states of quantum systems. For example, qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system. A variety of physical systems have been proposed for quantum computing applications. Examples include superconductive circuits, trapped ions, spin systems and others.BRIEF DESCRIPTION OF THE DRAWINGS

[0003] FIG. 1 is a block diagram of an example computing environment.

[0004] FIG. 2 is a diagram showing aspects of an example cryostat in a quantum computing system.

[0005] FIGS. 3A-3B are schematic diagrams showing a cross-sectional view of an example superconductive multilayer circuit board.

[0006] FIG. 4 is a flow chart showing aspects of an example process.DETAILED DESCRIPTION

[0007] In some example quantum computing systems, electromagnetic signals (e.g., radio or microwave frequency signals) are used to control and read qubit devices in a quantum processing unit or other types of system components of a quantum computing system. These signals can be routed from controller and signal hardware to the quantum processing unit through a superconductive multilayer circuit board structure. In some aspects of what is described here, a superconductive multilayer board structure is a Stack-Attorney Docket No.: RIGET-133WO1 up of multiple printed circuit boards (PCBs) which include multiple core layers laminated and bonded on one another through multiple composite layers. Each core layer includes a dielectric substrate on which a multilayer metallization is formed. In some instances, the multilayer metallization on the dielectric substrate includes two or more distinct metal layers stacked on one another to optimize electrical performance and thermal management for superconductive quantum processing units operating in a cryogenic environment. In some instances, the multilayer metallization includes a conductive layer of metallic copper or copper alloy; and a superconductive layer which shows superconductivity at a cryogenic temperature. In some instances, a conductive layer of a dielectric substrate in a respective core layer of the superconductive multilayer circuit board may be patterned according to the function of the respective core layer (e.g., for signal routing or as a ground plane]; and a superconductive layer can be plated on the patterned conductive layer. In certain examples, the superconductive layer may include metallic tin (Sn), metallic ruthenium (Ru), metallic rhenium (Re), or another superconductive metal. In some instances, the multilayer board structure, which is configured to support one or more quantum processing units, can be mechanically supported on and thermally anchored to a thermalization stage of a cryostat in a quantum computing system and electrically connected to an external control system outside the cryostat through communication links.

[0008] In some cases, the systems and methods described here can be used to address challenges introduced by the growth in the number of qubits in a quantum computing system. For example, in some instances, the systems and techniques presented here may reduce the joule heating of the non-superconductive components at a mixing chamber (MXC) stage which has a low cooling capacity, reduce the heating budget for signal lines, and allow more signal lines as the number of qubits scales. In some cases, the systems and techniques presented here may reduce settling time in the return path of the circuit boards and reduce return current asymmetry. In some cases, the systems and techniques presented here may reduce the effect of the thermal state of the PCBs on the quantum processing units and reduce the dephasing of the qubits. Other advantages and improvements may be achieved in some cases.Attorney Docket No.: RIGET-133WO1

[0009] FIG. 1 is a block diagram of an example computing environment 100. The example computing environment 100 shown in FIG. 1 includes a computing system 101 and user devices 110A, 110B, HOC. A computing environment may include additional or different features, and the components of a computing environment may operate as described with respect to FIG. 1 or in another manner.

[0010] The example computing system 101 includes classical and quantum computing resources and exposes their functionality to the user devices 110A, 110B, 110C (referred to collectively as "user devices 110”). The computing system 101 shown in FIG. 1 includes one or more servers 108, quantum computing systems 103A, 103B, a local network 109 and other resources 107. The computing system 101 may also include one or more user devices (e.g., the user device 110A) as well as other features and components. A computing system may include additional or different features, and the components of a computing system may operate as described with respect to FIG. 1 or in another manner.

[0011] The example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computer system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner. The computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115, the local network 109 or otherwise).

[0012] The user devices 110 shown in FIG. 1 may include one or more classical processors, memory, user interfaces, communication interfaces, and other components. For instance, the user devices 110 may be implemented as laptop computers, desktop computers, smartphones, tablets, or other types of computer devices. In the example shown in FIG. 1, to access computing resources of the computing system 101, the user devices 110 send information (e.g., programs, instructions, commands, requests, input data, etc.) to the servers 108; and in response, the user devices 110 receive information (e.g., application data, output data, prompts, alerts, notifications, results, etc.) from the servers 108. The user devices 110 may access services of the computing system 101 in anotherAttorney Docket No.: RIGET-133WO1 manner, and the computing system 101 may expose computing resources in another manner.

[0013] In the example shown in FIG. 1, the local user device 110A operates in a local environment with the servers 108 and other elements of the computing system 101. For instance, the user device 110A may be co-located with (e.g., located within 0.5 to 1 km of) the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, the user device 110A communicates with the servers 108 through a local data connection.

[0014] The local data connection in FIG. 1 is provided by the local network 109. For example, some or all of the servers 108, the user device 110A, the quantum computing systems 103A, 103B and the other resources 107 may communicate with each other through the local network 109. In some implementations, the local network 109 operates as a communication channel that provides one or more low-latency communication pathways from the server 108 to the quantum computer systems 103A, 103B (or to one or more of the elements of the quantum computer systems 103A, 103B). The local network 109 can be implemented, for instance, as a wired or wireless Local Area Network, an Ethernet connection, or another type of wired or wireless connection. The local network 109 may include one or more wired or wireless routers, wireless access points (WAPs), wireless mesh nodes, switches, high-speed cables, or a combination of these and other types of local network hardware elements. In some cases, the local network 109 includes a software-defined network that provides communication among virtual resources, for example, among an array of virtual machines operating on the server 108 and possibly elsewhere.

[0015] In the example shown in FIG. 1, the remote user devices HOB, HOC operate remotely from the servers 108 and other elements of the computing system 101. For instance, the user devices HOB, HOC may be located at a remote distance (e.g., more than 1 km, 10 km, 100 km, 1,000 km, 10,000 km, or farther) from the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, each of the user devices 110B, HOC communicates with the servers 108 through a remote data connection.Attorney Docket No.: RIGET-133WO1

[0016] The remote data connection in FIG. 1 is provided by a wide area network 115, which may include, for example, the Internet or another type of wide area communication network. In some cases, remote user devices use another type of remote data connection (e.g., satellite-based connections, a cellular network, a virtual private network, etc.) to access the servers 108. The wide area network 115 may include one or more internet servers, firewalls, service hubs, base stations, or a combination of these and other types of remote networking elements. Generally, the computing environment 100 can be accessible to any number of remote user devices.

[0017] The example servers 108 shown in FIG. 1 can manage interaction with the user devices 110 and utilization of the quantum and classical computing resources in the computing system 101. For example, based on information from the user devices 110, the servers 108 may delegate computational tasks to the quantum computing systems 103A, 103B and the other resources 107; the servers 108 can then send information to the user devices 110 based on output data from the computational tasks performed by the quantum computing systems 103A, 103B and the other resources 107.

[0018] As shown in FIG. 1, the servers 108 are classical computing resources that include classical processors 111 and memory 112. The servers 108 may also include one or more communication interfaces that allow the servers to communicate via the local network 109, the wide area network 115 and possibly other channels. In some implementations, the servers 108 may include a host server, an application server, a virtual server or a combination of these and other types of servers. The servers 108 may include additional or different features and may operate as described with respect to FIG. 1 or in another manner.

[0019] The classical processors 111 can include various kinds of apparatus, devices, and machines for processing data, including, byway of example, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or combinations of these. The memory 112 can include, for example, a random-access memory (RAM), a storage device (e.g., a writable read-only memory (ROM) or others), a hard disk, or another type of storageAttorney Docket No.: RIGET-133WO1 medium. The memory 112 can include various forms of volatile or non-volatile memory, media and memory devices, etc.

[0020] Each of the example quantum computing systems 103A, 103B operates as a quantum computing resource in the computing system 101. The other resources 107 may include additional quantum computing resources (e.g., quantum computing systems, quantum virtual machines (QVMs) or quantum simulators] as well as classical (nonquantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), etc., or combinations of these and other types of computing modules.

[0021] In some implementations, the servers 108 generate programs, identify appropriate computing resources (e.g., a QPU or QVM) in the computing system 101 to execute the programs, and send the programs to the identified resources for execution. For example, the servers 108 may send programs to the quantum computing system 103A, the quantum computing system 103B or any of the other resources 107. The programs may include classical programs, quantum programs, hybrid classical / quantum programs, and may include any type of function, code, data, instruction set, etc.

[0022] In some instances, programs can be formatted as source code that can be rendered in human-readable form (e.g., as text) and can be compiled, for example, by a compiler running on the servers 108, on the quantum computing systems 103, or elsewhere. In some instances, programs can be formatted as compiled code, such as, for example, binary code (e.g., machine-level instructions) that can be executed directly by a computing resource. Each program may include instructions corresponding to computational tasks that, when performed by an appropriate computing resource, generate output data based on input data. For example, a program can include instructions formatted for a quantum computer system, a quantum virtual machine, a digital microprocessor, co-processor or other classical data processing apparatus, or another type of computing resource.Attorney Docket No.: RIGET-133WO1

[0023] In some cases, a program may be expressed in a hardware-independent format. For example, quantum machine instructions may be provided in a quantum instruction language such as Quil, described in the publication "A Practical Quantum Instruction Set Architecture,” arXiv:1608.03355v2, dated Feb. 17, 2017, or another quantum instruction language. For instance, the quantum machine instructions may be written in a format that can be executed by a broad range of quantum processing units or quantum virtual machines. In some cases, a program may be expressed in high-level terms of quantum logic gates or quantum algorithms, in lower-level terms of fundamental qubit rotations and controlled rotations, or in another form. In some cases, a program may be expressed in terms of control signals (e.g., pulse sequences, delays, etc.) and parameters for the control signals (e.g., frequencies, phases, durations, channels, etc.). In some cases, a program may be expressed in another form or format.

[0024] In some implementations, the servers 108 include one or more compilers that convert programs between formats. For example, the servers 108 may include a compiler that converts hardware-independent instructions to binary programs for execution by the quantum computing systems 103A, 103B. In some cases, a compiler can compile a program to a format that targets a specific quantum resource in the computer system 101. For example, a compiler may generate a different binary program (e.g., from the same source code) depending on whether the program is to be executed by the quantum computing system 103A or the quantum computing system 103B.

[0025] In some cases, a compiler generates a partial binary program that can be updated, for example, based on specific parameters. For instance, if a quantum program is to be executed iteratively on a quantum computing system with varying parameters on each iteration, the compiler may generate the binary program in a format that can be updated with specific parameter values at runtime (e.g., based on feedback from a prior iteration, or otherwise). In some cases, a compiler generates a full binary program that does not need to be updated or otherwise modified for execution.

[0026] In some implementations, the servers 108 generate a schedule for executing programs, allocate computing resources in the computing system 101 according to the schedule, and delegate the programs to the allocated computing resources. The servers 108Attorney Docket No.: RIGET-133WO1 can receive, from each computing resource, output data from the execution of each program. Based on the output data, the servers 108 may generate additional programs that are then added to the schedule, output data that is provided back to a user device 110, or perform another type of action.

[0027] In some implementations, all or part of the computing environment operates as a cloud-based quantum computing (QC) environment, and the servers 108 operate as a host system for the cloud-based QC environment. The cloud-based QC environment may include software elements that operate on both the user devices 110 and the computer system 101 and interact with each other over the wide area network 115. For example, the cloud-based QC environment may provide a remote user interface, for example, through a browser or another type of application on the user devices 110. The remote user interface may include, for example, a graphical user interface or another type of user interface that obtains input provided by a user of the cloud-based QC environment. In some cases, the remote user interface includes, or has access to, one or more application programming interfaces [APIs], command line interfaces, graphical user interfaces, or other elements that expose the services of the computer system 101 to the user devices 110.

[0028] In some cases, the cloud-based QC environment may be deployed in a “serverless” computing architecture. For instance, the cloud-based QC environment may provide on-demand access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, services, quantum computing resources, classical computing resources, etc.] that can be provisioned for requests from user devices 110. Moreover, the cloud-based computing systems 104 may include or utilize other types of computing resources, such as, for example, edge computing, fog computing, etc.

[0029] In an example implementation of a cloud-based QC environment, the servers 108 may operate as a cloud provider that dynamically manages the allocation and provisioning of physical computing resources (e.g., GPUs, CPUs, QPUs, etc.). Accordingly, the servers 108 may provide services by defining virtualized resources for each user account. For instance, the virtualized resources may be formatted as virtual machine images, virtual machines, containers, or virtualized resources that can be provisioned for a user account and configured by a user. In some cases, the cloud-based QC environment is implemented usingAttorney Docket No.: RIGET-133WO1 a resource such as, for example, OPENSTACK ®. OPENSTACK ® is an example of a software platform for cloud-based computing, which can be used to provide virtual servers and other virtual computing resources for users.

[0030] In some cases, the server 108 stores quantum machine images (QMI) for each user account. A quantum machine image may operate as a virtual computing resource for users of the cloud-based QC environment. For example, a QMI can provide a virtualized development and execution environment to develop and run programs (e.g., quantum programs or hybrid classical / quantum programs). When a QMI operates on the server 108, the QMI may engage either of the quantum processor units 102A, 102B, and interact with a remote user device (110B or HOC) to provide a user programming environment. The QMI may operate in close physical proximity to and have a low-latency communication link with the quantum computing systems 103A, 103B. In some implementations, remote user devices connect with QMls operating on the servers 108 through secure shell (SSH) or other protocols over the wide area network 115.

[0031] In some implementations, all or part of the computing system 101 operates as a hybrid computing environment. For example, quantum programs can be formatted as hybrid classical / quantum programs that include instructions for execution by one or more quantum computing resources and instructions for execution by one or more classical resources. The servers 108 can allocate quantum and classical computing resources in the hybrid computing environment, and delegate programs to the allocated computing resources for execution. The quantum computing resources in the hybrid environment may include, for example, one or more quantum processing units (QPUs), one or more quantum virtual machines (QVMs), one or more quantum simulators, or possibly other types of quantum resources. The classical computing resources in the hybrid environment may include, for example, one or more digital microprocessors, one or more specialized coprocessor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), applicationspecific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), or other types of computing modules.Attorney Docket No.: RIGET-133WO1

[0032] In some cases, the servers 108 can select the type of computing resource (e.g., quantum or classical) to execute an individual program, or part of a program, in the computing system 101. For example, the servers 108 may select a particular quantum processing unit (QPU) or other computing resource based on availability of the resource, speed of the resource, information or state capacity of the resource, a performance metric (e.g., process fidelity) of the resource, or based on a combination of these and other factors. In some cases, the servers 108 can perform load balancing, resource testing and calibration, and other types of operations to improve or optimize computing performance.

[0033] Each of the example quantum computing systems 103A, 103B shown in FIG. 1 can perform quantum computational tasks by executing quantum machine instructions (e.g., a binary program compiled for the quantum computing system). In some implementations, a quantum computing system can perform quantum computation by storing and manipulating information within quantum states of a composite quantum system. For example, qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system. In some instances, quantum logic can be executed in a manner that allows large-scale entanglement within the quantum system. Control signals can manipulate the quantum states of individual qubits and the joint states of multiple qubits. In some instances, information can be read out from the composite quantum system by measuring the quantum states of the qubits. In some implementations, the quantum states of the qubits are read out by measuring the transmitted or reflected signal from auxiliary quantum devices that are coupled to individual qubits.

[0034] In some implementations, a quantum computing system can operate using gatebased models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic orAttorney Docket No.: RIGET-133WO1 annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation.

[0035] In some models, fault-tolerance can be achieved by applying a set of high-fidelity control and measurement operations to the qubits. For example, quantum error correcting schemes can be deployed to achieve fault-tolerant quantum computation. Other computational regimes may be used; for example, quantum computing systems may operate in non-fault-tolerant regimes. In some implementations, a quantum computing system is constructed and operated according to a scalable quantum computing architecture. For example, in some cases, the architecture can be scaled to a large number of qubits to achieve large-scale general purpose coherent quantum computing. Other architectures may be used; for example, quantum computing systems may operate in small- scale or non-scalable architectures.

[0036] The example quantum computing system 103A shown in FIG. 1 includes a quantum processing unit 102A and a control system 105A, which controls the operation of the quantum processing unit 102A. Similarly, the example quantum computing system 103B includes a quantum processing unit 102B and a control system 105B, which controls the operation of a quantum processing unit 102B. A quantum computing system may include additional or different features, and the components of a quantum computing system may operate as described with respect to FIG. 1 or in another manner.

[0037] In some instances, all or part of the quantum processing unit 102A functions as a quantum processor, a quantum memory, or another type of subsystem. In some examples, the quantum processing unit 102A includes a quantum circuit system. The quantum circuit system may include qubit devices, readout devices and possibly other devices that are used to store and process quantum information. In some cases, the quantum processing unit 102A includes a superconductive circuit, and the qubit devices are implemented as circuit devices that include Josephson junctions, for example, in superconducting quantum interference device [SQUID] loops or other arrangements, and are controlled by radiofrequency signals, microwave signals, and bias signals delivered to the quantum processingAttorney Docket No.: RIGET-133WO1 unit 102A. In some cases, the quantum processing unit 102A includes an ion trap system, and the qubit devices are implemented as trapped ions controlled by optical signals delivered to the quantum processing unit 102A. In some cases, the quantum processing unit 102A includes a spin system, and the qubit devices are implemented as nuclear, or electron spins controlled by microwave or radio-frequency signals delivered to the quantum processing unit 102A. The quantum processing unit 102A may be implemented based on another physical modality of quantum computing.

[0038] The quantum processing unit 102A may include, or may be deployed within, a controlled environment. The controlled environment can be provided, for example, by shielding equipment, cryogenic equipment, and other types of environmental control systems. In some examples, the components in the quantum processing unit 102A operate in a cryogenic temperature regime and are subject to very low electromagnetic and thermal noise. For example, magnetic shielding can be used to shield the system components from stray magnetic fields, optical shielding can be used to shield the system components from optical noise, thermal shielding and cryogenic equipment can be used to maintain the system components at controlled temperature, etc.

[0039] In some implementations, the example quantum processing unit 102A can process quantum information by applying control signals to the qubits in the quantum processing unit 102A. The control signals can be configured to encode information in the qubits, to process the information by performing quantum logic gates or other types of operations, or to extract information from the qubits. In some examples, the operations can be expressed as single-qubit quantum logic gates, two-qubit quantum logic gates, or other types of quantum logic gates that operate on one or more qubits. A quantum logic circuit, which includes a sequence of quantum logic operations, can be applied to the qubits to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.

[0040] In some implementations, the example quantum processing unit 102 is a modular quantum processing unit that includes multiple quantum processor modules. For example, the quantum processing unit 102 may include a two-dimensional or three-Attorney Docket No.: RIGET-133WO1 dimensional array of quantum processor modules, and each quantum processor module may include an array of quantum circuit devices. In some cases, the quantum processor modules are supported on a common substrate, and they are interconnected through circuitry (e.g., superconductive circuitry) on the common substrate.

[0041] In some instances, each of the quantum processor modules can include a superconductive quantum integrated circuit QuIC ) that includes one or more quantum circuit devices and superconductive lines that connect the one or more quantum circuit devices. For instance, each quantum processor module may include qubit devices, readout resonator devices, tunable-frequency coupler devices, capacitive coupler devices, or other quantum circuit devices. Each quantum processor module may include flux bias control lines, microwave drive lines, readout signal lines, or other types of control lines for providing control signals to respective quantum circuit devices. In some implementations, quantum processor modules can be coupled to each other by inter-chip coupler devices in one or more cap structures.

[0042] The example control system 105A includes controllers 106A and signal hardware 104A. Similarly, control system 105B includes controllers 106B and signal hardware 104B. All or part of the control systems 105A, 105B can operate in a roomtemperature environment or another type of environment, which may be located near the respective quantum processing units 102A, 102B. In some cases, the control systems 105A, 105B include classical computers, signaling equipment (e.g., microwave, radio, optical, bias, etc.), electronic systems, vacuum control systems, refrigerant control systems or other types of control systems that support operation of the quantum processing units 102A, 102B.

[0043] The control systems 105A, 105B may be implemented as distinct systems that operate independent of each other. In some cases, the control systems 105A, 105B may include one or more shared elements; for example, the control systems 105A, 105B may operate as a single control system that operates both quantum processing units 102A, 102B. Moreover, a single quantum computer system may include multiple quantum processing units, which may operate in the same controlled (e.g., cryogenic) environment or in separate environments.Attorney Docket No.: RIGET-133WO1

[0044] The example signal hardware 104A includes components that communicate with the quantum processing unit 102A. The signal hardware 104A may include, for example, waveform generators, amplifiers, digitizers, high-frequency sources, DC sources, AC sources, etc. The signal hardware may include additional or different features and components. In the example shown, components of the signal hardware 104A are adapted to interact with the quantum processing unit 102A. For example, the signal hardware 104A can be configured to operate in a particular frequency range, configured to generate and process signals in a particular format, or the hardware may be adapted in another manner.

[0045] In some instances, one or more components of the signal hardware 104A generate control signals, for example, based on control information from the controllers 106A. The control signals can be delivered to the quantum processing unit 102A during operation of the quantum computing system 103A. For instance, the signal hardware 104A may generate signals to implement quantum logic operations, readout operations or other types of operations. As an example, the signal hardware 104A may include arbitrary waveform generators (AWGs) that generate electromagnetic waveforms (e.g., microwave or radiofrequency) or laser systems that generate optical waveforms. The waveforms or other types of signals generated by the signal hardware 104A can be delivered to devices in the quantum processing unit 102A to operate qubit devices, readout devices, bias devices, coupler devices or other types of components in the quantum processing unit 102A.

[0046] In some instances, the signal hardware 104A receives and processes signals from the quantum processing unit 102A. The signals received can be generated by the execution of a quantum program on the quantum computing system 103A. For instance, the signal hardware 104A may receive signals from the devices in the quantum processing unit 102A in response to readout or other operations performed by the quantum processing unit 102A. Signals received from the quantum processing unit 102A can be mixed, digitized, filtered, or otherwise processed by the signal hardware 104A to extract information, and the information extracted can be provided to the controllers 106A or handled in another manner. In some examples, the signal hardware 104A may include a digitizer that digitizes electromagnetic waveforms (e.g., microwave or radiofrequency) or optical signals, and a digitized waveform can be delivered to the controllers 106A or toAttorney Docket No.: RIGET-133WO1 other signal hardware components. In some instances, the controllers 106A process the information from the signal hardware 104A and provide feedback to the signal hardware 104A; based on the feedback, the signal hardware 104A can in turn generate new control signals that are delivered to the quantum processing unit 102A.

[0047] In some implementations, the signal hardware 104A includes signal delivery hardware that interfaces with the quantum processing unit 102A. For example, the signal hardware 104A may include filters, attenuators, directional couplers, multiplexers, diplexers, bias components, signal channels, isolators, amplifiers, power dividers and other types of components. In some instances, the signal delivery hardware performs preprocessing, signal conditioning, or other operations to the control signals to be delivered to the quantum processing unit 102A. In some instances, signal delivery hardware performs preprocessing, signal conditioning or other operations on readout signals received from the quantum processing unit 102A.

[0048] In some implementations, the signal hardware 104A includes one or more multilayer board structure configured to mechanically support a quantum processing unit and electrically connect the quantum processing unit to external control systems through signal lines, n some implementations, the multilayer board structure is a stack-up of multiple circuit boards. In some implementations, the multilayer board structure maybe implemented as the multilayer board structure 300 shown in FIGS. 3A-3B or in another manner. In some implementations, the multilayer board structure can provide technical advantages. The multilayer board structure can improve the performance of the quantum processing unit and reduce the cooling time of the system.

[0049] The example controllers 106A communicate with the signal hardware 104A to control the operation of the quantum computing system 103A. The controllers 106A may include classical computing hardware that directly interfaces with components of the signal hardware 104A. The example controllers 106A may include classical processors, memory, clocks, digital circuitry, analog circuitry, and other types of systems or subsystems. The classical processors may include one or more single- or multi-core microprocessors, digital electronic controllers, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), orAttorney Docket No.: RIGET-133WO1 other types of data processing apparatus. The memory may include any type of volatile or non-volatile memory or another type of computer storage medium. The controllers 106A may also include one or more communication interfaces that allow the controllers 106A to communicate via the local network 109 and possibly other channels. The controllers 106A may include additional or different features and components.

[0050] In some implementations, the controllers 106A include memory or other components that store quantum state information, for example, based on qubit readout operations performed by the quantum computing system 103A. For instance, the states of one or more qubits in the quantum processing unit 102A can be measured by qubit readout operations, and the measured state information can be stored in a cache or other type of memory system in or more of the controllers 106A. In some cases, the measured state information is subsequently used in the execution of a quantum program, a quantum error correction procedure, a quantum processing unit (QPU) calibration or testing procedure, or another type of quantum process.

[0051] In some implementations, the controllers 106A include memory or other components that store a quantum program containing quantum machine instructions for execution by the quantum computing system 103A. In some instances, the controllers 106A can interpret the quantum machine instructions and perform hardware-specific control operations according to the quantum machine instructions. For example, the controllers 106A may cause the signal hardware 104A to generate control signals that are delivered to the quantum processing unit 102A to execute the quantum machine instructions.

[0052] In some instances, the controllers 106A extract qubit state information from qubit readout signals, for example, to identify the quantum states of qubits in the quantum processing unit 102A or for other purposes. For example, the controllers may receive the qubit readout signals (e.g., in the form of analog waveforms) from the signal hardware 104A, digitize the qubit readout signals, and extract qubit state information from the digitized signals. In some cases, the controllers 106A compute measurement statistics based on qubit state information from multiple shots of a quantum program. For example, each shot may produce a bitstring representing qubit state measurements for a singleAttorney Docket No.: RIGET-133WO1 execution of the quantum program, and a collection of bitsrings from multiple shots may be analyzed to compute quantum state probabilities.

[0053] In some implementations, the controllers 106A include one or more clocks that control the timing of operations. For example, operations performed by the controllers 106A may be scheduled for execution over a series of clock cycles, and clock signals from one or more clocks can be used to control the relative timing of each operation or groups of operations. In some implementations, the controllers 106A may include classical computer resources that perform some or all of the operations of the servers 108 described above. For example, the controllers 106A may operate a compiler to generate binary programs (e.g., full or partial binary programs) from source code; the controllers 106A may include an optimizer that performs classical computational tasks of a hybrid classical / quantum program; the controllers 106A may update binary programs (e.g., at runtime) to include new parameters based on an output of the optimizer, etc.

[0054] The other quantum computer system 103B and its components (e.g., the quantum processing unit 102B, the signal hardware 104B and controllers 106B) can be implemented as described above with respect to the quantum computer system 103A; in some cases, the quantum computer system 103B and its components may be implemented or may operate in another manner.

[0055] In some implementations, the quantum computer systems 103A, 103B are disparate systems that provide distinct modalities of quantum computation. For example, the computer system 101 may include both an adiabatic quantum computer system and a gate-based quantum computer system. As another example, the computer system 101 may include a superconductive circuit-based quantum computer system and an ion trap-based quantum computer system. In such cases, the computer system 101 may utilize each quantum computing system according to the type of quantum program that is being executed, according to availability or capacity, or based on other considerations.

[0056] FIG. 2 is a diagram showing aspects of an example cryostat 200 in a quantum computing system. As shown in FIG. 2, the example cryostat 200 includes a dilution refrigerator system 224 with multiple thermalization stages 212A, 212B, 212C. In someAttorney Docket No.: RIGET-133WO1 implementations, the example dilution refrigerator system 224 may be used to expose devices and samples to environments of very low temperature (e.g., T < 120 K). In some implementations, vacuum cryostats are used for thermal isolation, typically having a pressure in the range of 0.1 to 10'7Pascal, thereby allowing the example dilution refrigerator system 224 to operate at stable temperatures without appreciable thermal losses.

[0057] In some implementations, the one or more thermalization stages 212 may correspond to radiation shields, thermalization plates, or both. In some instances, a thermalization stage 212 in the dilution refrigerator system 224 may be formed of a material having a high thermal conductivity at cryogenic temperatures, such as below 120 K. For example, a thermalization stage 212 may be formed of a material having a thermal conductivity of at least 1 W / (m-K) as measured at 4 K. In some examples, a high thermal conductivity allows the thermalization stage 212 to mitigate the development of temperature gradients, thereby maintaining a substantially uniform temperature across their respective masses. In some implementations, such material in a thermalization stage 212 may include oxygen-free high conductivity copper and its alloys, including a C101 copper alloy or a beryllium-copper alloy (e.g., Cu with 0.5 - 3% Be) or another type of alloy.

[0058] In some instances, the dilution refrigerator system 224 may include any number of thermalization stages 212 to support subsystems, devices, and samples for cryogenic refrigeration. As a result, the dilution refrigerator system 224 may position the thermalization stages 212 to define a spatial sequence of thermalization stages, such as in a linear sequence or an angular sequence. FIG. 2 depicts three thermalization stages 212 in an equally spaced linear sequence. In some implementations, the dilution refrigerator system 224 may include any number and spacing of thermalization stages 212 as needed. In the example shown in FIG. 2, the dilution refrigerator system 224 includes one or more structural supports 214 to position the thermalization stages 212 into the spatial sequence of thermalization stages. In some examples, the structural supports 214 may be formed of a material having a low thermal conductivity at cryogenic temperatures, e.g., less than 0.5 W / (m-K) at or below 50 K, such as a stainless-steel alloy or a glass-epoxy laminate of G10 grade. In this case, the structural supports 214 thus additionally impedes a flow of heatAttorney Docket No.: RIGET-133WO1 between the thermalization stages 212. As such, the dilution refrigerator system 224 may include one or more thermalization stages 212 dedicated to a specific temperature during operation. For example, the dilution refrigerator system 224 may be configured such that each thermalization stage 212 operates at a progressively decreasing temperature as the depth of the dilution refrigerator system 224 increases along the Z axis.

[0059] In some implementations, the dilution refrigerator system 224 may also include one or more refrigeration systems (not shown) thermally coupled to each of the thermalization stages 212. For example, the dilution refrigerator system 224 may include a pulse-tube refrigeration system coupled to a second lowest temperature thermalization stage 212B and a3He / 4He dilution refrigerator system thermally coupled to a lowest temperature thermalization stage 212C. The dilution refrigerator system 224 establishes specific operating temperatures for the thermalization stages 212 to which they are respectively thermally coupled. In some implementations, the dilution refrigerator system 224 may define a distribution of operating temperatures along the spatial sequence of thermalization stages 212. In some implementations, a pulse-tube refrigeration unit may be configured to optimally extract heat at temperatures to about 4 K and a3He / 4He dilution refrigerator unit may be configured to optimally extract heat at temperatures below 1 K.

[0060] In some implementations, the example cryostat 200 includes a multilayer board structure 228 supported on a thermalization stage and enclosed in the dilution refrigerator system 224. In some instances, the multilayer board structure 228 is configured to mechanically support a quantum processing unit 230, and electrically connect the quantum processing unit 230 with transmission links 222. In some instances, the multilayer board structure 228 is mounted to the lowest temperature thermalization stage 212C; and mechanically anchored to and in thermal contact with the lowest temperature thermalization stage 212C of the dilution refrigerator system 224. In other words, heat generated in the multilayer board structure 228 can be dissipated to the lowest temperature thermalization stage. In some implementations, the multilayer board structure 228 is a stack-up of multiple circuit boards. In some implementations, the multilayer board structure 228 may be implemented as the multilayer board structure 300 shown in FIGS. 3A-3B or in another manner. In some implementations, the multilayerAttorney Docket No.: RIGET-133WO1 board structure 228 can provide technical advantages. The multilayer board structure 228 can improve the performance of the quantum processing unit and reduce the cooling time of the system.

[0061] In some implementations, the quantum processing unit 230 supported on the multilayer board structure 228 may receive signals from and transmit signals to the transmission links 222 via the multilayer board structure 228. The transmission links 222 can transmit control signals from a control system out of the dilution refrigerator system 224 (e.g., the control system 105 in FIG. 1] to the quantum processing unit 230, and readout signals from the quantum processing unit 230 out of the dilution refrigerator system 224. In some instances, the signals communicated on the transmission links 222 are microwave-frequency signals, radiofrequency signals, or other types of communication signals. As shown in FIG. 2, the transmission links 222 in the dilution refrigerator system 224 are configured separately from the structural supports 214 through the thermalization stages 212. In certain instances, the transmission links 222 may be arranged or routed in another manner to couple signal hardware in the control system (e.g., the signal hardware 104 in the control system 105 in FIG. 1). In some instances, the transmission link 222 includes signal lines, devices and other components that support the transmission of signals into or out of the multilayer board structure 228.

[0062] In some instances, the multilayer board structure 228 includes impedance- matched lines for RF signals, low resistance lines for DC signals, RF filters, or other types of signal lines allowing for high-density RF- and DC-signals passing through electrical connectors to the quantum processing unit 230. The multilayer board structure 228 includes a high density of signal lines (e.g., in a range of greater than or equal to 0.2 signals / mm2or another range). In some examples, the multilayer board structure 228 includes a stack of circuit boards each including a multilayer metallization; an array of electrically and thermally conductive through-hole vias; and other features. In some instances, the multilayer metallization in the stack includes a conductive layer with a high thermal conductivity and a superconductive layer to allow for lower electrical resistance operations in a cryogenic environment.Attorney Docket No.: RIGET-133WO1

[0063] In some implementations, components of the quantum processing unit 230 residing on the multilayer board structure 228 include a superconductive quantum circuit that can be operated under a superconducting condition. In certain instances, the superconductive quantum circuit of the quantum processing unit includes quantum circuit devices, such as qubit devices (e.g., transmon devices, fluxonium devices, or other types of superconducting qubit devices), coupler devices, readout resonators, or other types of quantum circuit devices that are used for quantum information processing in the quantum processing unit 230. In some examples, each of the qubit devices in the quantum processing unit 230 can be encoded with a single bit of quantum information. The quantum circuit devices may include one or more Josephson junctions, capacitors, inductors, and other types of circuit elements.

[0064] In some implementations, the superconductive quantum circuit on the quantum processing unit 230 may further include a variety of circuit elements to control or readout the qubit devices of the quantum processing unit. For example, the superconductive quantum circuit may include flux bias lines which can provide magnetic flux locally to tunable-frequency qubit devices to tune their frequencies. The superconductive quantum circuit may include tunable coupler devices, microwave feedlines, and resonator devices to readout qubits. In some examples, the superconductive quantum circuit may include micro wave feedlines which are coupled to one or several of the resonator devices of the quantum processing unit 230 to allow microwave excitation of the resonator devices used to readout qubits. In this case, the superconductive quantum circuit may include microwave drive lines which are capacitively coupled with qubit devices to drive qubits.

[0065] Typically, each of the qubit devices has two eigenstates that are used as computational basis states (e.g., |0) and |1)), and each qubit device can transition between its computational basis states or exist in an arbitrary superposition of its computational basis states. In some examples, the two lowest energy levels (e.g., the ground state and first excited state) of each qubit device are defined as a qubit and used as computational basis states for quantum computation. In some examples, higher energy levels (e.g., a second excited state or a third excited state) can be used to define a qubit, a qutrit, a qudit, or a multi-level quantum computational device in some instances. Quantum states (e.g., qubits)Attorney Docket No.: RIGET-133WO1 defined by respective qubit devices can be manipulated by control signals, or read by readout signals, generated by a control system, e.g., the control system 105 in FIG. 1. The qubit devices can be controlled individually, for example, by delivering control signals from a control system to the respective qubit devices. In some cases, readout devices can detect the states of the qubit devices, for example, by interacting directly with the respective qubit devices.

[0066] The superconductive quantum circuit in the quantum processing unit 230 may be fabricated on a substrate. In certain instances, the substrate supporting the superconductive quantum circuit may be an elemental semiconductor, for example silicon (Si), germanium (Ge), selenium (Se), tellurium (Te), or another elemental semiconductor. In some instances, the substrate may also include a compound semiconductor such as aluminum oxide (sapphire), silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), indium phosphide (InP), silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), gallium indium phosphide (GalnP), or another compound semiconductor. In some instances, the substrate may also include a multilayer structure with elemental or compound semiconductor layers. In certain instances, the substrate includes an epitaxial layer. In some examples, the substrate may have an epitaxial layer overlying a bulk semiconductor or may include a semiconductor-on-insulator (SOI) structure.

[0067] The superconductive quantum circuit may include superconductive materials and can be formed by patterning one or more superconductive (e.g., superconductive metal) layers or other materials. In some implementations, each of the one or more superconductive layers include a superconductive metal, such as aluminum (Al), niobium (Nb), rhenium (Re), tantalum (Ta), titanium (Ti), vanadium (V), tungsten (W), zirconium (Zr), or another superconductive metal. In some implementations, each of the one or more superconductive layers may include a superconductive metal alloy, such as molybdenumrhenium (Mo / Re), niobium-tin (Nb / Sn), or another superconductive metal alloy. In some implementations, each of the superconductive layers may include a superconductive compoundmaterial, including superconductive metal nitrides and superconductive metal oxides, such as titanium-nitride (TiN), niobium-nitride (NbN), zirconium-nitride (ZrN), hafnium-nitride (HfN), vanadium-nitride (VN), tantalum-nitride (TaN), molybdenum-Attorney Docket No.: RIGET-133WO1 nitride [MoN], yttrium barium copper oxide [Y-Ba-Cu-O], or another superconductive compoundmaterial. In some instances, the superconductive quantum circuit may include multilayer superconductor-insulator heterostructures.

[0068] In some implementations, the quantum processing unit 230 is fabricated on the top surface of a substrate and patterned using a microfabrication process or in another manner. For example, quantum circuit devices in a superconductive quantum circuit may be formed by performing at least some of the following fabrication steps: using chemical vapor deposition [CVD], physical vapor deposition [PVD], atomic layer deposition [ALD], spin-on coating, and / or other suitable techniques to deposit respective superconductive layers on the substrate; and performing one or more patterning processes (e.g., a lithography process, a dry / wet etching process, a soft / hard baking process, a cleaning process, etc.] to form openings in the respective superconductive layers.

[0069] FIGS. 3A-3B are schematic diagrams showing a cross-sectional view of an example multilayer board structure 300. In some implementations, the example multilayer board structure 300 is configured to mechanically support one or more quantum processing units; and electrically connect the quantum processing units with an external control system. In some implementations, the multilayer board structure 300 is used in a cryogenic system for communicating electrical signals to and from a quantum processing unit residing on the lowest temperature thermalization stage of a cryostat of a cryogenic system. The example multilayer board structure 300 is a stack of multiple printed circuit boards. In some instances, the example multilayer board structure 300 includes a stack of printed circuit boards in a range of equal to or less than 10, equal to or less than 20, equal to or less than 30, equal to or less than 40, or in another range. As shown in FIGS. 3A-3B, the example multilayer board structure 300 includes multiple core layers 302 laminated to one another through composite layers 304. Each of the outermost core layers 302 includes a termination layer 306. In some instances, the termination layer 306 on the outermost core layer 302 may be directly formed on the copper layer without an intermediate superconductive layer. The multilayer board structure 300 includes multiple conductive through-hole vias 308. The multilayer board structure 300 may include additional or different features, and the components of the example multilayer board structure 300 may operate as described with respect to FIGS. 3A-3B or in another manner. In someAttorney Docket No.: RIGET-133WO1 implementations, the example multilayer board structure 300 may be fabricated by performing operations in the example process 400 of FIG. 4, or in another manner.

[0070] In some implementations, each core layer 302 includes a dielectric substrate 312 and a multilayer metallization. In some instances, the dielectric substrate 312 of the core layer 302 includes fiberglass-reinforced epoxy laminate or another material. The multilayer metallization includes a conductive layer 314 residing on the surface of the dielectric substrate 312 and a superconductive layer 316 residing on surfaces of the conductive layer 314. In some instances, the superconductive layer 316 can be formed on or applied over the conductive layer 314. The superconductive layer 316 covers the conductive layer 312 such that the conductive layer 314 is sandwiched or structurally placed between the superconductive layer 316 and the dielectric substrate 312 along a direction perpendicular to the surface of the dielectric substrate 312. In some instances, when the conductive layer 314 is sandwiched between the superconductive layer 316 and the dielectric substrate, the conductive layer 314 is embedded or bounded by the dielectric substrate 312 below and the superconductive layer 316 above. As shown in FIGS. 3A-3B, each core layer 302 includes two conductive layers 314A, 314B, one on each surface of the dielectric substrate 312. In some instances, each conductive layer 314 may be patterned into conductive lines, pads, and ground planes. In some implementations, the conductive layer 314 is made of high thermal conductivity material, e.g., copper, and copper alloys.

[0071] In some implementations, the superconductive layer 316 on the conductive layer 314 of a core layer 302 is configured to provide a superconductive path for the signal to minimize the joule heating and active heat load. In some implementations, the superconductive layer 316A, 316B includes a conductive layer that is superconducting at a cryogenic temperature. In some implementations, the superconductive layer 316A, 316B includes a layer of metallic tin (Sn). In some instances, the metallic Sn can be plated on the copper layer 314 using electroless, immersion, or other plating method, which is lead-free and Restriction of Hazardous Substances [RoHS] compliant and can provide better tolerance on plating thickness. In some instances, the superconductive material used in the superconductive layer 316 has a transition temperature of around 3.7 K, which is high compared to the mixing chamber (MXC) temperature so any issues with the quality of theAttorney Docket No.: RIGET-133WO1 metal or the process that could affect the purity of the metal and hence its transition temperature (such as making Tcbroadened or shifting it down) can still leave a high margin to the MXC temperature. In some instances, the diffusion rate Sn into Cu is extremely low at low temperatures, and the multilayer board structure 300 can have a potentially long lifetime.

[0072] In some instances, the superconductive layer 316A, 316B may include other superconductive materials, such as metallic aluminum (Al), metallic rhenium (Re), metallic ruthenium (Ru), or other metals. The superconductive layer 316A, 316B may be plated on the conductive layer 314A, 314B. In some instances, during plating, the superconductive layer 316A, 316B is deposited on exposed surfaces of the patterned conductive layer 314A, 314B in contact with the plating solution, for example, on top surfaces and sidewalls.

[0073] As shown in FIGS. 3A-3B, the example multilayer board structure 300 includes multiple signal layers and multiple ground layers. Each signal layer includes a core layer 302 patterned with signal lines; and each ground layer includes a core layer 302 that carries a ground plane. In some instances, each signal layer may be sandwiched, placed, or situated between two ground layers. In other words, a signal layer is positioned between or bounded by a first ground layer below and a second ground layer above; and a ground layer is positioned between or bounded by a first signal layer above and a second signal layer below. In some instances, the outermost core layers 302A and 302D in FIGS. 3A-3B are ground layers. In some implementations, the signal line and the ground planes show superconductivity at a cryogenic temperature (e.g., equal to or lower than 4 K).

[0074] In some instances, the termination layer 306A, 306B are configured to cover and protect the superconductive layer on the outermost core layer 302A, 302D. In this case, the termination layer 306A, 306B including at least one noble metal (e.g., copper, silver, gold, nickel, platinum, palladium, etc.), is inert and can be used to stabilize the amorphous nature of the superconductive layer in the outermost core layers 302A, 302D. In some implementations, the termination layer 306A, 306B makes the multilayer board structure 300 solderable allowing the multilayer board structure 300 being solder-connected to electrical connectors without significantly affecting the superconductivity and critical temperature of the superconductive material in the stack. In some instances, theAttorney Docket No.: RIGET-133WO1 termination layer 306A, 306B may be formed on the superconductive layer 314A of the outermost core layers 302A, 302D using electroplating. In some implementations, the multilayer board structure 300 can be connectorized with standard high-density connectors using a solder that has a low melting temperature (T<150 °C or another range) for relatively short periods of time (t< 10 minutes or another time period).

[0075] In some implementations, the composite layer 304 is a pre-impregnated (prepreg) layer which includes a layer of fiberglass material impregnated with a resin that has been partially cured. The composite layer 304 is used as an adhesive dielectric layer between core layers 302 when stacked and pressed together. In some instances, the composite layer 304 may include other materials. For example, the composite layer may be an epoxy resin prepreg layer, a polyimide prepreg layer, a cyanate ester prepreg layer, a Teflon prepreg layer, a ceramic-filled prepreg layer, and another prepreg layer.

[0076] In some instances, each core layer 302 is superconducting at a cryogenic temperature, e.g., at or below the temperature of the second lowest temperature thermalization stage. In some implementations, the quantum processing unit may receive and transmit signals via the multilayer board structure 300. In some instances, the signals communicated on the multilayer board structure 300 are microwave or radio-frequency frequency signals. In some instances, the multilayer board structure 300 can be used for communicating electrical signals with other types of devices in the cryostat. For example, devices and components on the second lowest temperature thermalization stage may be supported on another multilayer board structure 300 communicating with the external control system through respective connectors.

[0077] FIG. 4 is a flow chart showing aspects of an example process 400. The example process 400 can be used to fabricate a multilayer board structure, e.g., the multilayer board structure 228, 300 shown in FIGS. 2-3 or in another manner. The process can be adapted for compatibility with standard PCB manufacturing processes, and may be used to fabricate a stack of PCBs for a scaled system. The example process 400 may include additional or different operations, including operations to fabricate additional or different components, and the operations may be performed in the order shown or in another order. In someAttorney Docket No.: RIGET-133WO1 cases, operations in the example process 400 can be combined, iterated, or otherwise repeated or performed in another manner.

[0078] At 402, core layers are prepared. The operation 402 includes sub-operation 412 during which a circuit board is received; and sub-operation 414 during which superconductive layer is formed on the circuit board.

[0079] At 412, a circuit board is prepared. The circuit board includes a dielectric substrate with a conductive layer residing on at least one of its surfaces. In some instances, the circuit board may include a conductive layer on each surface. In some instances, a photoresist layer is patterned on the conductive layer. In some implementations, the photoresist layer may include a negative or positive tone photoresist layer that is patternable in response to a photolithography light source. In some instances, the photoresist layer may include an e-beam (electron beam resist layer (e.g., poly methyl methacrylate, methyl methacrylate, or another e-beam resist material) that is patternable in response to an e-beam lithography energy source. In some examples, before patterning, the photoresist layer is formed directly on the surface of the conductive layer of the circuit board using a deposition process such as spin-coating, spray-coating, dip-coating, rollercoating, or another deposition method. After deposition, the photoresist layer is then patterned using a lithography process that may involve various exposure, developing, baking, stripping, etching, and rinsing / cleaning processes. As a result, the photoresist layer is patterned such that openings in the photoresist layer expose at least a portion of the surface of the conductive layer of the circuit board. In some implementations, the positions and shapes of the openings are determined according to the design of signal lines in the core layer.

[0080] In some instances, prior to the formation of the photoresist layer, the circuit board can be prepared. In some implementations, the circuit board is a printed circuit board, or other types of circuit board that is compatible with a plating process. In some instances, the circuit board can be cleaned to remove any organic contaminations, particles, or oxides that may have formed on the surface of the conductive layer. For example, when a printed circuit board is used as the substrate, the printed circuit board may be immersed in a solution of diluted sulfuric acid followed by a rinse of deionized water.Attorney Docket No.: RIGET-133WO1

[0081] After patterning the photoresist layer, the exposed conductive layer at the openings of the photoresist layer can be removed by performing an etching process. For example, a copper etching process can be performed when the circuit board is a printed circuit board. After the etching process, the photoresist layers can be removed. In some instances, the photoresist layers may be removed by one or more chemical cleaning processes using acetone, l-Methyl-2-pyrrolidon (NMP), Dimethyl sulfoxide (DMSO), or other suitable removing chemicals. In some examples, the chemicals used may need to be heated to temperatures higher than room temperature to effectively dissolve the photoresist layers. The selection of the remover is determined by the type and chemical structure of the photoresist layers, the conductive layer, and the dielectric substrate to assure the chemical compatibility of the conductive layer and the dielectric substrate with the chemical cleaning process. In some implementations, this chemical cleaning process is then followed by a rinsing process using isopropyl alcohol or another chemical, and then using DI water. After removing the photoresist layer, surfaces of the patterned conductive layer and at least a portion of the dielectric substrate of the circuit board are exposed.

[0082] At 414, a superconductive layer is formed on the circuit board. In some implementations, the superconductive layer is formed by plating superconductive material on the exposed surfaces of the patterned conductive layer. For example, a superconductive layer is electroplated on the patterned copper layer on a printed circuit board. In some implementations, the surfaces of the patterned conductive layer are cleaned prior to the electroplating process to remove oxides and other contaminants via chemical cleaning, mechanical abrasion, or ultrasonic cleaning.

[0083] In some instances, a plating solution can be prepared. For example, a tin electroplating solution includes a tin salt such as Stannous Sulfate (SnS04) or Stannous Chloride (SnCl2) dissolved in deionized water. The concentrations of the tin salt depend on the desired thickness and morphology of the superconductive layer, and electroplating time. In some instances, the plating solution may include complexing agents to stabilize the tin ions in the solution and preventing them from precipitating out, additives to improve the surface of the tin deposit and form a uniform layer, surfactant to reduce surface tension and improve the wettability of the substrate, or other components. In some instances,Attorney Docket No.: RIGET-133WO1 when other superconductive material (Re or Ru) is plated, the plating solution and conditions maybe varied and controlled accordingly. In some instances, the plating process may include certain adjustments to promote adhesion of the Sn layer to the composite layers, for example, using low electroplating potential, at elevated temperature, etc.

[0084] In some instances, an electroplating cell can be configured. The patterned circuit board can be mechanically supported on a cathode frame electrically contacting the patterned conductive layer. Gold, titanium, stainless steel, carbon mesh, or other types of conductive materials that are inert in the electroplating solutions can be used as an anode. The cathode frame with the patterned circuit board and the anode are first immersed in the electroplating solution of superconductive material (e.g., a tin electroplating solution). A direct current (DC) can be applied between the cathode frame and the anode. Once the desired thickness of the tin layer is obtained (e.g., by monitoring the total charge passed, electroplating time, weight increase on the cathode frame, etc.), the DC current can be stopped; and the tin layer is formed on exposed surfaces of the patterned conductive layer. The cathode frame supporting the patterned circuit board can be removed from the electroplating solution, rinsed using deionized water to remove any residual electroplating solution, and dried. In some instances, pulse plating, electrolyte flow during plating, or other electroplating techniques can be used as would be known by those skilled in the art of electroplating. In some instances, the superconductive layer may be deposited using an immersion deposition or electroless deposition by immersing the patterned circuit board in the solution containing superconductive metal ion (e.g., tin ions, ruthenium, rhenium, etc.) In some instances, the solution may contain two or more types of superconductive metal ions.

[0085] In some implementations, a termination layer of non-superconductive material is electroplated on the superconductive layer. After the superconductive layer is formed, the circuit board can then be rinsed, dried and transferred to a gold electroplating solution. In some instances, a gold electroplating solution includes a gold salt such as gold potassium cyanide dissolved in deionized water. After the termination layer is formed, the cathode frame can be removed from the rhenium electroplating solution, rinsed using deionized water to remove any residual rhenium electroplating solution, and dried. In someAttorney Docket No.: RIGET-133WO1 instances, other electroplating techniques can be used. Sub-operations 412, 414 may be repeated to prepare multiple core layers. The cathode frame can be removed from the gold electroplating solution, rinsed using deionized water to remove any residual gold electroplating solution, and dried. In some instances, other electroplating techniques can be used.

[0086] At 404, the multilayer board structure is formed by laminating the core layers together. In some implementations, a composite layer can be applied to a first core layer and a second core layer can be attached to the composite layer. In some instances, the second core layer may be aligned to the first core layer according to alignment features. The process can be repeated after all the core layers are stacked on one another. In some instances, the stacked core layers are pressed, for example, in a lamination press while applying heat and pressure to bond the core layers tightly together, removing air gaps and ensuring a solid bond. The stack is then held under heat and pressure for a specific amount of time, allowing the resin to cure and the layers to bond firmly together. The curing process ensures that the layers remain securely laminated after cooling. After the curing process, the laminated stack is allowed to cool under controlled conditions to maintain the integrity of the core layers.

[0087] In some instances, after the superconductive multilayer circuit board is formed, through-hole vias can be formed and electroplated to form electrical connections between different core layers. In some instances, the via holes are formed during the formation of individual core layer or after the lamination of all the core layers. In certain examples, the via holes can be formed in the laminated core layers using drilling or another method. In some instances, the conductive through-hole vias are formed by electroplating copper and tin sequentially.

[0088] In a general aspect, a superconductive multilayer circuit board is formed and operated for communicating electromagnetic signals in a cryogenic system.

[0089] In a first example, a multilayer board structure includes a plurality of printed circuit boards stacked on one another. Each printed circuit board includes a dielectric substrate, a copper layer on a surface of the dielectric substrate; and a superconductiveAttorney Docket No.: RIGET-133WO1 layer electroplated on a surface of the copper layer such that the copper layer is sandwiched between the superconductive layer and the dielectric substrate.

[0090] Implementations of the first example may include one or more of the following features. The superconductive layer includes tin. The superconductive layer includes rhenium. The superconductive layer includes ruthenium. The superconductive layer includes aluminum. The multilayer board structure includes superconductive through-hole vias. The copper layer includes patterned copper traces, and the superconductive layer is electroplated on the patterned copper traces. The copper layer includes a ground plane, and the superconductive layer is electroplated on the ground plane.

[0091] Implementations of the first example may include one or more of the following features. The multilayer board structure includes a plurality of composite layers. Each composite layer is sandwiched between two respective superconductive layers of two neighboring printed circuit boards. The copper layer is a first copper layer, the superconductive layer is a first superconductive layer, the surface is a first surface, each printed circuit board includes a second copper layer on a second, opposite surface of the dielectric substrate, and a second superconductive layer electroplated on the surface of the second copper layer such that the second copper layer is sandwiched between the second superconductive layer and the dielectric substrate. Each composite layer includes a preimpregnated material.

[0092] In a second example, a method of forming a multilayer board structure, includes receiving a plurality of printed circuit boards including respective copper layers; performing an electroplating process on the plurality of printed circuit boards to deposit respective superconductive layers over the respective copper layers; and stacking the plurality of electroplated printed circuit boards.

[0093] Implementations of the second example may include one or more of the following features. The method includes prior to performing the electroplating, patterning the respective copper layers to form conductive traces; and performing a surface treatment process to the conductive traces. Stacking the plurality of electroplated printed circuit boards includes applying a composite layer on a surface of a superconductive layer of aAttorney Docket No.: RIGET-133WO1 first electroplated printed circuit board; laminating a second electroplated printed circuit board on the composite layer; and curing the composite layer. The method includes forming a gold termination layer on the surface of the superconductive layer of an outermost electroplated printed circuit board of the multilayer board structure.

[0094] In a third example, a quantum computing system includes a cryostat, a multilayer board structure, and a superconductive quantum processing unit. The cryostat includes a plurality of thermalization stages. The multilayer board structure is mechanically supported and in thermal contact with a lowest temperature thermalization stage of the cryostat. The multilayer board structure includes a plurality of printed circuit boards stacked on one another. Each printed circuit board includes a dielectric substrate, a copper layer on a surface of the dielectric substrate; and a superconductive layer electroplated on a surface of the copper layer such that the copper layer is sandwiched between the superconductive layer and the dielectric substrate. The superconductive quantum processing unit includes superconductive circuitry and superconductive quantum circuit devices. The superconductive quantum processing unit is electrically and thermally connected to the multilayered board structure.

[0095] Implementations of the third example may include one or more of the following features. The superconductive layer includes tin. The superconductive layer includes rhenium. The superconductive layer includes ruthenium. The superconductive layer includes aluminum. The multilayer board structure includes superconductive through-hole vias. The copper layer is configured to thermalize the superconductive layer to the lowest- temperature thermalization stage. The copper layer includes patterned copper traces, and the superconductive layer is electroplated on the patterned copper traces. The copper layer includes a ground plane, and the superconductive layer is electroplated on the ground plane.

[0096] Implementations of the third example may include one or more of the following features. The multilayer board structure includes a plurality of composite layers. Each composite layer is sandwiched between two respective superconductive layers of two neighboring printed circuit boards. The copper layer is a first copper layer, the superconductive layer is a first superconductive layer, the surface is a first surface, eachAttorney Docket No.: RIGET-133WO1 printed circuit board includes a second copper layer on a second, opposite surface of the dielectric substrate, and a second superconductive layer electroplated on the surface of the second copper layer such that the second copper layer is sandwiched between the second superconductive layer and the dielectric substrate. Each composite layer includes a preimpregnated material.

[0097] While this specification contains many details, these should not be understood as limitations on the scope of what may be claimed, but rather as descriptions of features specific to particular examples. Certain features that are described in this specification or shown in the drawings in the context of separate implementations can also be combined. Conversely, various features that are described or shown in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination.

[0098] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single product or packaged into multiple products.

[0099] A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made. Accordingly, other embodiments are within the scope of the following claims.

Claims

Attorney Docket No.: RIGET-133WO1CLAIMSWhat is claimed is:

1. A multilayer board structure configured to operate within a cryostat of a quantum computing system, the multilayer board structure comprising: a stack of printed circuit boards, each printed circuit board in the stack comprising: a dielectric substrate, a copper layer on a surface of the dielectric substrate; and a superconductive layer electroplated on a surface of the copper layer such that the copper layer is sandwiched between the superconductive layer and the dielectric substrate.

2. The multilayer board structure of claim 1, wherein the superconductive layer comprises tin.

3. The multilayer board structure of claim 1, wherein the superconductive layer comprises rhenium.

4. The multilayer board structure of claim 1, wherein the superconductive layer comprises ruthenium.

5. The multilayer board structure of claim 1, wherein the superconductive layer comprises aluminum.

6. The multilayer board structure of claim 1, comprising: superconductive through-hole vias.

7. The multilayer board structure of any one of claims 1 through 6, wherein the copper layer comprises patterned copper traces, and the superconductive layer is electroplated on the patterned copper traces.

8. The multilayer board structure of any one of claims 1 through 6, wherein the copper layer comprises a ground plane, and the superconductive layer is electroplated on the ground plane.Attorney Docket No.: RIGET-133WO19. The multilayer board structure of any one of claims 1 through 6, comprising: a plurality of composite layers, each composite layer being sandwiched between two respective superconductive layers of two neighboring printed circuit boards.

10. The multilayer board structure of claim 9, wherein each composite layer comprises a pre-impregnated material.

11. The multilayer board structure of any one of claims 1 through 6, wherein the copper layer is a first copper layer, the superconductive layer is a first superconductive layer, the surface is a first surface, each printed circuit board comprises: a second copper layer on a second, opposite surface of the dielectric substrate, and a second superconductive layer electroplated on the surface of the second copper layer such that the second copper layer is sandwiched between the second superconductive layer and the dielectric substrate.

12. A method of forming a multilayer board structure configured to operate within a cryostat of a quantum computing system, the method comprising: receiving a plurality of printed circuit boards comprising respective copper layers; performing an electroplating process on the plurality of printed circuit boards to deposit respective superconductive layers over the respective copper layers; and stacking the plurality of electroplated printed circuit boards on one another to form a stack.

13. The method of claim 12, comprising: prior to performing the electroplating, patterning the respective copper layers to form conductive traces; and performing a surface treatment process to the conductive traces.

14. The method of claim 12, wherein stacking the plurality of electroplated printed circuit boards comprises: applying a composite layer on a surface of a superconductive layer of a first electroplated printed circuit board; laminating a second electroplated printed circuit board on the composite layer; and curing the composite layer.Attorney Docket No.: RIGET-133WO115. The method of claim 12, comprising: forming a gold termination layer on the surface of the superconductive layer of an outermost electroplated printed circuit board of the multilayer board structure.

16. A quantum computing system comprising: a cryostat comprising a plurality of thermalization stages; a multilayer board structure mechanically supported by, and in thermal contact with, a lowest temperature thermalization stage of the cryostat, the multilayer board structure comprising a stack of printed circuit boards, each printed circuit board in the stack comprising: a dielectric substrate, a copper layer on a surface of the dielectric substrate; and a superconductive layer electroplated on a surface of the copper layer such that the copper layer is sandwiched between the superconductive layer and the dielectric substrate; and a superconductive quantum processing unit electrically and thermally connected to the multilayered board structure.

17. The system of claim 16, wherein the superconductive layer comprises tin.

18. The system of claim 16, wherein the superconductive layer comprises rhenium.

19. The system of claim 16, wherein the superconductive layer comprises ruthenium.

20. The system of claim 16, wherein the superconductive layer comprises aluminum.

21. The system of claim 16, wherein the multilayer board structure comprises superconductive through-hole vias.

22. The system of claim 16, wherein the copper layer is configured to thermalize the superconductive layer to the lowest-temperature thermalization stage.

23. The system of any one of claims 16 through 22, wherein the copper layer comprises patterned copper traces, and the superconductive layer is electroplated on the patterned copper traces.Attorney Docket No.: RIGET-133WO124. The system of any one of claims 16 through 22, wherein the copper layer comprises a ground plane, and the superconductive layer is electroplated on the ground plane.

25. The system of any one of claims 16 through 22, wherein the multilayer board structure comprises a plurality of composite layers, each composite layer being sandwiched between two respective superconductive layers of two neighboring printed circuit boards.

26. The system of claim 25, wherein each composite layer comprises a pre-impregnated material.

27. The system of any one of claims 16 through 22, wherein the copper layer is a first copper layer, the superconductive layer is a first superconductive layer, the surface is a first surface, each printed circuit board comprises: a second copper layer on a second, opposite surface of the dielectric substrate, and a second superconductive layer electroplated on the surface of the second copper layer such that the second copper layer is sandwiched between the second superconductive layer and the dielectric substrate.

28. The system of any one of claims 16 through 22, comprising a control system, wherein the superconductive quantum processing unit comprises superconductive circuitry that is communicably coupled to the control system by the multilayer board structure.

29. The system of claim 28, wherein the superconductive circuitry comprises qubit devices that are configured to be controlled by the control system.

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