Dual-channel first-in first-out buffering

Abstract

Write data bursts directed to two different channels (or ranks) may be time-interleaved and transmitted to a data buffer device. The data buffer device deinterleaves the write data bursts and transmits them to memory devices via two different memory channel data interfaces. When one of the channels is not being written to, the host may time-interleave write data for two write data bursts that are directed to the same channel. The write data burst for the first channel is transmitted to the memory devices via the first channel. The time-demultiplexed write data burst for the next write transaction directed to the first channel is stored by the data buffer device. At a later time, the data buffer device transmits stored write data burst to the memory devices via the first channel.

Description

Docket: 765-0255WO1 - 11443WO01DUAL-CHANNEL FIRST-IN FIRST-OUT BUFFERING BRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figures 1 A-1I are diagrams illustrating dual-channel first-in first-out buffering.

[0002] Figure 2 is a timing diagram illustrating example operation of a multiplexing data buffer device.

[0003] Figure 3 is a block diagram illustrating an example memory system.

[0004] Figure 4 is a block diagram illustrating an example memory module.

[0005] Figure 5 is a flowchart illustrating a method of operating a memory module.

[0006] Figure 6 is a flowchart illustrating a method of operating a memory controller.

[0007] Figure 7 is a flowchart illustrating a method of operating a multiplexing data buffer device.

[0008] Figure 8 is a flowchart illustrating a method of operating a memory module.

[0009] Figure 9 is a flowchart illustrating a method of operating a registering clock driver device.

[0010] Figure 10 is a block diagram illustrating a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] In an embodiment, write data bursts directed to two different channels (or ranks) may be time-interleaved and transmitted to a data buffer device. The data buffer device deinterleaves the write data bursts and transmits them to memory devices via two different memory channel data interfaces (e.g., first and second). The time-interleaved bursts are transmitted to the data buffer device at twice the data rate that the deinterleaved data bursts are transmitted to the memory devices via the first and second channel interfaces.

[0012] In an embodiment, when one of the channels (e.g., second channel) is not being written to, the host may time-interleave write data for two write data bursts that are directed to the same channel (e.g., first channel). The write data burst for the first channel by the current write transaction is time-demultiplexed (a.k.a., deinterleaved) and transmitted by the data buffer device to the memory devices via the first channel. The time-demultiplexed write data burst for the next write transaction directed to the first channel is stored by the data buffer device (e.g., in a first-in first-out buffer). At a later time (determined by the host), the data buffer device transmits the demultiplexed write data burst for the next write transaction to the memory devices via the channel being that was written to by the “current” (now previous) write transaction (i.e., first channel).Docket: 765-0255WO1 - 11443WO01

[0013] Figures 1 A-l J are diagrams illustrating dual-channel first-in first-out buffering. InFigures 1 A-l J, multiplexing data buffer (MDB) device 130 comprises controller side data interface 154, time-demultiplexer 155, first-in first-out (FIFO) buffer 156a, FIFO buffer 156b, 2: 1 multiplexer (MUX) 157a, 2: 1 multiplexer (MUX) 157b, and memory device side data interface 132a, and memory device side data interface 132b. Controller side data interface 154 receives time-multiplexed write data bursts (e.g., from a controller - not shown in Figures 1A-1J) and provides these write data bursts to time-demultiplexer 155. Timedemultiplexer 155 time-demultiplexes these write data bursts into two non-multiplexed write data bursts. The non-multiplexed write data bursts are respectively provided to FIFO buffer 156a and FIFO buffer 156b. Multiplexer 157a receives write data from a selected one of FIFO buffer 156a and FIFO buffer 156b and outputs the non-interleaved data received from the selected FIFO buffer 156a-156b via memory device side data interface 132a. Multiplexer 157b receives write data from a selected one of FIFO buffer 156a and FIFO buffer 156b and outputs the non-interleaved data received from the selected FIFO buffer 156a-156b via memory device side data interface 132b.

[0014] In Figure 1A, data burst “A” (i.e., data bits ao.. .asi) is time-interleaved with data burst “B” (i.e., data bits bo. . . bsi) to form time-multiplexed write data burst 170. Time- multiplexed write data burst 170 is provided to controller side data interface 154 which provides time-multiplexed write data burst 170 to time-demultiplexer 155. As timedemultiplexer 155 provides the demultiplexed bits of data burst “A” and data burst “B”, in sequence, to FIFO buffer 156a and FIFO buffer 156b, respectively, each bit is stored in a respective corresponding FIFO entry 0 through 31 starting with entry 0 and ending with entry 31.

[0015] The start of a first process beginning with loading FIFO buffers 156a-156b is illustrated in Figure 1 A by arrow 101a and arrow 101b running from respective output ports of demultiplexer 155 to FIFO buffers 156a-156b. In Figure 1A, each arrow lOla-lOlb points to entry 0 representing FIFO buffer 156a-156b insertion pointers that illustrate where the next demultiplexed bit will be placed in the respective FIFO buffer 156a-156b.

[0016] In addition, arrows 102a- 102b in Figure 1A originate from entry 0 of a respective FIFO buffer 156a- 156b representing FIFO buffer 156a- 156b output pointers that illustrate the FIFO entry where the next bit from a FIFO buffer 156a-156b will be provided from. Arrows 102a-102b each terminate at an input port to both multiplexer 157a and multiplexer 157b. Thus, multiplexer 157a may be configured to provide the data bits output by FIFO buffer 156a to memory device side data interface 132a or be configured to provide the data bitsDocket: 765-0255WO1 - 11443WO01 output by FIFO buffer 156b to memory device side data interface 132a. Similarly, multiplexer 157b may be configured to provide the data bits output by FIFO buffer 156a to memory device side data interface 132b or be configured to provide the data bits output by FIFO buffer 156b to memory device side data interface 132b.

[0017] The continuation of the process of loading FIFO buffers 156a-156b is illustrated in Figure IB. In Figure IB, the remaining portion of write data burst 170 that is yet to be received by MDB 130 is illustrated by write data burst portion 171 having bits a2-asi interleaved with bits b2-bsi in the process of being provided to controller side data interface 154. The insertion pointers represented by arrow 103a and arrow 103b each point to entry 2. Entry 0 and 1 of FIFO buffer 156a are illustrated respectively storing data bits ao and ai. Entry 0 and 1 of FIFO buffer 156b are illustrated respectively storing data bits bo and bi. Arrows 102a- 102b still originate from entry 0 of their respective FIFO buffer 156a- 156b.

[0018] The process continues with the unloading of FIFO buffers 156a-156b concurrently with the loading of FIFO buffers 156a-156b. This is illustrated in Figure 1C. In Figure 1C, the remaining portion of write data burst 170 that is yet to be received by MDB 130 is illustrated by write data burst portion 172 having bits ax-asi interleaved with bits bx-bsi in the process of being provided to controller side data interface 154. The insertion pointers represented by arrow 105a and arrow 105b each point to an unspecified entry greater than entry 2. Entries 0-2 of FIFO buffer 156a are illustrated respectively storing data bits ao-a2. Entries 0-2 of FIFO buffer 156b are illustrated respectively storing data bits bo-b2. Arrows 106a- 106b representing output pointers, however, originate from entry 1 of their respective FIFO buffer 156a-156b. In addition, partial write data burst 181a with data bits ao and ai is illustrated being transmitted by memory device side data interface 132a. Similarly, partial write data burst 181b with data bits bo and bi is illustrated being transmitted by memory device side data interface 132b.

[0019] The completion of this first process is illustrated in Figure ID. In Figure ID, write data burst 182a with data bits ao-a3i is illustrated as having been transmitted by memory device side data interface 132a. Similarly, write data burst 182b with data bits bo-bsi is illustrated as having been transmitted by memory device side data interface 132b. The insertion pointers represented by arrow 107a and arrow 107b have been returned to pointing to entry 0 to await another time-interleaved data burst. Arrows 108a- 108b representing output pointers are illustrated as originating from entry 31 indicating completion of the transmission of write data burst 182a and write data burst 182b.Docket: 765-0255WO1 - 11443WO01

[0020] In Figure IE, data burst “C” (i.e., data bits co. . .C31) is time-interleaved with data burst “D” (i.e., data bits do. . . dsi) to form time-multiplexed write data burst 175. Time- multiplexed write data burst 175 is provided to controller side data interface 154 which provides time-multiplexed write data burst 175 to time-demultiplexer 155. As timedemultiplexer 155 provides the demultiplexed bits of data burst “C” and data burst “D”, in sequence, to FIFO buffer 156a and FIFO buffer 156b, respectively, each bit is stored in a respective corresponding FIFO entry 0 through 31 starting with entry 0 and ending with entry 31.

[0021] The start of a second process beginning with loading FIFO buffers 156a- 156b is illustrated in Figure IE by arrow I l la and arrow 111b running from respective output ports of demultiplexer 155 to FIFO buffers 156a-156b. In Figure IE, each insertion pointer arrow 11 la-11 lb points to entry 0 indicating where the next demultiplexed bit will be placed in the respective FIFO buffer 156a-156b. In addition, output pointer arrows 112a-l 12b in Figure IE originate from entry 0 indicating the FIFO entry where the next bit from a FIFO buffer 156a-156b will be provided from. Arrows 112a-l 12b each terminate at an input port to both multiplexer 157a and multiplexer 157b.

[0022] The continuation of the process of loading FIFO buffers 156a-156b is illustrated in Figure IF. In Figure IF, the remaining portion of write data burst 175 that is yet to be received by MDB 130 is illustrated by write data burst portion 176 having bits C2-C31 interleaved with bits d2-dsi in the process of being provided to controller side data interface 154. The insertion pointers represented by arrow 113a and arrow 113b each point to entry 2. Entry 0 and 1 of FIFO buffer 156a are illustrated respectively storing data bits co and ci. Entry 0 and 1 of FIFO buffer 156b are illustrated respectively storing data bits do and di. Arrows 112a-l 12b still originate from entry 0 of their respective FIFO buffer 156a- 156b.

[0023] The process continues with the unloading of FIFO buffer 156a (but not FIFO buffer 156b) concurrently with the loading of FIFO buffers 156a-156b. This is illustrated in Figure 1G. In Figure 1G, the remaining portion of write data burst 175 that is yet to be received by MDB 130 is illustrated by write data burst portion 177 having bits cx-C3i interleaved with bits dx-dsi in the process of being provided to controller side data interface 154. The insertion pointers represented by arrow 115a and arrow 115b each point to an unspecified entry greater than entry 2. Entries 0-2 of FIFO buffer 156a are illustrated respectively storing data bits C0-C2. Entries 0-2 of FIFO buffer 156b are illustrated respectively storing data bits do-d2. Arrow 116a representing the output pointer for FIFO buffer 156a, however, originates from entry 1 of FIFO buffer 156a while output pointer arrowDocket: 765-0255WO1 - 11443WO01112b remains originating from entry 0 of FIFO buffer 156b. In addition, partial write data burst 185a with data bits co and ci is illustrated being transmitted by memory device side data interface 132a. No data is illustrated as being transmitted by memory device side data interface 132b.

[0024] The completion of the unloading of FIFO buffer 156a and the loading of FIFO buffer 156b is illustrated in Figure 1H. In Figure 1H, write data burst 185a with data bits co- C3i is illustrated as having been transmitted by memory device side data interface 132a. The insertion pointers represented by arrow 117a and arrow 117b have been returned to pointing to entry 0 to await another time-interleaved data burst. Output pointer arrow 118a is illustrated originating from entry 31 of FIFO buffer 156a indicating completion of the transmission of write data burst 185a. Output pointer arrow 112b remains originating from entry 0 of FIFO buffer 156b. Entries 0-31 of FIFO buffer 156b are illustrated respectively storing data bits do-dsi.

[0025] The conditions between the unloading of FIFO buffer 156a until the start of the unloading of FIFO buffer 156b are illustrated in Figure II. The insertion pointers represented by arrow 117a and arrow 117b are pointing to entry 0 to await another time-interleaved data burst. Output pointer arrow 119a for FIFO buffer 156a is illustrated originating from entry 0. Output pointer arrow 112b remains originating from entry 0 of FIFO buffer 156b. Entries 0- 31 of FIFO buffer 156b are illustrated respectively storing data bits do-dsi. No data is illustrated being transmitted via either of memory device side data interface 132a-132b.

[0026] The completion of the unloading of FIFO buffer 156b is illustrated in Figure 1 J. In Figure 1J, write data burst 186b with data bits do-dsi is illustrated as having been transmitted by memory device side data interface 132a. The insertion pointers represented by arrow 117a and arrow 117b are pointing to entry 0 to await another time-interleaved data burst. Output pointer arrow 119a for FIFO buffer 156a is illustrated originating from entry 0. Output pointer arrow 118b is illustrated originating from entry 31 of FIFO buffer 156b indicating completion of the transmission of write data burst 186b via memory device side data interface 132a.

[0027] Figure 2 is a timing diagram illustrating example operation of a multiplexing data buffer device. The timings and operations illustrated in Figure 2 may be performed by, for example, MDB 130. The sequence illustrated in Figure 2 begins with a first interleaved write data burst (WR cd data — i.e., write “c” data interleaved with write “d” data) being communicated (e.g., to MDB 130) via a controller side memory access data bus (DQ[]). After the start of the first write data burst, a first non-interleaved write data burst with theDocket: 765-0255WO1 - 11443WO01 write “c” data is communicated (e.g., from MDB 130) via a first device side memory access data bus (MDQa[]). After the first non-interleaved write data burst is finished being communicated via MDQa[], optional additional write data bursts may be communicated via MDQa[] (but not via MDQb[]), a write-to-read turnaround (e.g., delay) may occur, and then optional reads may be communicated via MDQa[] and MDQb[], During this period, the FIFO buffer associated with MDQb[] (e.g., FIFO buffer 156b) is storing the write “d” data.

[0028] The sequence continues with a first non-interleaved read data burst (RD “e” data) being communicated via MDQa[] and a second non-interleaved read data burst (RD “f” data) being communicated via MDQb[], After the start of the first and second non-interleaved read data bursts, a first interleaved read data burst with the read “e” data interleaved with the read “f ’ data is communicated (e.g., from MDB 130) via DQ[], After the completion of the first and second read non-interleaved data bursts, the MDQb[] bus is idle for a period of time (tR2w) to allow for the turnaround of the DQ[] bus from reading to writing. However, during this read-to-write delay period, a second non-interleaved write data burst with the write “d” data is transmitted via the first device side memory access data bus MDQa[],

[0029] In Figure 2, the illustrated sequence concludes with a second interleaved write data burst (WR gh data — i.e., write “g” data interleaved with write “h” data) is being communicated via a controller side memory access data bus DQ[], As a result, at the end (or after) the read-to-write delay period, a third non-interleaved write data burst (WR “g” data) being communicated via MDQa[] and a fourth non-interleaved read data burst (WR “h” data) being communicated via MDQb[],

[0030] Figure 3 is a block diagram illustrating an example memory system. In Figure 3, memory system 300 comprises memory device(s) 310, controller 320, multiplexing data buffer (MDB) 330, registering clock driver (RCD) 335, interconnect 391, and interconnect 392. Controller 320 includes command / address (CA) bus drivers 321, data (DQ) bus drivers 322, time-interleaving (a.k.a., time-multiplexing) circuitry 323, channel A data steering multiplexers 324a, and channel B data steering multiplexers 324b. MDB 330 includes DQ receivers 354, time-deinterleaving (a.k.a., time-demultiplexing) 355, channel A write FIFO buffers 356a, channel B FIFO buffers 356b, channel A data steering multiplexers 357a, channel B data steering multiplexers 357b, channel A DQ drivers 332a, and channel B DQ drivers 332b.

[0031] Controller 320, memory devices 310, MDB 330, and RCD 335 may be one or more integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as controller 320, manages the flow of data going to and from memoryDocket: 765-0255WO1 - 11443WO01 devices and / or memory modules. Memory devices 310 may be standalone devices, or may be a component of a memory module such as a DIMM module used in servers. In an embodiment, memory devices 310 may be devices that adhere to, or are compatible with, a dynamic random access memory (DRAM) specification. In an embodiment, memory devices 310 may be, or comprise, a device that is or includes other memory device technologies and / or specifications. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 320 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect. In addition, memory controller functionality may be disposed on a separate Input / Output (I / O) die along with the transmitter / receiver circuits that interface to the memory device. Such an I / O die may include other types of I / O interfaces, as well as one or more chiplet interfaces that communicate with one or more respective CPU chiplet dies. The I / O die and CPU chiplet dies may be co-packaged together and coupled to one-another via a silicon interposer.

[0032] CA bus drivers 321 of controller 320 are operatively coupled with CA bus signal input ports (CAi[]) of RCD 335. CA bus drivers 321 of controller 320 are operatively coupled with CA bus signal ports of RCD 335 to receive, from controller 320, commands and addresses that are to be relayed to memory devices 310. CA bus signal input ports (CAo[]) of RCD 335 are operatively coupled with command / address bus CA[] inputs to memory devices 310. CA bus signal input ports (CAo[]) of RCD 335 are operatively coupled with command / address bus CA[] inputs to memory devices 310 to communicate commands and addresses relayed by RCD 335 to memory devices 310. Buffer control signal bus (BCOM[]) is operatively coupled with MDB 330. Buffer control signal bus (BCOM[]) is operatively coupled with MDB 330 to control the operation (e.g., read, write, load FIFO A, load FIFO B, unload FIFO A, unload FIFO B, etc.) of MDB 330.

[0033] A first input port of data steering multiplexers 324a of controller 320 receive write data bus A bits (wDQaa[]) that are to be directed to channel A time-division multiplexing time slots (e.g., even time slot numbers). In other words, the bus name “wDQaa[]” may be viewed as “write data from channel A circuitry that is to be transmitted via the channel A data timeslots, channel A FIFOs, to memory device channel A”. A second input port of data steering multiplexers 324a of controller 320 receive write data bus B bits (wDQba[]) that are to be directed to channel A time-division multiplexing time slots (e.g., even time slotDocket: 765-0255WO1 - 11443WO01 numbers). In other words, the bus name “wDQbaf]” may be viewed as “write data from channel B circuitry that is to be transmitted via the channel A data timeslots, channel A FIFOs, to memory device channel B”. A first input port of data steering multiplexers 324b of controller 320 receive write data bus B bits (wDQbbf]) that are to be directed to channel B time-division multiplexing time slots (e.g., odd time slot numbers). In other words, the bus name “wDQbbf]” may be viewed as “write data from channel B circuitry that is to be transmitted via the channel B data timeslots, channel B FIFOs, to memory device channel B”. A second input port of data steering multiplexers 324b of controller 320 receive write data bus B bits (wDQabf]) that are to be directed to channel B time-division multiplexing time slots (e.g., odd time slot numbers). In other words, the bus name “wDQabf]” may be viewed as “write data from channel A circuitry that is to be transmitted via the channel AB data timeslots, channel B FIFOs, to memory device channel A”.

[0034] The outputs of data steering multiplexers 324a are operatively coupled with the “A” (e.g., even) timeslot inputs of time-interleaving (a.k.a., time-multiplexing) circuitry 323. The outputs of data steering multiplexers 324b are operatively coupled with the “B” (e.g., odd) timeslot inputs of time-interleaving (a.k.a., time-multiplexing) circuitry 323. The time- interleaved data generated at the outputs of time-interleaving circuitry 323 is provided to DQ bus drivers 322. The outputs of DQ bus drivers 322 are operatively coupled with DQ receivers 354 of MDB 330 via interconnect 392.

[0035] The time-interleaved data received by DQ receivers 354 of MDB 330 via interconnect 392 is provided to time-deinterleaving circuitry 355. The “A” timeslot (e.g., even) outputs of time-deinterleaving circuitry 355 are provided to channel A write FIFO buffers 356a. The “B” timeslot (e.g., odd) outputs of time-deinterleaving circuitry 355 are provided to channel B write FIFO buffers 356a. Under the control of RCD 335 (e.g., via BC0M[] signals), as described herein, FIFO buffers 356a-356b may pass the deinterleaved data received by a respective FIFO buffer 356a-356b promptly to a corresponding data steering multiplexer 357a-357b, or store the data for later transmission. Under the control of RCD 335, the output of write FIFO buffers 356a may be steered, by multiplexers 357a-357b, to either channel A DQ drivers 332a or channel B DQ drivers 332b. Similarly, under the control of RCD 335, the output of FIFO buffers 356b may be steered, by multiplexers 357a- 357b, to either channel A DQ drivers 332a or channel B DQ drivers 332b. The outputs of channel A DQ drivers 332a are provided to the channel A DQ signal ports of memory devices 310. The outputs of channel B DQ drivers 332b are provided to the channel B DQ signal ports of memory devices 310.Docket: 765-0255WO1 - 11443WO01

[0036] Figure 4 is a block diagram illustrating an example memory module. In Figure 4, module 400 comprises channel 0 dual data channel DRAM devices 410a-410e (representing five DRAM device packages A0-A4), channel Idual channel DRAM devices 41 Of-41 Oj (representing five DRAM device packages B0-B4), channel 0 multiplexing (interleaving / deinterleaving) data buffer device (MDB) 430a, channel 1 multiplexing data buffer device(s) (MDB) 430b, multiplexing registering clock driver (MRCD) 435, channel 0 DQ interface 445a, and channel 1 DQ interface 445b. MRCD 435 receives command / address signals for channel 0 (CAA), command / address signals for channel 1 (CAB), and, in some embodiments, certain signals (e.g., command / address, clock, chip select) that may be common to the channel DQ interfaces 445a-445b. MDBs 430a-430b may be, comprise, and / or perform, the example circuitry, functions, and / or operations described herein with reference to MDB 130 and / or MDB 330. MRCD 435 may be, comprise, and / or perform, the example circuitry, functions, and / or operations described herein with reference to RCD 335.

[0037] Each dual data channel DRAM device 410a-410j includes two non-overlapping set of memory arrays that respectively communicate via two pseudo-channel DQ interfaces 41 laa-41 Ijb that, with the exception of communication direction, operate independently of each other. In other words, with the exception of communication direction of their two pseudo-channel DQ interfaces 41 laa-41 Ijb, which are operated in the same communication direction, each DRAM device 410a-410j device operates the command, address, and access functions of their respective nonoverlapping sets of memory arrays independently of the other set of memory arrays on the same DRAM device 410a-410j. Thus, for example, pseudochannel A DQ interface 41 laa of DRAM device 410a communicates with a first set of memory arrays in DRAM device 410a and pseudo-channel B interface 41 lab of DRAM device 410a accesses a second set of memory arrays in DRAM device 410a, where the first set of memory arrays and the second set of memory array do not have any common memory array (i.e., are non-overlapping sets).

[0038] At least the CA signals (CAA, CAB) with commands and addresses for respective channels 0-1 of module 400 are operatively coupled to MRCD 435. MRCD 435 operatively couples the CA signals for accesses to be communicated via channel 0 DQ interface 445a to the channel 0 DRAM devices 410a-410e. Similarly, MRCD 435 operatively couples the CA signals for accesses to be communicated via channel 1 DQ interface 445b to the channel 1 DRAM devices 41 Of-4 lOj . In Figure 4, the CA signals to be communicated via channel 0 DQ interface 445a are illustrated being coupled to DRAM device 410a via CA-A1 signals from MRCD 435, being coupled to DRAM devices 41 Ob-410c via CA-A2 signals fromDocket: 765-0255WO1 - 11443WO01MRCD 435, and being coupled to DRAM devices 410d-410e via CA-A3 signals from MRCD 435. Similarly, in Figure 4, the CA signals to be communicated via channel 0 DQ interface 445b are illustrated being coupled to DRAM device 41 Of via CA-B1 signals from MRCD 435, being coupled to DRAM devices 410g-410h via CA-B2 signals from MRCD 435, and being coupled to DRAM devices 41 Oi-41 Oj via CA-B3 signals from MRCD 435.

[0039] The pseudo-channel A DQ interface 41 laa of DRAM device 410a is operatively coupled to communicate N data signals with the memory side channel 0 DQ interface 432aa of data buffer device 430a. The pseudo-channel B interface 41 lab of DRAM device 410a is also operatively coupled to communicate N data signals with memory side channel 0 DQ interface 432aa of data buffer device 430a. Data buffer device 430a interleaves / deinterleaves the N data signals communicated with pseudo-channel A DQ interface 41 laa via memory side channel 0 DQ interface 432aa with the N data signals communicated with pseudo-channel B interface 41 lab memory side channel 0 DQ interface 432aa (a total of N*2 data signals) for communication via channel 0 DQ interface 445a using N signals (see Figures 1 A-l J and Figure 2 for an example of this type of interleaving / deinterleaving between different pseudo-channel interfaces of the same device for communication with a host).

[0040] The pseudo-channel A DQ interface 41 Iba of DRAM device 410b is operatively coupled to communicate N bits of data with the memory side channel 0 DQ interface 432ab of data buffer device 430a. The channel B interface 41 Ibb of DRAM device 410b is also operatively coupled to communicate N bits of data with memory side channel 0 DQ interface 432ab of data buffer device 430a. Data buffer device 430a interleaves / deinterleaves the N data signals communicated with pseudo-channel A DQ interface 41 Iba via memory side channel 0 DQ interface 432ab with the N data signals communicated with pseudo-channel B interface 41 Ibb memory side channel 0 DQ interface 432ab (a total of N*2 data signals) for communication via channel 0 DQ interface 445a using N signals.

[0041] The pseudo-channel A DQ interface 41 lea of DRAM device 410c is operatively coupled to communicate N bits of data with the memory side channel 0 DQ interface 432ac of data buffer device 430a. The channel B interface 41 leb of DRAM device 410c is also operatively coupled to communicate N bits of data with memory side channel 0 DQ interface 432ac of data buffer device 430a. A like pattern of connections is followed for all of the DRAM devices 410a-410j and data buffer devices 430a-430b on module 400 (which, for the sake of brevity will not be further detailed herein).Docket: 765-0255WO1 - 11443WO01

[0042] Controller side interleaved channel 0 DQ interface 431a is operatively coupled to channel 0 DQ interface 445a. Similarly, controller side interleaved channel 1 DQ interface 431b is operatively coupled to channel 1 DQ interface 445b. Controller side interleaved channel 0 DQ interface 431a communicates with channel 0 DQ interface 445a using 5*N signals. Controller side interleaved channel 1 DQ interface 431b communicates with channel 1 DQ interface 445b using 5*N signals. The 5*N signals communicated via each of channel 0 DQ interface 445a and channel 1 DQ interface 445b comprise N signals communicated with each of two (2) pseudo-channel DQ interfaces (i.e., N*2 signals per package 410a-410e) of each of five (5) DRAM packages (i.e., N*2 signals per package 410a-410e times five packages is N*2*5) for a total of Nx 10 number of signals that are time-multiplexed and demultiplexed (i.e., interleaved and deinterleaved) by a respective MDB 430a-430b down to [Nx2x5] / 2=5*N number of signals communicated via a respective pseudo-channel DQ interface 445a-445b. Thus, for example, for N=2, twenty (20) data signals are communicated with memory side channel 0 DQ interfaces 432aa-432ae of data buffer device 430a at a first data rate and ten (10) data signals are communicated via channel 0 DQ interface 445a at double the first data rate. Similarly, twenty (20) data signals are communicated with memory side channel 1 DQ interfaces 432bf-432bj of data buffer device 430b at the first data rate and ten (10) data signals are communicated via channel 1 DQ interface 445b at double the first data rate.

[0043] Figure 5 is a flowchart illustrating a method of operating a memory module. One or more of the steps illustrated in Figure 5 may be performed by, for example, buffer 130, system 300, module 400, and / or their components. From a controller and by a memory data buffer device, a first host data burst time-interleaved with a second host data burst is received (502). For example, MDB 130 may receive, from a controller (e.g., controller 320), data burst 170 which includes data burst “A” (i.e., data bits ao.. .asi) time-interleaved with data burst “B” (i.e., data bits bo. . . bsi).

[0044] From the controller and by the memory data buffer device, a third host data burst time-interleave with a fourth host data burst may be received (504). For example, MDB 130 may receive, from the controller, data burst 175 which includes data burst “c” (i.e., data bits co. . . C3i) time-interleaved with data burst “D” (i.e., data bits do. . . dsi). By the memory data buffer device, the first host data burst is transmitted to a first memory device data interface (506). For example, by MDB 130, write data burst 182a consisting of data bits ao. . .asi may be transmitted via memory device side data interface 132a (e.g., to pseudo-channel A DQ interface 41 laa of DRAM device 410a). By the memory data buffer device, the second hostDocket: 765-0255WO1 - 11443WO01 data burst is transmitted to a second memory device data interface (508). For example, by MDB 130, data burst 182b consisting of data bits bo. . . bsi may be transmitted via memory device side data interface 132b (e.g., to pseudo-channel B interface 41 lab of DRAM device 410a).

[0045] By the memory data buffer device, the third host data burst is transmitted to the first memory device data interface (510). For example, by MDB 130, data burst 186a consisting of data bits co. . ,C3i may be transmitted via memory device side data interface 132a (e.g., to pseudo-channel A DQ interface 41 laa of DRAM device 410a). By the memory data buffer device, the fourth host data burst is transmitted to the first memory device data interface (512). For example, by MDB 130, write data burst 186b consisting of data bits do. . . dsi may be transmitted via memory device side data interface 132a (e.g., to pseudochannel A DQ interface 41 laa of DRAM device 410a).

[0046] Figure 6 is a flowchart illustrating a method of operating a memory controller. One or more of the steps illustrated in Figure 6 may be performed by, for example, buffer 130, system 300, module 400, and / or their components. To a module, a first command to write a first data burst via a first memory device data interface and a second data burst via a second memory device data interface is transmitted (602). For example, controller 320 may transmit, to RCD 335 disposed on a module (e.g., module 400) a first command to write a first data burst (e.g., data bits ao.. . asi) via MDQa[] of memory devices 310 and to write a second data burst (e.g., data bits bo. . . bsi) via MDQb[] of memory devices 310. To the module, the first data burst is transmitted time-interleaved with the second data burst (604). For example, controller 320 may transmit, to MDB 330 disposed on the module, the first data burst time-interleaved with the second data burst (e.g., data burst 170).

[0047] To the module, a second command to write a third data burst via the first memory device data interface and to store a fourth data burst in a data buffer device is transmitted (608). For example, controller 320 may transmit, to RCD 335 disposed on the module a second command to write a third data burst (e.g., data bits co. . . C3i) via MDQa[] of memory devices 310 and to store a fourth data burst (e.g., data bits do. . . dsi) in a FIFO buffer 356b. To the module, the third data burst is transmitted time-interleaved with the fourth data burst (608). For example, controller 320 may transmit, to MDB 330 disposed on the module, the third data burst time-interleaved with the fourth data burst (e.g., data burst 175). To the module, a third command to write the fourth data burst via the first memory device interface is transmitted (610). For example, controller 320 may transmit, to RCD 335 disposed on theDocket: 765-0255WO1 - 11443WO01 module, a third command to write the fourth data burst (e.g., data bits do. . . dsi) to MDQa[] of memory devices 310.

[0048] Figure 7 is a flowchart illustrating a method of operating a multiplexing data buffer device. One or more of the steps illustrated in Figure 7 may be performed by, for example, buffer 130, system 300, module 400, and / or their components. A first command to transmit a first data burst via a first memory device data interface and a second data burst via a second memory device data interface is received (702). For example, MDB 330 may receive, from RCD 335, a first command to deinterleave quad-data rate write data received via DQ receivers 354 and transmit a first double data rate deinterleaved data burst (e.g., data burst 182a) via channel A DQ drivers 332a to MDQa[] of memory devices 310 and to also transmit a second double data rate deinterleaved data burst (e.g., data burst 182b) via channel B DQ drivers 332b to MDQb[] of memory devices 310.

[0049] Based on the first command, the first data burst time-interleaved with the second data burst is received (704). For example, MDB 330 may receive, from controller 320 and via DQ receivers 354, quad-data rate write data that comprises data directed to MDBa[] of memory devices 310 time-interleaved with data directed to MDBb[] of memory devices 310. Based on the first command, the first data burst is transmitted via the first memory device data interface and the second data burst is transmitted via the second memory device data interface (706). For example, MDB 330 may transmit the deinterleaved write data directed to MDBa[] of memory devices 310 via channel A DQ drivers 332a and the deinterleaved write data directed to MDBb[] of memory devices 310 via channel B DQ drivers 332b.

[0050] A second command to transmit a third data burst via the first memory device data interface and to store a fourth data burst is received (708). For example, MDB 330 may receive, from RCD 335, a second command to deinterleave quad-data rate write data received via DQ receivers 354 and transmit a third double data rate deinterleaved data burst (e.g., data burst 186a) via channel A DQ drivers 332a to MDQa[] of memory devices 310 and to also store a fourth data burst in write FIFO buffers 356b. Based on the second command, the third data burst time-interleaved with the fourth data burst is received (710). For example, MDB 330 may receive, from controller 320 and via DQ receivers 354, quad-data rate write data that comprises data directed to MDBa[] of memory devices 310 time-interleaved with data to be stored in write FIFO buffers 356b.

[0051] Based on the second command, the third data burst is transmitted via the first memory device data interface and the fourth data burst is stored in a FIFO buffer (712). For example, MDB 330 may transmit the deinterleaved write data directed to MDBa[] of memoryDocket: 765-0255WO1 - 11443WO01 devices 310 via channel A DQ drivers 332a and store the deinterleaved write data to be stored in write FIFO buffers 356b, in write FIFO buffers 356b. A third command to transmit the fourth data burst via the first memory device data interface is received (714). For example, MDB 330 may receive, from RCD 335, a third command to transmit the deinterleaved write data stored in write FIFO buffers 356b via channel A DQ drivers 332a. Based on the third command, the fourth data burst is transmitted via the first memory device data interface (716). For example, MDB 330 may transmit the deinterleaved write data stored in write FIFO buffers 356b via channel A DQ drivers 332a.

[0052] Figure 8 is a flowchart illustrating a method of operating a memory module. One or more of the steps illustrated in Figure 8 may be performed by, for example, buffer 130, system 300, module 400, and / or their components. A first command to write a first data burst via a first memory device data interface and a second data burst via a second memory device data interface is received (802). For example, RCD 335 may receive, from controller 320, a first command to write a first data burst (e.g., data bits ao.. . au) via MDQa[] of memory devices 310 and to write a second data burst (e.g., data bits bo. . . bsi) via MDQb[] of memory devices 310. The first data burst is received time-interleaved with the second data burst (804). For example, MDB 330 may receive, from controller 320, the first data burst time- interleaved with the second data burst (e.g., data burst 170).

[0053] A second command to write a third data burst via the first memory device data interface and to store a fourth data burst in a data buffer device is received (806). For example, RCD 335 may receive, from controller 320, a second command to write a third data burst (e.g., data bits co. . . C3i) via MDQa[] of memory devices 310 and to store a fourth data burst (e.g., data bits do. . . dsi) in a FIFO buffer 356b. The third data burst is received time- interleaved with the fourth data burst (808). For example, MDB 330 may receive, from controller 320, the third data burst time-interleaved with the fourth data burst (e.g., data burst 175). A third command to write the fourth data burst via the first memory device interface is received (810). For example, RCD 335 may receive, from controller 320, a third command to write the fourth data burst (e.g., data bits do. . . ds i) to MDQa[] of memory devices 310.

[0054] Figure 9 is a flowchart illustrating a method of operating a registering clock driver device. One or more of the steps illustrated in Figure 9 may be performed by, for example, buffer 130, system 300, module 400, and / or their components. A first command to write a first data burst via a first memory device data interface and a second data burst via a second memory device data interface is received (902). For example, RCD 335 may receive, from controller 320, a first command to write a first data burst (e.g., data bits ao. . . asi) via MDQa[]Docket: 765-0255WO1 - 11443WO01 of memory devices 310 and to write a second data burst (e.g., data bits bo. . .bsi) via MDQb[] of memory devices 310. Based on the first command, a second command and a third command are transmitted to a DRAM device, to respectively receive the first data burst and the second data burst (904). For example, based on the first command, RCD 335 may transmit, to DRAM devices 310, a second command to receive the first data burst via MDAa[] and a third command to receive the second data burst via MDQb[], Based on the first command, a fourth command to receive the first data burst time-interleaved with the second data burst is transmitted to a buffer device (906). For example, RCD 335 may transmit, to MDB 330, a fourth command to receive the first data burst time-interleaved with the second data burst (e.g., data burst 170) where the first data burst is to be transmitted promptly to memory devices 310 via channel A DQ drivers 332a and the second data burst is to be transmitted promptly to memory devices 310 via channel B DQ drivers 332b.

[0055] A fifth command to write a third data burst via the first memory device data interface and to store a fourth data burst in a data buffer device is received (908). For example, RCD 335 may receive, from controller 320, a fifth command to write a third data burst (e.g., data bits co. . . C3i) via MDQa[] of memory devices 310 and to store a fourth data burst (e.g., data bits do. . . dsi) in a FIFO buffer 356b. Based on the fifth command, a sixth command is transmitted, to to the DRAM device, to receive the third data burst (910). For example, based on the fifth command, RCD 335 may transmit, to DRAM devices 310, a sixth command to receive the third data burst via MDAa[], Based on the fifth command, a seventh command to receive the third data burst time-interleaved with the fourth data burst is transmitted to a buffer device (912). For example, RCD 335 may transmit, to MDB 330, a command to receive the third data burst time-interleaved with the fourth data burst (e.g., data burst 175) where the third data burst is to be transmitted promptly to memory devices 310 via channel A DQ drivers 332a and the fourth data burst is to be stored in FIFO buffers 356b.

[0056] An eighth command to write the fourth data burst via the first memory device interface is received (914). For example, RCD 335 may receive, from controller 320, an eighth command to write the fourth data burst (e.g., data bits dO. . . d31) to MDQa[] of memory devices 310. Based on the eighth command, a ninth command is transmitted, to the DRAM device, to receive the third data burst (916). For example, based on the eighth command, RCD 335 may transmit, to DRAM devices 310, a ninth command to receive the fourth data burst via MDAa[], Based on the eighth command, a tenth command to transmit the fourth data burst via the first memory device data interface is transmitted (918). For example, RCD 335 may transmit, to MDB 330, a command to transmit the fourth data burstDocket: 765-0255WO1 - 11443WO01(e.g., data burst 186a) stored in FIFO buffers 356b to memory devices 310 via channel A DQ drivers 332a.

[0057] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of buffer 130, system 300, and / or module 400, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry -level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0058] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0059] Figure 10 is a block diagram illustrating one embodiment of a processing system 1000 for including, processing, or generating, a representation of a circuit component 1020. Processing system 1000 includes one or more processors 1002, a memory 1004, and one or more communications devices 1006. Processors 1002, memory 1004, and communications devices 1006 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1008.

[0060] Processors 1002 execute instructions of one or more processes 1012 stored in a memory 1004 to process and / or generate circuit component 1020 responsive to user inputs 1014 and parameters 1016. Processes 1012 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 1020 includes data that describes all or portions of buffer 130, system 300, and / or module 400, and their components, as shown in the Figures.Docket: 765-0255WO1 - 11443WO01

[0061] Representation 1020 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 1020 may be stored on storage media or communicated by carrier waves.

[0062] Data formats in which representation 1020 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.

[0063] User inputs 1014 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1016 may include specifications and / or characteristics that are input to help define representation 1020. For example, parameters 1016 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0064] Memory 1004 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1012, user inputs 1014, parameters 1016, and circuit component 1020.

[0065] Communications devices 1006 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1000 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1006 may transmit circuit component 1020 to another system. Communications devices 1006 may receive processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 and cause processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 to be stored in memory 1004.

[0066] Implementations discussed herein include, but are not limited to, the following examples:

[0067] Example 1 : A module, comprising: a host data interface to receive a first host data burst directed to a first memory device data interface time-interleaved with a second host data burst directed to a second memory device data interface, and to receive a third host dataDocket: 765-0255WO1 - 11443WO01 burst directed to the first memory device data interface time-interleaved with a fourth host data burst directed to the first memory device data interface; and a memory data buffer device to receive the first host data burst time-interleaved with the second host data burst and the third host data burst time-interleaved with the fourth host data burst, the memory data buffer device to transmit, to the first memory device data interface as non-interleaved data bursts, the first host data burst, the third host data burst, and the fourth host data burst, the memory data buffer device to also transmit, to the second memory device data interface as a noninterleaved data burst, the second host data burst.

[0068] Example 2: The module of example 1, wherein a first memory integrated circuit die includes the first memory device data interface and a second memory integrated circuit die includes the second memory device data interface.

[0069] Example 3: The module of example 1, wherein a first memory integrated circuit die includes the first memory device data interface and the second memory device data interface.

[0070] Example 4: The module of example 1, wherein the first host data burst and the third host data burst are coupled between the host data interface and the first memory device data interface via a first first-in first-out (FIFO) buffer of the memory data buffer device, the second host data burst is coupled between the host data interface and the second memory device data interface via a second FIFO buffer of the memory data buffer device, and the fourth host data burst is coupled between the host data interface and the first memory device data interface via the second FIFO buffer of the memory data buffer device.

[0071] Example 5: The module of example 4, wherein the second FIFO stores the fourth host data burst while at least a first device data burst is transmitted via the host data interface.

[0072] Example 6: The module of example 5, wherein the fourth host data burst is transmitted between a first transmission, by the memory data buffer device, of the first device data burst to the host data interface and a second transmission, by the memory data buffer device, of a fifth host data burst to the first memory device data interface.

[0073] Example 7: The module of example 6, further comprising: a registering clock driver device to transmit commands to the memory data buffer device.

[0074] Example 8: A module, comprising: a first memory device disposed on the module and including a first memory device data interface; a second memory device disposed on the module and including a second memory device data interface; a host data interface; and a memory data buffer device coupled with the host data interface, the first memory device data interface, and the second memory device data interface, the memory data buffer device toDocket: 765-0255WO1 - 11443WO01 receive, via the host data interface, a first host data burst time-interleaved with a second host data burst, and to receive, via the host data interface, a third host data burst time-interleaved with a fourth host data burst, the memory data buffer device to transmit the first host data burst to the first memory device data interface, and to transmit the third host data burst to the first memory device data interface, and to transmit the fourth host data burst to the first memory device data interface, and to transmit the second host data burst to the second memory device data interface.

[0075] Example 9: The module of example 8, wherein a first memory integrated circuit die includes the first memory device data interface and a second memory integrated circuit die includes the second memory device data interface.

[0076] Example 10: The module of example 8, wherein a first memory integrated circuit die includes the first memory device data interface and the second memory device data interface.

[0077] Example 11 : The module of example 8, wherein the first host data burst and the third host data burst are coupled between the host data interface and the first memory device data interface via a first first-in first-out (FIFO) buffer of the memory data buffer device, the second host data burst is coupled between the host data interface and the second memory device data interface via a second FIFO buffer of the memory data buffer device, and the fourth host data burst is coupled between the host data interface and the first memory device data interface via the second FIFO buffer of the memory data buffer device.

[0078] Example 12: The module of example 11, wherein the second FIFO stores the fourth host data burst while at least a first device data burst is transmitted via the host data interface.

[0079] Example 13: The module of example 12, wherein the fourth host data burst is transmitted between a first transmission, by the memory data buffer device, of the first device data burst to the host data interface and a second transmission, by the memory data buffer device, of a fifth host data burst to the first memory device data interface.

[0080] Example 14: The module of example 6, further comprising: a registering clock driver device to transmit a command to the memory data buffer device to store the fourth host data burst in the second FIFO.

[0081] Example 15: A method of operating a memory data buffer device, comprising: receiving, from a controller, a first host data burst time-interleaved with a second host data burst; receiving, from the controller, a third host data burst time-interleaved with a fourth host data burst; transmitting, by the memory data buffer device, the first host data burst to a firstDocket: 765-0255WO1 - 11443WO01 memory device data interface; transmitting, by the memory data buffer device, the second host data burst to a second memory device data interface; transmitting, by the memory data buffer device, the third host data burst to the first memory device data interface; and transmitting, by the memory data buffer device, the fourth host data burst to the first memory device data interface.

[0082] Example 16: The method of example 15, wherein the first memory device data interface is disposed on a first memory integrated circuit die and the second memory device data interface is disposed on a second memory integrated circuit die.

[0083] Example 17: The method of example 15, wherein the first memory device data interface and the second memory device data interface are disposed on a first memory integrated circuit die.

[0084] Example 18: The method of example 15, further comprising: storing at least a first portion of the first host data burst in a first first-in first-out (FIFO) buffer; storing at least a second portion of the second host data burst in a second FIFO buffer; storing at least a third portion of the third host data burst in the first FIFO buffer; and storing the fourth host data burst in the second FIFO buffer.

[0085] Example 19: The method of example 18, further comprising: receiving, from a registering clock driver integrated circuit, a command to store the fourth host data burst in the second FIFO buffer.

[0086] Example 20: The method of example 18, further comprising: receiving, from a registering clock driver integrated circuit, a command to transmit the fourth host data burst stored in the second FIFO buffer to the first memory device data interface.

[0087] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

Docket: 765-0255WO1 - 11443WO01CLAIMSWhat is claimed is:

1. A module, comprising: a host data interface to receive a first host data burst directed to a first memory device data interface time-interleaved with a second host data burst directed to a second memory device data interface, and to receive a third host data burst directed to the first memory device data interface time-interleaved with a fourth host data burst directed to the first memory device data interface; and a memory data buffer device to receive the first host data burst time-interleaved with the second host data burst and the third host data burst time-interleaved with the fourth host data burst, the memory data buffer device to transmit, to the first memory device data interface as non-interleaved data bursts, the first host data burst, the third host data burst, and the fourth host data burst, the memory data buffer device to also transmit, to the second memory device data interface as a non-interleaved data burst, the second host data burst.

2. The module of claim 1, wherein a first memory integrated circuit die includes the first memory device data interface and a second memory integrated circuit die includes the second memory device data interface.

3. The module of claim 1, wherein a first memory integrated circuit die includes the first memory device data interface and the second memory device data interface.

4. The module of claim 1, wherein the first host data burst and the third host data burst are coupled between the host data interface and the first memory device data interface via a first first-in first-out (FIFO) buffer of the memory data buffer device, the second host data burst is coupled between the host data interface and the second memory device data interface via a second FIFO buffer of the memory data buffer device, and the fourth host data burst is coupled between the host data interface and the first memory device data interface via the second FIFO buffer of the memory data buffer device.

5. The module of claim 4, wherein the second FIFO stores the fourth host data burst while at least a first device data burst is transmitted via the host data interface.Docket: 765-0255WO1 - 11443WO016. The module of claim 5, wherein the fourth host data burst is transmitted between a first transmission, by the memory data buffer device, of the first device data burst to the host data interface and a second transmission, by the memory data buffer device, of a fifth host data burst to the first memory device data interface.

7. The module of claim 6, further comprising: a registering clock driver device to transmit commands to the memory data buffer device.

8. A module, comprising: a first memory device disposed on the module and including a first memory device data interface; a second memory device disposed on the module and including a second memory device data interface; a host data interface; and a memory data buffer device coupled with the host data interface, the first memory device data interface, and the second memory device data interface, the memory data buffer device to receive, via the host data interface, a first host data burst time-interleaved with a second host data burst, and to receive, via the host data interface, a third host data burst time-interleaved with a fourth host data burst, the memory data buffer device to transmit the first host data burst to the first memory device data interface, and to transmit the third host data burst to the first memory device data interface, and to transmit the fourth host data burst to the first memory device data interface, and to transmit the second host data burst to the second memory device data interface.

9. The module of claim 8, wherein a first memory integrated circuit die includes the first memory device data interface and a second memory integrated circuit die includes the second memory device data interface.

10. The module of claim 8, wherein a first memory integrated circuit die includes the first memory device data interface and the second memory device data interface.Docket: 765-0255WO1 - 11443WO0111. The module of claim 8, wherein the first host data burst and the third host data burst are coupled between the host data interface and the first memory device data interface via a first first-in first-out (FIFO) buffer of the memory data buffer device, the second host data burst is coupled between the host data interface and the second memory device data interface via a second FIFO buffer of the memory data buffer device, and the fourth host data burst is coupled between the host data interface and the first memory device data interface via the second FIFO buffer of the memory data buffer device.

12. The module of claim 11, wherein the second FIFO stores the fourth host data burst while at least a first device data burst is transmitted via the host data interface.

13. The module of claim 12, wherein the fourth host data burst is transmitted between a first transmission, by the memory data buffer device, of the first device data burst to the host data interface and a second transmission, by the memory data buffer device, of a fifth host data burst to the first memory device data interface.

14. The module of claim 6, further comprising: a registering clock driver device to transmit a command to the memory data buffer device to store the fourth host data burst in the second FIFO.

15. A method of operating a memory data buffer device, comprising: receiving, from a controller, a first host data burst time-interleaved with a second host data burst; receiving, from the controller, a third host data burst time-interleaved with a fourth host data burst; transmitting, by the memory data buffer device, the first host data burst to a first memory device data interface; transmitting, by the memory data buffer device, the second host data burst to a second memory device data interface; transmitting, by the memory data buffer device, the third host data burst to the first memory device data interface; and transmitting, by the memory data buffer device, the fourth host data burst to the first memory device data interface.Docket: 765-0255WO1 - 11443WO0116. The method of claim 15, wherein the first memory device data interface is disposed on a first memory integrated circuit die and the second memory device data interface is disposed on a second memory integrated circuit die.

17. The method of claim 15, wherein the first memory device data interface and the second memory device data interface are disposed on a first memory integrated circuit die.

18. The method of claim 15, further comprising: storing at least a first portion of the first host data burst in a first first-in first-out (FIFO) buffer; storing at least a second portion of the second host data burst in a second FIFO buffer; storing at least a third portion of the third host data burst in the first FIFO buffer; and storing the fourth host data burst in the second FIFO buffer.

19. The method of claim 18, further comprising: receiving, from a registering clock driver integrated circuit, a command to store the fourth host data burst in the second FIFO buffer.

20. The method of claim 18, further comprising: receiving, from a registering clock driver integrated circuit, a command to transmit the fourth host data burst stored in the second FIFO buffer to the first memory device data interface.

Images