Chip and manufacturing method therefor, and electronic device

Abstract

The present application relates to the technical field of chips, and provides a chip and a manufacturing method therefor, and an electronic device. Implementing bonding by means of back-to-back hybrid bonding can solve various problems in a BSPDN architecture caused by providing both an IO circuit and a logic circuit on the front side of a chip, and the problem of the reduction of power grid density in the top layer of a 3D chip. The chip comprises: a first substrate and a second substrate, wherein the back surface of the second substrate is bonded to the back surface of the first substrate by means of a bonding surface. A first logic circuit is provided on the front surface of the first substrate. A first IO circuit, a first power delivery network, and a plurality of first pads are all provided on the front surface of the second substrate. A plurality of through silicon via structures run through the first substrate and the second substrate, and at least one through silicon via is formed in each through silicon via structure. The first IO circuit is connected to the first logic circuit by means of the plurality of through silicon via structures, and the plurality of first pads are connected to the first IO circuit.

Description

Chips and their manufacturing methods, electronic devices Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip and its manufacturing method, and an electronic device. Background Technology

[0002] In traditional chip manufacturing processes, both signal networks and power networks are located on the front side of the wafer. However, with the evolution of process nodes, the number of devices within a chip has increased significantly. To maintain a constant chip area, the number of wiring layers on the front side has increased, leading to an increase in the length of the power network (power supply path). This makes the resistance-induced voltage drop (IR drop) and signal interference problems increasingly severe. To address this issue, existing technologies provide a backside power delivery network (BSPDN) technology, which places the power network on the back side of the wafer, thereby decoupling the power network from the signal network and resolving the contradiction between IR drop and area miniaturization.

[0003] Referring to Figure 1, current BSPDN structures share a common feature: active circuits (including input / output circuits and logic circuits) are placed on the front side of the wafer, while passive structures such as the power delivery network (PDN) and pads are placed on the back side. The pads are connected to the input / output circuits (IO circuits) through large through silicon vias (TSVs), and the PDN is connected to the logic circuits through small TSVs. This configuration has several drawbacks:

[0004] 1. Connecting pads to I / O circuits via TSVs increases the parasitic resistance between the pads and the I / O circuits. Since the connection between pads and I / O circuits often needs to consider scenarios with large ESD (electrostatic discharge) currents, the parasitic resistance of this path needs to be as low as possible. This requires a larger TSV array, which occupies a larger chip area.

[0005] 2. Both I / O circuits and logic circuits are located on the front side of the wafer and need to be fabricated using the same process. However, with the development of CMOS (complementary metal oxide semiconductor) technology, logic circuits often use advanced processes to fabricate small-channel devices, and the operating voltage of these devices is continuously decreasing, often below 1V. I / O circuits, as modules that interact with the external environment, require higher power supply voltages, typically 3V or 5V. Therefore, if I / O circuits use the same process as logic circuits, the devices in the I / O circuits need to be designed with withstand voltage to address input / output reliability issues. Summary of the Invention

[0006] This application provides a chip and its fabrication method, as well as an electronic device. By placing the I / O circuit and logic circuit on different substrate surfaces and bonding them using a back-to-back hybrid bonding method, it can solve various problems caused by the fact that the I / O circuit and logic circuit are both placed on the front side of the chip in the existing BSPDN structure.

[0007] This application provides a chip including a first substrate, a second substrate, a first logic circuit, a first I / O circuit, a first power supply network (also referred to as a back power supply network), a plurality of first pads, and a plurality of through-silicon via (TSV) structures. The back side of the second substrate is bonded to the back side of the first substrate via a bonding surface. The first logic circuit is disposed on the front side of the first substrate. The first I / O circuit, the first power supply network, and the plurality of first pads are all disposed on the front side of the second substrate. The TSV structure includes at least one TSV and penetrates through both the first and second substrates. The first I / O circuit is connected to the first logic circuit through the plurality of TSV structures, and the plurality of first pads are connected to the first I / O circuit.

[0008] The substrate structure in this application uses a back-to-back bonding method between the first substrate and the second substrate. When applied to BSPDN technology, this configuration places the first IO circuit and the first logic circuit on the surfaces of two different substrates (the first substrate and the second substrate). The first power supply network and the first IO circuit are connected to the first logic circuit through multiple through-silicon via structures to meet the power supply and input / output requirements of the first logic circuit.

[0009] In this configuration, the first I / O circuit and the first logic circuit can be fabricated using different processes, offering greater manufacturing flexibility. Furthermore, compared to existing BSPDN technology where the pads need to be connected to the I / O circuit via TSVs, in the chip provided in this application, both the first pad and the first I / O circuit are located on the back of the chip (i.e., the front side of the second substrate). The connection between the first I / O circuit and the first pad does not require a TSV, thus shortening the transmission path between the pad and the I / O circuit, reducing the parasitic resistance between them, and making it more suitable for high-current ESD scenarios.

[0010] Furthermore, in this application, the first substrate and the second substrate are bonded back-to-back. When this back-to-back bonding architecture is applied to 3D (dimensional) chip products, the 3D chip can also include a second logic circuit and a second power supply network (also known as a front-side power supply network, FSPDN). The second logic circuit is located on the front side of the second substrate and is connected to the first logic circuit through multiple through-silicon vias (TSVs). Both the first I / O circuit and the first power supply network (BSPDN) are connected to the second logic circuit to meet its power supply and input / output requirements. The second power supply network is located on the front side of the first substrate and is connected to the first logic circuit to meet its power consumption requirements.

[0011] Compared to existing technologies that use face-to-face (or back-to-face) bonding architectures, which disrupt the power mesh on the top layer of the two chips, leading to reduced power mesh density and consequently IR drop, the proposed method uses a back-to-back bonding approach. Through-silicon vias (TSVs) are used to achieve electrical interconnection between the power and signal layers of the two chips. This bonding structure does not occupy the thick metal layer on the top surface of the two chips and does not affect the top-layer metal wiring resources. This increases the power mesh density, reduces the parasitic resistance of the system power network, lowers the risk of IR drop, and improves power efficiency.

[0012] In some possible implementations, the first I / O circuit is connected to both the first logic circuit and the second power supply network (FSPDN) via multiple through-silicon vias (TSVs). In this case, in the 3D chip, while the first I / O circuit on the back of the chip satisfies the input / output requirements of the second logic circuit, the first I / O circuit on the back is connected to the first logic circuit on the front via TSVs. Thus, the first I / O circuit simultaneously satisfies the input / output requirements of both the first and second logic circuits, and the second power supply network obtains power through the first I / O circuit.

[0013] In some possible implementations, the chip also includes a second I / O circuit and multiple second pads located on the front side of the first substrate. The multiple second pads are connected to the second I / O circuit, and both the first logic circuit and the second power supply network are connected to the second I / O circuit. In this case, on the back side of the chip, the first I / O circuit and the first power supply network are connected to the second logic circuit to meet the power supply and input / output requirements of the second logic circuit; on the front side of the chip, the second I / O circuit and the second power supply network are connected to the first logic circuit to meet the input / output requirements of the first logic circuit. That is, the first logic circuit and the second logic circuit have independent power supply and input / output. In this configuration, the power, ground, and signal of the upper chip are interconnected with the upper substrate through the second pads, and the power, ground, and signal of the lower chip are interconnected with the lower substrate through the first pads. The upper and lower chips have independent power supply and input / output. Furthermore, in this configuration, signal transmission between the upper and lower chips is achieved through a through-silicon via (TSV) structure, thereby shortening the signal transmission distance between the upper and lower chips, reducing transmission path delay, and improving the performance of the circuit module.

[0014] In some possible implementations, the through-silicon via (TSV) structure includes a first TSV and a second TSV, with the first TSV penetrating a first substrate and the second TSV penetrating a second substrate. The first and second TSVs are electrically connected at a bonding surface. In this case, the TSV structure can be fabricated in segments, thereby reducing fabrication complexity. For example, the first TSV can be fabricated in the first substrate first, the second TSV in the second substrate, and then the first and second substrates can be bonded together.

[0015] In some possible implementations, the first through-silicon via (TSV) and the second TSV are directly bonded at the bonding surface. Direct bonding of TSVs offers the advantage of simple process, and is particularly suitable for larger TSVs.

[0016] In some possible implementations, the chip also includes multiple first micropads and multiple second micropads; the first micropads are located on the side of the first through-silicon via (TSV) near the second TSV and are connected to the first TSV, and the second micropads are located on the side of the second TSV near the first TSV and are connected to the second TSV. The first and second micropads are bonded together at the bonding surface. Using micropads for bonding can increase the bonding area, reduce the bonding difficulty, and thus reduce manufacturing costs.

[0017] In some possible implementations, the first and second through-silicon vias (TSVs) are connected by metal traces. With this configuration, the arrangement of multiple first and second TSVs does not need to be mirror images, increasing the flexibility of the TSVs during bonding and reducing the need for precise alignment.

[0018] In some possible implementations, multiple capacitor structures are also disposed on the front side of the second substrate, and these capacitor structures are connected to the first power supply network. The multiple capacitor structures include at least one of MOM (metal oxide metal) capacitors and MOS (metal oxide semiconductor) capacitors. Because active devices (IO circuits) are fabricated on the back side of the chip (i.e., the front side of the second substrate), the number of metal layers on the back side of the chip can be increased, thereby allowing the fabrication of one or more capacitor structures on the front side of the second substrate. These multiple capacitor structures can be used to filter and decouple the power supply signal provided by the first power supply network.

[0019] In some possible implementations, the chip is a system-on-a-chip (SOC).

[0020] This application also provides a method for fabricating a chip, which may include: fabricating a first semiconductor structure, including: providing a first substrate, forming a plurality of first through-silicon vias (TSVs) penetrating the first substrate, and fabricating a first logic circuit connected to the plurality of TSVs on the front side of the first substrate. Fabricating a second semiconductor structure, including: providing a second substrate, forming a plurality of second TSVs penetrating the second substrate, and fabricating a first I / O circuit, a first power supply network connected to the first I / O circuit, and a plurality of first pads on the front side of the second substrate; wherein the first I / O circuit and the first power supply network are respectively connected to the plurality of second TSVs. The first semiconductor structure and the second semiconductor structure are bonded to the back side of the first substrate and the back side of the second substrate through the back side of the first substrate, and the plurality of first TSVs and the plurality of second TSVs are electrically connected at the bonding surface to form a TSV structure, so that the first power supply network and the first I / O circuit are respectively connected to the first logic circuit through the plurality of TSV structures.

[0021] When fabricating a chip using the BSPDN architecture using the above method, the first I / O circuit and the first logic circuit are respectively placed on two different substrates (the first substrate and the second substrate), and the first substrate and the second substrate are bonded back-to-back. Furthermore, in this fabrication method, the first I / O circuit and the first logic circuit can be fabricated using different processes, providing greater fabrication flexibility. Compared to existing BSPDN technology where the pads need to be connected to the I / O circuit via TSVs, in this chip, both the first pad and the first I / O circuit are fabricated on the front side of the second substrate. The connection between the first I / O circuit and the first pad does not require a TSV, thus shortening the transmission path between the pad and the I / O circuit, reducing the parasitic resistance between the pad and the I / O circuit, and thus being more conducive to meeting the high-current ESD requirements.

[0022] This application also provides a method for fabricating a chip, which may include: fabricating a first semiconductor structure, including: providing a first substrate, forming a plurality of first through-silicon vias (TSVs) penetrating the first substrate, and fabricating a first logic circuit and a second power supply network (FSPDN) on the front side of the first substrate; wherein the first logic circuit is connected to the second power supply network (FSPDN) and the plurality of first TSVs. Fabricating a second semiconductor structure, including: providing a second substrate, forming a plurality of second TSVs penetrating the second substrate, and fabricating a first I / O circuit, a first power supply network (BSPDN) connected to the first I / O circuit, a second logic circuit, and a plurality of first pads on the front side of the second substrate; wherein the second logic circuit is connected to the first power supply network (BSPDN) and the plurality of second TSVs. The first semiconductor structure and the second semiconductor structure are bonded together through the back side of the first substrate and the back side of the second substrate, wherein the plurality of first TSVs and the plurality of second TSVs are electrically connected at the bonding surface to form a TSV structure, such that the second logic circuit is connected to the first logic circuit through the plurality of TSV structures, and the first I / O circuit is connected to the first logic circuit and the second power supply network (FSPDN) through the plurality of TSV structures.

[0023] Compared to the face-to-face (or back-to-face) bonding architecture used in existing technologies, the bonding structure will destroy the power mesh on the top layer of the two chips, resulting in a decrease in the density of the power mesh and thus causing IR drop.

[0024] When fabricating 3D chips using the above method, the first and second substrates are bonded back-to-back, and the electrical interconnection between the power supply and signals between the two chips is achieved through a through-silicon via (TSV) structure. The bonding structure does not occupy the thick metal layer on the top surface of the two chips and does not affect the top metal wiring resources of the two chips. This increases the density of the power mesh, reduces the parasitic resistance of the system power network, reduces the risk of IR drop, and improves power efficiency.

[0025] This application also provides a method for fabricating a chip, which may include: fabricating a first semiconductor structure, including: providing a first substrate, forming a plurality of first through-silicon vias (TSVs) penetrating the first substrate, and fabricating a second I / O circuit, a first logic circuit connected to the second I / O circuit, a second power supply network (FSPDN), the second I / O circuit, and a plurality of second pads on the front side of the first substrate; wherein the second power supply network (FSPDN) is connected to the first logic circuit, and the first logic circuit is connected to the plurality of first TSVs. Fabricating a second semiconductor structure, including: providing a second substrate, forming a plurality of second TSVs penetrating the second substrate, and fabricating a first I / O circuit, a first power supply network (BSPDN) connected to the first I / O circuit, a second logic circuit, and a plurality of first pads on the front side of the second substrate; wherein the first power supply network (BSPDN) is connected to the second logic circuit, and the second logic circuit is connected to the plurality of second TSVs. The first semiconductor structure and the second semiconductor structure are bonded together through the back side of the first substrate and the back side of the second substrate, and the plurality of first TSVs and the plurality of second TSVs are electrically connected at the bonding surface to form a TSV structure, so that the second logic circuit is connected to the first logic circuit through the TSV structure.

[0026] When fabricating 3D chips using the above method, the first and second substrates are bonded back-to-back, and through-silicon vias (TSVs) are used to achieve electrical interconnection between the power and signal components of the two chips. This bonding structure does not occupy the thick metal layer on the top surface of the two chips and does not affect the top-level metal wiring resources, thereby increasing the density of the power mesh, reducing the parasitic resistance of the system power network, lowering the risk of IR drop, and improving power efficiency. Furthermore, using this method, a second I / O circuit and a second power supply network (FSPDN) are fabricated on the front surface of the first substrate (i.e., the front surface of the chip) and connected to the first logic circuit to meet the input / output requirements of the first logic circuit; conversely, a first I / O circuit and a first power supply network (BSPDN) are fabricated on the front surface of the second substrate (i.e., the back surface of the chip) and connected to the second logic circuit. In this configuration, the power, ground, and signal of the upper chip are interconnected with the upper substrate through the second pad, while the power, ground, and signal of the lower chip are interconnected with the lower substrate through the first pad. The upper and lower chips are powered and input / output independently, and signals are transmitted between the upper and lower chips through a through-silicon via (TSV) structure. This shortens the signal transmission distance between the upper and lower chips, reduces transmission path delay, and improves the performance of the circuit module.

[0027] This application also provides an electronic device, which includes a circuit board and a chip as provided in any of the aforementioned possible implementations, wherein the circuit board and the chip are electrically connected. Attached Figure Description

[0028] Figure 1 is a schematic diagram of a chip using a BSPDN structure provided in the prior art;

[0029] Figure 2 is a schematic diagram of a BSPDN chip using back-to-back bonding provided in an embodiment of this application;

[0030] Figure 3 is a schematic diagram of a substrate structure in a chip provided in an embodiment of this application;

[0031] Figure 4 is a schematic diagram of a substrate structure in a chip provided in an embodiment of this application;

[0032] Figure 5 is a schematic diagram of a substrate structure in a chip provided in an embodiment of this application;

[0033] Figure 6 is a flowchart of a chip manufacturing method provided in an embodiment of this application;

[0034] Figure 7 is a schematic diagram of the structure of a chip during the manufacturing process according to an embodiment of this application;

[0035] Figure 8 is a schematic diagram of the structure of a chip during the manufacturing process according to an embodiment of this application;

[0036] Figure 9 is a schematic diagram of the structure of a chip during the manufacturing process according to an embodiment of this application;

[0037] Figure 10 is a schematic diagram of the structure of a chip during the manufacturing process according to an embodiment of this application;

[0038] Figure 11 is a schematic diagram of the architecture of a face-to-face bonded 3D chip provided in the prior art;

[0039] Figure 12 is a front view of the upper and lower chips in Figure 11;

[0040] Figure 13 is a schematic diagram of the architecture of a back-to-back bonded 3D chip provided in an embodiment of this application;

[0041] Figure 14 is a schematic diagram of the architecture of a back-to-back bonded 3D chip provided in an embodiment of this application;

[0042] Figure 15 is a flowchart of a 3D chip fabrication method provided in an embodiment of this application;

[0043] Figure 16 is a schematic diagram of the structure of a 3D chip during the manufacturing process according to an embodiment of this application;

[0044] Figure 17 is a schematic diagram of the structure of a 3D chip during the manufacturing process according to an embodiment of this application;

[0045] Figure 18 is a schematic diagram of the structure of a 3D chip during the manufacturing process according to an embodiment of this application;

[0046] Figure 19 is a schematic diagram of the structure of a 3D chip during the manufacturing process according to an embodiment of this application;

[0047] Figure 20 is a flowchart of a method for manufacturing a 3D chip according to an embodiment of this application;

[0048] Figure 21 is a schematic diagram of the structure of a 3D chip during the manufacturing process according to an embodiment of this application;

[0049] Figure 22 is a schematic diagram of the structure of a 3D chip during the manufacturing process according to an embodiment of this application;

[0050] Figure 23 is a schematic diagram of the structure of a 3D chip during the manufacturing process according to an embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0052] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. "At least one" means one or more, and "more" means two or more. "Installation," "connection," "linking," etc., should be interpreted broadly; for example, they can refer to electrical connections, direct connections, indirect connections via an intermediate medium, or internal connections between two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. "Upper," "lower," "left," "right," etc., are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0053] This application provides an electronic device that uses a novel chip. The chip can be a chip product with a BSPDN structure or a 3D (dimensional) IC product. By adopting a back-to-back stacked bonding architecture, various problems existing in the prior art can be solved.

[0054] In chip products using the BSPDN structure, by adopting a back-to-back stacked bonding architecture, the IO circuits and logic circuits are respectively placed on different substrate surfaces, thereby solving various problems caused by the existing BSPDN structure where both the IO circuits and logic circuits are placed on the front side of the chip. For details, please refer to the following section of the embodiments.

[0055] In 3D chips, by adopting a back-to-back stacked bonding architecture, the impact of face-to-face bonding or face-to-back bonding on the top layer metal wiring resources in traditional 3D chips can be avoided, the density of the power mesh is enhanced, and the risk of IR drop is reduced. For details, please refer to the second embodiment below.

[0056] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product with a chip, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronics, etc.

[0057] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronics products can include servers, storage devices, radar, base stations, and other communication equipment.

[0058] Depending on actual needs, the above-mentioned electronic devices may also include other devices electrically connected to the chip, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.

[0059] The chip provided in this application will be specifically described below through specific embodiments.

[0060] Example 1

[0061] As illustrated in Figure 2, this embodiment provides a chip employing BSPDN technology, such as a system-on-chip (SOC), but is not limited to this. The chip includes a substrate structure 100, logic circuitry 200 (also referred to as a first logic circuit), I / O circuitry 300 (also referred to as a first I / O circuit), and a first power supply network 400. The substrate structure 100 includes a first substrate 101 and a second substrate 102, with the back sides of the first substrate 101 and the back sides of the second substrate 102 bonded together, i.e., the back sides of the first substrate 101 and the back sides of the second substrate 102 are connected via a bonding surface M. Illustrated, the back sides of the first substrate 101 and the back sides of the second substrate 102 can be bonded together using hybrid bonding (HB), but is not limited to this method.

[0062] As illustrated, the first substrate 101 and the second substrate 102 mentioned above can be wafers such as silicon wafers, but are not limited to this.

[0063] The IO circuit involved in this application can also be called an input / output interface circuit, I / O circuit, etc. This circuit is a bridge for the interaction between the internal logic circuit of the chip and external information. It is usually located on the periphery of the chip layout and is used to realize functions such as level conversion, improve driving capability, and perform ESD protection.

[0064] It should be understood that the front side of the substrate refers to the side on which active devices are fabricated. For example, the front side of the substrate may have an active device layer (such as a field-effect transistor layer) fabricated using a front end of line (FEOL) process. The back side of the substrate, on the other hand, refers to the side opposite to the front side, where no active device layer is present.

[0065] Referring again to Figure 2, the front (upper surface) of the first substrate 101 has a logic circuit 200 formed using active devices, while the back (lower surface) of the first substrate 101 does not have any active devices. This logic circuit 200 can be a CPU (central processing unit), GPU (graphics processing unit), etc., in a System-on-a-Chip (SoC), but is not limited to these. The front (lower surface) of the second substrate 102 has an I / O circuit 300 formed using active devices, while the back (upper surface) of the second substrate 102 does not have any active devices. Additionally, the front of the second substrate 102 also has a first power supply network 400 and multiple pads P (PADs). The pads P are located on the side of the I / O circuit 300 away from the second substrate 102 and are connected to the I / O circuit 300. Furthermore, the chip also has multiple through-silicon vias (TSVs) 500, which penetrate the substrate structure 100, that is, the TSVs 500 penetrate both the first substrate 101 and the second substrate 102. The I / O circuit 300 and the first power supply network 400 located on the back of the chip are connected to the logic circuit 200 through multiple through-silicon via structures 500 to meet the power supply and input / output requirements of the logic circuit 200.

[0066] The logic circuits involved in this application are configured according to the functional requirements of the chip. The logic circuits usually occupy most of the chip area and are composed of a large number of transistors and other electronic components. These components can be regarded as switches, and different logic operations can be realized by controlling their switching states.

[0067] In addition, in this embodiment, the logic circuit 200 is located on the front side of the substrate structure 100, and the first power supply network 400 is located on the back side of the substrate structure 100. The first power supply network 400, as a backside power supply network (BSPDN), is composed of one or more layers of insulating material and one or more conductive layers. The conductive layers include a power distribution network formed by power lines, ground lines, etc., and power is supplied to the logic circuit 200 through the power distribution network.

[0068] Of course, solder balls 10 can also be provided on the back of the multiple pads P. The chip connects to the substrate through the solder balls, thereby transmitting input signals, output signals, and power and ground signals. Illustrated, in some possible implementations, the pads P can be aluminum pads (Al pads). Pads P have a relatively large thickness (e.g., 1.45μm, 2.8μm, etc.), resulting in low sheet resistance, which can meet the long-distance transmission requirements between the IO circuit 300 and the pads P, thereby reducing parasitic resistance.

[0069] It should be noted that, for ease of description, in this embodiment, the side with the pad P (that is, the front side of the second substrate) is regarded as the back side of the entire chip, while the opposite side (that is, the front side of the first substrate 101) is regarded as the front side of the entire chip.

[0070] It should also be noted that the active devices involved in this application can be active devices such as fin field effect transistors (finFETs), gate all around field effect transistors (GAA), and complementary metal oxide semiconductor field effect transistors (CFETs). This application does not limit these devices, and they can be set as needed in practice.

[0071] Compared to the prior art (Figure 1), where the pad needs to be connected to the IO circuit via a TSV, in the chip provided in this embodiment, both the pad P and the IO circuit 300 are located on the back of the chip (i.e., the front side of the second substrate). The IO circuit 300 is connected to the pad P without the need for a TSV, thereby shortening the transmission path between the pad P and the IO circuit 300 and reducing the parasitic resistance between the pad P and the IO circuit 300, which is more conducive to meeting the high current scenarios of ESD.

[0072] Furthermore, in the BSPDN architecture chip provided in this embodiment, the IO circuit 300 and the logic circuit 200 are respectively disposed on the surfaces of two different substrates (first substrate 101 and second substrate 102), and the two substrates are bonded back-to-back. In this way, the IO circuit 300 and the logic circuit 200 are fabricated on different substrates using different processes. For example, in some possible implementations, the field-effect transistors in the logic circuit 200 can be implemented using advanced processes (such as 7nm, 5nm, 3nm, etc.), while the field-effect transistors in the IO circuit 300 can be implemented using relatively outdated processes (such as 0.18μm, 90nm, 65nm, etc.). In this case, the logic circuit 200 can use small-channel devices to meet its functional requirements, while the IO circuit 300 can use large-channel devices with better voltage withstand capability, thereby improving the reliability of input and output.

[0073] Of course, depending on the actual needs, both the IO circuit 300 and the logic circuit 200 can be implemented using advanced processes (such as 7nm, 5nm, 3nm, etc.), and this embodiment does not impose any restrictions on this.

[0074] Furthermore, this application does not limit the configuration of the through-silicon via (TSV) structure 500. The TSV structure 500 can be a single TSV or multiple TSVs, as long as it meets the electrical connection requirements between the front and back sides of the substrate structure 100. For example, the I / O circuit 300 and the first power supply network 400 on the back side can be connected to the logic circuit 200 on the front side through the TSV structure 500. The TSV used in the TSV structure 500 can be a micrometer-scale TSV, such as on the 3μm scale, but is not limited to this. Of course, the TSV structure 500 can also be a nanometer-scale TSV (nTSV), such as on the 50nm to 100nm scale, and this application does not limit this.

[0075] For example, referring to Figure 3, in some possible implementations, the through-silicon via (TSV) structure 500 may include a TSV (nTSV), that is, a TSV that directly penetrates the first substrate 101 and the second substrate 102. In this case, the TSV can be fabricated after the first substrate 101 and the second substrate 102 are bonded together.

[0076] For example, referring to Figures 2, 4, and 5, the through-silicon via (TSV) structure 500 may include a first TSV1 and a second TSV2. The first TSV1 penetrates through the first substrate 101, and the second TSV2 penetrates through the second substrate 102. The first TSV1 and the second TSV2 can be electrically connected at the bonding surface M. In this case, the first TSV1 can be fabricated in the first substrate 101 first, and the second TSV2 can be fabricated in the second substrate 102. Then, the first substrate 101 and the second substrate 102 can be bonded together. For details, please refer to the subsequent related fabrication methods.

[0077] This embodiment does not restrict the connection method of the first through-silicon via (TSV1) and the second through-silicon via (TSV2) at the bonding surface M.

[0078] For example, referring to Figure 2, in some possible implementations, the through-silicon via (TSV) structure 500, in addition to including a first TSV1 and a second TSV2, may also include a first micropad (μbump) a1 and a second micropad a2. The first micropad a1 is located on the side of the first TSV1 closest to the second TSV2 and is connected to the first TSV1. The second micropad a2 is located on the side of the second TSV2 closest to the first TSV1 and is connected to the second TSV2. The first TSV1 and the second TSV2 are bonded together at the bonding surface M via the first micropad a1 and the second micropad a2, thereby forming the TSV structure 500. In this configuration, the layout of the plurality of first through-silicon vias (TSVs) 1 in the first substrate 101 can be mirrored with the layout of the plurality of second through-silicon vias (TSVs) 2, allowing for one-to-one connection between the TSVs 1 and 2 after bonding. Using micropads for bonding increases the bonding area, reduces bonding difficulty, and consequently lowers manufacturing costs.

[0079] For example, referring to Figure 4, in some possible implementations, the first through-silicon via (TSV1) and the second through-silicon via (TSV2) can be bonded together at the bonding surface M, i.e., without the need for micropads (μbumps). In this case, the layout of the plurality of first TSV1s in the first substrate 101 can be mirrored with the layout of the plurality of second TSV2s in the second TSV2s, so that after the first substrate 201 and the second substrate 202 are bonded, the plurality of first TSV1s and the plurality of second TSV2s can be bonded one-to-one. Using direct bonding of TSVs has the advantage of simple process, and is especially suitable for larger TSVs.

[0080] For example, referring to Figure 5, in some possible implementations, the through-silicon via (TSV) structure 500 may also include a metal trace b located between the first substrate 101 and the second substrate 102, with the first TSV1 and the second TSV2 connected by the metal trace b (one or more layers). In this configuration, the arrangement of the multiple first TSV1s and multiple second TSV2s does not need to be mirror images, which can increase the degree of freedom of the TSVs (TSV1, TSV2) during bonding and reduce the alignment process accuracy.

[0081] In addition, compared with the prior art (Figure 1), which does not have active devices on the back of the chip and uses fewer metal layers to set the BSPDN, in this embodiment, by fabricating active devices (IO circuits) on the back of the chip (that is, the front of the second substrate), the number of metal layers on the back of the chip can be increased. In this way, one or more capacitor structures can be fabricated on the front of the second substrate to achieve filtering and decoupling of the power supply signal.

[0082] As illustrated, in some possible implementations, at least one capacitor structure, either an MOM (metal oxide metal) capacitor or a MOS (metal oxide semiconductor) capacitor, can be disposed on the front side of the second substrate. This capacitor structure is connected to the first power supply network 400 (BSPDN) and can also be connected to the IO circuit 300 to filter and decouple the power supply signal provided by the first power supply network 400.

[0083] The structure of the above MOM capacitor is an interdigitated capacitor formed by the edge of the same metal layer, which uses the oxide layer between the metal layers for isolation and achieves the capacitance effect through multilayer wiring.

[0084] The aforementioned MOS capacitor utilizes the gate capacitance of a MOSFET (metal oxide semiconductor field effect transistor). The upper electrode is the gate terminal of the MOS transistor, and the lower electrode is the source and drain terminals of the MOS transistor. The middle is filled with a very thin layer of gate oxide (such as silicon dioxide, SiO2), which can provide a large capacitance per unit area.

[0085] In addition, to increase the heat dissipation capability of the entire chip architecture, as shown in Figure 2, a thermally conductive layer 103 can be disposed between the first substrate 101 and the second substrate 102. This thermally conductive layer 103 can be made of an insulating high thermal conductivity material, such as one or more of aluminum nitride (AlN) and hexagonal boron nitride (h-BN). The thermally conductive layer 103 can be a single film structure or multiple film structures; this application does not limit this, and it can be configured as needed in practice. Of course, in some possible implementations, the thermally conductive layer 103 can be an etch stop layer, as detailed in the following description.

[0086] This embodiment also provides a method for manufacturing a chip, as shown in Figure 6. The method may include:

[0087] Step 11: Referring to Figure 7, fabricate a first semiconductor structure A1, including: providing a first substrate 101, forming a plurality of first through silicon vias (TSVs) 1 through the first substrate 101, and fabricating a logic circuit 200 connected to the plurality of first through silicon vias (TSVs) 1 on the front side of the first substrate 101.

[0088] Indicatively, in some possible implementations, the process of fabricating the first semiconductor structure A1 in step 11 above may include: referring to FIG. 7(a), providing a first substrate 101, forming a first through-silicon via (TSV1) of a certain depth on the first substrate 101; then, forming an active device layer (such as a GAA) using a front-end process (FEOL) and a metal trace layer using a back-end process (BEOL) to form a logic circuit 300 connected to the first TSV1. Then, referring to FIG. 7(b), a carrier plate C1 (such as glass) may be temporarily bonded to one side of the metal trace layer, and the back side of the first substrate 101 is polished. An insulating layer is formed on the back side of the first substrate 101 using an insulating high thermal conductivity material, and the first TSV1 is exposed by opening a window in the insulating layer. A first micropad a1 is then fabricated on the surface of the exposed first TSV1.

[0089] The arrangement of the first substrate 101 can be configured as needed, and this application does not impose any restrictions on it.

[0090] For example, in some possible implementations, referring to Figure 7(a), the first substrate 101 may include two silicon wafers, and an etch stop layer (ESL) may be disposed between the two silicon wafers. In this case, the depth of the fabricated first through-silicon via (TSV1) needs to exceed the etch stop layer (ESL), and the subsequent grinding of the lower silicon wafer stops at the etch stop layer (ESL). Of course, the etch stop layer (ESL) can be made of an insulating, highly thermally conductive material, which can improve the heat dissipation of the chip.

[0091] For example, in some possible implementations, the first substrate 101 may include a silicon wafer without an etch stop layer (ESL), and the thickness of the silicon substrate needs to be controlled by controlling the polishing time during subsequent polishing. In this case, the depth of the fabricated first through-silicon via (TSV1) needs to exceed the thickness of the polished substrate.

[0092] Step 12, referring to Figure 8, fabricating the second semiconductor structure A2 includes: providing a second substrate 102, forming a plurality of second through-silicon vias (TSVs) 2 penetrating the second substrate 102, and fabricating an I / O circuit 300, a first power supply network (BSPDN) 400 connected to the I / O circuit 300, and a plurality of pads P on the front side of the second substrate 102; wherein the I / O circuit 300 and the first power supply network (BSPDN) 400 are respectively connected to a plurality of different second through-silicon vias (TSVs) 2.

[0093] Indicatively, in some possible implementations, the process of fabricating the second semiconductor structure A2 in step 12 above may include: referring to FIG8(a), providing a second substrate 102, forming a second through-silicon via (TSV2) of a certain depth on the second substrate 102; then, using a front-end process (FEOL) to fabricate an active device layer (such as a field-effect transistor layer), and using a back-end process (BEOL) to fabricate a metal trace layer, to form an I / O circuit 300, a first power supply network (BSPDN) 400, and multiple pads P. The I / O circuit 300 and the first power supply network (BSPDN) 400 can be connected to different second through-silicon vias TSV2 through contact holes, and the multiple pads P are connected to the I / O circuit 300. Next, referring to Figure 8(b), a carrier board C2 (such as glass) can be temporarily bonded to the side of the pad P, and the back side of the second substrate 102 is ground. An insulating layer is formed on the back side of the second substrate 102 using an insulating and highly thermally conductive material. A second through-silicon via (TSV2) is exposed by opening a window on the insulating layer, and a second micro pad a2 is fabricated on the surface of the exposed TSV2.

[0094] The arrangement of the second substrate 102 and the second through-silicon via (TSV2) is similar to that of the first substrate 101 and the first through-silicon via (TSV1), respectively. For details, please refer to the aforementioned descriptions of the first substrate 101 and the first through-silicon via (TSV1).

[0095] Step 13: Referring to Figure 9, the first semiconductor structure A1 and the second semiconductor structure A2 are bonded to the back side of the first substrate 101 and the back side of the second substrate 102 through the back side of the first substrate 101. Multiple first through-silicon vias (TSV1) and multiple second through-silicon vias (TSV2) are electrically connected at the bonding surface M to form a through-silicon via structure 500, so that the first power supply network 400 (BSPDN) and the IO circuit 300 are respectively connected to the logic circuit 200 through the multiple through-silicon via structures 500.

[0096] Indicatively, in some possible implementations, step 13 may include: referring to FIG. 9, a first micropad a1 on the back side of the first substrate 101 and a second micropad a2 on the back side of the second substrate 102 are hybrid bonded together; a first through-silicon via (TSV) 1 and a second through-silicon via (TSV) 2 are bonded together through the first micropad a1 and the second micropad a2 to form a through-silicon via structure 500, so that the first power supply network 400 (BSPDN) is connected to the logic circuit 200 through the through-silicon via structure 500, and the I / O circuit 300 is connected to the logic circuit 200 through multiple through-silicon via structures 500. Then, referring to FIG. 10, the carrier board C2 can be removed, and solder balls 10 can be fabricated on the pad P.

[0097] Of course, in some possible implementations, the fabrication steps of the micro pads (a1, a2) can be omitted, and the first through-silicon via (TSV1) and the second through-silicon via (TSV2) can be directly bonded at the bonding surface M.

[0098] Example 2

[0099] Figure 11 is a schematic diagram of the architecture of a face-to-face bonded 3D chip provided in the prior art.

[0100] Referring to the 3D chip illustrated in Figure 11, the chip includes an upper chip D1 and a lower chip D2 bonded face-to-face. Both upper chip D1 and lower chip D2 have a front-side power delivery network (FSPDN) on their front sides, while the lower chip D2 has a back-side power delivery network (BSPDN) and a power connector pad on its back side. Upper chip D1 requires power from lower chip D2, resulting in a relatively long path from the power connector pad to upper chip D1, thus generating a significant IR drop.

[0101] Figure 12 is a front view of the upper chip D1 and the lower chip D2 in Figure 11.

[0102] As shown in Figures 11 and 12, both the top layer of the front side of the upper chip D1 and the top layer of the front side of the lower chip D2 have power meshes (PMs). Since the upper chip D1 and the lower chip D2 use a face-to-face bonding architecture, they require the thick metal of the top layer for support. Therefore, bonding structure b disrupts the power meshes (PMs) on the top layers of both chips (D1 and D2), especially in applications with a large number of bonding structures b, reducing the density of the top-layer power meshes (PMs). Although the lower chip D2 has a backside power supply network (BSPDN) on its back side, which has a smaller impact on its power mesh (PMs), the upper chip D1 receives power from the backside power supply network (BSPDN) on the back side of the lower chip D2, and this power is transmitted through the weakened power mesh (PM) at the bonding surface M. Therefore, it is significantly affected, resulting in a large IR drop.

[0103] It should be understood that in the metal layer on the front of the chip, the top layer of thick metal is used to realize the interconnection of power and ground of the power grid PM, and the bottom layer of metal is used to realize the interconnection of logic circuits (such as SOC).

[0104] Based on this, this embodiment 2 provides a 3D chip that uses a back-to-back bonding method to bond two chips. This avoids the impact of face-to-face (or face-to-back) bonding on the top layer metal wiring resources in traditional 3D chips, enhances the density of the power mesh, and reduces the risk of IR drop.

[0105] The following describes the configuration structure of the 3D chip provided in this embodiment two.

[0106] As illustrated in Figure 13, this second embodiment provides a 3D chip, such as a system-on-a-chip (SOC), but is not limited thereto. The chip includes a substrate structure 100, a first logic circuit 201, a second logic circuit 202, a first I / O circuit 301, a first power supply network 401, and a second power supply network 402. The substrate structure 100 includes a first substrate 101 and a second substrate 102, and the back surfaces of the first substrate 101 and the second substrate 102 are bonded together, that is, the back surfaces of the first substrate 101 and the second substrate 102 are connected through a bonding surface M.

[0107] The first power supply network 400 is located on the back side of the substrate structure 100 (or the chip) and can also be called a backside power supply network (BSPDN). The second power supply network 402 is located on the front side of the substrate structure 100 (or the chip) and can also be called a frontside power supply network (FSPDN). The first power supply network 400 and the second power supply network 402 are composed of one or more layers of insulating material and one or more layers of conductive material. The conductive layer includes a power distribution network formed by power lines, ground lines, etc., and power is supplied to the logic circuit through the power distribution network.

[0108] In other words, in the 3D chip provided in this embodiment 2, the upper chip D1 and the lower chip D2 are bonded together in a back-to-back bonding manner.

[0109] As illustrated, the back side of the first substrate 101 and the back side of the second substrate 102 can be connected by hybrid bonding (HB), but are not limited to this.

[0110] As illustrated, the first substrate 101 and the second substrate 102 mentioned above can be wafer structures such as silicon wafers, and this application does not limit them.

[0111] Referring again to Figure 13, a first logic circuit 201 (logic A) formed by active devices (field-effect transistors) is disposed on the front (upper surface) of the first substrate 101, while no active devices are disposed on the back (lower surface) of the first substrate 101. A second logic circuit 202 (logic B) and a first I / O circuit 301 formed by active devices (field-effect transistors) are disposed on the front (lower surface) of the second substrate 102, while no active devices are disposed on the back (upper surface) of the second substrate 102. Additionally, a second power supply network 402 (FSPDN) is disposed on the front of the first substrate 101, and the second power supply network 402 (FSPDN) is connected to the first logic circuit 201 for supplying power to the first logic circuit 201. The front side of the second substrate 102 is also provided with a first power supply network 401 (BSPDN) and a plurality of first pads P1. The first pads P1 are located on the side of the first I / O circuit 301 away from the second substrate 102 and are connected to the first I / O circuit 301. The first power supply network 401 (BSPDN) is connected to the second logic circuit 202 (logic B) and is used to supply power to the second logic circuit 202 (logic B). The chip also has a plurality of through-silicon vias (TSVs) 500, and the TSVs 500 penetrate the substrate structure 100, that is, the TSVs 500 penetrate the first substrate 101 and the second substrate 102, to satisfy the electrical connection between the devices on the front side and the devices on the back side of the substrate structure 100. For example, the second logic circuit 202 (logic B) located on the back side of the chip can be connected to the first logic circuit 201 (logic A) on the front side through the plurality of TSVs 500 to realize the interaction between the second logic circuit 202 and the first logic circuit 201 (logic A).

[0112] Of course, solder balls 11 can be set on the back of the first pad P1, and the chip can be interconnected with the substrate through the solder balls 11.

[0113] As illustrated, the first logic circuit 201 can be a part of the logic circuit in the SOC, such as the CPU, GPU, etc.; the second logic circuit 202 can be a part of the logic circuit in the SOC, such as the memory circuit, etc., but is not limited to this.

[0114] Depending on actual needs, the first logic circuit 201 and the second logic circuit 202 can adopt the same process technology, such as 28nm, 12nm, 7nm, etc.; or they can adopt different process technologies according to the needs of system stability, reliability, cost, etc. This application does not impose any restrictions on this, and can be set as needed in practice.

[0115] Of course, the second logic circuit 202 (logic B) and the first IO circuit 301 located on the front side of the second substrate 102 can use the same process, thereby reducing manufacturing costs.

[0116] It should be understood that by dividing the logic circuits in the chip into two parts and placing them on the front and back sides respectively, the overall size of the chip can be reduced, the transistor density per unit area can be increased, the wafer area can be fully utilized, and the manufacturing cost can be reduced.

[0117] Furthermore, referring to Figure 13, on the back side of the chip, the first I / O circuit 301 is connected to the second logic circuit 202 to meet the input / output requirements of the second logic circuit 202. The first I / O circuit 301 can also be connected to the first logic circuit 201 (logic A) on the front side via multiple through-silicon vias (TSVs) 500 to meet the input / output requirements of the first logic circuit 201. The second power supply network 402 (FSPDN) can be connected to the first I / O circuit 301 via multiple TSVs 500 to obtain power, thereby meeting the power requirements of the first logic circuit 201.

[0118] Compared to Figure 13, where the first logic circuit 201 located on the front of the chip requires a first power supply network 400 (BSPDN) and a first I / O circuit 301 on the back to meet its power supply and input / output requirements, this embodiment provides another possible implementation method, as shown in Figure 14. A second I / O circuit 302 and multiple second pads P2 can be disposed on the front of the first substrate 101. The second pads P2 are located on the side of the second I / O circuit 302 away from the first substrate 101 and are connected to the second I / O circuit 302. In this case, the first logic circuit 201 is connected to the second I / O circuit 302 to meet its own input / output requirements; and the second power supply network 402 (FSPDN) is connected to both the second I / O circuit 302 and the first logic circuit 201 to obtain power through the second I / O circuit 302 to meet the power supply requirements of the first logic circuit 201.

[0119] Of course, solder balls 12 can be placed above the second pad P2, and the chip is interconnected with the upper substrate through the solder balls 12. In this case, the power, ground, and signal of the upper chip D1 are interconnected with the upper substrate through the second pad P2, and the power, ground, and signal of the lower chip D2 are interconnected with the lower substrate through the first pad P1. That is, the upper chip D1 and the lower chip D2 are independently powered and input / output. Furthermore, in this configuration, the upper chip D1 and the lower chip D2 transmit signals through the through-silicon via (TSV) structure 500, thereby shortening the signal transmission distance between the upper chip D1 and the lower chip D2, reducing transmission path delay, and improving the performance of the circuit module.

[0120] In addition, compared to the existing technology (Figures 11 and 12) which uses a face-to-face bonding architecture, the bonding structure b will destroy the power mesh PM on the top layer of the two chips (D1 and D2), resulting in a decrease in the density of the power mesh PM and thus causing IR drop.

[0121] In the 3D chip provided in this embodiment 2, the upper chip D1 and the lower chip D2 are bonded back to back. The power and signal electrical interconnection between the two chips (D1, D2) is achieved through a silicon via structure 500. The bonding structure does not occupy the thick metal layer on the top surface of the two chips (D1, D2) and does not affect the top metal wiring resources of the two chips (D1, D2). This can increase the density of the power mesh, reduce the parasitic resistance of the system power network, reduce the risk of IR drop, and improve power efficiency.

[0122] In this second embodiment, the through-silicon via (TSV) structure 500 is set in a similar manner to that in the first embodiment. It can be a single TSV or multiple TSVs. Furthermore, the TSVs used in the through-silicon via structure 500 can be micron-sized through-silicon vias or nano-sized through-silicon vias (nTSVs). This application does not impose any restrictions on this, as long as the actual needs can be met.

[0123] Schematic, the through-silicon via (TSV) structure 500 may include one TSV (nTSV); it may also include a first TSV1 and a second TSV2, wherein the first TSV1 penetrates through the first substrate 101, and the second TSV2 penetrates through the second substrate 102. The first TSV1 and the second TSV2 can be electrically connected at the bonding surface M. When the TSV structure 500 includes the first TSV1 and the second TSV2, the first TSV1 and the second TSV2 can be directly bonded together, or they can be bonded together through micropads (a1, a2), or they can be connected through metal traces. This application does not limit this; for details, please refer to the relevant description in Embodiment 1, which will not be repeated here.

[0124] In addition, to increase the heat dissipation capability of the entire chip architecture, as shown in Figures 13 and 14, a thermally conductive layer 103 can be disposed between the first substrate 101 and the second substrate 102. This thermally conductive layer 103 can be made of an insulating high thermal conductivity material, such as one or more of aluminum nitride (AlN) and hexagonal boron nitride (h-BN). The thermally conductive layer 103 can be a single film structure or multiple film structures; this application does not limit this, and it can be configured as needed in practice. Of course, in some possible implementations, the thermally conductive layer 103 can be an etch stop layer; for details, please refer to the relevant description in Embodiment 1.

[0125] This embodiment also provides a method for manufacturing a 3D chip as shown in Figure 13. As shown in Figure 15, the manufacturing method may include:

[0126] Step 21, referring to Figure 16, fabricating a first semiconductor structure A1 includes: providing a first substrate 101, forming a plurality of first through-silicon vias (TSVs) 1 through the first substrate 101, and fabricating a first logic circuit 201 and a second power supply network 402 (FSPDN) on the front side of the first substrate 101; wherein the first logic circuit 201 is connected to the second power supply network 402 (FSPDN) and the plurality of first through-silicon vias (TSVs).

[0127] Indicatively, in some possible implementations, the process of fabricating the first semiconductor structure A1 in step 21 above may include: referring to FIG. 16(a), providing a first substrate 101, forming a first through-silicon via (TSV1) of a certain depth on the first substrate 101; then, fabricating a field-effect transistor layer (such as a GAA) using a front-end process (FEOL), fabricating a metal wiring layer using a back-end process (BEOL), and connecting the metal wiring layer to the active device layer to form a first logic circuit 201 and a second power supply network (FSPDN) connected to multiple first TSV1s. Then, referring to FIG. 16(b), a carrier plate C1 (such as glass) may be temporarily bonded to one side of the metal wiring layer, and the back side of the first substrate 101 is polished. An insulating layer is formed on the back side of the first substrate 101 using an insulating high thermal conductivity material, and the first TSV1s are exposed by opening windows in the insulating layer. A first micropad a1 is then fabricated on the surface of the exposed first TSV1s.

[0128] The configuration of the first substrate 101 and the first through-silicon via (TSV1) can be referred to in Embodiment 1, and will not be described again here.

[0129] Step 22, referring to Figure 17, fabricating the second semiconductor structure A2 includes: providing a second substrate 102, forming a plurality of second through-silicon vias (TSVs) 2 penetrating the second substrate 102, and fabricating a first I / O circuit 301, a first power supply network 401 (BSPDN) connected to the first I / O circuit 301, a second logic circuit 202, and a plurality of first pads P1 on the front side of the second substrate 102; wherein, the second logic circuit 202 is connected to the first power supply network 401 (BSPDN) and the plurality of second through-silicon vias (TSVs) 2.

[0130] Indicatively, in some possible implementations, the process of fabricating the second semiconductor structure A2 in step 22 above may include: referring to FIG17(a), providing a second substrate 102, forming a second through-silicon via (TSV2) of a certain depth on the second substrate 102; then, using a front-end process (FEOL) fabricated field-effect transistor layer and a back-end process (BEOL) fabricated metal wiring layer to form a first I / O circuit connected to the plurality of second TSV2, and a second logic circuit 202 connected to the first I / O circuit 301, a plurality of first pads P1, and the second logic circuit 202 connected to the first power supply network 401 (BSPDN) and the plurality of second TSV2. Then, referring to Figure 17(b), a carrier board C2 (such as glass) can be temporarily bonded on one side of the first pad P1, and the back side of the second substrate 102 is ground. An insulating layer is formed on the back side of the second substrate 102 using an insulating and highly thermally conductive material. A second through-silicon via (TSV2) is exposed by opening a window on the insulating layer, and a second micro pad a2 is fabricated on the surface of the exposed second through-silicon via (TSV2).

[0131] The configuration of the second substrate 102 and the second through-silicon via (TSV2) can be referred to in Embodiment 1, and will not be described again here.

[0132] Step 23: Referring to Figure 18, the first semiconductor structure A1 and the second semiconductor structure A2 are bonded to the back side of the first substrate 101 and the back side of the second substrate 102 through the back side of the first substrate 101. Multiple first through-silicon vias (TSVs) 1 and multiple second through-silicon vias (TSVs) 2 are electrically connected at the bonding surface M to form a through-silicon via structure 500, so that the second logic circuit 202 is connected to the first logic circuit 201 through the multiple through-silicon via structures 500, and the first I / O circuit 301 is connected to the first logic circuit 201 and the second power supply network (FSPDN) through the multiple through-silicon via structures 500 respectively.

[0133] Indicatively, in some possible implementations, step 23 may include: referring to FIG18, hybrid bonding is performed between the back side of the first substrate 101 and the back side of the second substrate 102; the first through-silicon via (TSV1) and the second through-silicon via (TSV2) are bonded together through the first micropad a1 and the second micropad a2 to form a through-silicon via structure 500, such that the second logic circuit 202 is connected to the first logic circuit 201 through multiple through-silicon via structures 500, and the first I / O circuit 301 is connected to the first logic circuit 201 and the second power supply network (FSPDN) through multiple through-silicon via structures 500 respectively. Afterwards, referring to FIG19, the carrier board C2 can be removed, and solder balls 10 can be fabricated on the first pad P1.

[0134] Of course, in some possible implementations, the fabrication steps of the pads (a1, a2) can be omitted, and the first through-silicon via (TSV1) and the second through-silicon via (TSV2) can be directly bonded at the bonding surface M.

[0135] In addition, this embodiment two also provides a method for manufacturing a 3D chip as shown in Figure 14, and as shown in Figure 20, the manufacturing method may include:

[0136] Step 31, referring to Figure 21, fabricating a first semiconductor structure A1, including: providing a first substrate 101, forming a plurality of first through-silicon vias (TSVs) 1 penetrating the first substrate 101, and fabricating a second I / O circuit 302 and a first logic circuit 201, a second power supply network 402 (FSPDN), and a plurality of second pads P2 connected to the second I / O circuit 302 on the front side of the first substrate 101; wherein, the first logic circuit 201 is connected to the second power supply network (FSPDN) and the plurality of first through-silicon vias (TSVs).

[0137] In some possible implementations, the process of fabricating the first semiconductor structure A1 in step 31 above may include: referring to FIG21, providing a first substrate 101, forming a first through-silicon via (TSV1) of a certain depth on the first substrate 101; then, fabricating a field-effect transistor layer (such as a GAA) using a front-end process (FEOL) and a metal wiring layer using a back-end process (BEOL) to form a second I / O circuit 302 and a first logic circuit 201, a second power supply network 402 (FSPDN), and multiple second pads P2 connected to the second I / O circuit 302. The first logic circuit 201 is connected to the second power supply network 402 (FSPDN) and the multiple first TSV1s. Subsequently, a carrier board (such as glass) can be temporarily bonded to the side of the second pad P2, and the back side of the first substrate 101 is ground. An insulating layer is formed on the back side of the first substrate 101 using an insulating and highly thermally conductive material. A first through-silicon via (TSV1) is exposed on the insulating layer, and a first micro pad a1 is fabricated on the surface of the exposed TSV1.

[0138] The configuration of the first substrate 101 and the first through-silicon via (TSV1) can be referred to in Embodiment 1, and will not be described again here.

[0139] Step 32, referring to Figure 22, fabricating the second semiconductor structure A2 includes: providing a second substrate 102, forming a plurality of second through-silicon vias (TSVs) 2 penetrating the second substrate 102, and fabricating a first I / O circuit 301, a second logic circuit 202 connected to the first I / O circuit 301, a first power supply network (BSPDN) 401, and a plurality of first pads P1 on the front side of the second substrate 102; wherein, the second logic circuit 202 is connected to the first power supply network (BSPDN) 401 and the plurality of second through-silicon vias (TSVs) 2.

[0140] In some possible implementations, the process of fabricating the second semiconductor structure A2 in step 32 above may include: referring to FIG22, providing a second substrate 102, forming a second through-silicon via (TSV2) of a certain depth on the second substrate 102; then, fabricating a field-effect transistor layer using a front-end process (FEOL) and a metal wiring layer using a back-end process (BEOL) to form a first I / O circuit 301 and a second logic circuit 202, a first power supply network 401 (BSPDN), and a plurality of first pads P1 connected to the first I / O circuit 301; wherein the second logic circuit 202 is connected to the first power supply network 401 (BSPDN) and the plurality of second TSV2s. Afterwards, a carrier plate C2 (such as glass) may be temporarily bonded to one side of the first pads P1, and the back side of the second substrate 102 may be polished. An insulating layer is formed on the back side of the second substrate 102 using an insulating high thermal conductivity material, and the second TSV2s are exposed by opening windows in the insulating layer. A second micro pad a2 is then fabricated on the surface of the exposed second TSV2s.

[0141] The configuration of the second substrate 102 and the second through-silicon via (TSV2) can be referred to in Embodiment 1, and will not be described again here.

[0142] Step 33: Referring to Figure 23, the first semiconductor structure A1 and the second semiconductor structure A2 are bonded to the back side of the first substrate 101 and the back side of the second substrate 102 through the back side of the first substrate 101. A plurality of first through-silicon vias (TSV1) and a plurality of second through-silicon vias (TSV2) are electrically connected at the bonding surface M to form a through-silicon via structure 500, so that the second logic circuit 202 is connected to the first logic circuit 201 through the through-silicon via structure 500.

[0143] Indicatively, in some possible implementations, step 33 may include: referring to FIG23, hybrid bonding is performed between the back side of the first substrate 101 and the back side of the second substrate 102, and the first through-silicon via (TSV1) and the second through-silicon via (TSV2) are bonded together through the first micropad a1 and the second micropad a2 to form a through-silicon via structure 500, so that the second logic circuit 202 is connected to the first logic circuit 201 through the through-silicon via structure 500. Then, referring to FIG23, the carrier board C2 can be removed, and solder balls 11 can be fabricated on the first pad P1; the carrier board C1 can be removed, and solder balls 12 can be fabricated on the second pad P2.

[0144] Of course, in some possible implementations, the fabrication steps of the micro pads (a1, a2) can be omitted, and the first through-silicon via (TSV1) and the second through-silicon via (TSV2) can be directly bonded at the bonding surface M.

[0145] The settings for the first pad P1 and the second pad P2 can be referenced from the pad settings in Embodiment 1, and will not be repeated here.

[0146] In addition, in Embodiments 1 and 2 of this application, metal layers, pads, silicon vias, etc. located on different layers can be connected by vias. The vias in the chip can include contact holes (CT), metal vias (via), power contact holes (PCT), top metal vias (redistribution vias (RV), etc.) for connection. This application does not limit this, and it can be set according to the needs in practice.

[0147] It should be understood that, in the embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0148] For other related content in the above manufacturing method, please refer to the corresponding description in the chip structure section above, which will not be repeated here; for other settings in the above chip structure embodiment, please refer to the above manufacturing method and related manufacturing methods for adjustment, which will not be repeated here.

[0149] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, include: A first substrate and a second substrate, wherein the back side of the second substrate is bonded to the back side of the first substrate via a bonding surface; A first logic circuit is disposed on the front side of the first substrate; The first I / O circuit, the first power supply network, and a plurality of first pads are all disposed on the front side of the second substrate; Multiple through-silicon via (TSV) structures; The through-silicon via (TSV) structure includes at least one TSV, and the TSV structure penetrates through the first substrate and the second substrate. The first I / O circuit is connected to the first logic circuit through multiple TSV structures, and the multiple first pads are connected to the first I / O circuit.

2. The chip according to claim 1, characterized in that, The first power supply network is connected to the first logic circuit through a plurality of the aforementioned through-silicon via structures.

3. The chip according to claim 1, characterized in that, The chip also includes a second logic circuit and a second power supply network; The second logic circuit is located on the front side of the second substrate, and the second logic circuit is connected to the first logic circuit through a plurality of the aforementioned through-silicon via structures. The first I / O circuit and the first power supply network are both connected to the second logic circuit. The second power supply network is located on the front side of the first substrate, and the second power supply network is connected to the first logic circuit.

4. The chip according to claim 3, characterized in that, The first I / O circuit is connected to the first logic circuit and the second power supply network through a plurality of the aforementioned through-silicon via structures.

5. The chip according to claim 3, characterized in that, The chip also includes a second I / O circuit and a plurality of second pads located on the front side of the first substrate; Multiple second pads are connected to the second I / O circuit, and both the first logic circuit and the second power supply network are connected to the second I / O circuit.

6. The chip according to any one of claims 1-5, characterized in that, The through-silicon via structure includes a first through-silicon via and a second through-silicon via, wherein the first through-silicon via penetrates the first substrate and the second through-silicon via penetrates the second substrate; The first through-silicon via and the second through-silicon via are electrically connected at the bonding surface.

7. The chip according to claim 6, characterized in that, The first through-silicon via and the second through-silicon via are directly bonded at the bonding surface.

8. The chip according to claim 6, characterized in that, The chip also includes multiple first micro pads and multiple second micro pads; The first micro pad is located on the side of the first through-silicon via (TSV) close to the second TSV and is connected to the first TSV. The second micro pad is located on the side of the second TSV close to the first TSV and is connected to the second TSV. The first micro pad and the second micro pad are bonded together at the bonding surface.

9. The chip according to claim 6, characterized in that, The first through-silicon via (TSV) and the second TSV are connected by a metal trace.

10. The chip according to any one of claims 1-9, characterized in that, The front side of the second substrate is also provided with a plurality of capacitor structures, and the capacitor structures are connected to the first power supply network; The plurality of capacitor structures include at least one of MOM capacitors and MOS capacitors.

11. The chip according to any one of claims 1-9, characterized in that, The chip is a system-on-a-chip (SOC).

12. A method for manufacturing a chip, characterized in that, include: Fabricating a first semiconductor structure includes: providing a first substrate, forming a plurality of first through-silicon vias (TSVs) through the first substrate, and fabricating a first logic circuit connected to the plurality of TSVs on the front side of the first substrate; Fabricating a second semiconductor structure includes: providing a second substrate, forming a plurality of second through-silicon vias (TSVs) penetrating the second substrate, and fabricating a first I / O circuit, a first power supply network connected to the first I / O circuit, and a plurality of first pads on the front side of the second substrate; wherein the first I / O circuit and the first power supply network are respectively connected to the plurality of second TSVs; The first semiconductor structure and the second semiconductor structure are bonded together through the back side of the first substrate and the back side of the second substrate. The plurality of first through-silicon vias and the plurality of second through-silicon vias are electrically connected at the bonding surface to form a through-silicon via structure, so that the first power supply network and the first I / O circuit are respectively connected to the first logic circuit through the plurality of through-silicon via structures.

13. A method for manufacturing a chip, characterized in that, include: Fabricating a first semiconductor structure includes: providing a first substrate, forming a plurality of first through-silicon vias (TSVs) penetrating the first substrate, and fabricating a first logic circuit and a second power supply network on the front side of the first substrate; wherein the first logic circuit is connected to the second power supply network and the plurality of first TSVs. Fabricating a second semiconductor structure includes: providing a second substrate, forming a plurality of second through-silicon vias (TSVs) penetrating the second substrate, and fabricating a first I / O circuit, a first power supply network connected to the first I / O circuit, a second logic circuit, and a plurality of first pads on the front side of the second substrate; wherein the second logic circuit is connected to the first power supply network and the plurality of second TSVs. The first semiconductor structure and the second semiconductor structure are bonded together through the back side of the first substrate and the back side of the second substrate. The plurality of first through-silicon vias and the plurality of second through-silicon vias are electrically connected at the bonding surface to form a through-silicon via structure, so that the second logic circuit is connected to the first logic circuit through the plurality of through-silicon via structures, and the first I / O circuit is connected to the first logic circuit and the second power supply network through the plurality of through-silicon via structures respectively.

14. A method for manufacturing a chip, characterized in that, include: Fabricating a first semiconductor structure includes: providing a first substrate, forming a plurality of first through-silicon vias (TSVs) penetrating the first substrate, and fabricating a second I / O circuit, a first logic circuit, a second power supply network, the second I / O circuit, and a plurality of second pads connected to the second I / O circuit on the front side of the first substrate; wherein the first logic circuit is connected to the second power supply network and the plurality of first TSVs. Fabricating a second semiconductor structure includes: providing a second substrate, forming a plurality of second through-silicon vias (TSVs) penetrating the second substrate, and fabricating a first I / O circuit, a first power supply network connected to the first I / O circuit, a second logic circuit, and a plurality of first pads on the front side of the second substrate; wherein the second logic circuit is connected to the first power supply network and the plurality of second TSVs. The first semiconductor structure and the second semiconductor structure are bonded together through the back side of the first substrate and the back side of the second substrate. A plurality of first through-silicon vias and a plurality of second through-silicon vias are electrically connected at the bonding surface to form a through-silicon via structure, so that the second logic circuit is connected to the first logic circuit through the through-silicon via structure.

15. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-11, wherein the circuit board is electrically connected to the chip.

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