Input stage circuit

Abstract

Disclosed in the present invention is an input stage circuit. The input stage circuit is used for providing a differential current to a post-stage circuit on the basis of a differential input signal. The input stage circuit comprises: a first input transistor pair, and a first cascode structure and a first tail current source which are adaptively connected to the first input transistor pair; and a second input transistor pair, and a second cascode structure and a second tail current source adaptively connected to the second input transistor pair, wherein a first bias voltage is provided to the second cascode structure by means of a common node of the first input transistor pair and the first tail current source, and a second bias voltage is provided to the second cascode structure by means of a common node of the second input transistor pair and the second tail current source. Therefore, self-biasing can be achieved, thereby reducing power consumption and improving the response speed.

Description

Input stage circuit

[0001] This invention claims priority to Chinese Patent Application No. 202411898778.9, filed with the Chinese Patent Office on December 23, 2024, entitled “Input Stage Circuit”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of integrated circuit technology, and in particular to an input stage circuit. Background Technology

[0003] Rail-to-rail circuits are a type of circuit design primarily used in analog circuits such as operational amplifiers and comparators. In rail-to-rail input stage circuits, complementary differential input pairs (i.e., NMOS and PMOS pairs) are used to reduce limitations on the input signal range, enabling processing of the full range of input signals (i.e., from the negative rail to the positive rail). This maximizes the utilization of the power supply voltage and improves the flexibility and dynamic range of signal processing.

[0004] In existing technologies, a cascode structure is connected to the input pair transistors to achieve higher gain, stability, and linearity. However, the cascode structure requires additional bias circuitry to provide bias, and the introduction of bias circuitry increases power consumption while reducing bias following speed.

[0005] Therefore, a new input stage circuit is needed. Summary of the Invention

[0006] In view of the above problems, the object of the present invention is to provide an input stage circuit.

[0007] This application provides an input stage circuit for providing differential current to a subsequent stage circuit based on a differential input signal. The input stage circuit includes: a first input pair of transistors, and a first cascode structure and a first tail current source adapted and connected to the first input pair of transistors; and a second input pair of transistors, and a second cascode structure and a second tail current source adapted and connected to the second input pair of transistors. A first bias voltage is provided to the second cascode structure through a common node of the first input pair of transistors and the first tail current source, and a second bias voltage is provided to the first cascode structure through a common node of the second input pair of transistors and the second tail current source.

[0008] Optionally, the first input pair includes a first NMOS transistor and a second NMOS transistor. The common node of the second terminal of the first NMOS transistor and the second terminal of the second NMOS transistor is connected to the first tail current source. The control terminal of the first NMOS transistor receives one of the differential input signals, and the control terminal of the second NMOS transistor receives the other of the differential input signals. The first cascode structure includes a third NMOS transistor and a fourth NMOS transistor. The control terminals of the third NMOS transistor and the fourth NMOS transistor are connected and receive the second bias voltage. The second terminal of the third NMOS transistor is connected to the first terminal of the first NMOS transistor. The first terminal of the third NMOS transistor provides one path of the first pair of differential currents. The second terminal of the fourth NMOS transistor is connected to the first terminal of the second NMOS transistor, and the first terminal of the fourth NMOS transistor provides the other path of the first pair of differential currents.

[0009] Optionally, the second input pair includes a first PMOS transistor and a second PMOS transistor. The common node of the first terminal of the first PMOS transistor and the first terminal of the second PMOS transistor is connected to the second tail current source. The control terminal of the first PMOS transistor receives one of the differential input signals, and the control terminal of the second PMOS transistor receives the other of the differential input signals. The second cascode structure includes a third PMOS transistor and a fourth PMOS transistor. The control terminals of the third PMOS transistor and the fourth PMOS transistor are connected and receive the first bias voltage. The first terminal of the third PMOS transistor is connected to the second terminal of the first PMOS transistor. The second terminal of the third PMOS transistor provides one path of the second pair of differential currents. The first terminal of the fourth PMOS transistor is connected to the second terminal of the second PMOS transistor. The second terminal of the fourth PMOS transistor provides the other path of the second pair of differential currents.

[0010] Optionally, the subsequent circuitry includes resistors and / or current mirrors and / or diodes.

[0011] Optionally, the subsequent circuit can be multiplexed as the output stage circuit of an operational amplifier.

[0012] Optionally, the output stage circuit includes: an amplification unit for providing a differential first signal and a second signal based on the differential current; and an output unit for providing an output signal at an output node based on the first signal and the second signal.

[0013] Optionally, the amplification unit includes: a third cascode structure for receiving a first pair of differential currents provided by the first cascode structure and providing a first signal based on the first pair of differential currents; and a fourth cascode structure for receiving a second pair of differential currents provided by the second cascode structure and providing a second signal based on the second pair of differential currents. The output unit includes: a push-pull cascode structure capable of rail-to-rail output; and an output bias module for controlling the push-pull cascode structure to achieve Class AB operation.

[0014] Optionally, the third cascode structure includes: a fifth PMOS transistor and a seventh PMOS transistor connected to a control terminal, and a sixth PMOS transistor and an eighth PMOS transistor connected to a control terminal. The control terminal of the fifth PMOS transistor is connected to the second terminal of the sixth PMOS transistor, the first terminal is connected to the positive rail of the power supply, the second terminal is connected to the first terminal of the sixth PMOS transistor and receives one of the first pair of differential currents, the control terminal of the sixth PMOS transistor receives a first control voltage, the first terminal of the seventh PMOS transistor is connected to the positive rail of the power supply, the second terminal is connected to the first terminal of the eighth PMOS transistor and receives the other of the first pair of differential currents, and the second terminal of the eighth PMOS transistor provides the first signal.

[0015] Optionally, the fourth cascode structure includes: a fifth NMOS transistor and a seventh NMOS transistor connected to a control terminal, and a sixth NMOS transistor and an eighth NMOS transistor connected to a control terminal. The control terminal of the fifth NMOS transistor receives a second control voltage, its first terminal is connected to the control terminal of the sixth NMOS transistor, its second terminal is connected to the first terminal of the sixth NMOS transistor and receives one of the second pair of differential currents, and the second terminal of the sixth NMOS transistor is connected to the negative rail of the power supply. The first terminal of the seventh NMOS transistor provides the second signal, its second terminal is connected to the first terminal of the eighth NMOS transistor and receives the other of the second pair of differential currents, and the second terminal of the eighth NMOS transistor is connected to the negative rail of the power supply.

[0016] Optionally, the push-pull common-source structure includes a PMOS output transistor and an NMOS output transistor.

[0017] The output bias module includes a ninth PMOS transistor, a tenth PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. The common node of the first terminal of the ninth PMOS transistor and the first terminal of the ninth NMOS transistor is connected to the second terminal of the sixth PMOS transistor. The common node of the second terminal of the ninth PMOS transistor and the second terminal of the ninth NMOS transistor is connected to the first terminal of the fifth NMOS transistor. The common node of the first terminal of the tenth PMOS transistor and the first terminal of the tenth NMOS transistor is connected to the second terminal of the eighth PMOS transistor. The common node of the second terminal of the tenth PMOS transistor and the second terminal of the tenth NMOS transistor is connected to the first terminal of the seventh NMOS transistor. The control terminals of the ninth NMOS transistor and the tenth NMOS transistor receive a third control voltage, and the control terminals of the ninth PMOS transistor and the tenth PMOS transistor receive a fourth control voltage. The third control voltage and the fourth control voltage are differential signals.

[0018] According to the input stage circuit provided by the present invention, the bias voltage of the first cascode structure follows the first terminal voltage of the second input pair transistors (the first terminal voltage of the PMOS transistor), and the bias voltage of the second cascode structure follows the first terminal voltage of the first input pair transistors (the first terminal voltage of the NMOS transistor). The self-biasing of the first and second cascode structures can be realized without the need for an additional bias circuit, which helps to reduce the power consumption of the input stage circuit and improve the following speed of the cascode structure. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 shows a schematic circuit diagram of the input stage circuit provided by the present invention;

[0021] Figure 2 shows a schematic structural diagram of the operational amplifier provided by the present invention;

[0022] Figure 3 shows a schematic circuit diagram of the output stage circuit in Figure 2. Detailed Implementation

[0023] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0024] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0025] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0026] In this invention, the MOSFET includes a first terminal, a second terminal, and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. The first terminal, the second terminal, and the control terminal of the P-type MOSFET are the source, the drain, and the gate, respectively, and the first terminal, the second terminal, and the control terminal of the N-type MOSFET are the drain, the source, and the gate, respectively.

[0027] Figure 1 shows a schematic structural diagram of the input stage circuit provided by the present invention. Referring to Figure 1, the input stage circuit 100 provided by the present invention is connected between the positive and negative power rails, and is used to provide differential current to the subsequent circuit according to the differential input signal. The differential input signal includes, for example, a first input signal INN and a second input signal INP, and the differential current includes, for example, a first pair of differential currents Iout1 and Iout2 and a second pair of differential currents Iout3 and Iout4. The positive power rail receives the power supply voltage VDD, and the negative power rail receives the ground voltage GND. The power supply voltage VDD is higher than the ground voltage GND. For example, VDD is approximately 5V, and the ground voltage is approximately 0V.

[0028] Referring again to Figure 1, the input stage circuit 100 includes:

[0029] The first input pair transistor 120, and the first cascode structure 130 and the first tail current source 110 adapted and connected to the first input pair transistor 120. The first cascode structure 130 is connected to the subsequent circuit to provide a first pair of differential currents. In Figure 1, the first pair of differential currents includes a first output current Iout1 and a second output current Iout2.

[0030] The second input pair transistor 150, and the second cascode structure 160 and the second tail current source 140 adapted and connected to the second input pair transistor 150. The second cascode structure 160 is connected to the subsequent circuit to provide a second pair of differential currents. In Figure 1, the second pair of differential currents includes a third output current Iout3 and a fourth output current Iout4.

[0031] In order to achieve self-biasing of the cascode structure, in the input stage circuit 100 provided by the present invention, the common node of the first tail current source 110 and the first input pair transistor 120 provides a first bias voltage (i.e., point B voltage) to the second cascode structure 160, and the common node of the second tail current source 140 and the second input pair transistor 150 provides a second bias voltage (i.e., point A voltage) to the first cascode structure 130.

[0032] It should be understood that the first current source 110, the first input pair 120, the first cascode structure 130, the second current source 140, the second input pair 150, and the second cascode structure 160 can be implemented using any relevant circuits in the prior art. For example, the first input pair 120 and / or the second input pair 150 may also be implemented using transistors. No further limitations or descriptions are made in this invention.

[0033] As an example, in the embodiment shown in FIG1, the first tail current source 110 includes a single NMOS transistor M1 controlled by voltage B1, with a first terminal of NMOS transistor M1 providing a first current and a second terminal connected to the negative rail of the power supply. The second tail current source 140 includes a single PMOS transistor M2 controlled by voltage B2, with a first terminal connected to the positive rail of the power supply and a second terminal providing a second current. A first input pair 120 and a matched first cascode structure 130 provide a first pair of differential currents according to the first current, and a second input pair 150 and a matched second cascode structure 160 provide a second pair of differential currents according to the second current.

[0034] The first input pair 120 includes a first NMOS transistor NM1 and a second NMOS transistor NM2. The first cascode structure 130 includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4. The control terminal of the third NMOS transistor NM3 receives a second bias voltage, its first terminal is connected to the subsequent circuit to provide one of the first pair of differential currents (e.g., the first output current Iout1), its second terminal is connected to the first terminal of the first NMOS transistor, the second terminal of the first NMOS transistor is connected to the first current source 110, and its control terminal receives a first input signal INN. The control terminal of the fourth NMOS transistor receives a second bias voltage, its first terminal is connected to the subsequent circuit to provide the other of the first pair of differential currents (e.g., the second current Iout2), its second terminal is connected to the first terminal of the second NMOS transistor, the second terminal of the second NMOS transistor is connected to the first current source 110, and its control terminal receives a second input signal INP.

[0035] The second input pair 150 includes a first PMOS transistor PM1 and a second PMOS transistor PM2. The second cascode structure 160 includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4. The control terminal of the first PMOS transistor PM1 receives a first input signal INN, its first terminal is connected to a second current source 140, and its second terminal is connected to the first terminal of the third PMOS transistor PM3. The control terminal of the third PMOS transistor PM3 receives a first bias voltage, and its second terminal is connected to the subsequent circuit to provide one of the second pair of differential currents (e.g., the third current Iout3). The control terminal of the second PMOS transistor PM2 receives a second input signal INP, its first terminal is connected to the second current source 140, and its second terminal is connected to the first terminal of the fourth PMOS transistor PM4. The control terminal of the fourth PMOS transistor PM4 receives a first bias voltage, and its second terminal is connected to the subsequent circuit to provide the other of the second pair of differential currents (e.g., the fourth current Iout4).

[0036] The second bias voltage is determined by the second input transistor 150, and can be expressed by the following formula (1):

[0037] (1)

[0038] Among them, V A The second bias voltage is V, INN is the first input signal, INP is the second input signal, and V is the second bias voltage. GSPThis is the gate-source voltage when the PMOS transistor is turned on. It should be understood that the PMOS transistors in the second input pair 150 are of the same type, and the PMOS transistors in the second cascode structure 160 are of the same type. Therefore, the gate-source voltages when the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on are the same. In other words, the gate-source voltage when either the first PMOS transistor PM1 or the second PMOS transistor PM2 is turned on is this V. GSP Similarly, the source-drain voltages of the first PMOS transistor PM1 or the second PMOS transistor PM2 are the same when they are turned on, and both are represented by V. SDP Indicating that the gate-source voltages of the first NMOS transistor NM1 or the second NMOS transistor NM2 are the same when they are turned on, both are represented by... The drain-source voltage is also the same and is represented by V. DSN This will not be elaborated upon further below.

[0039] Furthermore, the voltage at point A can also be expressed by the following formula (2):

[0040] (2)

[0041] Among them, V A The second bias voltage is V, INN is the first input signal, INP is the second input signal, and V is the second bias voltage. DSN This is the drain-source voltage when the NMOS transistor is turned on.

[0042] Based on the differential characteristic, the input stage circuit 100 can only operate effectively when the first input signal INN and the second input signal INP are close. Let the voltage at this point be denoted as Vin, then:

[0043] Vin=INN≈INP (3)

[0044] Combining equations (1), (2), and (3) above, we can obtain:

[0045] (4)

[0046] Among them, V GSP V is the gate-source voltage when the PMOS transistor is turned on. DSN This is the drain-source voltage when the NMOS transistor is turned on.

[0047] The first bias voltage is determined by the first input transistor 120, and can be expressed by the following formula (5):

[0048] (5)

[0049] Among them, V B V is the first bias voltage, INN is the first input signal, INP is the second input signal, and V is the second bias voltage. GSN This is the gate-source voltage when the NMOS transistor is turned on.

[0050] Furthermore, the voltage at point B can also be expressed by the following formula (6):

[0051] (6)

[0052] Among them, V B V is the first bias voltage, INN is the first input signal, INP is the second input signal, and V is the second bias voltage. SDP This is the source-drain voltage when the PMOS transistor is turned on.

[0053] Combining equations (3), (5), and (6) above, we can obtain:

[0054] (7)

[0055] Among them, V GSN V is the gate-source voltage when the NMOS transistor is turned on. DSP This is the drain-source voltage when the PMOS transistor is turned on.

[0056] Furthermore, according to the saturation current formula, if:

[0057] (8)

[0058] The device is then in the saturation region, at V GS When the differences are minimal, both the conducting NMOS and PMOS transistors are biased in the saturation region. Furthermore, even if the first input signal INN / second input signal INP are close to the positive / negative power rail, it will not affect the input stage circuitry.

[0059] Furthermore, when the first input signal INN and the second input signal INP of the differential pair undergo rapid transitions (supporting a slew rate of 80MV / s at least with a total current of 160µA, and symmetrical pull-up and pull-down speeds), the first terminal voltage of the corresponding transistors in the first input pair 120 / second input pair 150 will also respond rapidly and change accordingly, so the above formula still holds true.

[0060] In summary, according to the input stage circuit provided by this invention, the bias voltage of the first cascode structure follows the first terminal voltage of the second input pair (the first terminal voltage of the PMOS transistor), and the bias voltage of the second cascode structure follows the first terminal voltage of the first input pair (the first terminal voltage of the NMOS transistor). This eliminates the need for additional bias circuitry, enabling self-biasing of both the first and second cascode structures. This reduces power consumption in the input stage circuit and improves the following speed of the cascode structure. Furthermore, the self-biased first and second cascode structures are easier to integrate with gain circuits in subsequent stages to achieve multi-stage gain.

[0061] Furthermore, in the embodiments of the present invention, no excessive restrictions are placed on the subsequent circuitry. For example, the subsequent circuitry may include resistors and / or current mirrors and / or diodes, etc. By adjusting the circuit structure of the subsequent circuitry, the rail-to-rail input stage circuitry provided by the present invention can be applied to different analog circuit structures such as operational amplifiers, comparators, digital-to-analog converters, and analog-to-digital converters.

[0062] For example, taking the input stage circuit 100 as the input stage circuit of an operational amplifier, Figure 2 shows a schematic block diagram of the operational amplifier, and Figure 3 shows a schematic circuit diagram of the output stage circuit 200 in Figure 2. The application of the input stage circuit provided by the present invention in an operational amplifier will be further described below with reference to Figures 2 and 3.

[0063] Referring to Figure 2, the operational amplifier 10 includes an input stage circuit 100 and an output stage circuit 200 (i.e., the aforementioned subsequent stage circuit) connected between the positive and negative power rails, respectively. The positive power rail receives the power supply voltage VDD, and the negative power rail receives the ground voltage GND.

[0064] The input stage circuit 100 receives a pair of differential input signals (i.e., the first input signal INN and the second input signal INP mentioned above) and provides differential current Iout (i.e., the first pair of differential currents and the second pair of differential currents mentioned above) to the output stage circuit 200. The specific structure of the input stage circuit 100 is as described above and will not be repeated here.

[0065] The output stage circuit 200 provides an output signal Vout based on the differential current Iout. The output stage circuit 200 can be implemented by any related circuit in the prior art. For example, in FIG3, the output stage circuit 200 includes: an amplification unit for providing a first signal and a second signal (the first signal and the second signal are differential signals) based on the differential current Iout, and an output unit for providing an output signal at the output node based on the first signal and the second signal.

[0066] Specifically, referring to Figure 3, the amplification unit includes a third cascode structure 210 for receiving a first pair of differential currents (e.g., the first output current Iout1 and the second output current Iout2 mentioned above) and providing a first signal S1 based on the first pair of differential currents, and a fourth cascode structure 230 for receiving a second pair of differential currents (e.g., the third output current Iout3 and the fourth output current Iout4 mentioned above) and providing a second signal S2 based on the second pair of differential currents. The output unit includes a push-pull cascode structure 240 capable of realizing rail-to-rail output, and an output bias module 230 for controlling the push-pull cascode structure to realize Class AB operation.

[0067] For example, the third cascode structure 210 includes: a fifth PMOS transistor PM5 and a seventh PMOS transistor PM7 connected to the control terminal, and a sixth PMOS transistor PM6 and an eighth PMOS transistor PM8 connected to the control terminal. The fourth cascode structure 220 includes: a fifth NMOS transistor NM5 and a seventh NMOS transistor NM7 connected to the control terminal, and a sixth NMOS transistor NM6 and an eighth NMOS transistor NM8 connected to the control terminal. The output bias module 230 includes a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a ninth NMOS transistor NM9, and a tenth NMOS transistor NM10. The push-pull cascode structure 240 includes a PMOS output transistor PM11 and an NMOS output transistor NM11.

[0068] Specifically, the common node of the first terminal of the ninth PMOS transistor PM9 and the first terminal of the ninth NMOS transistor NM9 is the first terminal of the output bias module 230, the common node of the first terminal of the tenth PMOS transistor PM10 and the first terminal of the tenth NMOS transistor NM10 is the second terminal of the output bias module 230, the common node of the second terminal of the ninth PMOS transistor PM9 and the second terminal of the ninth NMOS transistor NM9 is the third terminal of the output bias module 230, and the common node of the second terminal of the tenth PMOS transistor PM10 and the second terminal of the tenth NMOS transistor NM10 is the fourth terminal of the output bias module 230.

[0069] Among them, the control terminals of the ninth NMOS transistor NM9 and the tenth NMOS transistor NM10 receive the third control voltage VB3, and the control terminals of the ninth PMOS transistor and the tenth PMOS transistor receive the fourth control voltage VB4. The third control voltage VB3 and the fourth control voltage VB4 are differential signals.

[0070] The control terminal of the fifth PMOS transistor PM5 is connected to the second terminal of the sixth PMOS transistor PM6. The first terminal of PM5 is connected to the positive power rail, and the second terminal is connected to the first terminal of the sixth PMOS transistor PM6 and receives one of the first pair of differential currents (e.g., the second output current Iout2). The control terminal of the sixth PMOS transistor PM6 receives the first control signal VB1, and the second terminal is connected to the first terminal of the output bias module 230. The first terminal of the seventh PMOS transistor PM7 is connected to the positive power rail, and the second terminal is connected to the first terminal of the eighth PMOS transistor PM8 and receives the other of the first pair of differential currents (e.g., the first output current Iout1). The second terminal of the eighth PMOS transistor PM8 is connected to the second terminal of the output bias module 220 and provides the first signal S1.

[0071] The control terminal of the fifth NMOS transistor NM5 receives the second control signal VB2. Its first terminal is connected to the third terminal of the output bias module 230, and its second terminal is connected to the first terminal of the sixth NMOS transistor NM6 and receives one of the second pair of differential currents (e.g., the fourth output current Iout4). The second terminal of the sixth NMOS transistor NM6 is connected to the negative power rail. The first terminal of the seventh NMOS transistor NM7 is connected to the fourth terminal of the output bias module 230 and provides the second signal S2. Its second terminal is connected to the first terminal of the eighth NMOS transistor NM8 and receives the other of the second pair of differential currents (e.g., the third output current Iout3). The second terminal of the eighth NMOS transistor NM8 is connected to the negative power rail.

[0072] The control terminal of PMOS output transistor PM11 receives the first signal S1, and the first terminal is connected to the positive power rail. The second terminal is connected to the first terminal of NMOS output transistor NM11 and provides the output signal Vout (i.e., the common node of PMOS output transistor PM11 and NMOS output transistor NM11 is the output node of output stage circuit 200). The control terminal of NMOS output transistor NM11 receives the second signal S2, and the second terminal is connected to the negative power rail.

[0073] The operational amplifier provided in this application also includes the input stage circuit 100 provided in this application, and therefore also has the aforementioned beneficial effects of this application. Furthermore, since the input stage circuit 100 includes a self-biased first cascode structure and a second cascode structure, it can more easily cooperate with the third cascode structure and the fourth cascode structure to achieve multi-stage gain, thereby improving the linearity, stability, and overall gain of the operational amplifier.

[0074] The embodiments of the present invention described above are examples of specific examples, and do not exhaustively describe all details, nor do they limit the present invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to make good use of the present invention and modifications based on it. The scope of protection of the present invention should be determined by the scope defined in the claims of the present invention.

Claims

1. An input stage circuit for providing differential current to a subsequent stage circuit based on a differential input signal, wherein, The input stage circuit includes: A first input pair of transistors, and a first cascode structure and a first tail current source adapted and connected to the first input pair of transistors; and The second input pair, and the second cascode structure and the second tail current source adapted and connected to the second input pair. Specifically, a first bias voltage is provided to the second cascode structure through the common node of the first input pair transistors and the first tail current source, and a second bias voltage is provided to the first cascode structure through the common node of the second input pair transistors and the second tail current source.

2. The input stage circuit according to claim 1, wherein, The first input pair includes a first NMOS transistor and a second NMOS transistor. The common node of the second terminals of the first and second NMOS transistors is connected to the first tail current source. The control terminal of the first NMOS transistor receives one of the differential input signals, and the control terminal of the second NMOS transistor receives the other of the differential input signals. The first common-source common-gate structure includes a third NMOS transistor and a fourth NMOS transistor. The control terminals of the third NMOS transistor and the fourth NMOS transistor are connected and receive the second bias voltage. The second terminal of the third NMOS transistor is connected to the first terminal of the first NMOS transistor. The first terminal of the third NMOS transistor provides one of the first pair of differential currents. The second terminal of the fourth NMOS transistor is connected to the first terminal of the second NMOS transistor. The first terminal of the fourth NMOS transistor provides the other of the first pair of differential currents.

3. The input stage circuit according to claim 1, wherein, The second input pair includes a first PMOS transistor and a second PMOS transistor. The common node of the first terminal of the first PMOS transistor and the first terminal of the second PMOS transistor is connected to the second tail current source. The control terminal of the first PMOS transistor receives one of the differential input signals, and the control terminal of the second PMOS transistor receives the other of the differential input signals. The second common-source cascode structure includes a third PMOS transistor and a fourth PMOS transistor. The control terminals of the third PMOS transistor and the fourth PMOS transistor are connected and receive the first bias voltage. The first terminal of the third PMOS transistor is connected to the second terminal of the first PMOS transistor. The second terminal of the third PMOS transistor provides one of the second pair of differential currents. The first terminal of the fourth PMOS transistor is connected to the second terminal of the second PMOS transistor. The second terminal of the fourth PMOS transistor provides the other of the second pair of differential currents.

4. The input stage current according to claim 1, wherein, The subsequent circuitry includes resistors and / or current mirrors and / or diodes.

5. The input stage circuit according to claim 1, wherein, The subsequent stage circuit is reused as the output stage circuit of an operational amplifier.

6. The input stage circuit according to claim 5, wherein, The output stage circuit includes: An amplification unit is configured to provide a differential first signal and a differential second signal based on the differential current; and An output unit is used to provide an output signal at an output node based on the first signal and the second signal.

7. The input stage circuit according to claim 6, wherein, The amplification unit includes: A third cascode structure is configured to receive a first pair of differential currents provided by the first cascode structure and provide a first signal based on the first pair of differential currents; and The fourth cascode structure is used to receive the second pair of differential currents provided by the second cascode structure, and to provide a second signal based on the second pair of differential currents. The output unit includes: a push-pull common source structure capable of rail-to-rail output, and an output bias module that controls the push-pull common source structure to achieve Class AB operation.

8. The input stage circuit according to claim 7, wherein, The third common-source cascode structure includes: a fifth PMOS transistor and a seventh PMOS transistor connected to the control terminal, and a sixth PMOS transistor and an eighth PMOS transistor connected to the control terminal. The control terminal of the fifth PMOS transistor is connected to the second terminal of the sixth PMOS transistor. The first terminal is connected to the positive rail of the power supply, and the second terminal is connected to the first terminal of the sixth PMOS transistor and receives one of the first pair of differential currents. The control terminal of the sixth PMOS transistor receives a first control voltage. The first terminal of the seventh PMOS transistor is connected to the positive rail of the power supply, and the second terminal is connected to the first terminal of the eighth PMOS transistor and receives the other path of the first pair of differential currents. The second terminal of the eighth PMOS transistor provides the first signal.

9. The input stage circuit according to claim 8, wherein, The fourth common-source cascode structure includes: a fifth NMOS transistor and a seventh NMOS transistor connected to the control terminal, and a sixth NMOS transistor and an eighth NMOS transistor connected to the control terminal. The control terminal of the fifth NMOS transistor receives a second control voltage. Its first terminal is connected to the control terminal of the sixth NMOS transistor, and its second terminal is connected to the first terminal of the sixth NMOS transistor and receives one of the second pair of differential currents. The second terminal of the sixth NMOS transistor is connected to the negative power rail. The first terminal of the seventh NMOS transistor provides the second signal, and the second terminal is connected to the first terminal of the eighth NMOS transistor and receives the other path of the second pair of differential currents. The second terminal of the eighth NMOS transistor is connected to the negative rail of the power supply.

10. The input stage circuit according to claim 9, wherein, The push-pull common-source structure includes a PMOS output transistor and an NMOS output transistor. The output bias module includes: a ninth PMOS transistor, a tenth PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. The common node of the first terminal of the ninth PMOS transistor and the first terminal of the ninth NMOS transistor is connected to the second terminal of the sixth PMOS transistor, and the common node of the second terminal of the ninth PMOS transistor and the second terminal of the ninth NMOS transistor is connected to the first terminal of the fifth NMOS transistor. The common node of the first terminal of the tenth PMOS transistor and the first terminal of the tenth NMOS transistor is connected to the second terminal of the eighth PMOS transistor, and the common node of the second terminal of the tenth PMOS transistor and the second terminal of the tenth NMOS transistor is connected to the first terminal of the seventh NMOS transistor. The control terminals of the ninth NMOS transistor and the tenth NMOS transistor receive a third control voltage, and the control terminals of the ninth PMOS transistor and the tenth PMOS transistor receive a fourth control voltage. The third control voltage and the fourth control voltage are differential signals.

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