Delay circuit and drive circuit

Abstract

Provided in the present application are a delay circuit and a drive circuit. The delay circuit comprises a signal input terminal, a reference voltage terminal, a control switch, a delay unit, and a comparison unit, wherein the signal input terminal is used for receiving an input signal; the reference voltage terminal is used for receiving a reference voltage signal; the control switch is electrically connected to the signal input terminal; the delay unit is electrically connected between a power terminal and a ground terminal, and is electrically connected to the control switch; when the control switch is turned on or turned off under the control of the input signal, the delay circuit performs charging or discharging, so as to output a charging voltage or a discharging voltage; and the comparison unit is electrically connected to the delay unit and the reference voltage terminal, and the comparison unit is used for comparing the charging voltage or the discharging voltage with the reference voltage signal, so as to output an input signal. The delay circuit in the present application can accurately control the delay duration of an input signal, without being affected by factors such as process parameters, temperature and power voltage, thereby making the delay duration more stable.

Description

Delay circuit and drive circuit Cross-reference to related applications

[0001] This patent application claims priority to Chinese Patent Application No. 202411966101.4, filed on December 27, 2024, entitled "Delay Circuit and Drive Circuit", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of driving circuit technology, and in particular to a delay circuit and a driving circuit. Background Technology

[0003] In related technologies, traditional drive circuits typically generate delays using RC circuits, with the delay duration usually determined by an RC structure. However, because the resistance fluctuates significantly with process parameters, temperature, and power supply voltage, changes in these factors lead to substantial variations in the charging and discharging currents of the delay circuit. This results in changes to the delay duration, making it uncontrollable or inaccurate. Summary of the Invention

[0004] This application provides an improved delay circuit and driving circuit.

[0005] This application provides a delay circuit, comprising: a signal input terminal for receiving an input signal; a reference voltage terminal for receiving a reference voltage signal; a control switch electrically connected to the signal input terminal; a delay unit electrically connected between a power supply terminal and a ground terminal, and electrically connected to the control switch; when the control switch is controlled to open or close by the input signal, the delay circuit charges or discharges to output a charging voltage or a discharging voltage; and a comparison unit electrically connected to the delay unit and the reference voltage terminal; the comparison unit is used to compare the charging voltage or the discharging voltage with the reference voltage signal respectively to output the input signal.

[0006] Preferably, the delay unit includes a delay current source and a delay capacitor, the delay current source and the delay capacitor being connected in series between the power supply terminal and the ground terminal, and respectively electrically connected to the control switch; wherein, when the control switch is closed, the delay current source charges the delay capacitor, and the delay unit outputs the charging voltage; when the control switch is open, the delay capacitor discharges to the ground terminal, and the delay unit outputs the discharging voltage.

[0007] Preferably, the control switch includes a MOSFET, the first terminal of which is electrically connected to the signal input terminal, the second terminal of which is electrically connected to the delay unit and the comparison unit respectively, and the third terminal of which is electrically connected to the ground terminal.

[0008] Preferably, the MOS transistor is an N-type MOS transistor, wherein the first terminal of the N-type MOS transistor is the gate, the second terminal is the drain, and the third terminal is the source.

[0009] Preferably, the comparison unit includes a comparator, the first input terminal of the comparator is electrically connected to the delay unit, and the second input terminal of the comparator is electrically connected to the reference voltage terminal.

[0010] Preferably, the first input terminal is an inverting input terminal, and the second input terminal is a non-inverting input terminal; the inverting input terminal is electrically connected to the delay unit, and the non-inverting input terminal is electrically connected to the reference voltage terminal.

[0011] Preferably, the delay circuit includes a reference voltage generating circuit and a reference voltage terminal; the reference voltage generating circuit includes a reference current source and a Zener diode, the reference current source is electrically connected between the power supply terminal and the reference voltage terminal, the positive terminal of the Zener diode is connected to the ground terminal, and the negative terminal of the Zener diode is electrically connected to the reference voltage terminal.

[0012] Preferably, the delay circuit further includes a bias circuit, which includes a bias unit and a current mirror unit. The bias unit generates current, and the current mirror unit replicates the current of the bias unit and is electrically connected to the delay current source and the reference current source. The current mirror unit is provided with a fuse adjustment unit, which includes multiple fuses. The output current of the current mirror unit is adjusted by blowing at least one of the multiple fuses.

[0013] This application also provides a driving circuit, including at least one delay circuit as described in any of the above embodiments.

[0014] Preferably, the number of delay circuits is set to multiple, and the multiple delay circuits are connected in series.

[0015] Preferably, the charging time of the plurality of delay circuits is positively correlated with the number of delay circuits connected in series.

[0016] Preferably, the discharge duration of the plurality of delay circuits is positively correlated with the number of delay circuits connected in series.

[0017] This application discloses a delay circuit and a driving circuit. The delay circuit comprises a control switch, a delay unit, and a comparison unit. The delay unit is electrically connected between the power supply terminal and the ground terminal, and is also electrically connected to the control switch. The comparison unit is electrically connected to the delay unit and a reference voltage terminal. When the control switch is opened or closed by an input signal, the delay circuit charges or discharges to output a charging voltage or a discharging voltage. The comparison unit compares the charging voltage or discharging voltage with a reference voltage signal to output a delayed input signal. The delay circuit of this application can precisely control the delay duration of the input signal by controlling the magnitude of the charging current or discharging current. It is not affected by factors such as process parameters, temperature, and power supply voltage. The charging current and discharging current are also unaffected by these factors, resulting in a more stable delay duration. Attached Figure Description

[0018] Figure 1 shows a circuit diagram of one embodiment of the delay circuit of this application.

[0019] Figures 2a and 2b show the charging and discharging curves of the delay capacitor in the delay circuit shown in Figure 1.

[0020] Figure 3 shows a circuit diagram of an embodiment of the bias circuit of the delay circuit shown in Figure 1.

[0021] Figure 4 shows a circuit diagram of one embodiment of the driving circuit of this application. Detailed Implementation

[0022] The delay circuit and driving circuit of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0023] Figure 1 shows a circuit diagram of an embodiment of the delay circuit 10 of this application. As shown in Figure 1, the delay circuit 10 of this embodiment is used to delay the output of an input signal. Specifically, the delay circuit 10 includes a signal input terminal Vin, a reference voltage terminal Vref, a control switch Q1, a delay unit 11, and a comparison unit 12. The control switch Q1 is electrically connected to the signal input terminal Vin. The delay unit 11 is electrically connected between the power supply terminal VCC and the ground terminal GND, and is also electrically connected to the control switch Q1. The comparison unit 12 is electrically connected to the delay unit 11 and the reference voltage terminal Vref. In this embodiment, the signal input terminal Vin is used to receive the input signal. The reference voltage terminal Vref is used to receive a reference voltage signal. When the control switch Q1 is controlled to open or close by the input signal, the delay circuit 10 charges or discharges to output a charging voltage or a discharging voltage. The comparison unit 12 is used to compare the charging voltage or discharging voltage with the reference voltage signal respectively to output the input signal. In this embodiment, when the control switch Q1 is closed by the input signal, the delay circuit 10 charges to output a charging voltage. The comparison unit 12 compares the charging voltage with a reference voltage signal to output an input signal. When the control switch Q1 is opened by the input signal, the delay circuit 10 discharges to output a discharging voltage. The comparison unit 12 compares the discharging voltage with a reference voltage signal to output an input signal. With this configuration, the delay circuit 10 of this application can precisely control the delay duration of the input signal by controlling the magnitude of the charging current or discharging current, without being affected by factors such as process parameters, temperature, and power supply voltage. The charging current and discharging current are also unaffected by these factors, resulting in a more stable delay duration.

[0024] Figures 2a and 2b show the charging and discharging curves of the delay capacitor in the delay circuit 10 shown in Figure 1. Referring to Figures 1, 2a, and 2b, the delay unit 11 includes a delay current source I1 and a delay capacitor C1. The delay current source I1 and the delay capacitor C1 are connected in series between the power supply terminal VCC and the ground terminal GND, and are also electrically connected to the control switch Q1.

[0025] In this embodiment, when the control switch Q1 is closed, the delay current source I1 charges the delay capacitor C1, and the delay unit 11 outputs a charging voltage. The comparison unit 12 compares the charging voltage with a reference voltage signal to output an input signal. The charging duration of this input signal can be precisely controlled by the magnitude of the charging current of the delay capacitor C1 through the delay current source I1, and is not affected by factors such as process parameters, temperature, and power supply voltage, making the delay duration more stable.

[0026] In this embodiment, when the control switch Q1 is turned on, the delay capacitor C1 discharges to the ground terminal GND, and the delay unit 11 outputs a discharge voltage. The comparison unit 12 is used to compare the discharge voltage with the reference voltage signal to output an input signal. The discharge duration of this input signal can be precisely controlled by the discharge magnitude of the delay capacitor C1 to ground, and is not affected by factors such as process parameters, temperature, and power supply voltage, making the delay duration more stable.

[0027] In the embodiments shown in Figures 1 and 2a, during the charging process, when the control switch Q1 is closed, the delay current source I1 charges the delay capacitor C1, and the voltage at node V1 gradually increases. At this time, the voltage at node V1 and the reference voltage provided by the reference voltage terminal Vref are input to the comparison unit 12 for comparison. In the above process, the charge formula of the delay capacitor C1 is: q = ∫idt. Since the delay current source I1 is a constant current source, the charge of the delay capacitor C1 is: q = I·t. Combining the charge characteristic of the delay capacitor C1: q = CU, the voltage of the delay capacitor C1 can be determined as: V1 = I1*t / C.

[0028] As can be seen from the above formula, the voltage of node V1 is linearly related to the charging time (as shown in Figure 2a). Furthermore, by changing the current value of the delay current source I1, the charging speed of the delay capacitor C1 can be changed, thereby controlling the charging duration and thus precisely controlling the delay duration.

[0029] In the embodiments shown in Figures 1 and 2b, during the discharge process, when the control switch Q1 is turned on, the delay capacitor C1 discharges to the ground terminal GND through the control switch Q1. The voltage at node V1 decreases over time, and the discharge expression is: V1 = VCC * exp(-t / RC). At this time, the voltage at node V1 is compared with the voltage provided by the reference voltage terminal Vref in the comparison unit 12. When V1 = Vref, the output voltage of the comparison unit 12 flips. With this configuration, the delay time can be precisely controlled by controlling the magnitude of the discharge current.

[0030] Based on the charging and discharging processes described above, the expression for the delay duration is: Turn-on duration: ton = Vref * C / I1; Turn-off duration: tof = -RCln(Vref / VCC).

[0031] As can be seen from the above formula, the charging rise time and the discharging fall time are only related to the internal parameters of the circuit and are not affected by factors such as process parameters, temperature and power supply voltage. Thus, by adjusting the parameters, ton and toff can be precisely designed.

[0032] In the embodiments shown in Figures 2a and 2b, the charging process of the delay capacitor C1 is linear, and the discharging process is faster at the beginning and slower later. That is, when an error of ΔV is generated, the Δt corresponding to Vref1 is smaller than that of Vref2. This means that the discharge time accuracy is higher at the beginning of the discharge. To improve the accuracy of the discharge time, in practical applications, at least one delay circuit 10 can be set, that is, multiple delay circuits 10 can be connected in series, so that the delay time of a single delay unit is smaller, the discharge process of the delay capacitor C1 is kept in the first half of the curve, and the accuracy of toff is improved.

[0033] In the embodiments shown in Figures 1, 2a, and 2b, the delay circuit 10 outputs the input signal input at the signal input terminal Vin after a controllable delay. Without considering the delay, the signal truth table of the delay circuit 10 is shown in Table 1: Table 1: Signal Truth Table of the Delay Circuit

[0034] As shown in Table 1 above, the delay circuit 10 can complete the delayed transmission function of the input signal. Specifically, the delay working principle of the delay circuit 10 includes: when the signal input terminal Vin is 0, the control switch Q1 is closed, and the delay current source I1 charges the delay capacitor C1. At this time, the voltage of node V1 slowly rises from 0V. When the voltage of node V1 rises to a level greater than the reference voltage of the reference voltage terminal Vref, the comparison unit 12 outputs 0 through the output terminal Vout. When the signal input terminal Vin is 1, the control switch Q1 is opened, and the delay capacitor C1 discharges to the ground terminal GND through the control switch Q1. At this time, the voltage of node V1 slowly decreases. When the voltage of node V1 decreases to a level less than the reference voltage of the reference voltage terminal Vref, the comparison unit 12 outputs 1 through the output terminal Vout. According to the above process, since the charging and discharging of the delay capacitor C1 takes time, the delayed transmission of the input signal from the signal input terminal Vin to the signal output terminal Vout is completed, thus completing the delayed transmission function of the input signal. In the above process, the delay duration of the input signal can be precisely controlled by controlling the magnitude of the charging current or discharging current. It is not affected by factors such as process parameters, temperature and power supply voltage. The charging current and discharging current are also not affected by related factors, making the delay duration more stable.

[0035] In the embodiment shown in Figure 1, the control switch Q1 includes a MOSFET. The first terminal of the MOSFET is electrically connected to the signal input terminal Vin, the second terminal of the MOSFET is electrically connected to the delay unit 11 and the comparator unit 12, and the third terminal of the MOSFET is electrically connected to the ground terminal GND. In this embodiment, the MOSFET can be an N-type MOSFET. The first terminal of the N-type MOSFET can be the gate, the second terminal is the drain, and the third terminal is the source. In this embodiment, the gate of the N-type MOSFET is electrically connected to the signal input terminal Vin, the drain of the N-type MOSFET is electrically connected to the delay current source I1, the delay capacitor C1, and the input terminal of the comparator unit 12, and the source of the N-type MOSFET is electrically connected to the ground terminal GND. The input signal includes a pulse signal with a high level (1) or a low level (0). The N-type MOSFET is turned off when a low level is received and turned on when a high level is received. In this embodiment, the voltage drop across the N-type MOSFET is small, resulting in low power consumption. Furthermore, the N-type MOSFET can respond to changes in the input signal more quickly, achieving fast signal processing and high sensitivity.

[0036] In the embodiment shown in Figure 1, the comparison unit 12 includes a comparator. The first input terminal of the comparator is electrically connected to the delay unit 11, and the second input terminal of the comparator is electrically connected to the reference voltage terminal Vref. In this embodiment, the first input terminal of the comparator is an inverting input terminal, and the second input terminal is a non-inverting input terminal. The inverting input terminal of the comparator is electrically connected to the delay current source I1 and the delay capacitor C1. The non-inverting input terminal of the comparator is electrically connected to the reference voltage terminal Vref. The comparator receives the voltage of node V1 through the inverting input terminal and receives the reference voltage signal through the non-inverting input terminal, compares the voltage of node V1 with the reference voltage signal, and outputs the signal through the output terminal Vout. In the above process, the voltage of node V1 can be the charging voltage during charging or the discharging voltage during discharging. The comparator is used to output a delayed input signal when the charging voltage is greater than the reference voltage signal. The comparator is used to output a delayed input signal when the discharging voltage is less than the reference voltage signal. With this configuration, the input signal can be delayed and output, resulting in a simple circuit structure and low cost.

[0037] In the embodiment shown in Figure 1, the delay circuit 10 includes a reference voltage generation circuit 13 and a reference voltage terminal Vref. The reference voltage generation circuit 13 includes a reference current source I2 and a Zener diode D1. The reference current source I2 is electrically connected between the power supply terminal VCC and the reference voltage terminal Vref. The positive terminal of the Zener diode D1 is connected to the ground terminal GND, and the negative terminal of the Zener diode D1 is electrically connected to the reference voltage terminal Vref. In this embodiment, the reference current source I2 is electrically connected between the power supply terminal VCC and the reference voltage terminal Vref to provide a stable current for the Zener diode D1 to operate normally. The regulated voltage of the Zener diode D1 is the reference voltage at the Vref voltage terminal. This configuration assists the comparator in stabilizing the input signal output, making the system stable and reliable.

[0038] Figure 3 shows a circuit diagram of an embodiment of the bias circuit 14 of the delay circuit 10 shown in Figure 1. In the embodiment shown in Figure 3, the delay circuit 10 further includes a bias circuit 14, which includes a bias unit 141 and a current mirror unit 142. The bias unit 141 generates current, and the current mirror unit 142 replicates the current of the bias unit 141 and is electrically connected to the delay current source I1 and the reference current source I2. The current mirror unit 142 includes a fuse adjustment unit 143, which includes multiple fuses Rs. By blowing at least one of the multiple fuses Rs, the output current of the current mirror unit 142 is adjusted. This bias circuit 14 is used to generate current for the delay circuit 10, providing current to the delay current source I1 and the reference current source I2. The constant delay current source I1 generated by the bias circuit 14 charges and discharges the delay capacitor C1, and then compares it with the reference voltage signal to achieve a delayed output of the input signal. Furthermore, resistor R4 in bias circuit 14 is composed of a resistor with positive temperature characteristic and a resistor with negative temperature characteristic connected in series, thus providing temperature compensation. This configuration minimizes the impact of power supply voltage and temperature changes on the charging and discharging current of delay capacitor C1, and the duration parameter is adjustable. Fuse adjustments were also made to the charging and discharging current and the current flowing through the Zener diode, ensuring the accuracy of the current-to-voltage conversion on the capacitor entering the comparator and the accuracy of the reference voltage. This makes the switching point controllable, resulting in more stable ton and tooff values ​​and a more accurate delay duration.

[0039] In this embodiment, the bias circuit 14 adopts a Beta Multiplier structure, and the current expression is as follows:

[0040] W, L, R, and K are parameters of the devices in the Beta Multiplier structure. W and L represent the aspect ratio of N8, R represents the value of R4, and K represents the ratio of the number of N9 and N8 connected in parallel. As can be seen from the above expression, the output current is independent of the power supply voltage. Therefore, the current in this application is not affected by power supply voltage fluctuations.

[0041] In the embodiment shown in Figure 3, the left half of the circuit is a bias unit 141, and the right half is a current mirror unit 142, which contains a fuse adjustment unit 143. MOSFETs P3 and P1 form a current mirror structure, replicating Iout to the P3-N13 branch. MOSFETs N14 and N13 also form a current mirror, replicating Iout to the P4-N14 branch, and then replicating I1 to I4 through the current mirror. MOSFETs N10, N11, and N13 are connected in parallel to the circuit, and MOSFETs N12 and N14 are connected in parallel to the circuit. Adjusting the total W ratio of the left and right transistors can adjust the current ratio, thereby achieving fine-tuning.

[0042] If I1 is measured to be too high due to process fluctuations or other reasons, simply burn the fuse Rs below MOSFET N12, disconnecting MOSFET N12 from the circuit. This reduces the ratio of the right-side dimensions to the left-side dimensions, thus decreasing I1. If I1 is measured to be too low, burn the fuses of MOSFETs N10 / N11 / N10+N11, disconnecting them from the circuit. This increases the ratio of the right-side dimensions to the left-side dimensions, thus increasing I1. The above-mentioned fuse burning Rs process is performed during intermediate measurement, which can compensate for the deviation of I1 to I4 caused by process variations, thereby avoiding deviations in ton and tooff. With this setup, the current section uses the fuse adjustment unit 143, which can eliminate current errors caused by the process and make the delay time more accurate.

[0043] In some other embodiments, an oscillator + counter + controller approach can be used. The oscillator generates a square wave, and the desired delay time is calculated based on the oscillator frequency and the required delay time. The counter counts the square wave to obtain the desired delay time, and then the output signal is fed into the controller to produce a delay effect on the circuit.

[0044] Figure 4 shows a circuit diagram of one embodiment of the driving circuit 20 of this application. As shown in Figure 4, the driving circuit 20 includes at least one delay circuit 10 as shown in the embodiments of Figures 1, 2a, and 2b above. One or more delay circuits 10 can be provided. By providing one or more delay circuits 10, the driving circuit 20 can accurately control the delay duration of ton and toff, and is less affected by fluctuations in process parameters, temperature changes, and power supply voltage fluctuations, and the delay duration is stable and reliable.

[0045] In some embodiments, the number of delay circuits 10 is set to multiple, and the multiple delay circuits 10 are connected in series. In the embodiment shown in FIG. 4, two delay circuits 10 are connected in series. In some other embodiments, three or more delay circuits 10 are connected in series. The series-connected delay circuits 10 are connected by an inverter. The output signal of the previous stage delay circuit 10 is used as the input signal of the next stage delay circuit 10, and so on for delayed output. By connecting multiple delay circuits 10 in series, the delay duration can be precisely controlled.

[0046] In some embodiments, the charging time of the multiple delay circuits 10 is positively correlated with the number of delay circuits 10 connected in series. That is, the more delay circuits 10 are provided in the driving circuit 20, the longer their charging time will be. For example, when there are two delay circuits 10 connected in series, the charging time of the driving circuit 20 will be twice as long, thereby extending the delay time of the input signal by twice. In some embodiments, the discharging time of the multiple delay circuits 10 is positively correlated with the number of delay circuits 10 connected in series. That is, the more delay circuits 10 are provided in the driving circuit 20, the longer their discharging time will be. For example, when there are two delay circuits 10 connected in series, the discharging time of the driving circuit 20 will be twice as long, thereby shortening the delay time of the input signal by half.

[0047] Referring to Figures 2a, 2b, and 4, assuming the desired delay duration is T, for example, the drive circuit 20 contains two identical delay circuits 10, each with a delay duration of T / 2, corresponding to a voltage of Vref1. The drive circuit 20 may also contain only one delay circuit 10, corresponding to a voltage of Vref2. Vref1 has a larger slope, meaning that when generating an error of ΔV, the Δt corresponding to Vref1 is smaller than that of Vref2. Therefore, including two identical delay circuits 10 in the drive circuit 20 improves the accuracy of the delay duration. This principle can be applied to improve the accuracy of the delay duration, but will not be elaborated further here.

[0048] It should be understood that this application is not limited to the content already described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A delay circuit, characterized in that, include: The signal input terminal is used to receive input signals. The reference voltage terminal is used to receive the reference voltage signal; A control switch is electrically connected to the signal input terminal; The delay unit is electrically connected between the power supply terminal and the ground terminal, and is also electrically connected to the control switch. When the control switch is opened or closed by the input signal, the delay circuit charges or discharges to output a charging voltage or a discharging voltage. and The comparison unit is electrically connected to the delay unit and the reference voltage terminal; the comparison unit is used to compare the charging voltage or the discharging voltage with the reference voltage signal respectively, so as to output the input signal.

2. The delay circuit according to claim 1, characterized in that, The delay unit includes a delay current source and a delay capacitor, which are connected in series between the power supply terminal and the ground terminal, and are also electrically connected to the control switch. When the control switch is closed, the delay current source charges the delay capacitor, and the delay unit outputs the charging voltage. When the control switch is open, the delay capacitor discharges to the ground terminal, and the delay unit outputs the discharging voltage.

3. The delay circuit according to claim 1, characterized in that, The control switch includes a MOSFET, the first terminal of which is electrically connected to the signal input terminal, the second terminal of which is electrically connected to the delay unit and the comparator unit, and the third terminal of which is electrically connected to the ground terminal.

4. The delay circuit according to claim 3, characterized in that, The MOS transistor is an N-type MOS transistor, with the first terminal being the gate, the second terminal being the drain, and the third terminal being the source.

5. The delay circuit according to claim 1, characterized in that, The comparison unit includes a comparator, the first input terminal of which is electrically connected to the delay unit, and the second input terminal of which is electrically connected to the reference voltage terminal.

6. The delay circuit according to claim 5, characterized in that, The first input terminal is an inverting input terminal, and the second input terminal is a non-inverting input terminal; the inverting input terminal is electrically connected to the delay unit, and the non-inverting input terminal is electrically connected to the reference voltage terminal.

7. The delay circuit according to claim 1, characterized in that, The delay circuit includes a reference voltage generation circuit and a reference voltage terminal; The reference voltage generating circuit includes a reference current source and a Zener diode. The reference current source is electrically connected between the power supply terminal and the reference voltage terminal. The positive terminal of the Zener diode is connected to the ground terminal, and the negative terminal of the Zener diode is electrically connected to the reference voltage terminal.

8. The delay circuit according to claim 1, characterized in that, The delay circuit further includes a bias circuit, which includes a bias unit and a current mirror unit. The bias unit generates current, and the current mirror unit replicates the current of the bias unit and is electrically connected to the delay current source and the reference current source. The current mirror unit is provided with a fuse adjustment unit, which includes multiple fuses. The output current of the current mirror unit is adjusted by blowing at least one of the multiple fuses.

9. A driving circuit, characterized in that, include: At least one delay circuit as described in any one of claims 1 to 8.

10. The driving circuit according to claim 9, characterized in that, The number of delay circuits is set to multiple, and the multiple delay circuits are connected in series.

11. The driving circuit according to claim 10, characterized in that, The charging time of the multiple delay circuits is positively correlated with the number of delay circuits connected in series.

12. The driving circuit according to claim 10, characterized in that, The duration of discharge of the multiple delay circuits is positively correlated with the number of delay circuits connected in series.

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