Encoding method, decoding method, communication apparatus, and communication system

Abstract

The present application relates to the technical field of communications, and discloses an encoding method, a decoding method, a communication apparatus, and a communication system. On the basis of the encoding method, by exchanging positions of check bits in a second bit sequence, corresponding columns in a check matrix are exchanged accordingly, so that puncturing positions during rate matching can be changed, helping to improve decoding performance.

Description

An encoding method, a decoding method, a communication device, and a communication system.

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411982077.3, filed on December 27, 2024, entitled "An Encoding Method, Decoding Method, Communication Device and Communication System", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, a communication device, and a communication system. Background Technology

[0004] Low-density parity-check (LDPC) codes are a channel coding scheme very close to Shannon lines, characterized by high performance and low complexity. They have been selected by the 3rd Generation Partnership Project (3GPP) as the coding and decoding scheme for data channels in 5G communication. Mainstream LDPC codes have a quasi-cyclic (QC) structure, which avoids bad structures such as short cycles and improves code distance by setting the shift amount of each block.

[0005] How to continuously improve the decoding performance of LDPC codes remains to be solved. Summary of the Invention

[0006] This application provides an encoding method, a decoding method, a communication device, and a communication system to improve decoding performance.

[0007] In a first aspect, embodiments of this application provide an encoding method, which can be executed by a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: performing LDPC channel coding on an information bit sequence according to a base matrix to obtain a first bit sequence, wherein the parity bits in the first bit sequence correspond to multiple parity bit sets, and the multiple parity bit sets correspond one-to-one with multiple columns in the base matrix; performing intra-set interleaving on the parity bits in at least one of the multiple parity bit sets to obtain a second bit sequence; and performing rate matching on the second bit sequence to obtain a third bit sequence.

[0008] Based on the above scheme, since the positions of the parity bits in the second bit sequence are swapped, it is equivalent to swapping the corresponding columns of the parity check matrix. Therefore, the puncturing position during rate matching can be changed, which helps to improve decoding performance.

[0009] In one possible implementation, the method of performing intra-set interleaving of the parity bits in at least one of the plurality of parity bit sets to obtain a second bit sequence includes: performing intra-set interleaving of the parity bits in the at least one parity bit set, and performing inter-set global interleaving of at least two of the plurality of parity bit sets to obtain the second bit sequence.

[0010] Based on the above scheme, the range of interleaving can be expanded, and decoding performance can be further improved.

[0011] In one possible implementation, the process of interleaving the parity bits in at least one of the plurality of parity bit sets to obtain a second bit sequence includes: interleaving the parity bits in the at least one parity bit set according to an interleaving pattern to obtain the second bit sequence, wherein the interleaving pattern is used to indicate the interleaving method of the parity bits in the at least one parity bit set.

[0012] Based on the above scheme, bit interleaving based on the interleaving pattern can achieve accurate interleaving.

[0013] In one possible implementation, the at least one set of check bits includes a first set of check bits, and the second bit sequence includes a plurality of bits corresponding to the first set of check bits, wherein at least one bit in the first set of check bits is uniformly distributed among the plurality of bits.

[0014] Based on the above scheme, uniform bit interleaving can improve decoding performance.

[0015] In one possible implementation, the number of the at least one bit is half the size of the first set of parity bits.

[0016] In one possible implementation, the first set of parity bits corresponds to the last column of the core parity region in the base matrix. This core parity region can be region B of the base matrix, referring to the region corresponding to the core parity at high bit rates.

[0017] Based on the above scheme, comparing and interleaving the parity bit set corresponding to the last column of the core parity region in the base matrix can improve decoding performance.

[0018] In one possible implementation, the first set of parity bits corresponds to the first column of the zero matrix region in the base matrix. The core parity region can be region C of the base matrix, which is an all-zero matrix, and the number of rows in region C is the same as the number of rows in the core parity region.

[0019] Based on the above scheme, comparing and interleaving the parity bit set corresponding to the first column of the zero matrix region in the base matrix can improve decoding performance.

[0020] In one possible implementation, the indices of the bits in the first parity bit set are {x, x+1, ..., x+Z}. c -1}, where x represents the starting index of the bit in the first parity bit set, Z c This represents the size of the first set of parity bits, where σ0(i) represents {x, x+1, ..., x+Z}. c From {-1} to {x,x+1,…,x+Z} c A mapping from {x, x+1, ..., x+Z} to {x, x+1, ..., x+Z}. c -1}.

[0021] In one possible implementation, In {x, x+1, ..., x+Z c The number of any consecutive L numbers in the set {-1} is greater than 1 / 4L and less than 3 / 4L, where L is a multiple of 4.

[0022] Based on the above scheme, uniform bit interleaving can improve decoding performance.

[0023] In one possible implementation, L equals 8, 16, or 32.

[0024] In one possible implementation, It does not contain t+1 consecutive natural numbers, where t is an integer greater than or equal to 1.

[0025] Based on the above scheme, uniform bit interleaving can improve decoding performance.

[0026] In one possible implementation, t equals 16, 8, or 4.

[0027] In one possible implementation, or

[0028] Based on the above scheme, bit interleaving can improve decoding performance. For example, it can improve decoding performance with a low number of iteration rounds.

[0029] In one possible implementation, for σ0(i)=2i-x; for

[0030] Based on the above scheme, uniform bit interleaving can improve decoding performance. For example, it can improve decoding performance with a low number of iteration rounds.

[0031] In one possible implementation, for σ0(i)=2i+1-x; for

[0032] Based on the above scheme, uniform bit interleaving can improve decoding performance. For example, it can improve decoding performance with a low number of iteration rounds.

[0033] In one possible implementation, the parity bits within at least one of the plurality of parity bit sets are interleaved within the set to obtain a second bit sequence, including: when the code rate is greater than the first code rate, performing intra-set interleaving on the parity bits within the at least one parity bit set to obtain the second bit sequence.

[0034] Based on the above solution, decoding performance in high-bitrate scenarios can be improved.

[0035] In one possible implementation, the first code rate is the code rate corresponding to the core region of the basis matrix.

[0036] In one possible implementation, the first bit rate is equal to 22 / 24 or 22 / 25.

[0037] Secondly, embodiments of this application provide a decoding method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, network device, etc.), a component within that communication device (e.g., a processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: receiving information to be decoded; performing rate matching on the information to be decoded to obtain a second bit sequence; wherein the second bit sequence is obtained by interleaving the parity bits in at least one of a plurality of parity bit sets, the plurality of parity bit sets corresponding to the parity bits in a first bit sequence, the first bit sequence being obtained by performing LDPC channel coding on an information bit sequence based on a base matrix, the plurality of parity bit sets corresponding one-to-one with a plurality of columns in the base matrix; and performing LDPC channel decoding on the second bit sequence to obtain the information bit sequence.

[0038] In one possible implementation, the second bit sequence is obtained by interleaving the parity bits within at least one parity bit set from a plurality of parity bit sets, and by performing overall interleaving between at least two parity bit sets from the plurality of parity bit sets.

[0039] In one possible implementation, the second bit sequence is obtained by interleaving the parity bits in at least one of a plurality of parity bit sets according to an interleaving pattern, wherein the interleaving pattern is used to indicate the interleaving method of the parity bits in the at least one parity bit set.

[0040] In one possible implementation, the at least one set of check bits includes a first set of check bits, and the second bit sequence includes a plurality of bits corresponding to the first set of check bits, wherein at least one bit in the first set of check bits is uniformly distributed among the plurality of bits.

[0041] In one possible implementation, the number of the at least one bit is half the size of the first set of parity bits.

[0042] In one possible implementation, the first set of parity bits corresponds to the last column of the core parity region in the base matrix.

[0043] In one possible implementation, the first set of parity bits corresponds to the first column of the zero matrix region in the basis matrix.

[0044] In one possible implementation, the indices of the bits in the first parity bit set are {x, x+1, ..., x+Z}. c-1}, where x represents the starting index of the bit in the first parity bit set, Z c This represents the size of the first set of parity bits, where σ0(i) represents {x, x+1, ..., x+Z}. c From {-1} to {x,x+1,…,x+Z} c A mapping from {x, x+1, ..., x+Z} to {x, x+1, ..., x+Z}. c -1}.

[0045] In one possible implementation, In {x, x+1, ..., x+Z c The number of any consecutive L numbers in the set {-1} is greater than 1 / 4L and less than 3 / 4L, where L is a multiple of 4.

[0046] In one possible implementation, L equals 8, 16, or 32.

[0047] In one possible implementation, It does not contain t+1 consecutive natural numbers, where t is an integer greater than or equal to 1.

[0048] In one possible implementation, t equals 16, 8, or 4.

[0049] In one possible implementation, or

[0050] In one possible implementation, for σ0(i)=2i-x; for

[0051] In one possible implementation, for σ0(i)=2i+1-x; for

[0052] In one possible implementation, the second bit sequence is obtained by interleaving the parity bits in at least one of a plurality of parity bit sets with a code rate greater than the first code rate.

[0053] In one possible implementation, the first code rate is the code rate corresponding to the core region of the basis matrix.

[0054] In one possible implementation, the first bit rate is equal to 22 / 24 or 22 / 25.

[0055] For the beneficial effects of the second aspect or any implementation of the second aspect, refer to the beneficial effects of the first aspect or the corresponding implementation of the first aspect described above.

[0056] Thirdly, this application provides a communication device that performs the functions described in the first aspect. For example, the communication device includes modules, units, or means corresponding to the operations described in the first aspect. These functions, units, or means can be implemented by software, hardware, or by hardware executing corresponding software.

[0057] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit can correspond to the operations involved in the first aspect described above.

[0058] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store computer programs or instructions necessary to implement the functions described in the first aspect above. The processor may execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the first aspect above, when executed.

[0059] In one possible design, the communication device includes a processor and a memory, the memory of which can store the necessary computer programs or instructions for implementing the functions described in the first aspect above. The processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the first aspect above.

[0060] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the methods in any possible design or implementation of the first aspect described above.

[0061] Understandably, the processor in the fifth aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor or separated from it. In specific implementations, the memory can be integrated with the processor on the same chip or disposed on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0062] Fourthly, this application provides a communication device that performs the functions described in the second aspect above. For example, the communication device includes modules, units, or means for performing the operations described in the second aspect above. These functions, units, or means can be implemented by software, hardware, or hardware executing corresponding software.

[0063] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit can correspond to the operations involved in the second aspect above.

[0064] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store computer programs or instructions necessary to implement the functions described in the second aspect above. The processor may execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the second aspect above, when the computer programs or instructions are executed.

[0065] In one possible design, the communication device includes a processor and a memory, the memory of which can store the necessary computer programs or instructions for implementing the functions described in the second aspect above. The processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the second aspect above.

[0066] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the methods in any possible design or implementation of the second aspect described above.

[0067] Understandably, the processor in the sixth aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor, or the memory and processor can be separate. In specific implementations, the memory can be integrated with the processor on the same chip, or they can be set on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0068] Fifthly, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to execute the method described in the first aspect and any implementation of the first aspect, and the second communication device is used to execute the method described in the second aspect and any implementation of the second aspect.

[0069] In a sixth aspect, this application provides a computer-readable storage medium storing a computer program (or computer-readable instructions) in which, when a computer reads and executes some or all of the computer-readable instructions, the method in any of the possible designs in the first to second aspects described above is executed.

[0070] For example, a computer-readable storage medium can be any available medium that a computer can access. This includes, but is not limited to, non-transient computer-readable media, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer.

[0071] In a seventh aspect, this application provides a computer program product that, when read and executed by a computer, causes any of the possible designs in the first to second aspects described above to be performed.

[0072] Eighthly, this application provides a chip (or chip system) including a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory, such that any of the possible designs in the first to second aspects described above are executed. Attached Figure Description

[0073] Figure 1 is a schematic diagram of the architecture of the communication system applicable to the embodiments of this application;

[0074] Figure 2 is a schematic diagram of a processing flow for information sources and receivers;

[0075] Figure 3 is a schematic diagram of a 4*4 cyclic shift matrix;

[0076] Figure 4 shows an example diagram of the basis matrix in an LDPC code;

[0077] Figure 5 shows an example diagram of the check matrix;

[0078] Figure 6 shows the region division method of the basis matrix;

[0079] Figure 7 is a schematic diagram of the matrix regions corresponding to different code rates;

[0080] Figure 8 is a schematic diagram of the high bit rate region of BG1;

[0081] Figure 9 is a schematic diagram of the high bit rate region of BG1;

[0082] Figure 10 is a flowchart illustrating the encoding method provided in an embodiment of this application;

[0083] Figure 11 is a schematic diagram of the verification matrix H and the vector d;

[0084] Figure 12 is an example diagram of rate matching provided in this application;

[0085] Figure 13 is a flowchart illustrating the decoding method provided in an embodiment of this application;

[0086] Figure 14 is a schematic diagram of the simulation results under a specific example provided in this application;

[0087] Figure 15 is an exemplary block diagram of a communication device provided in an embodiment of this application;

[0088] Figure 16 is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0089] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0090] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, wireless fidelity, Wi-Fi, Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, 5th generation (5G) mobile communication systems (such as New Radio (NR) systems), Future Communication Systems, or other similar communication systems, without limitation. This application describes the communication system shown in Figure 1 as an example. When applying the technical solution of this application to other communication systems, the devices, components, modules, etc. in the embodiment can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0091] Figure 1 is a schematic diagram of the architecture of the communication system applied in the embodiments of this application. As shown in Figure 1, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as 110a and 110b in Figure 1, and may also include at least one terminal device, such as 120a-120j in Figure 1. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop computer, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example, the mobile phones in Figure 1 are 120a, 120e, 120f and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can access micro-station 110b, connect to laptop 120g and printer 120h. Mobile phone 120j can control drone 120i.

[0092] (1) Network equipment

[0093] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device within a radio access network (RAN) that provides wireless communication functionality to terminal devices; this is called a RAN device. The RAN can be an access network in 3GPP, such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0094] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0095] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and packet data convergence protocol (PDCP) of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) layer and medium access control (MAC) layer of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the CU (or CU-CP, CU-UP), DU, and RU units in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RAN equipment can be a macro base station (as shown in Figure 1, 110a), a micro base station or an indoor station (as shown in Figure 1, 110b), or a relay node or donor node, etc. The embodiments of this application do not limit the specific technology or equipment form used in the network equipment.

[0096] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0097] (2) Terminal equipment

[0098] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. They can be widely used in various scenarios, such as D2D communication, V2X communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicle devices (such as vehicle units, in-vehicle modules, in-vehicle chips, on-board units (OBUs) or telematics boxes (T-BOXs), etc.), drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, satellite terminals, Internet of Things (IoT) terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability UE (REDCAP UE), etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or a device capable of supporting the terminal device in implementing that function, such as a chip system or a combination of devices or components capable of implementing the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0099] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device containing the functions of the terminal device.

[0100] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0101] The roles of network devices and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device. That is, 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol. In this case, relative to 110a, 120i is also a network device. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. 110a and 110b in Figure 1 can be called communication devices with network device functions, and 120a-120j in Figure 1 can be called communication devices with terminal device functions.

[0102] Network devices and terminal devices, network devices and network devices, and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0103] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0104] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0105] (1) Channel coding and channel decoding

[0106] Figure 2 illustrates a processing flow diagram for the source and sink. As shown in Figure 2, the transmitting end (i.e., the source) obtains the bit sequence to be encoded (i.e., the information bit sequence) through source encoding, and then performs channel encoding on the bit sequence to be encoded to obtain the encoded bit sequence. Correspondingly, after the receiving end (i.e., the sink) obtains the symbol sequence to be decoded, it performs channel decoding on the symbol sequence to be decoded to obtain the information bit sequence, and then performs source recovery on the information bit sequence to obtain useful information.

[0107] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0108] There are various channel coding methods, such as polar coding or LDPC coding. Polar codes were selected as the control channel coding method in the 5G standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, and have the advantages of good decoding performance and low complexity. LDPC codes were selected as the data channel coding method in the 5G standard. LDPC codes are linear block codes with a sparse parity-check matrix, which not only have good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure.

[0109] (2) Modulation and demodulation

[0110] Referring to Figure 2, the transmitting end can also map the encoded bit sequence to the modulation symbol sequence, and then transmit the modulation symbol sequence; correspondingly, the receiving end can receive the modulation symbol sequence and obtain the symbol sequence to be decoded by demodulation.

[0111] Modulation refers to the process by which the transmitting end maps the encoded bit sequence to a constellation based on a constellation diagram to obtain a modulated symbol sequence. Demodulation is the reverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0112] (3) Information bit sequence

[0113] An information bit sequence refers to a sequence of multiple information bits to be transmitted. For example, if the bits to be transmitted are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the resulting information bit sequence is: 10101100101. In this embodiment, K represents the length of the information bit sequence.

[0114] (4) Code length

[0115] Code length refers to the length of the encoded bit sequence to be transmitted, obtained by encoding the information bit sequence. The code length is greater than or equal to the length of the information bit sequence. In this embodiment, E represents the code length.

[0116] (5) Bitrate

[0117] The code rate is the ratio of the length of the information bit sequence to the code length. In this embodiment, R represents the code rate, and R = K / E.

[0118] The length, code length, and code rate of the information bit sequence can be pre-configured by higher-layer signaling, medium access control (MAC) layer signaling, or downlink physical layer signals, and can also be obtained or calculated by the transmitting and receiving devices. For example, the transmitting and receiving devices can determine the code length based on the coding scheme, the frame structure used to transmit the information bits, the number of layers, and the modulation scheme. For example, the transmitting and receiving devices can obtain the code rate based on higher-layer signaling, MAC layer signaling, or downlink physical layer signals, or determine the code rate based on the modulation and coding scheme (MCS).

[0119] (6) LDPC code

[0120] LDPC codes are a channel coding scheme very close to Shannon lines, characterized by high performance and low complexity. They have been adopted by 3GPP as the coding and decoding scheme for 5G communication data channels. Mainstream LDPC codes employ a QC structure, which avoids bad structures such as short loops and improves code distance by setting the shift amount for each block.

[0121] LDPC codes can be represented using a basis matrix, where elements are either 0 or 1. Expanding the basis matrix by adding 1 elements results in a Zc*Zc cyclic shift matrix, and expanding by adding 0 elements results in a Zc*Zc zero matrix. This expansion yields a parity-check matrix (denoted by H), which can be used for encoding or decoding. Zc can be referred to as the lifting value, spread factor, spread coefficient, lifting size, etc. BG BG is an abbreviation for base graph. A basis matrix can also be represented by a base graph, and the two have a corresponding relationship.

[0122] For example, if the element in the i-th row and j-th column of the basis matrix has a value of 1 and corresponds to a shifting value (SV), it can be represented by P. i,jThis represents the shift value corresponding to the i-th row and j-th column. A shift value can be used to calculate the corresponding number of cyclic shifts.

[0123] Taking Zc=4 as an example, the matrix obtained by cyclically shifting the 4*4 identity matrix to the right by 1, 2, 3, and 0 times respectively is shown in Figure 3. That is, the number of cyclic shifts are 1, 2, 3, and 0 respectively.

[0124] The following example illustrates this. Figure 4 shows an example of the basis matrix in an LDPC code. This basis matrix is ​​a 3x3 matrix, and we assume Zc = 4, and P 0,0 The corresponding right circular shift count is 1, P 0,1 The corresponding right circular shift count is 2, P 1,0 The corresponding number of right circular shifts is 3, P 1,2 The corresponding number of right circular shifts is 3, P 2,2 The corresponding right circular shift count is 1. After expanding the base matrix, we can obtain the parity check matrix as shown in Figure 5.

[0125] Currently, the 3GPP TS 38.212 protocol defines various values ​​for the lift size (Zc) as shown in Table 1.

[0126] Table 1

[0127] Referring to Table 1, the values ​​of the lifting dimension Zc can be... Where j represents the j-th row in Table 1, j = 0, 1, 2, 3, 4, 5, 6, 7, a0, a1, a2, a3, a 4, a 5, a6 and a7 are 2, 3, 5, 7, 9, 11, 13, and 15 respectively. k j The value of traverses from 0 to max(k) j ), where max(k0), max(k1), max(k2), max(k3), max(k4), max(k5), max(k6), and max(k7) are 7, 7, 6, 5, 5, 5, 4, and 4, respectively.

[0128] For example, if j = 0, then a0 = 2, and k0 iterates through 0 to 7, so the value of Zc can be 2*2. 0 ,2*2 1 ,2*2 2 ,2*2 3 ,2*2 4 ,2*2 5 ,2*2 6 ,2*2 7That is, 2, 4, 8, 16, 32, 64, 128, 256. The cases where j takes values ​​from 1 to 7 are similar and will not be elaborated further.

[0129] The protocol also stipulates that each row of Zc in Table 1 corresponds to a set of SV. When constructing the parity check matrix, the size of Zc is first determined, then the set of SV corresponding to that Zc is determined, and then the parity check matrix is ​​constructed based on Zc and SV.

[0130] Table 2 below shows a partial example of a set of SVs defined in the 3GPP TS 38.212 protocol.

[0131] Table 2

[0132] Table 2 shows the basis matrix H. BG The translation values ​​SV corresponding to the elements with a value of 1 in row 0 i,j The set index i in Table 2 LS That is, the set index i in Table 1 LS Furthermore, the basis matrix H BG The cyclic shift value corresponding to each element with a value of 1 in row 0 can be obtained by taking the modulo of Zc using the corresponding translation value.

[0133] It should be noted that Table 2 only shows the translation values ​​corresponding to each element in row 0. In practice, it also includes the translation values ​​corresponding to each element in other rows (such as row 1, row 2, etc.).

[0134] Referring to Table 2, when Zc takes the values ​​2, 4, 8, 16, 32, 64, 128, or 256, then i LS =0, basis matrix H BG The SV values ​​of the elements with a value of 1 in row 0 are 250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0. Assuming Zc = 4, then the basis matrix H... BGThe cyclic shift counts corresponding to the elements with a value of 1 in row 0 are 250 mod 4, 69 mod 4, 226 mod 4, 159 mod 4, 100 mod 4, 10 mod 4, 59 mod 4, 229 mod 4, 110 mod 4, 191 mod 4, 9 mod 4, 195 mod 4, 23 mod 4, 190 mod 4, 35 mod 4, 239 mod 4, 31 mod 4, 1 mod 4, 0 mod 4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. This means that the 4x4 identity matrix is ​​cyclically shifted 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0 times to obtain the basis matrix H. BG The elements in row 0 that have a value of 1 correspond to a 4x4 matrix. For the basis matrix H... BG The elements in the 0th row that have a value of 0 correspond to a zero matrix of size 4*4.

[0135] Similarly, for other values ​​of Zc, there are corresponding translation values ​​and cyclic shift counts, as detailed in Table 2.

[0136] Similarly, for the basis matrix H BG The rows other than row 0 are also determined using a similar method to determine the corresponding Zc*Zc matrix.

[0137] In this embodiment, the lifting and translation operations of the LDPC code are described as follows: For a given lifting size Zc, from the basis matrix H BG Upgraded to the parity check matrix H, specifically, the basis matrix H BG t in i,j (where t) i,j =1) will be replaced with a Zc×Zc matrix I(P) i,j ), where I(P i,j ) is a cyclic shift of the identity matrix I of Zc×Zc by P i,j One (either left or right circular shift is possible) or circular shift P i,j A matrix of degree mod Zc, P i,j The translation value corresponding to the i-th row and j-th column; basis matrix H BG The zeros in H will be replaced with a Zc×Zc matrix of all zeros. It can be seen that the purpose of lifting is to improve the basis matrix H. BG To transform it into a larger parity check matrix H, the translation aims to shift each H... BG The identity matrix corresponding to the non-zero elements is cyclically shifted into a predefined matrix.

[0138] (7) The basis matrix of LDPC code

[0139] The basis matrices of LDPC codes include BG1 and BG2. BG1 is a 46x68 matrix, and BG2 is a 42x52 matrix. Both BG1 and BG2 have the matrix structure shown in Figure 6. Region A corresponds to the information columns (or information bits, system bits) at high code rates; region B corresponds to the core parity check region at high code rates (also called the core parity check region, core parity check bit region, or core parity check area); region C is an all-zero matrix region; region D is the incremental redundancy part of the basis matrix corresponding to low code rates; and region E is the identity matrix. The values ​​of the basis matrices are either 0 or 1. A value of 0 represents an empty element, and a value of 1 represents an edge in the basis graph, or the association between the parity check and the variable.

[0140] As can be seen, the columns of the LDPC basis matrix consist of information columns and parity columns. The information columns correspond to the information bits and are the columns corresponding to region A. The parity columns correspond to the parity bits and are the columns corresponding to regions B and C, with the columns corresponding to region B being the core parity columns and the columns corresponding to region C being the extended parity columns. Alternatively, the core parity columns are the parity columns in region B with a column weight greater than 1, and the extended parity columns are the remaining parity columns excluding the core parity columns.

[0141] The core rows of the LDPC basis matrix correspond to the core check columns. In other words, the core rows are the rows corresponding to high bitrate regions, or regions A, B, or C.

[0142] The core columns of the LDPC basis matrix can include all information columns and all core check columns. In other words, the core columns are the columns corresponding to high bitrate regions, or the columns corresponding to regions A and B.

[0143] The kernel matrix of the LDPC base matrix is ​​a matrix region consisting of all the kernel rows and all the kernel columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high-bitrate region of the LDPC base matrix, or a matrix composed of regions A and B.

[0144] To improve the bit rate, LDPC encoding supports puncturing. For example, referring to Figure 6, the first two columns of the matrices BG1 and BG2 are punctured columns. In terms of matrix characteristics, the column weight of the punctured column is relatively large, where column weight refers to the number of non-zero elements in a column. In terms of transmission characteristics, the bits corresponding to the punctured column are not transmitted, and the receiver does not need to pay attention to the received information of this part. Its log-likelihood ratio is set to 0, and it is recovered through decoding.

[0145] It should be noted that BG1 and BG2 are designed for the lowest bitrate. When different bitrates need to be supported, the upper left portion of BG1 or BG2 can be used. Figure 7 is a schematic diagram of the matrix regions corresponding to different bitrates. This matrix can be BG1, BG2, or other types of base matrices. This matrix includes a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region corresponds to regions A and B in Figure 6, and the high-rate region also becomes the core region. The all-zero region corresponds to region C in Figure 6, the incremental redundancy region corresponds to region D in Figure 6, and the raptor-like region corresponds to region E in Figure 6, corresponding to the parity bits of the low-rate extension. In this context, regions B and E are both verification regions. Region B is defined as the core verification region, and its features can be the non-lower triangular coding part (i.e., the values ​​above the diagonal are not all 0) or the coding part with a column weight greater than 1. Region E is defined as the extended verification region, and its features can be the lower triangular coding part (i.e., the values ​​above the diagonal are all 0) or a diagonal matrix.

[0146] When a base matrix is ​​constructed from the rows and columns of the high-bitrate region as shown in the figure, the base matrix has the highest bitrate; therefore, it is also called the highest bitrate matrix. If more rows and columns are selected from BG1 or BG2 than from the high-bitrate region to construct the base matrix, the bitrate of the base matrix will be lower than the highest bitrate. Furthermore, as the number of rows and columns increases, the bitrate of the corresponding matrix region gradually decreases. Referring to Figure 7, the rows and columns of each dashed box region constitute a base matrix; as the size of the dashed box region increases, the bitrate of the corresponding base matrix gradually decreases.

[0147] Figure 8 is a schematic diagram of the high bitrate region of BG1. The high bitrate region of BG1 is a matrix region composed of region A and region B of BG1. Region A of BG1 is a 4x22 matrix used to carry data information (or information bits), and region B of BG1 is a 4x4 matrix used to carry parity information (or parity bits). When the first two columns are perforated, the bitrate supported by the high bitrate region is 22 / (22+4-2) = 22 / 24 ≈ 0.917. To further improve the bitrate, columns in region A can be perforated simultaneously with columns in region B. For example, in the example in Figure 9, the first two columns of region A and the last column of region B are perforated, meaning the number of perforated columns is 3. The bitrate supported by the high bitrate region is then 22 / (22+4-3) = 22 / 23 ≈ 0.956.

[0148] (8) LDPC code encoding

[0149] Let the sequence of bits to be encoded be denoted as vector c, and c = [c0, c1, c2, ..., c K-1 ] T Where K is the number of information bits to be encoded. The bit sequence after LDPC encoding is denoted as vector d, and d = [d0, d1, d2, ..., dn]. N-1 ] T For LDPC base map 1 (BG1 for short), N = 66Z c For LDPC base map 2 (BG2 for short), N = 50Z c Z c This indicates the increase value.

[0150] In this context, base graph 1 is also called base matrix 1, and base graph 2 is also called base matrix 2.

[0151] The process of encoding vector c using LDPC code to obtain vector d is as follows:

[0152] Step 1: Select Z c .

[0153] Step 2: Based on the first 2Z of vector c c Other than the bit values, determine the first K-2Z of vector d. c Each bit value.

[0154] The process can be referenced as follows:

[0155] Here, NULL represents empty, that is, there is no corresponding content or information.

[0156] Step 3: Generate vectors And it satisfies:

[0157] The 0 on the right side of the above formula (1) represents a column vector with all elements being 0.

[0158] The parity-check matrix H is obtained by using the basis matrix H BG Replace each element in with Z c ×Z c The matrix obtained is as follows:

[0159] a) Basis matrix H BG Each element with a value of 0 is replaced with an element of size Z. c ×Z c A zero matrix;

[0160] b) Basis matrix H BG Each element with a value of 1 in the array is replaced with an element of size Z. c ×Z cThe identity matrix, or replaced with a matrix of size Z. c ×Z c The cyclic shift matrix is ​​obtained from the identity matrix.

[0161] Where, when matrix H BG If it is BG1, then H BG It is a matrix with 46 rows and 68 columns. When matrix H... BG If it is BG2, then H BG It is a matrix with 42 rows and 52 columns.

[0162] Step 4: Based on vector w, obtain the other N+2Z of vector d. c -K bits.

[0163] The process is as follows:

[0164] From the above four steps of LDPC encoding, it can be seen that:

[0165] First, the above formula (1) implies a one-to-one correspondence between an information bit and a column in the parity check matrix H, that is, c0 corresponds to the first column of H, c1 corresponds to the second column of H, and so on.

[0166] Second, the encoded bit sequence (i.e., vector d) does not contain the first 2^Z of the information bit sequence to be encoded (i.e., vector c). c The first 2Z bits, that is, the first 2Z bits of the information bit sequence to be encoded. c Each bit is punched. For example, the first 2Z bits of the information bit sequence to be encoded are... c Each bit corresponds to a column with a larger column weight in the parity check matrix.

[0167] (9) LDPC rate matching

[0168] Rate matching refers to the process of removing some bits from the encoded bit sequence or repeating the transmission of some bits to meet the actual transmission rate. The methods of rate matching are further explained below in three categories.

[0169] Punching: Punching refers to directly creating holes in certain bit positions within the encoded bit sequence without transmitting them, thus generating bit sequences of arbitrary length. On the decoding side, since there is no information at the corresponding "punched" positions, the decoder can set the LLR of the corresponding bit to 0.

[0170] Shortening: This makes certain bit positions in the encoded bit sequence fixed values ​​and do not need to be transmitted. On the decoding side, since the corresponding "shortened" positions are equivalent to being known at the receiving end (usually 0), the decoding end can set the LLR of the corresponding bit to infinity.

[0171] Repetition: "Repetition" refers to obtaining a longer bit sequence by repeatedly sending a portion of the encoded bit sequence.

[0172] The LDPC rate matching process is as follows:

[0173] The encoded bit sequence (i.e., vector d) is placed in a circular buffer, and a bit sequence of the corresponding length is read from it as the bit sequence after rate matching. This will be explained in detail below.

[0174] The encoded bit sequence d0, d1, d2, ..., d N-1 Write to a circular buffer, the length of which is denoted as N. cb .

[0175] The redundancy version (RV) currently being transmitted is denoted as rv. id Optional, where rv id = 0, 1, 2 or 3.

[0176] The bit sequence after rate matching of the ring buffer output is denoted as e = e0, e1, e2, ..., e E-1 .

[0177] For example, the process of generating this sequence is as follows:

[0178] Where k0 represents the bit sequence e0, e1, e2, ..., e after rate matching from the ring buffer. E-1 The starting bit position, that is, starting from the bit indicated by k0, is used to read e0, e1, e2, ..., e E-1 The value of k0 is related to rv. id And related to the LDPC basis matrix. Table 3 below shows the relationship between the values ​​of k0 and rv. id And an example of the relationship between the LDPC basis matrices.

[0179] Table 3: Values ​​of k0 and rv id and the relationship between the LDPC basis matrix

[0180] (10) Translation value matrix

[0181] A translation value matrix is ​​a matrix obtained by replacing each non-zero element in the base matrix with its corresponding translation value. It can be seen that the size of the translation value matrix is ​​the same as the size of the base matrix, and the elements in the translation value matrix are either zero or translation values.

[0182] Currently, to adapt to the business needs of certain scenarios, the industry has proposed expanding the improvement value based on the existing standard definition, for example, by doubling or tripling the improvement value, without changing the shift matrix. These scenarios include, for example, enhanced mobile broadband (eMBB), high-throughput scenarios, peak rate scenarios, ultra-reliable and low-latency communication (URLLC) scenarios, and massive machine-type communication (mMTC) scenarios.

[0183] However, changing the boost value without altering the translation matrix can lead to poor decoding performance. For example, under high code rate matching and low iteration counts, decoding performance is significantly worse. Therefore, how to improve decoding performance when changing the boost value without changing the translation matrix remains to be addressed. Furthermore, how to improve decoding performance without changing the boost value also needs to be addressed.

[0184] To address the aforementioned issues, this application provides corresponding solutions.

[0185] The methods provided in the embodiments of this application are described in detail below. The methods provided in the embodiments of this application involve a first communication device and / or a second communication device. The first communication device is a signal transmitter, and the second communication device is a signal receiver. Unless otherwise specified, the term "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. Similarly, the term "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, a decoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. For example, the first communication device may be a network device, and the second communication device may be a terminal device; or, the first communication device may be a terminal device, and the second communication device may be a network device.

[0186] Figure 10 is a flowchart illustrating an encoding method provided in an embodiment of this application. The method includes the following steps:

[0187] Step 1001: The first communication device performs LDPC channel coding on the information bit sequence according to the base matrix to obtain the first bit sequence.

[0188] The basis matrix is ​​also called the basis graph (BG). For example, for LDPC codes, the basis matrix includes BG1 and BG2. For an introduction to BG1 and BG2, please refer to the above description.

[0189] An information bit sequence refers to a sequence of information bits to be transmitted.

[0190] As described above, the information bit sequence can be represented by vector c, and the first bit sequence can be represented by vector d, where vector d is determined based on vector c and vector w. Where c = [c0, c1, c2, ..., cw] K-1 ] T d = [d0, d1, d2, ..., d N-1 ] T , Specifically, based on the first 2Z of vector c c Other than the bit values, determine the first K-2Z of vector d. c Each bit value, and the other N+2Z bits of vector d derived from vector w. c -K bit values, and satisfying the above formula (1), that is Where H is the check matrix after the boosting value.

[0191] The first bit sequence (i.e., vector d) includes information bits and check bits, and optionally, padding bits.

[0192] The parity bits in the first bit sequence are vector w. These parity bits correspond to multiple parity bit sets, meaning they can be divided into multiple parity bit sets. Each parity bit set contains Zc parity bits, where Zc is the boost value. These multiple parity bit sets correspond one-to-one with multiple columns in the basis matrix.

[0193] Figure 11 is a schematic diagram of the verification matrix H and the vector d. The vector d includes N+2Z. c -K parity bits, and N+2Z c -K is an integer multiple of Zc. The N+2Z c -K parity bits are divided into (N+2Z) cThere are -K) / Zc parity bit sets, each containing Zc parity bits, and each parity bit set corresponds to an element in the Zc column of the parity check matrix. For example, the first parity bit set includes... The second set of parity bits includes

[0194] Step 1002: The first communication device performs intra-set interleaving of the parity bits in at least one of the multiple parity bit sets to obtain a second bit sequence.

[0195] Taking the last set of parity bits as an example, this set of parity bits includes The elements within the parity bit set are interleaved, which means the positions of the elements within the set are swapped.

[0196] Step 1003: The first communication device performs rate matching on the second bit sequence to obtain the third bit sequence.

[0197] The second bit sequence is the encoded bit sequence, and the number of bits in the second bit sequence is N. The number of bits in the third bit sequence after rate matching is E.

[0198] The first communication device can then modulate the third bit sequence to obtain modulation symbols, and map the modulation symbols onto resources for transmission.

[0199] Based on the above scheme, since the positions of the parity bits in the second bit sequence are swapped, it is equivalent to swapping the corresponding columns of the parity-check matrix. Therefore, the puncturing position during rate matching can be changed, which helps to improve decoding performance by changing the boost value without changing the shift matrix. Furthermore, this scheme can also improve decoding performance without changing the boost value.

[0200] Figure 12 is an example diagram of rate matching provided in this application. In this example, each element in the base matrix is ​​promoted to an 8*8 cyclic shift value, i.e., Zc = 8. If 2.5 columns of the base matrix are punctured according to the prior art, specifically the first 2 columns and the last half column of the base matrix, it is equivalent to puncturing the first 16 columns (i.e., 2*8) and the last 4 columns (i.e., 0.5*8) of the parity check matrix. Assuming that according to the scheme of this application, the 8 bits in the last parity bit set in the second bit sequence are interleaved, it is equivalent to performing column swapping on the last 8 columns of the parity check matrix. Assuming that the elements of columns 1, 3, 5, and 7 in the last 8 columns of the parity check matrix are swapped to the positions of columns 5, 6, 7, and 8 in the last 8 columns, then puncturing columns 5, 6, 7, and 8 in the last 8 columns is equivalent to puncturing columns 1, 3, 5, and 7 in the last 8 columns, thus changing the continuous puncturing of the last 8 columns to intermittent puncturing. By changing the puncturing position during rate matching, decoding performance can be improved.

[0201] The specific implementation method of step 1002 above is explained below.

[0202] As one implementation method, step 1002 above can specifically be: the first communication device performs intra-set interleaving on the parity bits within at least one parity bit set from a plurality of parity bit sets, and performs inter-set overall interleaving on at least two parity bit sets from a plurality of parity bit sets to obtain a second bit sequence. That is, the first communication device not only performs intra-set interleaving on the parity bits within one or more parity bit sets, but also performs inter-set overall interleaving on two or more parity bit sets from a plurality of parity bit sets to obtain a second bit sequence. Here, inter-set overall interleaving refers to the overall exchange of positions between sets, so elements in one parity bit set will not be exchanged into another parity bit set.

[0203] As one implementation method, step 1002 above can specifically be as follows: The first communication device performs intra-set interleaving of the parity bits in at least one parity bit set among multiple parity bit sets according to the interleaving pattern to obtain a second bit sequence. The interleaving pattern indicates the interleaving method of the parity bits in at least one parity bit set among multiple parity bit sets. For example, when Zc = 8, each parity bit set includes 8 elements. Assuming the interleaving pattern is {2 4 6 8 1 3 5 7}, after interleaving, the 2nd, 4th, 6th, and 8th elements in the parity bit set are interleaved to the front in sequence, and the 1st, 3rd, 5th, and 7th elements in the parity bit set are interleaved to the back in sequence.

[0204] As one implementation method, assuming the parity bit set undergoing intra-set bit interleaving includes a first parity bit set, the aforementioned second bit sequence includes multiple bits corresponding to the first parity bit set, which are the interleaved bits within the first parity bit set. After intra-set bit interleaving, at least one bit in the first parity bit set is evenly distributed among these multiple bits. Based on this scheme, the puncture positions for rate matching can be evenly distributed, which helps improve decoding performance. For example, half of the bits in the first parity bit set are evenly distributed among these multiple bits. For example, the first parity bit set corresponds to the last column of the core parity region in the base matrix, or the first column of the zero matrix region in the base matrix. The core parity region can be region B in Figure 6, and the zero matrix region can be region C in Figure 6.

[0205] As one implementation method, the parity bit set for bit interleaving within the set can include two or more sets, such as parity bit set #1 and parity bit set #2. Parity bit set #1 corresponds to the last column of the core parity region in the base matrix, and parity bit set #2 corresponds to the first column of the zero matrix region in the base matrix.

[0206] As one implementation method, step 1002 above can specifically be: when the code rate is greater than the first code rate, the first communication device performs intra-set interleaving on the parity bits in at least one parity bit set among the multiple parity bit sets to obtain a second bit sequence; or when the code rate is greater than the first code rate, the first communication device performs intra-set interleaving on the parity bits in at least one parity bit set among the multiple parity bit sets according to the interleaving pattern to obtain a second bit sequence; or when the code rate is greater than the first code rate, the first communication device performs intra-set interleaving on the parity bits in at least one parity bit set among the multiple parity bit sets, and performs inter-set overall interleaving on at least two parity bit sets among the multiple parity bit sets to obtain a second bit sequence. For example, the first code rate is the code rate corresponding to the core region of the base matrix. The core region can be, for example, the region composed of region A and region B in Figure 6. As a specific example, the first code rate is equal to 22 / 24, or 22 / 25, or it can be any other code rate.

[0207] This application does not limit the number of parity bit sets that need to be interleaved within the above-mentioned multiple parity bit sets. For example, interleaving can be performed only on bits within a single parity bit set, or interleaving can be performed on bits within multiple parity bit sets.

[0208] This application does not limit the number of parity bit sets that need to be interleaved among the above-mentioned multiple parity bit sets. For example, it is not necessary to perform interleaving between any two parity bit sets, or it is necessary to perform interleaving between only two of the parity bit sets, or it is necessary to perform interleaving between more than two parity bit sets.

[0209] The following are some specific implementation methods for interleaving the parity bit set within the set.

[0210] As one implementation method, the aforementioned method obtains the other N+2Z of vector d based on vector w. c The process of -K bits can be replaced by:

[0211] Where σ is a permutation of the subscript W, i.e., {0,1,…,N+2Z} c From {-K-1} to {0,1,…,N+2Z} c -K-1} mapping.

[0212] As one implementation method, for a specific parity bit set among the aforementioned multiple parity bit sets, if this parity bit set needs to undergo intra-set interleaving, the function σ0 can be used to represent the intra-set interleaving method. For example, suppose the first parity bit set among the aforementioned multiple parity bit sets needs to undergo intra-set interleaving, and the bit indices in this first parity bit set are {x, x+1, ..., x+Z}. c -1}, where x represents the starting index of the bit in the first parity bit set, Z c Let σ0(i) represent the size of the first set of parity bits, where σ0(i) represents {x, x+1, ..., x+Z}. c From {-1} to {x,x+1,…,x+Z} c A mapping from {x, x+1, ..., x+Z} to {x, x+1, ..., x+Z}. c -1}. For example, for the above multiple parity bit sets, the index of the bit in the first parity bit set is {0,1,…,Z}. c -1}, the index of the bit in the second set of parity bits is {Z}. c Z c +1,…,2Z c -1}, and so on.

[0213] In one possible implementation, In {x, x+1, ..., x+Z c The number of any L consecutive numbers in the expression {-1} is greater than 1 / 4L and less than 3 / 4L, where L is a multiple of 4. This application does not limit the value of L; for example, L can be 8, 16, or 32. This indicates rounding down, which occurs anywhere in this application. It can also be replaced with (i.e., round up).

[0214] In one possible implementation, The integer does not contain t+1 consecutive natural numbers, where t is an integer greater than or equal to 1. This application does not limit the value of t; for example, t equals... 16, 8, or 4.

[0215] In one possible implementation, or or or or or Among them, Z c It can be either odd or even. Here, "∪" represents the union of sets; this will be explained in detail here and will not be repeated later.

[0216] In one possible implementation, or or or or or Among them, Z c It is an even number.

[0217] In one possible implementation, for σ0(i)=2i-x; for Among them, Z c It can be either odd or even.

[0218] In one possible implementation, for σ0(i)=2i-x; for σ0(i)=2i+1-Z c -x. Where Z c It is an even number.

[0219] In one possible implementation, for σ0(i)=2i+1-x; for Among them, Z cIt can be either odd or even.

[0220] In one possible implementation, for σ0(i)=2i+1-x; for σ0(i)=2i-Z c -x. Where Z c It is an even number.

[0221] It should be noted that, for the set of parity bits that needs to be interleaved within the multiple parity bit sets mentioned above (e.g., the first parity bit set), the index of the bits in the first parity bit set can also be represented as {0,1,…,Z}. c -1},Z c Let σ0(i) represent the size of the first set of parity bits, where σ0(i) represents {0, 1, ..., Z}. c -1} to {0,1,…,Z} c A mapping of {-1}, i∈{0,1,…,Z} c -1}. That is, for each set of parity bits that needs to be interleaved within the set, the index of the bits in that set is represented as {0,1,…,Z}. c -1}. Accordingly, the various implementation methods described above can also be replaced using the following expressions.

[0222] In one possible implementation, In {0,1,…,Z} c The number of any consecutive L numbers in the expression {-1} is greater than 1 / 4L and less than 3 / 4L, where L is a multiple of 4. This application does not limit the value of L; for example, L can be 8, 16, or 32.

[0223] In one possible implementation, The integer does not contain t+1 consecutive natural numbers, where t is an integer greater than or equal to 1. This application does not limit the value of t; for example, t equals... 16, 8, or 4.

[0224] In one possible implementation, or or or or or Among them, Z c It can be either odd or even.

[0225] In one possible implementation, or or or or or 1,…,Z c -1}. Where Z c It is an even number.

[0226] In one possible implementation, for σ0(i)=2i; for Among them, Z c It can be either odd or even.

[0227] In one possible implementation, for σ0(i)=2i; for σ0(i) = 2i + 1. Where, Z c It is an even number.

[0228] In one possible implementation, for σ0(i)=2i+1; for Among them, Z c It can be either odd or even.

[0229] In one possible implementation, for σ0(i)=2i+1; for σ0(i)=2i-Z c Among them, Z c It is an even number.

[0230] Figure 13 is a flowchart illustrating an encoding method provided in an embodiment of this application. The method includes the following steps:

[0231] Step 1301: The second communication device receives the information to be decoded.

[0232] Step 1302: The second communication device performs rate matching on the information to be decoded to obtain the second bit sequence.

[0233] The second bit sequence is obtained by interleaving the parity bits in at least one of the multiple parity bit sets. The multiple parity bit sets correspond to the parity bits in the first bit sequence. The first bit sequence is obtained by LDPC channel coding of the information bit sequence based on the basis matrix. The multiple parity bit sets correspond one-to-one with multiple columns in the basis matrix.

[0234] The method for generating the second bit sequence can be found in the description in the embodiment of Figure 10, and will not be repeated here.

[0235] Step 1303: The second communication device performs LDPC channel decoding on the second bit sequence to obtain the information bit sequence.

[0236] Based on the above scheme, since the positions of the parity bits in the second bit sequence are swapped, it is equivalent to swapping the corresponding columns of the parity-check matrix. Therefore, the puncturing position during rate matching can be changed, which helps to improve decoding performance by changing the boost value without changing the shift matrix. Furthermore, this scheme can also improve decoding performance without changing the boost value.

[0237] Figure 14 is a schematic diagram of the simulation results under a specific example provided in this application. The performance of LDPC codes is compared using a Min-sum decoding algorithm with 5 iterations. In the figure, the horizontal axis represents Zc, and the vertical axis represents the signal-to-noise ratio (SNR) corresponding to a block error ratio (BLER) of 0.01; therefore, a lower value indicates better performance. The translation matrix of both lines in the figure is taken from BG_1, and doubling Zc does not change the translation matrix. For example, when Zc = 768, the translation matrix of the group with Zc = 384 is used, and the first two columns are punched. The code rate is 22 / 23.5 = 0.936. The dashed line corresponds to the rate-matching punching scheme of this invention; the solid line represents the rate-matching punching scheme used in existing 5G technology. It can be seen that, with the same Zc value, the scheme of this invention has a smaller SNR, and therefore superior performance.

[0238] The above mainly describes the solution provided by the embodiments of this application from the perspective of the interaction between the first communication device and the second communication device. It is understood that, in order to achieve the above functions, the first communication device and the second communication device may include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0239] In this application embodiment, the first communication device and the second communication device can be divided into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0240] In the case of using integrated units, FIG15 shows a possible exemplary block diagram of the device involved in the embodiments of this application. As shown in FIG15, the device 1500 may include a processing unit 1502 and a communication unit 1503. The processing unit 1502 is used to control and manage the operation of the device 1500. The communication unit 1503 is used to support communication between the device 1500 and other devices. Optionally, the communication unit 1503 is also called a transceiver unit, and may include a receiving unit and / or a sending unit, respectively used to perform receiving and sending operations. The device 1500 may also include a storage unit 1501 for storing the program code and / or data of the device 1500.

[0241] The device 1500 can be the first communication device in the above embodiments. The processing unit 1502 can support the device 1500 in performing the operations of the first communication device in the above method embodiments. Alternatively, the processing unit 1502 mainly performs the internal operations of the first communication device in the method embodiments, and the communication unit 1503 can support communication between the device 1500 and other devices.

[0242] For example, in one embodiment, the processing unit 1502 is configured to perform LDPC channel coding on the information bit sequence according to the base matrix to obtain a first bit sequence, wherein the parity bits in the first bit sequence correspond to multiple parity bit sets, and the multiple parity bit sets correspond one-to-one with multiple columns in the base matrix; perform intra-set interleaving on the parity bits in at least one of the multiple parity bit sets to obtain a second bit sequence; and perform rate matching on the second bit sequence to obtain a third bit sequence.

[0243] In one possible implementation, the processing unit 1502 is configured to perform intra-set interleaving of the parity bits in at least one of the plurality of parity bit sets to obtain a second bit sequence, including: performing intra-set interleaving of the parity bits in the at least one parity bit set, and performing inter-set overall interleaving of at least two of the plurality of parity bit sets to obtain the second bit sequence.

[0244] In one possible implementation, the processing unit 1502 is configured to perform intra-set interleaving of the parity bits in at least one of the plurality of parity bit sets to obtain a second bit sequence, including: performing intra-set interleaving of the parity bits in the at least one parity bit set according to an interleaving pattern to obtain the second bit sequence, wherein the interleaving pattern is used to indicate the interleaving mode of the parity bits in the at least one parity bit set.

[0245] In one possible implementation, the at least one set of check bits includes a first set of check bits, and the second bit sequence includes a plurality of bits corresponding to the first set of check bits, wherein at least one bit in the first set of check bits is uniformly distributed among the plurality of bits.

[0246] In one possible implementation, the number of the at least one bit is half the size of the first set of parity bits.

[0247] In one possible implementation, the first set of parity bits corresponds to the last column of the core parity region in the base matrix.

[0248] In one possible implementation, the first set of parity bits corresponds to the first column of the zero matrix region in the basis matrix.

[0249] In one possible implementation, the indices of the bits in the first parity bit set are {x, x+1, ..., x+Z}. c -1}, where x represents the starting index of the bit in the first parity bit set, Z c This represents the size of the first set of parity bits, where σ0(i) represents {x, x+1, ..., x+Z}. c From {-1} to {x,x+1,…,x+Z} c A mapping from {x, x+1, ..., x+Z} to {x, x+1, ..., x+Z}. c -1}.

[0250] In one possible implementation, In {x, x+1, ..., x+Z c The number of any consecutive L numbers in the set {-1} is greater than 1 / 4L and less than 3 / 4L, where L is a multiple of 4.

[0251] In one possible implementation, L equals 8, 16, or 32.

[0252] In one possible implementation, It does not contain t+1 consecutive natural numbers, where t is an integer greater than or equal to 1.

[0253] In one possible implementation, t equals 16, 8, or 4.

[0254] In one possible implementation, or

[0255] In one possible implementation, for σ0(i)=2i-x; for

[0256] In one possible implementation, for σ0(i)=2i+1-x; for

[0257] In one possible implementation, the processing unit 1502 is configured to perform intra-set interleaving of the parity bits in at least one of the plurality of parity bit sets to obtain a second bit sequence, including: performing intra-set interleaving of the parity bits in the at least one parity bit set to obtain the second bit sequence when the code rate is greater than the first code rate.

[0258] In one possible implementation, the first code rate is the code rate corresponding to the core region of the basis matrix.

[0259] In one possible implementation, the first bit rate is equal to 22 / 24 or 22 / 25.

[0260] The device 1500 can be the second communication device in the above embodiments. The processing unit 1502 can support the device 1500 in performing the operations of the second communication device in the above method embodiments. Alternatively, the processing unit 1502 mainly performs the internal operations of the second communication device in the method embodiments, and the communication unit 1503 can support communication between the device 1500 and other devices.

[0261] For example, in one embodiment, a communication unit 1503 is used to receive information to be decoded; a processing unit 1502 is used to perform rate matching on the information to be decoded to obtain a second bit sequence; wherein, the second bit sequence is obtained by interleaving the parity bits in at least one of a plurality of parity bit sets, the plurality of parity bit sets corresponding to the parity bits in the first bit sequence, the first bit sequence being obtained by LDPC channel coding of the information bit sequence according to the basis matrix, the plurality of parity bit sets corresponding one-to-one with a plurality of columns in the basis matrix; and LDPC channel decoding is performed on the second bit sequence to obtain the information bit sequence.

[0262] In one possible implementation, the second bit sequence is obtained by interleaving the parity bits within at least one parity bit set from a plurality of parity bit sets, and by performing overall interleaving between at least two parity bit sets from the plurality of parity bit sets.

[0263] In one possible implementation, the second bit sequence is obtained by interleaving the parity bits in at least one of a plurality of parity bit sets according to an interleaving pattern, wherein the interleaving pattern is used to indicate the interleaving method of the parity bits in the at least one parity bit set.

[0264] In one possible implementation, the at least one set of check bits includes a first set of check bits, and the second bit sequence includes a plurality of bits corresponding to the first set of check bits, wherein at least one bit in the first set of check bits is uniformly distributed among the plurality of bits.

[0265] In one possible implementation, the number of the at least one bit is half the size of the first set of parity bits.

[0266] In one possible implementation, the first set of parity bits corresponds to the last column of the core parity region in the base matrix.

[0267] In one possible implementation, the first set of parity bits corresponds to the first column of the zero matrix region in the basis matrix.

[0268] In one possible implementation, the indices of the bits in the first parity bit set are {x, x+1, ..., x+Z}. c -1}, where x represents the starting index of the bit in the first parity bit set, Z c This represents the size of the first set of parity bits, where σ0(i) represents {x, x+1, ..., x+Z}. c From {-1} to {x,x+1,…,x+Z} c A mapping from {x, x+1, ..., x+Z} to {x, x+1, ..., x+Z}. c -1}.

[0269] In one possible implementation, In {x, x+1, ..., x+Z c The number of any consecutive L numbers in the set {-1} is greater than 1 / 4L and less than 3 / 4L, where L is a multiple of 4.

[0270] In one possible implementation, L equals 8, 16, or 32.

[0271] In one possible implementation, It does not contain t+1 consecutive natural numbers, where t is an integer greater than or equal to 1.

[0272] In one possible implementation, t equals 16, 8, or 4.

[0273] In one possible implementation, or

[0274] In one possible implementation, for σ0(i)=2i-x; for

[0275] In one possible implementation, for σ0(i)=2i+1-x; for

[0276] In one possible implementation, the second bit sequence is obtained by interleaving the parity bits in at least one of a plurality of parity bit sets with a code rate greater than the first code rate.

[0277] In one possible implementation, the first code rate is the code rate corresponding to the core region of the basis matrix.

[0278] In one possible implementation, the first bit rate is equal to 22 / 24 or 22 / 25.

[0279] It should be understood that the division of units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, all units in the device can be implemented entirely through software calls from processing elements; all units can be implemented entirely in hardware; or some units can be implemented through software calls from processing elements, and some units can be implemented in hardware. For example, each unit can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as a program in memory, called and executed by a processing element of the device. Moreover, these units can be fully or partially integrated together, or implemented independently. The processing element mentioned here can also be called a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, the operations of the above methods or the various units can be implemented through integrated logic circuits in the processor element or through software calls from processing elements.

[0280] In one example, a unit in any of the above devices can be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. As another example, when a unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a processor, such as a general-purpose central processing unit (CPU), or other processor capable of calling programs. Furthermore, these units can be integrated together and implemented as a System-on-a-Chip (SoC).

[0281] The receiving unit described above is an interface circuit of the device, used to receive signals from other devices. For example, when the device is implemented as a chip, the receiving unit is an interface circuit for the chip to receive signals from other chips or devices. The transmitting unit described above is an interface circuit of the device, used to transmit signals to other devices. For example, when the device is implemented as a chip, the transmitting unit is an interface circuit for the chip to transmit signals to other chips or devices.

[0282] Based on the same technical concept, this application also provides a communication device for implementing the functions of the first or second communication device described above. As shown in FIG16, the device may be a communication equipment or a component of a communication equipment (e.g., a processor, chip, or chip system). The device includes a processor 1601 and a communication interface 1602, and optionally, a memory 1603. The memory 1603 may be independent of the processor 1601 or integrated into the processor 1601; no specific limitation is made. It is understood that FIG16 only shows the main components of the communication device. Furthermore, the communication device may further include input / output devices (not shown in the figure).

[0283] The processor 1601 is used to execute the program code stored in the memory 1603, specifically to perform the actions of the aforementioned processing unit 1502, which will not be described in detail here. The communication interface 1602 is specifically used to perform the actions of the aforementioned communication unit 1503, which will not be described in detail here.

[0284] Processor 1601 can be a CPU, a digital processing unit, etc. Processor 1601 can be used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data, such as, but not limited to, baseband-related processing. Communication interface 1602 can be used for transmitting and receiving signals, such as, but not limited to, radio frequency transceiver. The above-mentioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. For example, processor 1601 can be further divided into an analog baseband processor and a digital baseband processor. The analog baseband processor can be integrated with the transceiver on the same chip, while the digital baseband processor can be disposed on a separate chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with multiple application processors (such as, but not limited to, graphics processors, multimedia processors, etc.) on the same chip. Such a chip can be called a system-on-a-chip (SoC). Whether to dispose of individual devices independently on different chips or integrate them on one or more chips often depends on the specific needs of the product design. The embodiments of the present invention do not limit the specific implementation of the above-mentioned devices.

[0285] The communication interface 1602 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. Optionally, the communication interface 1602 may include radio frequency (RF) circuitry and an antenna. The RF circuitry is mainly used for converting baseband signals to RF signals and processing RF signals. The antenna is mainly used for transmitting and receiving RF signals in the form of electromagnetic waves. Input / output devices, such as touchscreens, displays, and keyboards, are mainly used for receiving user input data and outputting data to the user.

[0286] Memory 1603 is used to store programs executed by processor 1601. Memory 1603 can be non-volatile memory, such as a hard disk drive (HDD) or solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). Memory 1603 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited to these.

[0287] When the communication device is powered on, the processor 1601 can read the software program in the memory 1603, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 1601 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit processes the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1601. The processor 1601 converts the baseband signal into data and processes the data.

[0288] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0289] This application embodiment does not limit the specific connection medium between the communication interface 1602, processor 1601, and memory 1603. In Figure 16, the memory 1603, processor 1601, and communication interface 1602 are connected via a bus 1604, which is represented by a thick line in Figure 16. The connection methods between other components are only illustrative and not intended to be limiting. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is used in Figure 16, but this does not indicate that there is only one bus or one type of bus.

[0290] Optionally, the communication device described above can be a standalone device or part of a larger device. For example, the communication device can be:

[0291] (1) An independent integrated circuit (IC), or chip, or chip system or subsystem;

[0292] (2) A collection of one or more ICs, optionally including a storage component for storing data and instructions;

[0293] (3) Application-specific integrated circuit (ASIC), such as modem;

[0294] (4) Modules that can be embedded in other devices;

[0295] (5) Receivers, smart terminals, wireless devices, handheld devices, mobile units, vehicle-mounted devices, cloud devices, artificial intelligence devices, etc.;

[0296] (6) Others, etc.

[0297] In this application embodiment, "multiple" can refer to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A, B, and C. "And / or" describes the association relationship between related objects. Specifically, there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0298] Furthermore, the terms "system" and "network" in the embodiments of this application can be used interchangeably, as can "according to" and "based on". The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are generally used to distinguish different objects and are not used to limit the order, sequence, priority, or importance of multiple objects. For example, the first communication device and the second communication device in the embodiments of this application are used to distinguish between two communication devices, and do not limit the priority or importance of these two communication devices.

[0299] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0300] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0301] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0302] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

Claims

1. An encoding method, characterized in that, The method includes: Based on the basis matrix, the information bit sequence is coded using low-density parity-check (LDPC) channel coding to obtain a first bit sequence. The parity bits in the first bit sequence correspond to multiple parity bit sets, and the multiple parity bit sets correspond one-to-one with multiple columns in the basis matrix. Interleave the parity bits in at least one of the multiple parity bit sets to obtain a second bit sequence; Rate matching is performed on the second bit sequence to obtain the third bit sequence.

2. The method of claim 1, wherein, The step of interleaving the parity bits within at least one of the plurality of parity bit sets to obtain the second bit sequence includes: The parity bits within the at least one parity bit set are interleaved within the set, and the parity bits between at least two of the plurality of parity bit sets are interleaved globally to obtain the second bit sequence.

3. The method as described in claim 1 or 2, characterized in that, The step of interleaving the parity bits within at least one of the plurality of parity bit sets to obtain the second bit sequence includes: According to the interleaving pattern, the parity bits in the at least one parity bit set are interleaved within the set to obtain the second bit sequence. The interleaving pattern is used to indicate the interleaving method of the parity bits in the at least one parity bit set.

4. The method according to any one of claims 1 to 3, characterized in that, The at least one set of check bits includes a first set of check bits, and the second bit sequence includes a plurality of bits corresponding to the first set of check bits, wherein at least one bit in the first set of check bits is evenly distributed among the plurality of bits.

5. The method as described in claim 4, characterized in that, The number of the at least one bit is half the size of the first set of check bits.

6. The method as described in claim 4 or 5, characterized in that, The first set of parity bits corresponds to the last column of the core parity region in the base matrix.

7. The method as described in claim 4 or 5, characterized in that, The first set of parity bits corresponds to the first column of the zero matrix region in the base matrix.

8. The method according to any one of claims 1 to 7, characterized in that, The step of interleaving the parity bits within at least one of the plurality of parity bit sets to obtain the second bit sequence includes: When the code rate is greater than the first code rate, the parity bits in the at least one parity bit set are interleaved within the set to obtain the second bit sequence.

9. The method as described in claim 8, characterized in that, The first bitrate is the bitrate corresponding to the core region of the base matrix.

10. The method as described in claim 9, characterized in that, The first bit rate is equal to 22 / 24 or 22 / 25.

11. A decoding method, characterized in that, The method includes: Receive the information to be decoded; The information to be decoded is rate-matched to obtain a second bit sequence; wherein the second bit sequence is obtained by interleaving the parity bits in at least one of the multiple parity bit sets, the multiple parity bit sets correspond to the parity bits in the first bit sequence, the first bit sequence is obtained by LDPC channel coding of the information bit sequence according to the basis matrix, and the multiple parity bit sets correspond one-to-one with multiple columns in the basis matrix. The second bit sequence is then subjected to LDPC channel decoding to obtain the information bit sequence.

12. The method as described in claim 11, characterized in that, The second bit sequence is obtained by interleaving the parity bits within at least one parity bit set from a plurality of parity bit sets, and by interleaving the parity bits between at least two parity bit sets from the plurality of parity bit sets.

13. The method as described in claim 11 or 12, characterized in that, The second bit sequence is obtained by interleaving the parity bits in at least one parity bit set among a plurality of parity bit sets according to an interleaving pattern, wherein the interleaving pattern is used to indicate the interleaving method of the parity bits in the at least one parity bit set.

14. The method according to any one of claims 11 to 13, characterized in that, The at least one set of check bits includes a first set of check bits, and the second bit sequence includes a plurality of bits corresponding to the first set of check bits, wherein at least one bit in the first set of check bits is evenly distributed among the plurality of bits.

15. The method as described in claim 14, characterized in that, The number of the at least one bit is half the size of the first set of check bits.

16. The method as described in claim 14 or 15, characterized in that, The first set of parity bits corresponds to the last column of the core parity region in the base matrix.

17. The method as described in claim 14 or 15, characterized in that, The first set of parity bits corresponds to the first column of the zero matrix region in the base matrix.

18. The method according to any one of claims 11 to 17, characterized in that, The second bit sequence is obtained by interleaving the parity bits in at least one parity bit set from multiple parity bit sets when the code rate is greater than the first code rate.

19. The method as described in claim 18, characterized in that, The first bitrate is the bitrate corresponding to the core region of the base matrix.

20. The method as described in claim 19, characterized in that, The first bit rate is equal to 22 / 24 or 22 / 25.

21. The method according to any one of claims 1 to 20, characterized in that, The indices of the bits in the first set of parity bits are {x, x+1, ..., x+Z}. c -1}, where x represents the starting index of the bit in the first parity bit set, Z c Let σ0(i) represent the size of the first set of parity bits, where σ0(i) represents {x, x+1, ..., x+Z}. c From {-1} to {x,x+1,…,x+Z} c A mapping from {x, x+1, ..., x+Z} to {x, x+1, ..., x+Z}. c -1}.

22. The method as described in claim 21, characterized in that, In {x, x+1, ..., x+Z c The number of any consecutive L numbers in the set {-1} is greater than 1 / 4L and less than 3 / 4L, where L is a multiple of 4.

23. The method as described in claim 22, characterized in that, L can be 8, 16, or 32.

24. The method according to any one of claims 21 to 23, characterized in that, It does not contain t+1 consecutive natural numbers, where t is an integer greater than or equal to 1.

25. The method of claim 24, wherein, t equals 16, 8, or 4.

26. The method according to any one of claims 21 to 25, characterized in that, or 27. The method according to any one of claims 21 to 26, characterized in that, To σ0(i)=2i-x; To 28. The method according to any one of claims 21 to 26, characterized in that, To σ0(i)=2i+1-x; To 29. A communications device, characterized by The device includes a processor coupled to a memory in which a computer program is stored; the processor is configured to invoke part or all of the computer program in the memory such that the method as claimed in any one of claims 1 to 10, 21 to 28 is executed, or the method as claimed in any one of claims 11 to 28 is executed.

30. A communication system, characterized by The communication system includes a first communication device and a second communication device; wherein the first communication device is used to perform the method as described in any one of claims 1 to 10, 21 to 28, and the second communication device is used to perform the method as described in any one of claims 11 to 28.

31. A computer readable storage medium, characterized in that, The storage medium stores a computer program that, when some or all of the computer program is executed by a computer, causes the method as described in any one of claims 1 to 10, 21 to 28 to be performed, or causes the method as described in any one of claims 11 to 28 to be performed.

32. A computer program product, characterised in that, When the computer reads and executes the computer program product, the method as described in any one of claims 1 to 10, 21 to 28 is performed, or the method as described in any one of claims 11 to 28 is performed.

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