MEMS device packaging method and MEMS chip unit

Abstract

Provided are an MEMS device packaging method and an MEMS chip unit. The method comprises: manufacturing a substrate wafer, a glass capping wafer and a silicon wafer by means of an etching process; bonding the glass capping wafer and the silicon wafer on the basis of a second alignment mark and a third alignment mark, so as to form a cap wafer; constructing a through-hole structure and a silicon bonding ring of the cap wafer; manufacturing a metal intermediate layer on the surface of the silicon bonding ring; bonding the cap wafer and the substrate wafer by means of the metal intermediate layer on the basis of a first alignment mark and the second alignment mark, so as to form a packaging wafer having a vacuum-tight chamber; and respectively performing wafer dicing on the packaging wafer along a first scribe lane and a second scribe lane, so as to obtain an MEMS chip unit.

Description

MEMS device packaging methods and MEMS chip units Technical Field

[0001] This application relates to the field of chip packaging, and more particularly to packaging methods for MEMS devices and MEMS chip units. Background Technology

[0002] Currently, microelectromechanical systems (MEMS) device packaging technologies are mainly divided into chip-level packaging and wafer-level packaging. While wafer-level packaging offers advantages such as small package size, high transmission speed, high connection density, and the ability to achieve rapid mass production to reduce manufacturing costs, its manufacturing process is complex, requiring sophisticated equipment and technology. Issues such as yield problems, dicing efficiency and output rate, poor maintainability, and limitations in technology maturity and compatibility also present challenges for wafer-level packaging. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] The purpose of this application is to at least partially solve one of the technical problems existing in the related technologies. The embodiments of this application provide a packaging method for MEMS devices and a MEMS chip unit, which can improve the bonding quality and strength of MEMS devices, simplify the process, and enhance the reliability and performance stability of MEMS device packaging.

[0005] An embodiment of the first aspect of this application provides a packaging method for a MEMS device, characterized in that it includes:

[0006] Obtain a substrate wafer, wherein the substrate wafer is provided with MEMS devices, a wafer bonding area, a first alignment mark and a first dicing groove;

[0007] Based on the MEMS device and the wafer bonding region, a second dicing groove and a second alignment mark are fabricated on the first wafer to form a first bonded wafer;

[0008] Based on the wafer bonding region, a third alignment mark is fabricated on the second wafer to form a second bonded wafer;

[0009] The first bonding wafer and the second bonding wafer are bonded according to the second alignment mark and the third alignment mark to form a cap wafer;

[0010] Based on the wafer bonding region, a silicon bonding ring is formed in the cap wafer via;

[0011] A metal interlayer is fabricated on the silicon bonding ring;

[0012] The cap wafer and the substrate wafer are bonded together through the metal interlayer according to the first alignment mark and the second alignment mark to form a packaged wafer with a vacuum-sealed chamber;

[0013] The packaged wafer is diced along the first dicing groove and the second dicing groove respectively to obtain MEMS chip units.

[0014] According to certain embodiments of the first aspect of this application, the first wafer is a glass wafer and the second wafer is a silicon wafer; the bonding method for bonding the first bonding wafer and the second bonding wafer according to the second alignment mark and the third alignment mark is silicon-glass anodic bonding.

[0015] According to certain embodiments of the first aspect of this application, the bonding method for bonding the cap wafer and the substrate wafer through the metal interlayer based on the first alignment mark and the second alignment mark is metal interlayer bonding.

[0016] According to certain embodiments of the first aspect of this application, the process temperature for silicon-glass anodic bonding is higher than the process temperature for metal interlayer bonding.

[0017] According to certain embodiments of the first aspect of this application, the metal interlayer bonding is gold-silicon eutectic bonding, gold-gold diffusion bonding, or copper-tin solder bonding.

[0018] According to certain embodiments of the first aspect of this application, the substrate wafer contains a getter that is activated at the process temperature for bonding the metal interlayer.

[0019] A second aspect of this application provides a MEMS chip unit, characterized in that it is fabricated according to the packaging method of the MEMS device according to the first aspect of this application; the MEMS chip unit comprises:

[0020] The substrate wafer is provided with MEMS devices, a wafer bonding area, a first alignment mark and a first dicing groove;

[0021] The first wafer is provided with a second dicing groove and a second alignment mark;

[0022] The second wafer is provided with through-holes, silicon bonding rings and a third alignment mark, wherein the silicon bonding rings are provided with a metal interlayer;

[0023] The first wafer, the second wafer, and the substrate wafer are sequentially bonded together to form a packaged wafer with a vacuum-sealed chamber.

[0024] According to certain embodiments of the second aspect of this application, the metal interlayer includes a metal adhesive layer and a metal bonding layer.

[0025] According to certain embodiments of the second aspect of this application, the metal bonding layer is made of one or more of Ti, Gr and Ta, and the metal bonding layer is made of one or more of Au, Cu and Sn.

[0026] According to certain embodiments of the second aspect of this application, the substrate wafer contains a getter, which is a Ti metal or a Ti-based alloy thin film material.

[0027] The above-described solution offers at least the following advantages: MEMS device packaging is achieved through a two-stage bonding process. Bonding alignment is performed using first, second, and third alignment marks, sequentially bonding the glass cap wafer, silicon wafer, and substrate wafer together to form a packaged wafer. This wafer encloses a vacuum-sealed chamber, providing an optical pathway. This approach satisfies both the hermeticity and optical pathway compatibility requirements of MEMS devices while avoiding the problems of complex packaging, low efficiency, and high cost inherent in traditional packaging processes. Therefore, this invention improves the bonding quality and strength of MEMS devices, simplifies the process, and enhances the reliability and performance stability of MEMS device packaging. Attached Figure Description

[0028] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0029] Figure 1 is a flowchart of a packaging method for a MEMS device provided in an embodiment of this application;

[0030] Figure 2 is a schematic diagram of the structure of the substrate wafer provided in an embodiment of this application;

[0031] Figure 3 is a schematic diagram of the structure of the glass-capped wafer provided in an embodiment of this application;

[0032] Figure 4 is a schematic diagram of the structure of the capped wafer provided in an embodiment of this application;

[0033] Figure 5 is a schematic diagram of the structure of the silicon bonding ring provided in an embodiment of this application;

[0034] Figure 6 is a schematic diagram of the structure of the metal interlayer provided in an embodiment of this application;

[0035] Figure 7 is a cross-sectional view of the packaged wafer provided in an embodiment of this application;

[0036] Figure 8 is a cross-sectional view of a MEMS chip unit provided in an embodiment of this application;

[0037] Figure 9 is a three-dimensional cross-sectional view of a MEMS chip unit provided in an embodiment of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0039] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, or the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0040] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0041] The embodiments of this application provide a packaging method and structure for MEMS devices, which can improve the bonding quality and strength of MEMS devices, simplify the process, and enhance the reliability and performance stability of MEMS device packaging.

[0042] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0043] As shown in Figure 1, Figure 1 is a flowchart of a packaging method for a MEMS device provided in an embodiment of the present invention. The packaging method for the MEMS device includes, but is not limited to, steps S1, S2, S3, S4, S5, S6, S7 and S8.

[0044] Step S1: Obtain the substrate wafer.

[0045] As shown in Figure 2, in some embodiments, a pre-fabricated substrate wafer 200 is obtained. The substrate wafer 200 is provided with MEMS devices 201, getter 202, wafer bonding area 203, metal pads 204, driving circuit 205, first alignment mark 206, and first dicing groove 207. The positions of components such as the MEMS devices 201, metal pads 204, and driving circuit 205 in the substrate wafer 200 are fixed and cannot be modified during later fabrication processes. However, the positions of components such as the getter 202, wafer bonding area 203, first alignment mark 206, and first dicing groove 207 can be modified during later fabrication according to actual conditions, and are not specifically limited here.

[0046] Understandably, the positioning of each component on the substrate wafer 200 can provide a positional reference for the subsequent fabrication of the glass cap wafer 400 and the silicon wafer 300. Bonding the obtained substrate wafer 200 to the subsequently fabricated first bonding wafer 300 and second bonding wafer 400 enables the packaging of the MEMS device 201, which helps improve the packaging yield of the MEMS device 201.

[0047] Step S2: Based on the MEMS device and the wafer bonding area, a second dicing groove and a second alignment mark are fabricated on the first wafer to form a first bonded wafer.

[0048] The first wafer is a glass wafer 301.

[0049] Using glass wafer 301 as raw material, the glass wafer 301 is pre-processed. Based on MEMS device 201 and wafer bonding region 203, a second dicing groove 302 is fabricated by etching process, and a second alignment mark 303 is fabricated by etching process to form first bonding wafer 300.

[0050] As shown in Figure 3, it can be understood that in some embodiments, glass wafer 301 is used as the raw material. The glass wafer 301 is pre-processed, and the position of the second dicing groove 302 is determined based on the positions of the MEMS device 201 on the substrate wafer 200 and the wafer bonding region 203. The second dicing groove 302 is then fabricated using an etching process. The position of the second alignment mark 303 is determined according to the bonding alignment requirements, and the second alignment mark 303 is fabricated using an etching process. A first bonded wafer 300 can then be fabricated.

[0051] It should be noted that the 301 glass wafer is a high-precision optical glass material, and using it as a packaging cover meets the required optical requirements.

[0052] Step S3: Based on the wafer bonding region, a third alignment mark is fabricated on the second wafer to form a second bonded wafer.

[0053] The second wafer is silicon wafer 401.

[0054] As shown in Figure 4, it can be understood that in some embodiments, silicon wafer 401 is used as raw material, the silicon wafer 401 is pre-processed, the position of the third alignment mark 402 is determined according to the bonding alignment requirements, the third alignment mark 402 is made by etching process, and the second bonding wafer is formed.

[0055] Step S4: Bond the first bonding wafer and the second bonding wafer according to the second alignment mark and the third alignment mark to form a capping wafer.

[0056] As shown in Figure 4, based on the first bonding method, the first bonding wafer 300 and the second bonding wafer 400 can be bonded together using the second alignment mark 303 and the third alignment mark 402 to form a cap wafer 500.

[0057] Step S5: Based on the wafer bonding region, form a silicon bonding ring in the cap wafer via.

[0058] For example, silicon wafers are used as raw materials and processed. Based on the wafer bonding region 203, through-holes are formed at the target locations on the cap wafer 500 by an etching process to form silicon bonding rings 404;

[0059] As shown in Figure 5, it can be understood that the wafer thickness is determined based on the MEMS device 201 on the substrate wafer 200, the position and size of the via 403 are determined based on the wafer bonding region 203, and the via 403 structure of the corresponding size is fabricated at the target position through the etching process, so that the via 403 provides the packaging cavity of the MEMS device 201, thereby forming the silicon bonding ring 404 for wafer bonding;

[0060] Step S6: Fabricate a metal intermediate layer on the silicon bonding ring.

[0061] A metal interlayer 600 was fabricated on the surface of the silicon bonding ring 404 of the cap wafer using a metal thin film deposition process.

[0062] As shown in Figure 6, it can be understood that a metal interlayer 600 is fabricated on the silicon bonding ring 404 forming the cap wafer 500. The cap wafer 500 and the substrate wafer 200 can be bonded through the metal interlayer 600 to obtain the packaged wafer 700.

[0063] Step S7: Based on the first alignment mark and the second alignment mark, the cap wafer and the substrate wafer are bonded through a metal interlayer to form a packaged wafer with a vacuum-sealed chamber.

[0064] Based on the second bonding method, the cap wafer 500 and the substrate wafer 200 are bonded through the metal interlayer 600 according to the first alignment mark 206 and the second alignment mark 303 to form a packaged wafer 700 with a vacuum-sealed chamber 701.

[0065] As shown in Figure 7, since the first bonding wafer 300 and the second bonding wafer 400 have completed the bonding operation in step S3 to form the cap wafer 500, at this time, based on the second bonding method, the first alignment mark 206 and the second alignment mark 303 are used for bonding alignment, and the cap wafer 500 and the substrate wafer 200 can be bonded through the metal interlayer 600 to form a packaged wafer 700 with a vacuum-sealed chamber 701.

[0066] Step S8: Divide the packaged wafer along the first dicing groove and the second dicing groove respectively to obtain MEMS chip units.

[0067] Figure 8 shows a cross-sectional view of a MEMS chip unit. Individual MEMS chip units can be obtained by mechanically or laser-cutting the packaged wafer 700 along the first dicing groove 207 and the second dicing groove 302, respectively.

[0068] It is understandable that MEMS device packaging is achieved through a secondary bonding method. Bonding alignment is performed using a first alignment mark 206, a second alignment mark 303, and a third alignment mark 402. Based on the first bonding method, the first bonding wafer 300 and the second bonding wafer 400 are bonded to form a cap wafer 500. Then, based on the second bonding method, the cap wafer 500 and the substrate wafer 200 are bonded together through a metal interlayer 600 to form a packaged wafer 700, which forms a vacuum-sealed chamber 701 providing an optical path. This method can meet the requirements of hermeticity and optical path compatibility for MEMS devices while avoiding the problems of complex packaging, low efficiency, and high cost inherent in traditional packaging processes. It can improve the bonding quality and strength of MEMS devices, simplify the process, and enhance the reliability and performance stability of MEMS device packaging.

[0069] It should be noted that the pre-processing operation includes cleaning, coating, photolithography, development and other processes. The pre-processing operation facilitates the subsequent etching operation of the wafer structure, so as to obtain a packaged wafer 700 that meets the requirements.

[0070] It should be noted that in some embodiments, the first alignment mark 206, the second alignment mark 303, and the third alignment mark 402 are cross-shaped alignment marks.

[0071] It should be noted that in some embodiments, the etching process is reactive ion etching.

[0072] In some embodiments, the first bonding method is silicon-glass anodic bonding, that is, the bonding method in which the first bonding wafer and the second bonding wafer are bonded according to the second alignment mark and the third alignment mark is silicon-glass anodic bonding.

[0073] In some embodiments, the second bonding method is metal interlayer bonding, that is, the bonding method in which the cap wafer and the substrate wafer are bonded through a metal interlayer according to the first alignment mark and the second alignment mark is metal interlayer bonding.

[0074] In some embodiments, the process temperature of the first bonding method is higher than that of the second bonding method.

[0075] It is understood that in some embodiments, the first bonding method is silicon-glass anodic bonding, and the second bonding method is metal interlayer bonding. Encapsulating the MEMS device 201 through a two-stage bonding process ensures the packaging yield and efficiency of the MEMS device 201. Furthermore, setting the process temperature for the silicon-glass anodic bonding between the first bonding wafer 300 and the silicon wafer 200 to be higher than the process temperature for the metal interlayer bonding between the cap wafer 500 and the substrate wafer 200 ensures that the wafer bonding operation of the second metal interlayer bonding will not negatively affect the cap wafer 500. This guarantees the bonding quality and strength of the MEMS device 201, simplifies the process, and enhances the reliability and performance stability of the MEMS device 201 packaging.

[0076] In some embodiments, the second bonding method includes gold-silicon eutectic bonding, gold-gold diffusion bonding, and copper-tin solder bonding.

[0077] It is understandable that the second bonding method, namely the bonding of the cap wafer 500 and the substrate wafer 200 through the metal interlayer 600, can include three methods: gold-silicon eutectic bonding, gold-gold diffusion bonding, and copper-tin eutectic bonding. It should be noted that the bonding temperature of the metal interlayer is different for different bonding methods.

[0078] In some embodiments, the substrate wafer 200 includes a getter 202, which is activated at the process temperature at which the metal interlayer 600 is bonded.

[0079] As shown in Figure 9, it can be understood that operations such as cleaning, spin coating, photolithography, development, and etching on the wafer yield a first bonding wafer 300, a second bonding wafer 400, and a substrate wafer 200. Bonding the first bonding wafer 300 and the second bonding wafer 400 together via silicon-glass anodic bonding yields a cap wafer 500. Further bonding the cap wafer 500 and the substrate wafer 200 together via metal interlayer bonding yields a packaged wafer 700, thus realizing the packaging of the MEMS device. Simultaneously, the substrate wafer 200 is also provided with a getter 202, which is activated at the process temperature of the metal interlayer bonding to absorb residual gases. After obtaining the packaged wafer 700, dicing the packaged wafer 700 along the first dicing groove 207 and the second dicing groove 302 respectively yields independent MEMS chip units. This packaging method enables the packaging of MEMS devices through secondary bonding, ensuring the bonding quality and strength of MEMS devices, simplifying the process, and enhancing the reliability and performance stability of MEMS device packaging.

[0080] It should be noted that the packaging method for MEMS devices can also be applied to other devices such as infrared devices, such as angular velocity accelerators, energy harvesters, or infrared sensors, without specific limitations here.

[0081] Referring to Figures 2 to 9, an embodiment of this application provides a MEMS chip unit.

[0082] The MEMS chip unit includes: a substrate wafer 200, a first bonding wafer 300, and a second bonding wafer 400.

[0083] The substrate wafer 200 is provided with a MEMS device 201, a wafer bonding region 203, a first alignment mark 206, and a first dicing groove 207; the first bonding wafer 300 is provided with a second dicing groove 302 and a second alignment mark 303; the second bonding wafer 400 is provided with a through-hole 403, a silicon bonding ring 404, and a third alignment mark 402, wherein the silicon bonding ring 404 is provided with a metal interlayer 600; the first bonding wafer 300, the second bonding wafer 400, and the substrate wafer 200 are sequentially bonded together to form a packaged wafer 700 with a vacuum-sealed chamber 701.

[0084] It is understood that, further, the MEMS chip unit includes a substrate wafer 200, a first bonding wafer 300, a second bonding wafer 400, a metal interlayer 600, and other structures. By sequentially bonding the first bonding wafer 300, the second bonding wafer 400, and the substrate wafer 200 together, a packaged wafer 700 with a vacuum-sealed chamber 701 can be formed. In other words, according to the technical solution of the present invention, MEMS device packaging is achieved through a secondary bonding method. Bonding alignment is performed using a first alignment mark 206, a second alignment mark 303, and a third alignment mark 402. Based on the first bonding method, the first bonding wafer 300 and the second bonding wafer 400 are bonded to form a cap wafer 500. Based on the second bonding method, the cap wafer 500 and the substrate wafer 200 are bonded together through the metal interlayer 600, thereby forming a packaged wafer 700 with a vacuum-sealed chamber 701. The vacuum-sealed chamber 701 provides an optical path, which, while meeting the requirements of hermeticity and optical path compatibility for MEMS devices, avoids the problems of complex packaging, low efficiency, and high cost in traditional packaging processes. Therefore, this invention can improve the bonding quality and strength of MEMS devices, simplify the process, and enhance the reliability and performance stability of MEMS device packaging.

[0085] In some embodiments, the metal interlayer 600 includes a metal adhesive layer 601 and a metal bonding layer 602.

[0086] In some embodiments, the metal bonding layer 601 is made of one or more of Ti, Gr, and Ta, and the metal bonding layer 602 is made of one or more of Au, Cu, and Sn.

[0087] It is understandable that the material of the metal interlayer 600 can be selected according to the actual situation. The metal bonding layer 601 can be made of Ti, Cr, or Ta, and the metal bonding layer 602 can be made of one or more combinations of Au, Cu, and Sn. No specific limitation is made here.

[0088] In some embodiments, the substrate wafer 200 includes a getter 202, which is a Ti metal or Ti-based alloy thin film material.

[0089] It should be noted that, based on the metal interlayer bonding method, the cap wafer 500 and the substrate wafer 200 can be bonded together through the metal interlayer 600 to form the packaged wafer 700. Specifically, the metal interlayer bonding includes gold-silicon eutectic bonding, gold-gold diffusion bonding, and copper-tin solder bonding. It should also be noted that the bonding temperatures for different metal interlayer bonding methods are different.

[0090] Specifically, the following embodiment illustrates the packaging method of MEMS devices in detail, with the specific steps as follows.

[0091] The first step involves fabricating a substrate wafer 200 and setting up structures including a MEMS device 201, a getter 202, a wafer bonding region 203, metal pads 204, a driving circuit 205, a first alignment mark 206, and a first dicing groove 207. In this embodiment, the wafer bonding region 203 of the substrate wafer 200 is a metal interlayer 600, which includes a metal bonding layer 601 and a metal bonding layer 602. The metal bonding layer 601 is a 50nm thick Cr metal layer, and the metal bonding layer is a 500nm thick Au metal layer.

[0092] The second step is to fabricate the first bonding wafer 300. The glass wafer 301 undergoes pattern transfer through steps such as cleaning, homogenization, photolithography, development, and etching. Using photoresist as a mask, the second dicing groove 302 and the second alignment mark 303 structure are fabricated through etching, thereby completing the fabrication of the first bonding wafer 300.

[0093] The third step involves fabricating the cap wafer 500. First, using silicon wafer 401 as the raw material, pre-process the silicon wafer 401. Based on the bonding alignment requirements, the position of the third alignment mark 402 is determined in the silicon wafer 401. The third alignment mark 402 is then fabricated using an etching process to complete the preparation of the second bonded wafer 400. Next, based on the first bonding method, the second alignment mark 303 and the third alignment mark 402 are used to align the first bonded wafer 300 and the second bonded wafer 400. Finally, silicon-glass anodic bonding is performed. Specifically, the silicon-glass anodic bonding process is as follows: First, a vacuum is drawn, evacuating the bonding chamber to a certain level and maintaining this level until bonding is complete. Second, the temperature is gradually increased in three stages to the rated temperature of 400°C. Third, pressure is applied, with the two electrodes applying pressure to the first bonding wafer 300 and the second bonding wafer 400 to a certain level and maintaining this pressure until bonding is complete. Fourth, a high voltage is applied to the first bonding wafer 300 and the second bonding wafer 400 by the two electrodes and maintained for a certain period of time. Under these process conditions, the silicon-glass anodic bonding process can be completed, resulting in a capped wafer 500.

[0094] The fourth step involves fabricating a silicon bonding ring 404 using the second bonding wafer 400 as the raw material. First, the positions of the vias 403 and the silicon bonding ring 404 on the second bonding wafer 400 are determined. The mask pattern is transferred to the surface of the silicon wafer 401 using cleaning, spin coating, photolithography, and development. The wafer thickness is determined based on the MEMS device 201 on the substrate wafer 200, and the position and size of the vias 403 are determined based on the wafer bonding region 203. Through etching, vias 403 of the corresponding size are fabricated at the target positions, providing the packaging cavity for the MEMS device 201, thereby forming the silicon bonding ring 404 for wafer bonding.

[0095] The fifth step involves fabricating a metal interlayer 600. Using magnetron sputtering and other processes, a metal interlayer 600, comprising a metal binder layer 601 and a metal bonding layer 602, is fabricated on the surface of the silicon bonding ring 404. By adjusting the sputtering power and sputtering gas flow rate, the capped wafer 500 is maintained within a specific temperature range, allowing the target material to gradually deposit on the surface of the silicon bonding ring 404 to form a continuous thin film. The metal interlayer 600 obtained through the above process includes a metal binder layer 601 and a metal bonding layer 602. The metal binder layer 601 is a 50 nm thick Ti metal layer, and the metal bonding layer 602 is a 2 μm thick Cu metal layer.

[0096] Step 6: Fabricate the packaging wafer 700. The substrate wafer 200 and the cap wafer 500 are interconnected under vacuum through metal interlayer bonding, and the getter 202 is activated at the bonding temperature. On a lithography machine, the substrate wafer 200 and the cap wafer 500 are aligned using the first alignment mark 206, the second alignment mark 303, and the third alignment mark 402, so that the metal interlayer 600 on the silicon bonding ring 404 structure is in close contact with the wafer bonding region 203 of the substrate wafer 200. Specifically, the metal interlayer bonding process is as follows: First, a vacuum is drawn, removing gas from the bonding cavity to a certain level and maintaining this level until bonding is complete. Second, the temperature is gradually increased in three stages to the rated temperature of 300°C and maintained for a certain period. Third, pressure is applied to the substrate wafer 200 and the cap wafer 500 to a certain pressure and maintained until bonding is complete. Fourth, the getter 202 is activated when the bonding process temperature reaches a certain level, absorbing residual active gases within the sealed cavity of the encapsulated MEMS. Fifth, annealing is performed; after the temperature reaches the rated level and is maintained for a certain period, heating is stopped, allowing the wafer to cool naturally, thus completing the bonding process. Under these process conditions, completing the Au-Au diffusion bonding process yields a vacuum-encapsulated optical MEMS wafer 700. The first bonding wafer 300, the second bonding wafer 400, and the substrate wafer 200 are connected to form a vacuum-sealed cavity 701 for the MEMS device and provide an optical path.

[0097] The seventh step is wafer dicing. The cap wafer 500 and the substrate wafer 200 in the wafer-level packaging are diced separately, that is, the packaging wafer 700 is diced to obtain independent MEMS chip units, thereby realizing the packaging of MEMS devices.

[0098] This application proposes a packaging structure that combines a glass-capped wafer 400, a silicon-capped wafer 500, and a substrate wafer 200. This design not only improves the packaging quality and strength of the MEMS device 201, but also enhances the reliability and performance stability of the packaging through the combination of multi-layer structures.

[0099] A high-precision bonding process was achieved by fabricating second alignment marks 303 and third alignment marks 402 on the glass cap wafer 400 and silicon wafer 300, respectively, and by using these alignment marks for precise alignment. This technology significantly improves the accuracy and reliability of the packaging. Simultaneously, two bonding methods (a first bonding method and a second bonding method) were employed, respectively for bonding the glass cap wafer 400 to the silicon wafer 300, and for bonding the cap wafer 500 to the substrate wafer 200. This multi-step bonding technology further enhances the strength and stability of the packaging.

[0100] Furthermore, etching processes are used to create dicing grooves and alignment marks on the glass wafer 301 and silicon wafer 300, avoiding complex machining steps in traditional packaging methods and thus simplifying the process. A metal interlayer 600 is fabricated on the silicon bonding ring using a metal thin-film deposition process, providing excellent conductivity and adhesion for the bonding process, further simplifying the packaging workflow.

[0101] Finally, by using glass wafer 301 as the sealing material, the hermeticity and vacuum retention capability of the MEMS device 201 are improved, thereby enhancing the device's performance stability. Simultaneously, the multi-layer packaging structure and precise bonding technology give it higher reliability and durability, making it suitable for various complex and harsh working environments. First and second dicing grooves are respectively set on the packaging wafer, allowing for convenient wafer dicing along these grooves after packaging to obtain independent MEMS chip units. This design improves the flexibility and production efficiency of the packaging process.

[0102] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A packaging method of a MEMS device, characterized by, include: Obtain a substrate wafer, wherein the substrate wafer is provided with MEMS devices, a wafer bonding area, a first alignment mark and a first dicing groove; Based on the MEMS device and the wafer bonding region, a second dicing groove and a second alignment mark are fabricated on the first wafer to form a first bonded wafer; Based on the wafer bonding region, a third alignment mark is fabricated on the second wafer to form a second bonded wafer; The first bonding wafer and the second bonding wafer are bonded according to the second alignment mark and the third alignment mark to form a cap wafer; Based on the wafer bonding region, a silicon bonding ring is formed in the cap wafer via; A metal interlayer is fabricated on the silicon bonding ring; The cap wafer and the substrate wafer are bonded together through the metal interlayer according to the first alignment mark and the second alignment mark to form a packaged wafer with a vacuum-sealed chamber; The packaged wafer is diced along the first dicing groove and the second dicing groove respectively to obtain MEMS chip units.

2. The packaging method of a MEMS device according to claim 1, wherein, The first wafer is a glass wafer, and the second wafer is a silicon wafer; the bonding method for bonding the first bonding wafer and the second bonding wafer according to the second alignment mark and the third alignment mark is silicon-glass anodic bonding.

3. The packaging method of a MEMS device according to claim 2, wherein, The bonding method in which the cap wafer and the substrate wafer are bonded through the metal interlayer according to the first alignment mark and the second alignment mark is metal interlayer bonding.

4. The packaging method of a MEMS device according to claim 3, wherein, The process temperature for silicon-glass anodic bonding is higher than that for metal interlayer bonding.

5. The packaging method of a MEMS device according to claim 3, wherein, The metal interlayer bonding is gold-silicon eutectic bonding, gold-gold diffusion bonding, or copper-tin solder bonding.

6. The packaging method of a MEMS device according to claim 4, wherein, The substrate wafer contains a getter, which is activated at the process temperature for bonding the metal interlayer.

7. A MEMS chip unit, characterized by The MEMS device is prepared by the packaging method according to any one of claims 1 to 6; the MEMS chip unit comprises: The substrate wafer is provided with MEMS devices, a wafer bonding area, a first alignment mark and a first dicing groove; The first wafer is provided with a second dicing groove and a second alignment mark; The second wafer is provided with through-holes, silicon bonding rings and a third alignment mark, wherein the silicon bonding rings are provided with a metal interlayer; The first wafer, the second wafer, and the substrate wafer are sequentially bonded together to form a packaged wafer with a vacuum-sealed chamber.

8. The MEMS chip unit of claim 7, wherein, The metal interlayer includes a metal bonding layer and a metal bonding layer.

9. The MEMS chip unit of claim 8, wherein, The metal bonding layer is made of one or more of Ti, Gr and Ta, and the metal bonding layer is made of one or more of Au, Cu and Sn.

10. The MEMS chip unit of claim 7, wherein, The substrate wafer contains a getter, which is a Ti metal or a Ti-based alloy thin film material.

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