Method of manufacturing a solar cell

Abstract

A method of manufacturing a solar cell is provided The method comprises: providing a substrate comprising a back surface; and arranging an interdigitated back contact structure on the back surface of the substrate. The interdigitated back contact structure comprises: a first charge-carrier collector comprising a plurality of A-elements having a first doping type; and a second charge-carrier collector interdigitated with the first charge-carrier collector, the second charge-carrier collector comprising a plurality of C-elements having a second doping type. The method further comprises: an etching step to provide a deposition mask for arranging the A-elements and / or C-elements; and screen printing an etching mask for use in the etching step.

Description

[0001] 8885261

[0002] METHODS OF MANUFACTURING A SOLAR CELL AND A SOLAR MODULE, AND A SOLAR CELL AND A SOLAR MODULE MANUFACTURED THEREBY

[0003] FIELD OF THE DISCLOSURE

[0004] The present disclosure relates to a method of manufacturing a solar cell, a method of manufacturing a solar module, and a solar cell and a solar module manufactured according to said methods.

[0005] BACKGROUND

[0006] A typical solar module for providing electrical energy from sunlight comprises an array of solar cells, each comprising a photovoltaic element, or substrate.

[0007] A general aim for solar cell development is to attain high conversion efficiency balanced by a need for reduced production costs. Efforts to achieve this have focussed on interdigitated back contact (IBC) solar cells, as they allow front contact electrodes to be omitted from the solar cell. However, known IBC solar cells often require complex manufacturing methods with several patterning and alignment steps, which result in increased production time and cost. Moreover, there is a general desire to continue increasing the efficiency of solar cells.

[0008] In spite of the effort already invested in the development of IBC solar cells, further improvements are desirable.

[0009] SUMMARY

[0010] In a first aspect there is provided a method of manufacturing a solar cell, wherein the method comprises:

[0011] providing a substrate comprising a back surface;

[0012] arranging an interdigitated back contact structure on the back surface of the substrate, the interdigitated back contact structure comprising:

[0013] a first charge-carrier collector comprising a plurality of A-elements having a first doping type; and

[0014] a second charge-carrier collector interdigitated with the first charge-carrier collector, the second charge-carrier collector comprising a plurality of C-elements having a second doping type; and

[0015] an etching step to provide a deposition mask for arranging the A-elements and / or C-elements; wherein the method further comprises screen printing an etching mask for use in the etching step.

[0016] Typically, in order to create patterned structures within IBC solar cells, lithography is used. However, lithography requires more expensive manufacturing equipment, and also demands more highly-skilled8885261

[0017] operators than other methods. Screen printing equipment is less expensive, and also is simpler to operate, meaning that fewer highly-skilled operators are required in manufacturing the present solar cell, thereby reducing capital and operational manufacturing costs.

[0018] The plurality of A-elements may be spaced apart from each other over the back surface of the substrate in a first direction, e.g. in a lengthwise or widthwise direction of the solar cell. The plurality of C-elements may also be spaced apart from each other in said first direction. It can be understood that the first charge-carrier collector and second charge-carrier collector may be interdigitated with each other by the A-elements being interdigitated with the C-elements. The interdigitated nature of the IBC structure and the A- and C-elements means that there are pairs of adjacent A- and C-elements, because the interdigitated A- and C-elements alternate in order across the back surface of the substrate (e.g. in a lengthwise or widthwise direction of the solar cell).

[0019] A portion, or all, of the deposition mask may form part of the completed solar cell. It can be understood that the deposition mask may be discontinuous (e.g. comprising apertures between elements of the deposition mask or having spaced apart elements of the deposition mask that are not contiguous with each other).

[0020] The etching mask may protect portions of underlying layers of material during the etching step and thereby result in these portions being conserved (e.g. to provide the deposition mask).

[0021] The etching mask may be a soft mask, e.g. the etching mask may comprise a polymer (for example, comprising polystyrene or polylactic acid). The soft mask may be printed from a paste comprising silicon powder. Accordingly, the soft mask may comprise silicon. This can allow the mask to be printed quickly and cheaply, and make removal of the etching mask easier. The method may further comprise removing the etching mask, e.g. by dissolution of the etching mask in isopropyl alcohol.

[0022] The step of screen printing the etching mask may be conducted at room temperature. In this way, the step of arranging the etching mask can be simplified as it does not need to be conducted in a temperature-controlled chamber.

[0023] The step of screen printing the etching mask may comprise curing the etching mask. By way of example, the curing step may involve heating the etching mask, for example, to 80°C. Curing the etch mask can increase its resistance to the etching solutions that are subsequently applied in the manufacturing process.

[0024] The first and second doping types may be different. Preferably, the first doping type may be negative, and the second doping type may be positive. Alternatively, the first doping type may be positive, and the second doping type may be negative. However, it is preferable for the second doping type to be positive, as this then reduces the number of thermal cycles that the positive doping type material goes8885261

[0025] through in the fabrication of the solar cell, because the deposition of the positive doping type semiconductor material is the last (PECVD) step in arranging the interdigitated back contact structure. This can then lead to improved solar cell performance, for example, by reducing boron tailing in the case that the positive doping type semiconductor material comprises boron dopant atoms. Where the first doping type is negative and the second doping type is positive, the first charge-carrier collector is an electron collector, and the second charge-carrier collector is a hole collector.

[0026] The positive doping type may be provided by one or more dopant elements selected from the group consisting of boron (B), gallium (Ga), and indium (In). Preferably, the positive doping type is provided by boron dopant atoms.

[0027] The negative doping type may be provided by one or more dopant elements selected from the group consisting of phosphorus (P), arsenic (As), and antimony (Sb). Preferably, the negative doping type is provided by phosphorus dopant atoms.

[0028] The substrate may be negatively doped. The substrate may define a photovoltaic element on which other layers of the solar cell are arranged (e.g., deposited). The substrate may be a crystalline substrate, for example, comprising crystalline silicon (e.g., monocrystalline, or polycrystalline silicon). According to an exemplary arrangement, the photovoltaic element defines a crystalline silicon wafer which has been cut from an ingot, as will be understood by the skilled person.

[0029] The solar cell may further comprise a back passivation layer arranged on (e.g. directly on) the back surface of the substrate. The back passivation layer may have a back surface spaced (furthest) from the back surface of the substrate. The back passivation layer may be interposed between the substrate and the A-elements. The back passivation layer may be interposed between the substrate and the C-elements. The back passivation layer may comprise amorphous semiconductor material such as amorphous silicon, e.g. intrinsic amorphous silicon, a-Si:H(i). The back passivation layer can act to reduce charge-carrier recombination at the interface between the substrate and the first charge-carrier collector. The back passivation layer may have a thickness greater than or equal to 9 nm and / or less than or equal to 12 nm.

[0030] The front portion of the solar cell may be arranged on a front surface of the substrate on the opposite side of the substrate to the back surface of the substrate. The front portion of the solar cell may comprise a front passivation layer. The front passivation layer may be an intrinsic layer. The front passivation layer may be an amorphous layer, e.g. an amorphous silicon layer or hydrogenated amorphous silicon layer. The front passivation layer can act to reduce charge-carrier recombination at the interface between the substrate and the front portion of the solar cell. The front portion of the solar cell may comprise an anti-reflective coating. The anti-reflective coating may be arranged on the front passivation layer. The anti-reflective coating may be formed of silicon nitride or a transparent conductive oxide (e.g. titanium dioxide or silicon oxide). The anti-reflective coating may reduce the reflectance of light incident8885261

[0031] on the solar cell and increases selectivity of a predetermined wavelength band, thereby increasing the efficiency of the solar cell.

[0032] The front and / or the back surface(s) of the solar cell or constituent elements / layers thereof may be textured to form a textured surface corresponding to an uneven surface (i.e. a non-planar surface). In this way, the fraction of the light incident on the solar cell that passes into the substrate (rather than reflecting off a surface of the solar cell) increases because of the textured surface of the solar cell, and thus the efficiency of the solar cell is improved.

[0033] The method may comprise a first etching step through a first etching mask (also known as a barrier layer etching mask or deposition-mask etching mask) to provide a first deposition mask for deposition of the A-elements therethrough. The method may comprise a second etching step through a second etching mask (also known as an A-element etching mask) to provide a second deposition mask for deposition of the C-elements therethrough. In this manner, the etching steps can provide patterned deposition masks that then facilitate arranging the elements of the interdigitated back contact in the first charge-carrier collector and / or the second charge-carrier collector.

[0034] The method may further comprise depositing a continuous (e.g. global or blanket) layer of deposition mask material (also known as a continuous barrier layer) on the back surface of the substrate; and arranging (e.g. screen printing) the first etching mask on the continuous layer of deposition mask material. The first etching step may then comprise etching the continuous layer of deposition mask material through the first etching mask to provide the first deposition mask. The first etching mask may comprise a plurality of apertures therethrough and a plurality of resist elements. The apertures may have a width (e.g. in the first direction, in which the A-elements are to be spaced apart) of greater than or equal to 150 micrometres and less than or equal to 3120 micrometres, for example between 300 micrometres and 320 micrometres. The width of the resist elements (e.g. in the first direction, in which the A-elements are to be spaced apart) may be greater than or equal to 250 micrometres and less than or equal to 5000 micrometres, for example, between 480 micrometres and 520 micrometres.

[0035] The first etching step may use an acidic etching solution (e.g. hydrofluoric acid). The concentration of hydrofluoric acid in the acidic etching solution may be greater than or equal to 0.45% and less than or equal to 0.55% (e.g. about 0.5 %). The pH may be greater than or equal to 1.89 and less than or equal to 1.94 (e.g. about 1.91 ) . The duration of the etching may be greater than or equal to 108 seconds and less than or equal to 132 seconds (e.g. about 2 minutes).

[0036] The first etching mask may be a soft mask, e.g. a polymer mask (for example, comprising polystyrene or polylactic acid). This can allow the mask to be printed quickly and make removal of the etching mask easier. The first etching mask may be printed (e.g. screen printed) onto the deposition mask material. Typically, in order to create patterned structures within IBC solar cells, lithography is used. However, lithography requires more expensive manufacturing equipment, and also demands more highly-skilled8885261

[0037] operators. Screen printing equipment is less expensive, and also is simpler to operate, meaning that fewer highly-skilled operators are required in manufacturing the present solar cell, thereby reducing capital and operational manufacturing costs. The method may further comprise removing the first etching mask, e.g. by dissolution of the first etching mask in isopropyl alcohol.

[0038] The continuous layer of deposition mask material may comprise an insulating material, e.g. a dielectric material, such as silicon oxide. The step of depositing the continuous layer of deposition mask material may be deposited by chemical vapour deposition (CVD) (e.g. plasma-enhanced chemical vapour deposition (PECVD)). The PECVD may be conducted with one or more conditions selected from the group consisting of: a chamber temperature of greater than or equal to 180°C and less than or equal to 220°C (e.g. about 200°C); a frequency of greater than or equal to 24.41 MHz and less than or equal to 29.83 MHz (e.g. about 27.12 MHz); a power density of greater than or equal to 1800 mW / cm2and less than or equal to 2200 mW / cm2(e.g. about 2000 mW / cm2); a chamber pressure of greater than or equal to 3.6 Torr and less than or equal to 4.4 Torr (e.g. about 4.0 Torr); an electrode gap of greater than or equal to 12.6 mm and less than or equal to 15.4 mm (e.g. about 14 mm); a hydrogen dilution of greater than or equal to 84 % and less than 100 %, (e.g. about 93.3 %); and a duration of greater than or equal to 36 seconds and less than or equal to 44 second (e.g. about 40 seconds). The PECVD may deposit silicon oxide. The PECVD deposition of silicon oxide may be conducted in two steps with a CO2 plasma treatment therebetween. The precursor gas for deposition of silicon oxide may comprise silane (SIH4) and CO2. The PECVD deposition of silicon oxide may be preceded by a CO2 plasma pre-treatment of the surface the SIOx is to be deposited on. The PECVD deposition of silicon oxide may be followed by a CO2 plasma treatment. The CO plasma pre-treatment, and / or the CO2 plasma treatment between the two steps of PECVD deposition of silicon oxide (where present), and / or the CO2 plasma treatment following PECVD deposition of silicon oxide may be conducted with one or more conditions selected from the group consisting of: a chamber temperature of greater than or equal to 180°C and less than or equal to 220°C (e.g. about 200°C); a frequency of greater than or equal to 24.41 MHz and less than or equal to 29.83 MHz (e.g. about 27.12 MHz); a power density of greater than or equal to 1800 mW / cm2and less than or equal to 2200 mW / cm2(e.g. about 2000 mW / cm2); a chamber pressure of greater than or equal to 0.54 Torr and less than or equal to 0.66 Torr (e.g. about 0.6 Torr); an electrode gap of greater than or equal to 12.6 mm and less than or equal to 15.4 mm (e.g. about 14 mm); a CO2 flowrate of greater than or equal to 315 seem and less than or equal to 385 seem, (e.g. about 350 seem); and a duration of greater than or equal to 54 seconds and less than or equal to about 66 seconds, (e.g. about 60 seconds).

[0039] The step of depositing the continuous layer of deposition mask material and the step of the CO2 plasma treatment (where present) may be preceded by deposition of an intrinsic semiconductor layer (e.g. onto the back surface of the substrate). The intrinsic semiconductor layer may be a sacrificial layer later in the manufacturing process by preventing PECVD or the CO2 plasma pre-treatment from oxidising layers underlying the intrinsic semiconductor layer. The intrinsic semiconductor layer may be deposited on the back passivation layer (i.e. may be in addition to the back passivation layer). In this way, when8885261

[0040] subsequent acidic etching is conducted, the back passivation layer is not etched because it has been protected from oxidation by the intrinsic semiconductor layer. In this way, the Voc performance of the solar cell can be conserved. In this way, the Voc performance of the solar cell can be conserved. The intrinsic semiconductor layer may have a thickness greater than or equal to 1 nm and less than or equal to 2 nm. The intrinsic semiconductor layer may be intrinsic amorphous semiconductor material (e.g. intrinsic amorphous (hydrogenated) silicon). Portions of the intrinsic semiconductor layer may be retained in the finished solar cell as a plurality of intrinsic semiconductor elements (e.g. formed of intrinsic amorphous silicon), each intrinsic semiconductor element interposed between a respective barrier element and the back surface of the substrate, e.g. interposed between a respective barrier element and the back surface of the back passivation layer. It can be understood that the intrinsic semiconductor layer is a distinct layer from the back passivation layer. Typically, the back passivation layer is deposited (e.g. using PECVD) from a precursor gas comprising silane and not comprising hydrogen gas (e.g. consisting of silane). In contrast, the sacrificial intrinsic semiconductor layer is typically deposited (e.g. using PECVD) from a precursor gas comprising silane and hydrogen gas. The material providing the intrinsic semiconductor layer may therefore comprise many large voids and a low mass density, being referred to as “underdense” e.g. underdense hydrogenated amorphous silicon. The density of the intrinsic semiconductor layer may be greater than or equal to 2.1 g cm-3and less than or equal to 2.2 g cm'3. The density of the back passivation layer may be greater than 2.2 g cm-3and less than or equal to 2.4 g cm3, e.g. about 2.3 g cm3.

[0041] The method may further comprise depositing a continuous (e.g. global or blanket) layer of first-doping-type semiconductor material through, and, optionally, over, the first deposition mask. The method may further comprise arranging (e.g. screen printing) the second etching mask on the first-doping-type semiconductor material. The first etching mask may be removed prior to depositing the first-doping-type semiconductor material, e.g. removed by dissolution in isopropyl alcohol. That is, the semiconductor material having the first doping type (first-doping-type semiconductor material) may be deposited through apertures in the first deposition mask created by the first etching step, and also over the back surface of resist elements of the first deposition mask that were protected by the first etching mask during the first etching step. The apertures in the first deposition mask may have a width (e.g. in the first direction, in which the A-elements are to be spaced apart) of greater than or equal to 150 micrometres and less than or equal to 3120 micrometres, for example between 300 micrometres and 320 micrometres. Such A-elements contribute to providing the beneficial photovoltaic performance parameters of the solar cell.

[0042] The first-doping-type semiconductor material (and thus the A-elements) may be polycrystalline semiconductor material (e.g. nanocrystalline semiconductor material or microcrystalline semiconductor material). Said first-doping-type semiconductor material may be silicon. Said nanocrystalline semiconductor material may be nanocrystalline silicon. Nanocrystalline silicon has a high conductivity that makes it suited for forming the A-elements of the first charge-carrier collector.8885261

[0043] The crystallinity of a layer / element / portion may be defined as the proportion (e.g. expressed as a fraction or percentage) of a layer / element / portion, by mass or volume, that is in the crystalline phase. In some examples, the crystallinity (i.e. crystalline fraction or percentage) of a given element may be measured using Raman spectroscopy (i.e. the crystallinity may be the Raman crystallinity). The method of measuring the crystallinity using Raman spectroscopy may comprise the method set out in C. Droz etal.: Relationship between Raman crystallinity and open-circuit voltage in micro-crystalline silicon solar cells, Solar Energy Materials & Solar Cells 81 (1), 61-71 , 2004). The Raman crystallinity, Xc, may be defined as:

[0044]

[0045] Where I480, I510, and I520are the integrated areas below a gaussian peak at 480 cm-1, 510 cm'1, and 520 cm'1, respectively. A crystalline (e.g. micro-crystalline or nano-crystalline) silicon element / layer / portion may be defined as an element with Xc> 1 %, preferably Xc> 0 %, whilst an amorphous silicon element may be defined as an element with Xc< 1 %, preferably Xc< 0 %. Referring to the “crystallinity” of a layer / element / portion does not imply that said layer / element / portion is in fact crystalline (e.g. it can be understood that such a layer may have a crystallinity of less than or equal to 1 %).

[0046] Nano-crystalline silicon may be defined as nanometre-sized silicon crystals within a matrix comprising hydrogenated amorphous silicon. Similarly, micro-crystalline silicon may be defined as micrometresized silicon crystals within a matrix comprising hydrogenated amorphous silicon. Nanometre-sized crystals may be defined as crystals having a maximum dimension greater than equal to a nanometre. Nanometre-sized crystals may be defined as crystals having a maximum dimension less than one micrometre. Micrometre-sized crystals may be defined as having a maximum dimension greater than or equal to a micrometre. Micrometre-sized crystals may be defined as having a maximum dimension less than one millimetre.

[0047] The solar cell may comprise a substantially planar structure. For example, the solar cell may comprise a length and / or a width which is substantially greater than its thickness in the depth direction. The lengthwise and widthwise directions of the solar cell may define the plane of the solar cell. The depth direction may be substantially perpendicular to the widthwise and lengthwise directions. The at least one solar cell may comprise a first (i.e., front) surface, upon which light from a radiative source (e.g., the sun) is incident during normal use, and a second (i.e., back) surface that is opposite the front surface. That is, the front surface may be configured in use to face the sun, whereas the back surface may be configured in use to face away from the sun.8885261

[0048] At least one, or each, of the solar cell’s constituent elements / layers may be configured with a width, a length, and a thickness. The width and length of each element may be measured in perpendicular directions that are parallel to the plane of the solar cell. The thickness may be measured in a direction that is substantially perpendicular to the plane of the solar cell (i.e. in the depth direction) and / or substantially perpendicular to the back surface of the substrate. At least one, or each of the elements may be configured such that its width and / or length may be substantially greater than its thickness. As an exception to the above definition, the thickness of the second semiconductor elements, which are deposited on the sides of the A-elements that themselves typically face in a direction lying substantially in the plane of the solar cell, may be measured in a direction perpendicular to the sides of the A-elements that they are deposited on (that is, typically in a direction lying substantially in the plane of the solar cell). The thickness of a layer or element or a portion / part thereof may be measured by ellipsometry (e.g. according to ISO 23131 :2021 ). The thickness of a layer or element or a portion / part thereof may be defined as the average thickness of the layer or element or a portion / part thereof across the back surface of the substrate or the minimum thickness of the layer or element or a portion / part thereof.

[0049] In exemplary arrangements in which the at least one solar cell is formed from a semiconductor wafer (e.g., a crystalline silicon wafer), the dimensions of the solar cell may substantially correspond to that of the wafer (e.g., a whole wafer silicon cell). The at least one solar cell may be formed from a wafer which is cut into a plurality of sections. For example, the substantially planar wafer may be cut along an in-plane direction (e.g., a widthwise or lengthwise direction of the wafer) to define a cut solar cell (e.g., a half-cut solar cell, where one of the length and width is roughly half as long as the other of the length and width).

[0050] The solar cell may have a substantially rectangular front and / or back surface. The solar cell may comprise four straight sides arranged at right angles to each other. At least one, or each, of the corners between the sides may be square, or pointed. Alternatively, the corners may be chamfered (or rounded), so as to define a pseudo-rectangular shape.

[0051] The first-doping-type semiconductor material (e.g. first-doping-type (nanocrystalline) silicon) may be arranged by: pre-treating a deposition surface for the first-doping-type semiconductor material (e.g. the back passivation layer and / or the first deposition mask) with a hydrogen and carbon dioxide plasma pre-treatment; and subsequently depositing the first-doping-type semiconductor material (for example, by CVD (e.g. PECVD)). The hydrogen and carbon dioxide plasma pre-treatment may use a treatment precursor gas comprising about 95% hydrogen and about 5% CO2. The plasma pre-treatment may be conducted with one or more conditions selected from the group consisting of: a chamber temperature of greater than or equal to 190°C and less than or equal to 231 °C (e.g. about 210°C); a frequency of greater than or equal to 24.41 MHz and less than or equal to 29.83 MHz (e.g. about 27.12 MHz); a power density of greater than or equal to 210 mW / cm2and less than or equal to 257 mW / cm2(e.g. about 234 mW / cm2); a chamber pressure of greater than or equal to 0.54 Torr and less than or equal8885261

[0052] to 0.66 Torr (e.g. about 0.6 Torr); an electrode gap of greater than or equal to 12.6 mm and less than or equal to 15.4 mm (e.g. about 14 mm); and a duration greater than or equal to 9 seconds and less than or equal to 11 second (e.g. about 10 seconds).

[0053] Where the first-doping-type semiconductor material (i.e. to provide the A-elements) is deposited by PECVD, the PECVD may be conducted with one or more conditions selected from the group consisting of: a chamber temperature of greater than or equal to 190°C and less than or equal to 231 °C (e.g. about 210°C); a frequency of greater than or equal to 24.41 MHz and less than or equal to 29.83 MHz (e.g. about 27.12 MHz); a power density greater than or equal to 260 mW / cm2and less than or equal to 440 mW / cm2; a chamber pressure of greater than or equal to 3.6 Torr and less than or equal to 4.4 Torr (e.g. about 4 Torr); an electrode gap of greater than or equal to 12.6 mm and less than or equal to 15.4 mm (e.g. about 14 mm); a hydrogen dilution of greater than or equal to 98 % and less than 100 % (e.g. greater than or equal to 99.5 % and less than or equal to 99.9%) ; and a duration greater than or equal to 335 seconds and less than or equal to 410 second (e.g. about 372 seconds). A precursor gas for deposition of the A-elements by PECVD may comprise hydrogen, silane (SIH4) and a dopant species (e.g. PH3); the molar percentage of silane in the precursor gas may be greater than or equal to 0.15 % and less than or equal to 0.50 %; the molar percentage of the dopant species in the precursor gas may be greater than or equal to 0.016 % and less than or equal to 0.035%. The composition of the precursor gas and / or any one or more of the PECVD conditions may be varied during the deposition of the A-elements (e.g. varied within the above ranges).

[0054] The second etching mask may comprise a plurality of resist elements. The second etching mask may comprise a plurality of apertures therethrough (e.g. spaced-apart by the resist elements). The resist elements of the second etching mask may be aligned with respective apertures in the deposition mask. In this way, the resist elements of the second etching mask can prevent etching of parts of the first-doping-type semiconductor material deposited through the deposition mask during the second etching step, because portions of the first doping type semiconductor material deposited through the first deposition mask are covered by respective resist elements of the second etching mask. The covered portions of the first-doping-type semiconductor material can then provide parts of the first charge-carrier collector (i.e. the A-elements) after the second etching step.

[0055] The second etching step may separate the first-doping-type semiconductor material into the plurality of A-elements. The second deposition mask may then be provided by the plurality of A-elements. In this way, it can be understood that a portion (or all) of the second deposition mask may form part of the finished solar cell (as the A-elements). By the second deposition mask being provided by the plurality of A-elements, which are part of the solar cell structure, it is possible to omit arranging a further layer on the back surface of the substrate to then provide the second deposition mask after being etched in the second etching step. That is, the plurality of C-elements comprised in the second charge-carrier collector can be provided by depositing the semiconductor material having the second doping type (second-doping-type semiconductor material) through the apertures between the plurality of A-8885261

[0056] elements. This provides a convenient way to arrange the A-elements and C-elements in an interdigitated manner.

[0057] The second etching step may etch the first deposition mask. By way of example, the second etching step may etch through portions of first deposition mask that are not covered by respective resist elements of the second etching mask. In this way, a portion, or all, of the first deposition mask can be removed by the second etching step to provide apertures between the A-elements in which to arrange the C-elements of the second charge-carrier collector. The first deposition mask is typically formed of a dielectric material, and accordingly removing the first deposition mask such that the C-portions can be deposited on the back surface of the substrate (e.g. on the back surface of the back passivation layer) increases the current density of charge-carriers into the C-portions during operation of the solar cell.

[0058] In some embodiments, each resist element of the second etching mask may have a width greater than a width of the respective aperture in the deposition mask. In this way, the second etching step through the second etching mask may conserve portions of the first-doping-type semiconductor material covered by the resist elements of the second etching mask to provide the plurality of A-elements, and conserve portions of the first deposition mask covered by the resist elements of the second etching mask to provide portions of the first deposition mask as barrier elements between A-elements and C-elements. The plurality of barrier elements can then act to reduce the leakage current between adjacent A-elements and C-elements, e.g. where the first deposition mask is formed of an insulating material (such as silicon oxide), because each barrier element has a lower conductivity than a respective pair of adjacent A- and C-elements that it is interposed between. This can then increase the fill factor of the solar cell. In this way, it can be understood that a portion (or all) of the first deposition mask may form part of the finished solar cell. Each resist element of the second etching mask may be aligned centrally with a respective aperture through the first deposition mask (e.g. in the first direction, in which the A-elements are to be spaced apart). Each resist element of the second etching mask may overlap a portion of the first deposition mask on each side of the respective aperture in the first deposition mask that the resist element of the second etching mask is aligned with. In this way, portions of the first deposition mask on each side of the apertures therethrough are conserved during etching through the second etching mask, thereby providing barrier elements on either side of the respective aperture through the first deposition mask. The width of the resist elements of the second etching mask may be between 240 micrometres and 4870 micrometres, for example, between 480 micrometres and 490 micrometres, and the width of the respective apertures in the first deposition mask may be between 150 micrometres and 3120 micrometres, for example, between 300 micrometres and 320 micrometres. The apertures through the second etching mask between the resist elements may have a width greater than or equal to 220 micrometres and less than or equal to 4420 micrometres, for example, between 435 micrometres and 450 micrometres.

[0059] The A-elements and / or C-elements may have a thickness greater than the barrier elements. The barrier elements may have a thickness of greater than or equal to 10 nm and less than or equal to 18 nm, e.g.8885261

[0060] about 15 nm. The width of the barrier elements (e.g. in the first direction, in which the A-elements are spaced apart) may be less than the width of the A-elements and / or the C-elements. The width of the barrier elements may be greater than 45 micrometres and less than or equal to 875 micrometres, for example greater than or equal to 80 micrometres and less than or equal to 100 micrometres.

[0061] A boundary region may be defined between each pair of adjacent A- and C-elements. Each barrier element may be interposed between a respective pair of adjacent A- and C-elements along a first part of the respective boundary region. Where the barrier element does not extend along the entire boundary region, a portion of each A-element may be positioned (e.g. deposited / grown) on an adjacent barrier element (i.e. on a back surface of the barrier element). Said portion of the A-element may have a lower crystallinity than the bulk of the A-element (which is not position on the barrier element), and thus the leakage current between the adjacent A- and C-elements along the second part of the respective boundary region may be reduced, and thus the fill factor of the cell increased. The first part of each boundary region may be positioned closer to the back surface of the substrate than the second part of the boundary region. The A-elements and C-elements may be arranged on an underlying layer (e.g. the back passivation layer, or the substrate) and the first part of the boundary region may extend from proximate the underlying layer along the boundary region in a direction away from the back surface of the substrate.

[0062] The width of the A-elements may be greater than or equal to 150 micrometres and less than or equal to 4870 micrometres, e.g. between 312 micrometres (for example, at a position between the first parts of the boundary regions on each side of an A-element, e.g. between the barrier elements on each side of an A-element) and 487 micrometres (for example, at a position between the second parts of the boundary region on each side of an A-element, e.g. between the sides of an A-element at a position where a barrier element is not present on each side of said A-element).

[0063] The width of the A-elements may be greater than or equal to 330 % of the width of one of the barrier elements and less than or equal to 560 % of the width of one of the barrier elements, for example, between 350 % (for example, at a position between the first parts of the boundary regions on each side of an A-element, e.g. between the barrier elements on each side of an A-element) and 560 % (for example, at a position between the second parts of the boundary region on each side of an A-element, e.g. between the sides of an A-element at a position where a barrier element is not present on each side of said A-element) of the width of the barrier element.

[0064] The width of the B-elements may be greater than or equal to 240 micrometres and less than or equal to 4870 micrometres, e.g. between 480 micrometres and 490 micrometres. The width of the B-elements may be greater than or equal to 530 % of the width of one of the barrier elements and less than or equal to 560% of the width of one of the barrier elements, for example, about 557 % of the width of one of the barrier elements.8885261

[0065] The width of the C-elements may be greater than or equal to 220 micrometres and less than or equal to 4420 micrometres, e.g. between 440 and 450 micrometres. The width of the C-elements may be greater than or equal to 490 % of the width of one of the barrier elements and less than or equal to 510 % of the width of one of the barrier elements, for example, about 505 % of the width of one of the barrier elements.

[0066] The first deposition mask may alternatively be referred to as a patterned barrier layer. The portions of the first deposition mask that are conserved by the etching through the second etching mask may then provide the barrier elements. In this way, it can be understood that portions of the deposition mask / patterned barrier layer are retained in the completed solar cell. Accordingly, the deposition mask may be formed from an insulating material, e.g. a dielectric material such as silicon oxide.

[0067] The second etching step may use an acidic etching solution (e.g. hydrofluoric acid). The concentration of hydrofluoric acid in the acidic etching solution may be greater than or equal to 0.45% and less than or equal to 0.55% (e.g. about 0.5 %). The pH of the acidic etching solution may be greater than or equal to 1.89 and less than or equal to 1 .94 (e.g. about 1.91 ). The duration of the etching may be greater than or equal to 9 minutes and less than or equal to 11 minutes (e.g. about 10 minutes).

[0068] The second etching mask may be a soft mask, e.g. a polymer mask (for example, comprising polystyrene or polylactic acid). This can allow the mask to be printed quickly and make removal of the etching mask easier. The second etching mask may be printed (e.g. screen printed) onto the first-doping-type semiconductor material. Typically, in order to create patterned structures within IBC solar cells, lithography is used. However, lithography requires more expensive manufacturing equipment, and also demands more highly-skilled operators. Screen printing equipment is less expensive, and also is simpler to operate, meaning that fewer highly-skilled operators are required in manufacturing the present solar cell, thereby reducing capital and operational manufacturing costs. The method may further comprise removing the second etching mask, e.g. by dissolution of the second etching mask in isopropyl alcohol.

[0069] The step of screen printing the second etching mask may be conducted at room temperature. In this way, the step of arranging the etching mask can be simplified as it does not need to be conducted in a temperature-controlled chamber. The step of screen printing the etching mask may comprise curing the etching mask. By way of example, the curing step may involve heating the etching mask, for example, to 80°C. Curing the etch mask can increase its resistance to the etching solutions that are subsequently applied in the manufacturing process.

[0070] Arranging the plurality of C-elements may comprise depositing semiconductor material having a second doping type through the second deposition mask. This provides a convenient manner in which to arrange the plurality of C-elements, as the second deposition mask results in the plurality of C-elements being spaced apart across the back surface of the substrate and interdigitated with the A-elements.8885261

[0071] The first charge-carrier collector may further comprise a plurality of B-elements arranged on respective A-elements, the B-elements comprising second-doping-type semiconductor material. It can be understood that the combination of the A-elements that have the first doping type and B-elements that have the second doping type provides a tunnel junction in the first-charge carrier collector.

[0072] Arranging the plurality of B-elements and the plurality of C-elements may comprise depositing a continuous (e.g. global or blanket) layer of second-doping-type semiconductor material through and over the second deposition mask (e.g. the A-elements). The B-elements and the C-elements may then be provided by portions of said continuous layer. That is, the continuous layer of second-doping-type semiconductor material may be deposited through apertures in the second deposition mask (i.e. apertures between the A-elements) created by the second etching step, and also over the back surface of the second deposition mask (i.e. on the back surface of the A-elements) that were protected by the second etching mask during the second etching step. In this way, the B-elements and C-elements can be arranged without an alignment step, which makes the manufacturing method faster and easier to execute, and reduce the frequency with which manufacturing defects arise.

[0073] The continuous layer of second-doping-type semiconductor material that provides the B-elements and / or the C-elements may comprise (e.g. be formed of) crystalline semiconductor material. The crystalline semiconductor material forming the B-elements and / or C-elements may be polycrystalline semiconductor material (e.g. nanocrystalline semiconductor material or microcrystalline semiconductor material). Said semiconductor material may be silicon. Said nanocrystalline semiconductor material may be nanocrystalline silicon.

[0074] The crystallinity of the A-elements may be less than the crystallinity of the B-elements and / or the C-elements. The A-elements may have a crystallinity greater than or equal to 45%. The A-elements may have a crystallinity less than or equal to 60%, e.g. greater than or equal to 45% and less than or equal to 60%. The B-elements and / or the C-elements may have a crystallinity greater than or equal to 50%. The B-elements and / or the C-elements may have a crystallinity less than or equal to 70%, e.g. greater than or equal to 50% and less than or equal to 70%. Providing the A-elements, B-elements, and / or C-elements with such crystallinities improves their conductivities, which can provide improved solar cell performance where the leakage current can be limited and / or the tunnel junction path in the first chargecarrier collector can be promoted.

[0075] The A-elements may have a thickness greater than or equal to 20 nm and less than or equal to 35 nm. The B-elements may have a thickness greater than or equal to 20 nm and less than or equal to 30 nm. The C-elements have a thickness greater than or equal to 22 nm and less than or equal to 32 nm. Such thicknesses may provide the A-, B-, and / or C-elements with the desired physical properties (e.g. conductivity, crystallinity); in particular, where such elements are crystalline, such thicknesses can allow the desired crystallinity to be provided.8885261

[0076] The B-elements and / or the C-elements may be arranged by: pre-treating a deposition surface for the B-elements and / or the C-elements (e.g. a back surface of the first semiconductor elements and / or a back surface of the third semiconductor elements, respectively) with a hydrogen plasma treatment; and subsequently depositing the B-elements and / or the C-elements (for example, by CVD (e.g. PECVD)). The hydrogen plasma treatment may be conducted with one or more conditions selected from the group consisting of: a chamber temperature of greater than or equal to 190°C and less than or equal to 231 °C (e.g. about 210°C); a frequency of greater than or equal to 24.41 MHz and less than or equal to 29.83 MHz (e.g. about 27.12 MHz); a power density of greater than or equal to 66 mW / cm2and less than or equal to 80 mW / cm2(e.g. about 73 mW / cm2; a chamber pressure of greater than or equal to 3.15 Torr and less than or equal to 3.85 Torr (e.g. about 3.5 Torr); an electrode gap of greater than or equal to 12.6 mm and less than or equal to 15.4 mm (e.g. about 14 mm); and a duration greater than or equal to 9 seconds and less than or equal to 11 second (e.g. about 10 seconds).

[0077] Where the B-elements and / or C-elements are deposited by PECVD, the PECVD may be conducted with one or more conditions selected from the group consisting of: a chamber temperature of greater than or equal to 190°C and less than or equal to 231 °C (e.g. about 210°C); a frequency of greater than or equal to 24.41 MHz and less than or equal to 29.83 MHz (e.g. about 27.12 MHz); a power density greater than or equal to 260 mW / cm2and less than or equal to 320 mW / cm2, e.g. about 289 mW / cm2; a chamber pressure of greater than or equal to 3.5 Torr and less than or equal to 6.5 Torr; an electrode gap of greater than or equal to 12.6 mm and less than or equal to 15.4 mm (e.g. about 14 mm); a hydrogen dilution of greater than or equal to 99 % and less than 100 % (e.g. greater than or equal to 99.7% and less than or equal to 99.8%); and a duration greater than or equal to 234 seconds and less than or equal to 286 second (e.g. about 260 seconds). A precursor gas for deposition of the B-elements and / or C-elements by PECVD may comprise hydrogen, silane (Si H4) and a dopant species (e.g. B2H6); the molar percentage of silane in the precursor gas may be greater than or equal to 0.18 % and less than or equal to 0.28 %; the molar percentage of the dopant species in the precursor gas may be greater than or equal to 0.003 % and less than or equal to 0.010%. The composition of the precursor gas and / or any one or more of the PECVD conditions may be varied during the deposition of the B-elements and / or C-elements (e.g. varied within the above ranges).

[0078] The interdigitated back contact structure may comprise a plurality of first (e.g. amorphous) semiconductor elements, each first semiconductor element interposed between a respective pair of an A-element and a B-element, having the second doping type, and having a lower conductivity than the A-elements and / or the B-elements. By providing the first semiconductor elements between the A-elements and the B-elements of the first charge-carrier collector, the crystallinity of the B-elements may be reduced compared to if no such first semiconductor element was present, which can increase the charge carrier current density through the tunnel junction. The interdigitated back contact structure may comprise a plurality of second (e.g. amorphous) semiconductor elements, each second semiconductor element interposed between a respective pair of adjacent A- and C-elements, having the second doping8885261

[0079] type, and having a lower conductivity than the A-elements and / or the C-elements. By providing the second semiconductor elements between the A-elements and the C-elements, and these second semiconductor elements having a lower conductivity than the A-elements and / or the C-elements, the second semiconductor elements provide a barrier to charge-carrier transport between the A-elements and C-elements (i.e. reduce the leakage current) by increasing the shunt resistance (i.e. increasing the resistance of the transport path between the A- and C-elements. Because the C-elements typically have a lower crystallinity than the A-elements and / or B-elements, and because the growth of the second semiconductor elements is on the sidewall of the A-elements, the resulting leakage current path from an A-element, through the second semiconductor element, and into the C-element (or vice versa) has a higher resistance than the equivalent path between the A-elements and B-elements.

[0080] The method may further comprise depositing a continuous layer of semiconductor material (e.g. amorphous semiconductor material) through the second deposition mask to provide the first semiconductor elements and / or the second semiconductor elements. That is, the first and second semiconductor elements may be portions of a continuous layer of (amorphous) semiconductor material. In this way, the first semiconductor elements and second semiconductor elements can be arranged within the IBC structure without an alignment step. This can make the solar cell faster and easier to manufacture and reduce the frequency with which manufacturing defects arise in certain steps. The method may comprise subsequently depositing a continuous layer of second-doping-type semiconductor material through and over the second deposition mask to provide the B-elements and / or the C-elements. That is, the B-elements and / or the C-elements may be provided by portions of said continuous layer of second-doping-type semiconductor material. In this way, the B-elements and C-elements can be arranged within the IBC structure without an alignment step. This can make the solar cell faster and easier to manufacture and reduce the frequency with which manufacturing defects arise.

[0081] In other examples, the first semiconductor elements may be arranged (e.g. formed, deposited) separately to the second semiconductor elements (e.g. as distinct elements, rather than as a continuous layer of semiconductor material and / or in separate deposition processes). Accordingly, it can be appreciated that the first semiconductor elements may be provided independently of the second semiconductor elements. In this way, the IBC structure may comprise the first semiconductor elements and may not comprise the second semiconductor elements, or vice versa. The skilled person can appreciate that there are various ways in which this could be achieved. By way of example, the material for the first and / or second semiconductor elements may be deposited through a mask, such that the there is not a continuous layer of semiconductor material. Alternatively, the material for the first and / or second semiconductor elements may be deposited, and portions thereof may subsequently be removed (e.g. by an etching process or an ablation process).

[0082] Where the solar cell comprises a plurality of second semiconductor elements, each second semiconductor element may also be positioned in the boundary region and interposed between the respective pair of adjacent A- and C-elements. Each second semiconductor element may be interposed8885261

[0083] between the respective barrier element and C-element. Each second semiconductor element may extend along the entire boundary region.

[0084] The IBC structure may further comprise a plurality of third (e.g. amorphous) semiconductor elements, each third semiconductor element interposed between a respective C-element and the back surface of the substrate and having the second doping type. Each third semiconductor elements may have a lower conductivity than the C-elements. The first semiconductor elements, second semiconductor elements and third semiconductor elements may be portions of a continuous (e.g. global or blanket) layer of semiconductor material (e.g. amorphous semiconductor material, such as amorphous silicon). In this way, the first semiconductor elements and second semiconductor elements can be arranged within the IBC structure without an alignment step and without any masking step, which then results in the third semiconductor elements also being provided. As with the first and second semiconductor elements, it can be appreciated that the third semiconductor elements may alternatively be arranged (e.g. formed, deposited) separately to the first and / or second semiconductor elements (e.g. as distinct elements, rather than as a continuous layer of semiconductor material and / or in separate deposition processes). Accordingly, it can be appreciated that the third semiconductor elements may be provided independently of the first and / or second semiconductor elements. In this way, the IBC structure may comprise the first semiconductor elements and third semiconductor elements and may not comprise the second semiconductor elements or may comprise the second semiconductor elements and third semiconductor element and may not comprise the first semiconductor elements. The back passivation layer may be interposed between the substrate and the third semiconductor elements.

[0085] The first semiconductor elements and / or the second semiconductor elements may have a thickness of greater than or equal to 1.0 nm and less than or equal to 3.5 nm. Where the first semiconductor elements are thinner, then the reduction in the leakage current they provide may be smaller than with a thicker element. Where the second semiconductor elements are thicker, then they may provide a higher resistance to the flow of charge carriers through the tunnel junction that outweighs the reduction in leakage current provided by the second semiconductor elements. Preferably, the first semiconductor elements and / or second semiconductor elements have a thickness of about 2.1 nm. The thickness of the first semiconductor elements and the thickness of the second semiconductor elements may be the same. The first semiconductor elements and / or the second semiconductor elements may have a thickness of greater than or equal to 1.0 nm, e.g. about 2.1 nm. Thefirst semiconductor elements and / or the second semiconductor elements may have a thickness of less than or equal to 3.5 nm, e.g. about 2.1 nm. The third semiconductor elements may have a thickness of greater than or equal to 1.0 nm and less than or equal to 3.5 nm. Preferably, the third semiconductor elements have a thickness of about 2.1 nm. The thickness of the third semiconductor elements may be the same as the first semiconductor elements and / or the second semiconductor elements.

[0086] The first semiconductor elements and / or the second semiconductor elements may be deposited from a precursor gas mixture. By way of example, the first and / or second semiconductor elements may be8885261

[0087] deposited by CVD (e.g. PECVD) from said precursor gas mixture. The molar concentration of a dopant species in the precursor gas mixture may be greater than or equal to 0.80 %, e.g. about 1.15 %. The molar concentration of a dopant species in the precursor gas mixture may be less than or equal to 1 .34 %, e.g. greater than or equal to 0.80 % and less than or equal to 1.34 %, e.g. about 1.15%. The dopant species may be Diborane(6) (i.e. B2H6); in this way, the first and / or second semiconductor elements may be p-type doped. The precursor gas mixture may further comprise silane (SIFU) and hydrogen (H2). The precursor gas mixture may further comprise silane (SiF ) and hydrogen (H2).. Where the first semiconductor elements and / or second semiconductor elements have a higher dopant concentration (due to deposition from a precursor gas having a higher molar concentration of dopant species) the short circuit current density of the solar cell may be reduced. Where the first semiconductor elements and / or second semiconductor elements have a lower dopant concentration (due to deposition from a precursor gas having a lower molar concentration of dopant species) the short circuit current density and / or open circuit voltage of the solar cell may be reduced. The dopant concentration in the first semiconductor elements and the dopant concentration in the second semiconductor elements may be the same. The third semiconductor elements may be deposited from a precursor gas mixture. By way of example, the third semiconductor elements may be deposited by CVD (e.g. PECVD) from said precursor gas mixture. The molar concentration of a dopant species in the precursor gas mixture may be greater than or equal to 0.80 %, e.g. about 1.15 %. The molar concentration of a dopant species in the precursor gas mixture may be less than or equal to 1.34 %, e.g. greater than or equal to 0.80 % and less than or equal to 1.34 %, e.g. about 1.15%. The dopant species may be Diborane(6) (i.e. B2H6); in this way, the third semiconductor elements may be p-type doped. The precursor gas mixture may further comprise silane (Sil- ) and hydrogen (H2). The dopant concentration in the third semiconductor elements may be the same as the first semiconductor elements and / or the second semiconductor elements.

[0088] The method may further comprise removing the second etching mask prior to depositing the continuous layer of second-doping-type semiconductor material having the second doping to provide the B-elements and / or C-elements, and, where present, prior to depositing the continuous layer of (amorphous) semiconductor material to provide the first semiconductor elements and / or the second semiconductor elements. The second etching mask may be removed by dissolution, e.g. in isopropyl alcohol.

[0089] The first, second and / or third semiconductor elements may be deposited by CVD (e.g. PECVD). The PECVD may be conducted with one or more conditions selected from the group consisting of: a chamber temperature of greater than or equal to 190°C and less than or equal to 231 °C (e.g. about 210°C); a frequency of greater than or equal to 24.41 MHz and less than or equal to 29.83 MHz (e.g. about 27.12 MHz); a power density of greater than or equal to 27.9 mW / cm2and less than or equal to 34.1 mW / cm2(e.g. about 31 mW / cm2); a chamber pressure of greater than or equal to 0.54 Torr and less than or equal to 0.66 Torr (e.g. about 0.6 Torr); an electrode gap of greater than or equal to 18.98885261

[0090] mm and less than or equal to 23.1 mm (e.g. about 21 mm); a hydrogen dilution of greater than or equal to 64.3 % and less than or equal to 78.5 % (e.g. about 71.4 %); and a duration of greater than or equal to 5.4 seconds and less than or equal to 6.6 seconds (e.g. about 6 seconds). Using these conditions, first, second and / or third semiconductor elements having a lower conductivity than the A-elements, B-elements and / or C-elements can be provided, thereby improving solar cell performance by increasing fill factor. The hydrogen dilution may be defined as the % molar concentration of hydrogen in a precursor gas mixture used in the PECVD. The power density may be defined as the excitation power provided to the PECVD process divided by the surface area of deposition. The electrode gap may be defined as the distance between two electrodes in the PECVD chamber used for generating plasma by applying a voltage therebetween.

[0091] The solar cell may further comprise a plurality of first transparent conductive oxide (TCO) elements arranged on the first charge carrier collector (e.g. a respective first TCO element arranged on each B-element). The solar cell may further comprise a plurality of second TCO elements arranged on the second charge carrier collector. The first TCO elements and / or second TCO elements may be formed from indium tin oxide (ITO), tin (IV) oxide (SnO2), fluorine-doped tin (IV) oxide (FTO), zinc oxide (ZnO) or tin (II) oxide (SnO). The TCO element(s) may be configured to increase lateral carrier transport to the electrode arranged on the respective surface of the layered structure.

[0092] Where the solar cell comprises a plurality of first TCO elements or second TCO elements, the method may comprise arranging the plurality of first TCO elements and / or arranging the plurality of second TCO elements. In some examples, the first TCO elements may be deposited through a mask, e.g. such that the first TCO elements are only positioned on the B-elements. Each first TCO elements may be separated from adjacent second TCO elements by an isolation region (i.e. such that adjacent TCO elements are not in direct ohmic contact). In some examples, the second TCO elements may be deposited through a mask, e.g. such that the second TCO elements are only positioned on the C-elements. In other examples, a continuous TCO layer may be deposited over the B-elements and C-elements and subsequently separated into first TCO elements and second TCO elements (e.g. with a laser ablation step or an etching step).

[0093] The solar cell may further comprise a plurality of first electrodes arranged on the first charge-carrier collector, for example, first electrodes may be arranged on respective first TCO elements. The solar cell may further comprise a plurality of second electrodes arranged on the second charge-carrier collector, for example, second electrodes may be arranged on respective second TCO elements. The first electrodes and / or second electrodes may be metal electrodes (e.g. electrodes comprising silver, copper, or an alloy thereof).

[0094] The first electrodes and / or the second electrodes may be finger electrodes. Each finger electrode may be configured with a length which is substantially greater than its width. Both the width and length of the finger electrode may be measured in a plane parallel to the plane of the solar cell, but in8885261

[0095] perpendicular directions to each other. The length dimension of the electrodes may extend in a direction which is parallel with the widthwise direction of the solar cell. The first electrodes may be spaced apart across the back surfaces of the first TCO elements to define spaces between the first electrodes that extend in the lengthwise direction of the solar cell. Alternatively, the first electrodes may extend in a longitudinal direction which is parallel with the lengthwise direction of the solar cell. The first electrodes arranged on first TCO elements may be spaced apart across a back surfaces of the first TCO elements to define spaces between the electrodes that extend in the widthwise direction of the solar cell. The second finger electrodes may be equivalently configured with respect to, and are hereby restated in respect of, the second charge-carrier collector and second TCO elements.

[0096] Where the solar cell comprises a plurality of first electrodes or second electrodes, the method may comprise arranging the plurality of first electrodes and / or arranging the plurality of second electrodes. The step of arranging the first electrodes and / or second electrodes may comprise a printing step (e.g. a screen-printing step). The first electrodes and second electrodes may be arranged as part of the same deposition process, such that the number of separate deposition steps in the manufacturing process is reduced.

[0097] In a second aspect, there is provided a method of manufacturing a solar module, the method comprising arranging one or more solar cells according to the first aspect in a housing.

[0098] Any one of more of the optional features set out with respect to the first aspect is equally applicable to the second aspect, except where such a combination is expressly avoided or is clearly impermissible.

[0099] A solar module (e.g., a solar panel) may define an apparatus for generating electrical power from sunlight. The solar module may comprise at least one solar cell which is arranged (e.g., housed, or supported) by a structural frame, or housing. The at least one solar cell may be configured to absorb sunlight and generate electrical current.

[0100] The at least one solar cell may be configured with an electrical connector which enables electrical current to be extracted from the solar cell (e.g., to an electrical circuit of the solar module). The at least one solar cell and the electrical connector, when connected together, may define a solar cell assembly.

[0101] Two or more solar cells may be electrically connected in series (e.g., by one or more electrical connectors) to form a solar cell string. The solar module may comprise two or more solar cell strings, which may be electrically connected together in series and / or in parallel.

[0102] The solar module may comprise electrical circuitry which may be configured to extract electrical current from the solar panel to an external circuit (e.g., a second solar module).8885261

[0103] The solar module housing (e.g. a structural frame, or support) may comprise a front plate and a back plate which are arranged, respectively, on the front and back sides of the plurality of solar cells. At least one or each of the front and back plates may be formed of glass (e.g., a glass sheet).

[0104] The solar module may comprise an encapsulant which may be configured to provide adhesion between the front and back plates and the plurality of solar cells. In this way, the encapsulant may be arranged between the glass sheet of the solar module housing, and the at least one solar cell. The encapsulant may be configured to prevent the ingress of moisture into the solar module housing. For example, the encapsulant may be formed of ethylene vinyl acetate (EVA), or any other suitably moisture resistant material.

[0105] In a third aspect, there is provided a solar cell manufactured according to the method of the first aspect.

[0106] Any one of more of the optional features set out with respect to the first aspect and / or second aspect is equally applicable to the third aspect, except where such a combination is expressly avoided oris clearly impermissible.

[0107] In a fourth aspect, there is provided a solar module manufactured according to the method of the second aspect.

[0108] Any one of more of the optional features set out with respect to the first aspect, second aspect and / or third aspect is equally applicable to the fourth aspect, except where such a combination is expressly avoided or is clearly impermissible.

[0109] The term “continuous layer” may mean that the plurality of elements that make up that layer are not arranged by separate deposition processes but rather a single deposition process where the elements are grown / deposited simultaneously. The “continuous layer” may alternatively be referred to as a “global layer” or “blanket layer”. This can simplify the steps of arranging the elements, as no patterned deposition or alignment steps are required for depositing such layers.

[0110] It will be understood that the terms ‘conductive’ and ‘insulating’ as used herein, are expressly intended to mean electrically conductive and electrically insulating, respectively. The meaning of these terms will be particularly apparent in view of the technical context of the disclosure, being that of photovoltaic solar cell devices. It will also be understood that the term ‘ohmic contact’ is intended to mean a non-rectifying electrical junction (i.e., a junction between two conductors which exhibits a substantially linear currentvoltage (l-V) characteristic).

[0111] The preceding summary is provided for purposes of summarising some examples to provide a basic understanding of aspects of the subject matter described herein. Accordingly, the above-described features should not be construed to narrow the scope or spirit of the subject matter described herein in8885261

[0112] any way. Moreover, the above and / or proceeding examples may be combined in any suitable combination to provide further examples, except where such a combination is clearly impermissible or expressly avoided. Other features, aspects, and advantages of the subject matter described herein will become apparent from the following text and the accompanying drawings.

[0113] BRIEF DESCRIPTION OF THE DRAWINGS

[0114] Aspects, features, and advantages of the present disclosure will now be described by way of example only, with reference to the appended drawings in which like numerals denote like elements.

[0115] Figs. 1 A and 1 B are schematic plan views of a solar module including a plurality of solar cells, wherein Fig. 1A is a front view and Fig. 1B is a back view;

[0116] Fig. 2A is a schematic cross-sectional side view of an interdigitated back contact solar cell according to the first aspect;

[0117] Fig. 2B is a schematic plan view of the back side of the solar cell in Fig. 2A;

[0118] Figs. 3A - 3M are schematic sectional side views of different stages of manufacturing the solar cell of Figs. 2A and 2B;

[0119] Fig. 4 is a flow chart for a method of manufacturing a solar cell according to the first aspect.

[0120] Fig. 5 is a flow chart for a step in the method of manufacturing a solar cell according to the first aspect.

[0121] DETAILED DESCRIPTION

[0122] Aspects and embodiments of the present disclosure will now be discussed with reference to the accompanying figures. Further aspects and embodiments will be apparent to those skilled in the art.

[0123] Figs. 1A and 1 B show a solar module 100 (e.g. solar panel) according to the present disclosure. The solar module 100 includes a plurality of solar cells (including a first solar cell 10 and a second solar cell 10) which are arranged within a housing 102 (e.g., a structural frame, or support) of the solar module 100, as will be described in more detail below. The solar cells are sandwiched between a front plate 104 and a back plate 108 of the solar module housing 102.

[0124] The solar module 100 includes electrical circuitry (e.g. an electrical assembly) to enable electrical power to be extracted from the solar cells 10 arranged inside the module housing 102. The electrical circuitry includes a pair of electrical connectors 112 (as shown in Fig. 1 b) which couple the module 100 to an external circuit (e.g., two adjacent solar modules 100). The external connector 112 is connected, at one8885261

[0125] end, to a junction box 110 which is arranged on the back side of the solar module 100 (e.g. mounted to the back plate 108). At least one further connector provides an electrical connection between the junction box 110 and the solar cells which are arranged within the module 100 (e.g. an internal connector). The electrical circuity may include at least one diode (e.g., bypass diodes) which regulates the flow of charge between the solar cells 10 and / or between the solar module 100 and the external electrical circuit. The electrical circuitry components can be arranged within the junction box 110 and / or within the module housing 102 itself. It will be appreciated that the solar module 100 may comprise a plurality of connectors and / or junction boxes 110 as appropriate.

[0126] The solar module 100 has a length which is the horizontal dimension of Figs. 1 Aand 1 B, a width which is the vertical direction of Figs. 1 A and 1 B, and a thickness which is substantially into the page of Figs.

[0127] 1A, and 1B.

[0128] According to the exemplary arrangement shown in Fig. 1A, the solar module 100 includes ninety-six solar cells 10 arranged in a rectangular array comprising six rows and sixteen columns (arranged horizontally and vertically, in Fig. 1A, respectively). It will be appreciated that the solar module 100 may be configured with any numberof solar cells 10 (e.g., arranged in different array shapes, and comprising different numbers of columns and rows), without departing from the scope of the present disclosure. At least some of the solar cells 10 are electrically coupled together (e.g., in series) to form a solar cell string. The solar module 100 includes a plurality of solar cell strings. At least some of the strings are electrically coupled together in series. Two or more of the strings may be coupled together in parallel. Different strings may be connected together using one or more cross-connectors which are mounted within the solar module housing 102.

[0129] The front plate 104 of the module housing 102 comprises a transparent (e.g. glass) sheet which is configured to allow light to pass through into a central chamber in which the solar cells 100 are mounted. The back plate 108 is arranged to enclose the solar cells 10 within the central chamber. The back plate 108 comprises a reflective sheet which reflects any light incident upon its front surface (i.e., front facing surface) back towards the solar cells 10. The central chamber is filled with an encapsulating material which prevents ingress of fluid (e.g. gas and / or liquid) which could degrade the solar module’s performance.

[0130] Fig. 2A is a schematic sectional side view of a solar cell 10 according to the first aspect. The solar cell 10 comprises a substrate 1 comprising a front surface 1a upon which light from a radiative source (e.g. the sun) is incident during normal use, and a back surface 1 b that is opposite the front surface 1a. That is, the front surface 1a may be configured in use to face the sun, whereas the back surface 1b may be configured in use to face away from the sun.

[0131] The substrate 1 comprises crystalline n-type doped silicon (c-Si(n)). The substrate 1 divides the solar cell 10 into a front portion that is forward (i.e. in front of) of the substrate 1 , and a rear portion that is8885261

[0132] rearward of the substrate 1. Light incident on the solar cell 10 passes through the front portion, the substrate 1 and then the rear portion.

[0133] Each of the front and rear portions comprises a plurality of layers. The front portion is arranged on the front surface 1a of the substrate 1 and the rear portion is arranged on the back surface 1b of the substrate 1. The constituent layers of the front and rear portions are sequentially arranged (e.g. deposited) onto the respective front and back surfaces 1a, 1 b of the substrate 1.

[0134] Each of the layers of the front and rear portions are configured with a width, a length and a thickness. The solar cell 10 comprises a substantially planar structure, with the width in the widthwise direction (W) and length in the lengthwise direction (L) of the solar cell 10 being substantially greater than its thickness in the depth direction (D), such that the width and length dimensions define the plane of the solar cell 10. The width and length of each layer are measured in perpendicular directions that lie parallel to the plane of the solar cell 10. For each layer, its width and length are substantially greater than its thickness, which is measured in a direction that is substantially perpendicular to the plane of the solar cell 10 (i.e. vertically in the orientation of the solar cell 10 in Fig. 2A) and / or substantially perpendicular to the back surface 1 b of the substrate 1.

[0135] In the rear portion, the solar cell 10 comprises an electron collector and a hole collector. The electron collector comprises a plurality of A-elements 4 that have a negative doping type arranged on the back surface 1 b of the substrate 1 , and a plurality of B-elements 6a arranged on the A-elements 4 (i.e. with the A-elements 4 interposed between the substrate 1 and the B-elements 6a). The A-elements 4 are spaced apart from each other in the lengthwise direction L of the solar cell 10 to provide gaps therebetween. The hole collector comprises a plurality of C-portions 6b arranged on the back surface 1b of the substrate 1 and interdigitated with the plurality of A-elements (i.e. positioned in the gaps between A-elements 4) such that they alternate in the lengthwise direction L of the solar cell 10.

[0136] The B-elements 6a and C-elements 6b are portions of a continuous layer of p-type nanocrystalline silicon (nc-Si(p)) 6 (with a crystallinity between 50% and 70%), with that layer only divided up into the B-elements 6a and C-elements 6b based on where an A-element 4 is interposed between the layer 6 and the back surface 1b of the substrate 1 (i.e. in the depth direction D of the solar cell 10). The A-elements 4 are formed of n-type nanocrystalline silicon (nc-Si(n)) (with a crystallinity between 45% and 60%) and together with the B-elements 6a form a tunnel junction contact for collecting the electrons of the electron-hole pairs generated in the solar cell 10 by the absorption of light.

[0137] The solar cell 10 further comprises a back passivation layer 2 interposed between the substrate 1 and the A-elements 4 and also interposed between the substrate 1 and the C-elements 5b. The back passivation layer 2 comprises intrinsic amorphous silicon (a-Si:H(i)) and acts to passivate the back surface 1 b of the substrate 1 in order to reduce charge-carrier trapping and recombination at the back surface 1b.8885261

[0138] The IBC structure further comprises a continuous layer of amorphous p-type doped silicon (a-Si(p)) 5 that is arranged between the continuous layer of nc-Si(p) 6 and both the A-elements 4 and back passivation layer 2 (in the gaps between the A-elements 4). The continuous a-Si(p) layer 5 can be conceptually divided up into a plurality of first amorphous semiconductor elements 5a that are each interposed between a respective pair of an A-element 4 and a B-element 6a, a plurality of second amorphous semiconductor elements 5b that are each interposed between a respective pair of an A-element and an adjacent C-element, and a plurality of third amorphous semiconductor elements 5c that are each interposed between a respective C-element 6b and the back surface 1b of the substrate 1. The continuous layer of a-Si(p) 5, being amorphous, has a lower conductivity than the nc-Si(n) A-elements 3.

[0139] By providing the first amorphous semiconductor elements 5a between the A-elements 4 and the B-elements 6a in the electron collector, the crystallinity of the B-elements 6a, which are grown on the first amorphous semiconductor elements 5a, is reduced compared to if no such first amorphous semiconductor element 5a was present and the B-element 6a was instead grown directly on the A-elements 4. This can increase the charge carrier current density through the tunnel junction that is present in the electron collector.

[0140] By providing the second amorphous semiconductor elements 5b between the A-elements 4 and the C-elements 6b, with the second amorphous semiconductor elements 5b having a lower conductivity than the A-elements 4 and C-elements 6b, the second amorphous semiconductor elements 5b can act as a barrier to charge-carrier transport between the A-elements 4 and the C-elements 6b (i.e. reduce the leakage current in the IBC structure) by increasing the shunt resistance. This increase in shunt resistance then increases the fill factor of the solar cell 10.

[0141] In order to further increase the shunt resistance of the solar cell 10, the IBC structure further comprises a plurality of barrier elements 3, each barrier element 3 interposed between a respective pair of adjacent A- and C-elements 4, 6b. Specifically, the barrier elements 3 are formed of silicon oxide, and because the barrier elements are insulating, they have a lower conductivity than the A-elements 4, the C-elements 6b and the second amorphous semiconductor elements 5b.

[0142] A boundary region is defined between each pair of adjacent A- and C-elements. As can be seen in Fig.

[0143] 2A, each barrier element 3 is interposed between a respective pair of adjacent A- and C-elements along a first part of the boundary region closest to the back surface 1 b of the substrate, whilst in a second part of the boundary region spaced further from the substrate 1 than the first boundary region, there is no barrier element 3 present. Each second amorphous semiconductor element 5b is also interposed between the respective pair of adjacent A- and C-elements in the boundary region, but in contrast to the barrier element 3, each second amorphous semiconductor element 5b extends along the entire boundary region of a respective pair of A- and C-elements.8885261

[0144] The solar cell further comprises a plurality of intrinsic amorphous silicon elements 14, each intrinsic semiconductor element 14 interposed between a respective barrier element 3 and the back surface 2b of the back passivation layer 2. The intrinsic semiconductor elements 14 are the remnants of an intrinsic semiconductor layer deposited during manufacture, and are discussed further below with reference to Figs. 3A - 3M.

[0145] The solar cell 10 further comprises plurality of first TCO elements 7a arranged on the electron collector (e.g. on respective B-elements 6a) and a plurality of second TCO elements 7b arranged on the hole collector (e.g. on respective C-elements 6b). The TCO elements 7a, 7b are typically formed of one or more layers of indium tin oxide and / or tin oxide. Arranged on each first TCO element 7a and second TCO element 7b are a first electrode 8a and a second electrode 8b, respectively. The TCO elements 7a, 7b may be configured to increase lateral carrier transport to the electrodes 8a, 8b arranged on the respective TCO elements 7a, 7b. The first and second electrodes 8a, 8b are then used to extract electrons and holes, respectively, from the solar cell 10. Typically, the electrodes 8a, 8b are formed of silver, copper or an alloy thereof. Each B-element 6a has a respective first electrode 8a arranged thereon, with a respective first TCO element 7a interposed therebetween. Similarly, each C-element 6b has a respective second electrode 8b arranged thereon, with a respective second TCO element 7b interposed therebetween.

[0146] Although not illustrated in Fig. 2A, one or more of the layers of the solar cell 10 may have textured front and / or back surfaces in order to provide the surfaces of that layer with anti-reflective properties.

[0147] Figure 2B further illustrates the structure of the IBC solar cell 10. Figure 2B is a schematic of the back side of the solar cell 10 of Fig. 2A. Fig. 2B includes the line A - A that is the section along which the cross-section in Fig. 2A is taken. The electron collector comprises a plurality of A-elements 4 (not visible in Fig. 2B) spaced apart from each other in the lengthwise direction of the solar cell 10, with respective B-elements 6b arranged thereon, and the A-elements 4 and B-elements 6b each extend along the widthwise direction of the solar cell 10. The hole collector comprises a plurality of C-elements 6b spaced apart from each other in the lengthwise direction of the solar cell 10, with an A-element 4 and B-element 6a interposed between each adjacent pair of spaced apart C-elements 6b in the lengthwise direction of the solar cell 10. The first and second electrodes 8a, 8b are then arranged on first and second TCO elements 7a, 7b, respectively, the first and second TCO elements 7a, 7b being arranged on the B-elements 6a and C-elements 6b, respectively. Each electrode 8a, 8b extends along a respective B-element 6a or C-element 6b, with an elongate dimension of the electrodes 8a, 8b extending in the widthwise direction of the solar cell 10.

[0148] Returning to Fig. 2A, the front portion of the solar cell 10 comprises a front passivation layer 9 and an anti-reflective coating 11. The front passivation layer 9 comprises intrinsic amorphous silicon a-Si:H(i) and acts to passivate the front surface 1a of the substrate 1 in order to reduce charge-carrier trapping8885261

[0149] and recombination at this surface. The anti-reflective coating 11 acts to reduce the reflection of light from the front surface of the solar cell 10.

[0150] The structure of the solar cell 10 in Figs. 2A and 2B is discussed further with reference to Figs. 3A -3M, which illustrate steps within a method of manufacturing the solar cell 10, and Figs. 4 and 5, which provides flow charts for the manufacturing method.

[0151] Fig. 3A illustrates the first steps of manufacturing the IBC solar cell illustrated in Figs. 2A and 2B, corresponding to steps S100 and S200 in Fig. 4. At step S100, the substrate 1 is provided, for example, by cutting a crystalline silicon wafer from an ingot of n-type doped silicon and subsequently at step S200, the back passivation layer 2 is deposited on the back surface 1b of the substrate 1. The back passivation layer 2 is deposited as a continuous (i.e. blanket or global) layer on the back surface 1b of the substrate such that no patterning of the back passivation layer 2 is provided. Step S200 can be conducted by a PECVD process.

[0152] Subsequently at step S300 in Fig. 4, a patterned barrier layer 3’ is arranged on the back surface 1 b of the substrate 1 , the patterned barrier layer 3’ comprising a plurality of apertures therethrough. The patterned barrier layer 3’ is formed of silicon oxide (SIOx), which is an insulating and dielectric material. The patterned barrier layer 3’ is illustrated in Fig. 3D. The flowchart in Fig. 5 and Figs. 3B and 3C illustrate one way in which to arrange the patterned barrier layer 3’.

[0153] At step S310 in Fig. 5, the back surface 2b of the back passivation layer 2 is prepared for deposition of the silicon oxide material by depositing the intrinsic semiconductor layer 14’ that acts as a sacrificial layer later in the manufacturing process. The intrinsic semiconductor layer 14’ has a thickness of between 1 nm and 2 nm and is typically formed of intrinsic hydrogenated amorphous silicon.

[0154] At step S320, a continuous barrier layer 3” is deposited on the back surface 1 b of the substrate 1 , with the back passivation layer 2 interposed between the substrate 1 and the continuous barrier layer 3”. The continuous barrier layer 3” is deposited directly onto the intrinsic semiconductor layer 14. This is illustrated in Fig. 3B. The silicon oxide forming the continuous barrier layer 3” can be deposited using a PECVD process. The continuous barrier layer 3” has a thickness of between 10 nm and 20 nm. The PECVD process for SIOx commences with a CO2 plasma pre-treatment of the surface the SIOx is to be deposited on, followed by deposition using a precursor gas comprising silane (SiFU) and CO2. The CO2 plasma treatment causes oxidation of the first few layers of the intrinsic semiconductor layer 14 that is deposited at step S310, this layer protecting the underlying back passivation layer 2 from oxidation. Table 1 sets out deposition process conditions for the continuous barrier layer 3”, with step 1 corresponding to the CO2 plasma treatment; the process was carried out in a deposition chamber having a volume of 2870 cm3.

[0155] Table 18885261

[0156]

[0157] At step S330, a soft etching mask 12 is screen printed onto the continuous barrier layer 3”. The etching mask 12 comprises a plurality of resist elements with apertures provided through the etching mask 12 between the resist elements, as illustrated in Fig. 3C. The etching mask 12 is formed of a polymer such as polystyrene.

[0158] Subsequently, at step S340 a first etching step is conducted through the etching mask 12 to etch portions of the continuous barrier layer 3” exposed through the etching mask 12 at the apertures therethrough. The first etching step is an acidic etching using hydrofluoric acid with a concentration of about 0.5%. An etching time of around 2 minutes is used in order to etch through the continuous barrier layer 3” and the intrinsic semiconductor layer 14’ and expose the back passivation layer 2 between the resist elements of the etching mask 12. Because the intrinsic semiconductor layer 14 is oxidised by the CO2 plasma pre-treatment when depositing the continuous barrier layer 3”, this oxidised layer is readily removed during the acidic first etching step at step S330. In this way, the intrinsic semiconductor layer 14 acts as a sacrificial layer that is removed during the etching where portions of the continuous barrier layer 3” are also removed, and the back passivation layer 2 is not etched during the first etching step. Having conducted the first etching step, at step S350 the etching mask 12 is removed by dissolution in isopropyl alcohol, thereby providing the structure illustrated in Fig. 3D.

[0159] As a result of the etching step at S340, the continuous barrier layer 3” is formed into the patterned barrier layer 3’, with a plurality of apertures therethrough exposing the back passivation layer 2.

[0160] Returning to Fig. 4, the method continues with step S400, where a continuous layer of n-type nanocrystalline silicon (nc-Si(n)) 4’ is deposited both over the back surface of the patterned barrier layer 3’ and through the patterned barrier layer 3’ at the apertures. The resulting structure is illustrated in Fig.

[0161] 3E. It can be appreciated that the patterned barrier layer 3’ acts as a deposition mask for the continuous layer of nc-Si(n) 4’. Because the nc-Si(n) 4’ has a greater thickness (about 27 nm) than the patterned barrier layer 3’ (about 15 nm), the nc-Si(n) 4’ completely covers the patterned barrier layer 3’. The nc-Si(n) layer 4’ is deposited by PECVD, Table 2 sets out deposition process conditions for the continuous nc-Si(n) layer 4’. Step 1 represents a hydrogen and CO2 plasma pre-treatment that is conducted prior8885261

[0162] to starting to deposit the nc-Si(n) layer 4’. The process was carried out in a deposition chamber having a volume of 2870 cm3.

[0163] Table 2

[0164]

[0165] At step S500, a second soft etching mask 13 is screen printed, this time onto the continuous layer of nc-Si(n) 4’. As with the first etching mask 12. The second etching mask 13 also comprises a plurality of resist elements with apertures provided through the second etching mask 13 between the resist elements, as illustrated in Fig. 3F. The etching mask 13 is formed of a polymer such as polystyrene. Figure 3F illustrates how the resist elements of the second etching mask 13 are aligned with the apertures through the patterned barrier layer 3’ such that each resist element is aligned centrally with a respective aperture through the patterned barrier layer 3’ in the lengthwise direction of the solar cell 10. The resist elements also each have a width (in the lengthwise direction of the solar cell 10) that is greater than the width of the respective aperture through the patterned barrier layer 3’ - typically, the width of the resist elements is about 490 micrometres, whilst the width of the apertures through the patterned barrier layer are about 310 micrometres. As a result, portions of the patterned barrier layer 3’ on each side of each of the apertures therethrough are covered by parts of the resist elements of the second etching mask 13. However, the majority of each of the elements of the patterned barrier layer 3’ and the overlying portions of the nc-Si(n) layer 4’ are exposed through the apertures in the second etching mask 13 - the width of the elements of the patterned barrier layer are typically about 500 micrometres, whilst the width of the apertures in the second etching mask 13 are typically about 440 micrometres.

[0166] Then, at step S600 in Fig. 4, a second etching step is conducted through the second etching mask 13 to etch portions of the continuous nc-Si(n) layer 4’ and portions of the patterned barrier layer 3’ exposed through the second etching mask 13 at the apertures therethrough. The second etching step is an acidic8885261

[0167] etching using hydrofluoric acid with a concentration of about 0.5%. An etching time of around 10 minutes is used in order to etch through nc-Si(n) layer 4’ and the patterned barrier layer 3’ and expose the back passivation layer 2 between the resist elements of the second etching mask 13. The resulting structure is illustrated in Fig. 3G. As can be seen, portions of the continuous nc-Si(n) layer 4’ that were deposited through the apertures in the patterned barrier layer 3’, which were then covered by the second etching mask 13, have been retained as the A-elements 4 of the solar cell 10, the A-elements 4 spaced apart from each other on the back surface 2b of the back passivation layer 2 in the lengthwise direction of the solar cell 10. Additionally, as a result of the width of the resist elements of the second etching mask 13 being wider than the apertures through the patterned barrier layer 3’, portions of the patterned barrier layer 3’ have been conserved to provide a barrier element 3 on each side of each A-element in the lengthwise direction of the solar cell 10. It can be appreciated that not only does the patterned barrier layer 3’ act as a deposition mask used in forming the A-elements, but also parts of the patterned barrier layer 3’ are retained in the complete solar cell 10 as the barrier elements 3. Portions of the very thin intrinsic semiconductor layer 14 have also been conserved between the barrier elements 3 and the back passivation layer 2. The second etching mask 13 is then removed by dissolution in isopropyl alcohol, thereby providing the structure illustrated in Fig. 3H.

[0168] Having arranged the A-elements 4 and barrier elements 3 of the solar cell 10, at step S700 the first, second and third amorphous semiconductor elements 5a, 5b, 5c of the solar cell 10 are then arranged by depositing a continuous layer of p-type amorphous silicon (a-Si(p)) 5 over the back surface of the solar cell such that the A-elements 4 and the portions of the back surface 2b of the back passivation layer 2 exposed between the A-elements are covered by the a-Si(p) layer 5. As illustrated in Fig. 3I The first amorphous semiconductor elements 5a are provided by the portions of the a-Si(p) layer 5 on the back surfaces of the A-elements 4 (such that they will eventually each be interposed between a respective pair of an A-element 4 and B-element 6a), the second amorphous semiconductor elements 5b are provided by the portions of the a-Si(p) layer 5 on the sides of the A-elements and the barrier elements 3 (such that they will eventually each be interposed between a respective pair of an A-element 4 and an adjacent C-element 6b), and the third amorphous semiconductor elements 5c are provided by the portions of the a-Si(p) layer 5 on the back surface 2b of the back passivation layer (such that they will eventually each be interposed between a respective C-element and the back surface 1b of the substrate 1). The a-Si(p) layer 5 is also deposited by PECVD, and this is conducted such that the a-Si(p) layer 5 has a thickness of about 2.1 nm and is deposited from a precursor gas having a molar concentration of B2H6 of 1.15%. Typically, the dopant atoms used to provide the positive conductivity type in the a-Si(p) layer 5 are boron atoms. Table 3 sets out PECVD process conditions for the a-Si(p) layer 5; the process was carried out in a deposition chamber having a volume of 2870 cm3.

[0169] Table 3

[0170]

[0171] 8885261

[0172]

[0173] Although Fig. 3I illustrates the first, second and third semiconductor elements 5a, 5b, 5c being deposited as a single continuous layer, it can be appreciated that the first, second and third semiconductor elements 5a, 5b, 5c may be provided separately of each other (e.g. by using a mask that results in the p-type amorphous silicon (a-Si(p)) 5 being deposited in a patterned manner). Accordingly, in other embodiments, the first semiconductor elements 5a or the second semiconductor elements 5b may be omitted, and the third semiconductor elements 5c may or may not be present within the IBC structure.

[0174] Subsequently, at step S800 the B-elements 6a and C-elements 6b of the solar cell are arranged by depositing a continuous layer of p-type nanocrystalline silicon (nc-Si(p)) 6 on the back of the a-Si(p) layer 5, with the B-elements 6a and C-elements 6b being portions of the continuous nc-Si(p) layer 6, as shown in Fig. 3J. Specifically, each B-element 6a is arranged on a respective A-element 4 (i.e. such that the A-element 4 is interposed between the B-element 6a and the substrate 1 ) and the C-elements 6b are interdigitated with the A-elements 4. In this way, the B-elements 6a and C-elements 6b can be provided without a patterned deposition step. As with the nc-Si(n) A-elements 4, the nc-Si(p) layer 6 is deposited by PECVD, with the PECVD process comprising pre-treating the a-Si(p) layer 5 with a hydrogen plasma treatment and subsequently depositing the nc-Si(n) layer from a precursor gas comprising hydrogen, SiF and dopant atoms. Together, the A-elements 4, the first amorphous semiconductor elements 5a, and the B-elements 6a form the tunnel-junction electron collector of the solar cell 10, whilst the third amorphous semiconductor elements 5c and the C-elements 6b provide the hole collector of the solar cell 10. Table 4 sets out PECVD process conditions for the continuous nc-Si(p) layer 6. Step 1 corresponds to the hydrogen plasma pre-treatment.

[0175] Table 4

[0176]

[0177] At step S900 in Fig. 4, the plurality of first TCO elements 7a are arranged on respective B-elements 6a and second TCO elements 7b are arranged on respective C-elements 6b, as illustrated in Fig. 3K.8885261

[0178] Step S900 may be conducted by depositing the first TCO elements 7a and second TCO elements 7b through one or more masks, such that the TCO elements 7a, 7b are separated from each other, or a continuous TCO layer may be deposited over the nc-Si(n) layer 6 and subsequently separated into the TCO elements 7a, 7b (e.g. with a laser ablation step).

[0179] At step S1000 the first electrodes 8a and second electrodes 8b are arranged on respective B-elements 6a and C-elements 6b of the nc-Si(n) layer 6, respectively, such that a first TCO element 7a is interposed between each B-element 6a and the respective first electrode 8a and a second TCO element 7b is interposed between each C-element 6b and the respective second electrode 8b. Typically, the electrodes 8a, 8b are screen printed onto the respective TCO elements 7a, 7b from silver, copper, or an alloy thereof. The resulting structure is illustrated in Fig. 3L.

[0180] Finally, at step S1100, the front portion of the solar cell 10 is arranged on the front surface 1a of the substrate 1. At step S1100, a front passivation layer 9 formed of a-Si:H(i) is arranged directly on the front surface 1a of the substrate 1 and subsequently an anti-reflective coating 11 (e.g. formed of silicon nitride) is arranged on the front passivation layer 9. Both the front passivation layer 9 and the anti-reflective coating 10 are deposited using PECVD. The resulting structure is illustrated in Fig. 3M.

[0181] EXAMPLES

[0182] Table 5

[0183]

[0184] Table 5 provides performance data for Examples 1 - 3 of solar cells according to the present invention. Examples 1 - 3 have a-Si(p) layers 4 of different thicknesses and all of Examples 1 - 3 are deposited from a precursor gas having a molar concentration of B2H6 of 1.15%. The performance parameters of each solar cell are provided as percentages with respect to Comparative Example 1 , in which there is no first, second, or third (amorphous) semiconductor elements within the solar cell structure 10. That is, Comparative Example 1 has the structure illustrated in Fig. 2A absent the a-Si(p) layer 4.

[0185] Table 5 firstly illustrates how Examples 1 and 2 provide a solar cell with a greater efficiency than the Reference solar cell and each of Comparative Examples 1 - 3. Solar cell efficiency, CE, is calculated according to the formula:

[0186]

[0187] 8885261

[0188] Where FF is the fill factor, Jsc is the short-circuit current density, A is the illuminated surface area of the solar cell (which was constant for the Examples and Comparative Examples in Tables 1 - 3), Voc is the open circuit voltage and Pin is the input radiation power to the solar cell (which was constant for the Examples and Comparative Examples in Tables 1 - 3).

[0189] Although Example 1 has a lower open circuit voltage and short circuit current density than Comparative Examples 1 , this is outweighed by the greater fill factor of Example 1 compared to Comparative Examples 1 , leading to a higher cell efficiency.

[0190] The thickness of the a-Si(p) layer in Example 3 is sufficiently high that it starts to provide a resistance to charge carrier transport, and results in a drop in fill factor that negatively impacts the fill factor of the solar cell. However, the pseudo fill factor, pFF, of Example 3 is still 4.3% higher than that of Comparative Example 1. The pseudo fill factor is obtained by shifting the sunsVoc curve (i.e. where a separate solar cell is used to monitor the illumination intensity rather than using the Jsc of the solar cell being measured) along the current density axis by Jsc (1 sun) and provides a virtually-series-resistance-free pseudo fill factor measurement.

[0191] The best solar cell performance is obtained by Example 2, having an a-Si(p) layer thickness of 2.1 nm.

[0192] Table 6

[0193]

[0194] Table 6 provides performance data for Examples 2, 4 and 5 of solar cells according to the present invention. Examples 2, 4 and 5 all have a a-Si(p) layer 4 having a thickness of 2.1 nm and vary in the dopant concentration in the a-Si(p) layer. The performance parameters of each solar cell are provided as percentages with respect to Comparative Example 1 discussed above.

[0195] Examples 2, 4 and 5 all provide an improvement in all of the performance parameters of the solar cell compared to Comparative Example 1. However, the largest improvement in each of the performance parameters is obtained with Example 2 that has an a-Si(p) layer 4 that has been deposited from a precursor gas with a molar concentration of B2H6 of1.15%..8885261

[0196] Table 7

[0197]

[0198] Table 7 provides performance data for Example 6 of a solar cell according to the present invention in which the SiOx barrier elements are present between respective pairs of adjacent A- and C-elements and the a-Si(p) layer providing the first, second and third semiconductor elements is also present. The performance parameters of Example 6 are provided as percentages with respect to Comparative Example 2, where there are no barrier elements present between respective pairs of adjacent A- and C-elements, but the a-Si(p) layer providing the first, second and third semiconductor elements is present.

[0199] Example 6, in which the barrier elements are present, has a slightly lower short circuit current density than comparative Example 2, but this is outweighed by the increase in Voc and FF that is achieved with the barrier elements present, resulting in Example 6 having a cell efficiency 6.6% higher than that of Comparative Example 2.

[0200] It is to be understood that the present disclosure is not limited by specific construction details or process steps set forth in the preceding description and accompanying drawings. Rather, it will be apparent to those skilled in the art having the benefit of the present disclosure that the systems, apparatuses and / or methods described herein could be embodied differently and / or be practiced or carried out in various alternative ways.

[0201] Unless otherwise defined herein, scientific and technical terms used in connection with the presently disclosed inventive concept(s) shall have the meanings that are commonly understood by those of ordinary skill in the art, and known techniques and procedures may be performed according to conventional methods well known in the art and as described in various general and more specific references that may be cited and discussed in the present specification.

[0202] All examples implementing the present disclosure can be made and executed without undue experimentation in light of the present disclosure. While particular examples have been described, it will be apparent to those of skill in the art that variations may be applied to the systems, apparatus, and / or methods and in the steps or in the sequence of steps of the methods described herein without departing from the concept, spirit, and scope of the inventive concept(s). All such similar substitutions and modifications apparent to those skilled in the art are deemed to be within the spirit, scope, and concept of the inventive concept(s) as defined by the appended claims.8885261

[0203] In the drawings, the thickness of layers, films, elements etc., are exaggerated for clarity. Furthermore, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “over” another element, it can be directly on or over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present.

[0204] The use of the term “a” or “an” in the claims and / or the specification may mean “one,” as well as “one or more,” “at least one,” and “one or more than one.” As such, the terms “a,” “an,” and “the,” as well as all singular terms, include plural referents unless the context clearly indicates otherwise. Likewise, plural terms shall include the singular unless otherwise required by context.

[0205] The use of the term “or” in the present disclosure (including the claims) is used to mean an inclusive “and / or” unless explicitly indicated to refer to alternatives only or unless the alternatives are mutually exclusive. For example, a condition “A or B” is satisfied by any of the following: A is true (or present), and B is false (or not present), A is false (or not present), and B is true (or present), and both A and B are true (or present).

[0206] As used in this specification and claim(s), the words “comprising, “having,” “including,” or “containing” (and any forms thereof, such as “comprise” and “comprises,” “have” and “has,” “includes” and “include,” or “contains” and “contain,” respectively) are inclusive or open-ended and do not exclude additional, unrecited elements or method steps.

[0207] Unless otherwise explicitly stated as incompatible, or the physics or otherwise of the embodiments, examples, or claims prevent such a combination, the features of examples disclosed herein, and of the claims, may be integrated together in any suitable arrangement, especially ones where there is a beneficial effect in doing so. This is not limited to only any specified benefit, and instead may arise from an “ex post facto” benefit. This is to say that the combination of features is not limited by the described forms, particularly the form (e.g., numbering) of example(s), embodiment(s), or dependency of claim(s). Moreover, this also applies to the phrase “in one embodiment,” “according to an embodiment,” and the like, which are merely a stylistic form of wording and are not to be construed as limiting the following features to a separate embodiment to all other instances of the same or similar wording. This is to say, a reference to ‘an,’ ‘one,’ or ‘some’ embodiment(s) may be a reference to any one or more, and / or all embodiments, or combination(s) thereof, disclosed. Also, similarly, the reference to “the” embodiment may not be limited to the immediately preceding embodiment. Further, all references to one or more embodiments or examples are to be construed as non-limiting to the claims.

Claims

1. 8885261CLAIMS1. A method of manufacturing a solar cell, wherein the method comprises:providing a substrate comprising a back surface;arranging an interdigitated back contact structure on the back surface of the substrate, the interdigitated back contact structure comprising:a first charge-carrier collector comprising a plurality of A-elements having a first doping type; anda second charge-carrier collector interdigitated with the first charge-carrier collector, the second charge-carrier collector comprising a plurality of C-elements having a second doping type; andan etching step to provide a deposition mask for arranging the A-elements and / or C-elements; wherein the method further comprises screen printing an etching mask for use in the etching step.

2. The method according to claim 1 , wherein the etching mask is a soft mask.

3. The method according to any preceding claim, wherein the step of screen printing an etching mask comprises screen printing etching mask material at room temperature.

4. The method according to any preceding claim, wherein the step of screen printing an etching mask comprises curing the etching mask.

5. The method according to any preceding claim, wherein the etching mask comprises a polymer.

6. The method according to any preceding claim, wherein:the first doping type is negative, andthe second doping type is positive.

7. The method according to any preceding claim, wherein:the method comprises a first etching step through a first etching mask to provide a first deposition mask for deposition of the A-elements therethrough; and / orthe method comprises a second etching step through a second etching mask to provide a second deposition mask for deposition of the C-elements therethrough.

8. The method according to claim 7, wherein:the method further comprises depositing a continuous layer of deposition mask material on the back surface of the substrate; andthe first etching mask is screen printed onto the continuous layer of deposition mask material.3588852619. The method according to claim 8, wherein the deposition mask material comprises silicon oxide.

10. The method according to claims 9, wherein the step of depositing the deposition mask material comprises:pre-treating a deposition surface for the silicon oxide with a CO2 plasma treatment; and a CVD deposition of silicon oxide from a precursor gas comprising silane and carbon dioxide.

11. The method according to any one of claims 7 to 10, wherein:the first etching step comprises acidic etching; and / orthe second etching step comprises acidic etching.

12. The method according to any one of claims 8 to 11 , wherein the method further comprises:arranging a back passivation layer on the back surface of the substrate, the back passivation layer comprising a back surface; anddepositing an intrinsic semiconductor layer onto the back surface of the back passivation layer prior to depositing the continuous layer of deposition mask material.

13. The method according to any one of claims 7 to 12, wherein the method comprises:depositing a continuous layer of semiconductor material having the first doping type through the first deposition mask; andscreen printing the second etching mask onto the semiconductor material having the first doping type.

14. The method according to claim 13, wherein the semiconductor material having the first doping type is first-doping-type nanocrystalline silicon.

15. The method according to claims 13 or 14, wherein the semiconductor material having the first doping type is deposited by:pre-treating a deposition surface for the semiconductor material having the first doping type with a hydrogen and carbon dioxide plasma treatment; andsubsequently depositing the semiconductor material having the first doping type by CVD.

16. The method according to any one of claims 13 to 15, wherein:the second etching mask comprises a plurality of resist elements;the first deposition mask comprises a plurality of apertures therethrough; andthe plurality of resist elements are aligned with respective apertures in the first deposition mask such that portions of the semiconductor material having the first doping type deposited through the first deposition mask are covered by respective resist elements.

17. The method according to claim 16, wherein:368885261the second etching step separates the semiconductor material having the first doping type into the plurality of A-elements; andthe second deposition mask is provided by the plurality of A-elements.

18. The method according to claim 16 or 17, wherein the second etching step etches the first deposition mask.

19. The method according to any one of claims 16 to 18, wherein each resist element has a width greater than a width of the respective aperture in the first deposition mask.

20. The method according to any one of claims 7 to 19, wherein:arranging the plurality of C-elements comprises depositing semiconductor material having the second doping type through the second deposition mask.

21. The method according to claim 20, wherein:the first charge-carrier collector further comprises a plurality of B-elements arranged on respective A-elements, the B-elements comprising semiconductor material having the second doping type; andarranging the plurality of B-elements and the plurality of C-elements comprises depositing a continuous layer of semiconductor material having the second doping type through and over the second deposition mask, the B-elements and C-elements provided by portions of said continuous layer.

22. The method according to any one of claims 7 to 19, wherein:the first charge-carrier collector further comprises a plurality of B-elements arranged on respective A-elements, the B-elements having the second doping type, and the interdigitated back contact structure further comprises a plurality of first semiconductor elements, each first amorphous semiconductor element interposed between a respective pair of an A-element and B-element, having the second doping type, and having a lower conductivity than the A-elements and / or the B-elements; and / orthe interdigitated back contact structure further comprises a plurality of second semiconductor elements, each second amorphous semiconductor element interposed between a respective pair of adjacent A- and C- elements, having the second doping type, and having a lower conductivity than the A-elements and / or the C-elements; andthe method further comprises depositing a continuous layer of semiconductor material through the second deposition mask to provide the first semiconductor elements and / or the second semiconductor elements, and subsequently depositing a continuous layer of semiconductor material having the second doping type through and over the second deposition mask to provide the B-elements and / or the C-elements.888526123. The method according to any one of claims 20 to 22, wherein the semiconductor material having the second doping type is arranged by:pre-treating a deposition surface for the semiconductor material having the second doping type with a hydrogen plasma treatment; andsubsequently depositing the semiconductor material having the second doping type by CVD.

24. The method according to any one of claims 7 to 23, wherein:the first etching mask comprises a plurality of resist elements and a plurality of apertures therethrough; andeach aperture has a width dimension greater than or equal to 150 pm and less than or equal to 3120 pm; and / oreach resist element has a width dimension greater than or equal to 250 pm and less than or equal to 5000 pm.

25. The method according to any one of claims 7 to 24, wherein:the second etch mask comprises a plurality of resist elements and a plurality of apertures therethrough; andeach aperture has a width dimension greater than or equal to 220 pm and less than or equal to 4420 pm; and / oreach resist element has a width dimension greater than or equal to 240 pm and less than or equal to 4870 pm.

Images