Display panel, driving method and display apparatus

Abstract

A display panel, a driving method and a display apparatus. The display panel comprises a pixel circuit (10) and a light-emitting element (20). The pixel circuit (10) comprises a data writing module (11), a driving module (12) and a compensation module (13), the compensation module (13) being configured to be controlled by a first scan signal (S2N), the data writing module (11) being configured to be controlled by a second scan signal (SP), and V11<V11', or V11<V12, wherein V11 is the high-level voltage of the first scan signal (S2N) in a refresh frame (Trefresh), V11' is the high-level voltage of the first scan signal (S2N) in a hold frame (Thold), and V12 is the high-level voltage of the second scan signal (SP) in the refresh frame (Trefresh).

Description

Display panel, driving method and display device

[0001] This application claims priority to Chinese Patent Application No. 202411997849.0, filed with the Chinese Patent Office on December 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, such as a display panel, driving method, and display device. Background Technology

[0003] With the continuous development of display technology, more and more electronic devices with display functions are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work.

[0004] Electronic products use different refresh rates for display in different application scenarios. For example, a higher refresh rate is used to drive the display of dynamic images (such as game scenes) to ensure the smoothness of the display; a lower refresh rate is used to drive the display of slow-motion images or static images to reduce power consumption.

[0005] However, when display devices use different refresh modes, especially low-frequency refresh, flickering or even abnormal screen flickering may occur, which will seriously affect the display effect. Summary of the Invention

[0006] This application provides a display panel, a driving method, and a display device to avoid flickering or even abnormal screen flickering on the display panel, thereby improving display quality.

[0007] In a first aspect, embodiments of this application provide a display panel, including pixel circuitry and light-emitting elements;

[0008] The pixel circuit includes a data writing module, a driving module, and a compensation module;

[0009] The driving module includes a driving transistor;

[0010] The data writing module is connected between the data signal input terminal and the first pole of the driving transistor;

[0011] The compensation module is connected between the gate and the second electrode of the driving transistor;

[0012] The display process of the display panel includes display frames, which include refresh frames and hold frames;

[0013] The compensation module is configured to be controlled by a first scan signal; the first scan signal satisfies: V11 < V11'; where V11 is the high-level voltage of the first scan signal in the refresh frame, and V11' is the high-level voltage of the first scan signal in the hold frame.

[0014] Secondly, embodiments of this application also provide a display panel, including pixel circuits and light-emitting elements;

[0015] The pixel circuit includes a data writing module, a driving module, and a compensation module;

[0016] The driving module includes a driving transistor;

[0017] The data writing module is connected between the data signal input terminal and the first pole of the driving transistor;

[0018] The compensation module is connected between the gate and the second electrode of the driving transistor;

[0019] The display process of the display panel includes display frames, and the display frames include refresh frames;

[0020] The compensation module is configured to be controlled by a first scan signal; the data writing module is configured to be controlled by a second scan signal.

[0021] The first scan signal and the second scan signal satisfy: V11 < V12;

[0022] Wherein, V11 is the high-level voltage of the first scan signal in the refresh frame, and V12 is the high-level voltage of the second scan signal in the refresh frame.

[0023] Thirdly, embodiments of this application also provide a driving method for a display panel, the display panel including pixel circuits and light-emitting elements;

[0024] The pixel circuit includes a data writing module, a driving module, and a compensation module;

[0025] The driving module includes a driving transistor;

[0026] The data writing module is connected between the data signal input terminal and the first pole of the driving transistor;

[0027] The compensation module is connected between the gate and the second electrode of the driving transistor;

[0028] The display panel's screen display process includes multiple display frames, which include refresh frames and hold frames.

[0029] The driving method for the display panel includes:

[0030] The compensation module is controlled using a first scanning signal; wherein the first scanning signal satisfies: V11 < V11'; wherein V11 is the high-level voltage of the first scanning signal in the refresh frame, and V11' is the high-level voltage of the first scanning signal in the hold frame.

[0031] Fourthly, embodiments of this application also provide a display device, including any of the display panels and mid-frames provided in embodiments of this application, wherein the mid-frame is located outside the display panel. Attached Figure Description

[0032] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0033] Figure 2 is a circuit diagram of the pixel circuit and light-emitting element in the display panel shown in Figure 1;

[0034] Figure 3 is a timing diagram of a pixel circuit driving in a related technology;

[0035] Figure 4 is a timing diagram of a pixel circuit driving embodiment provided in this application;

[0036] Figure 5 is a comparison diagram of the display panel brightness under two first scanning signals provided in the embodiments of this application;

[0037] Figure 6 is a graph showing the high-level voltage of the first scan signal and the flickering of the display panel in the refresh frame provided in the embodiment of this application.

[0038] Figure 7 is a graph showing the flickering of the display panel in the holding frame provided in the embodiment of this application, where the high-level voltage of the first scan signal in the holding frame is compared with the voltage of the display panel.

[0039] Figure 8 is a flowchart of a display panel driving method provided in an embodiment of this application;

[0040] Figure 9 is another pixel circuit driving timing diagram provided in an embodiment of this application;

[0041] Figure 10 is a timing diagram of another pixel circuit driving embodiment provided in this application;

[0042] Figure 11 is a schematic diagram of another display panel provided in an embodiment of this application;

[0043] Figure 12 is a partial signal timing diagram of different zones in the display panel shown in Figure 11;

[0044] Figure 13 is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0045] Figure 14 is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0046] Figure 15 is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0047] Figure 16 is a timing diagram of another pixel circuit driving embodiment provided in this application;

[0048] Figure 17 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0049] The present application will now be described in conjunction with the accompanying drawings and embodiments. The embodiments described herein are merely illustrative and not intended to limit the scope of the application. For ease of description, only the parts relevant to the present application are shown in the drawings, not the entire structure.

[0050] The terminology used in the embodiments of this application is for the purpose of describing specific embodiments only and is not intended to limit the application. It should be noted that directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this application are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this application. Furthermore, in the context, it should be understood that when referring to an element being formed "upper" or "lower" of another element, it can be formed not only directly "upper" or "lower" of the other element, but also indirectly "upper" or "lower" of the other element through intermediate elements. The terms "first," "second," etc., are used for descriptive purposes only and do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Those skilled in the art can understand the meaning of the above terms in this application according to the circumstances.

[0051] The term "comprising" and its variations as used in this application are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment".

[0052] It should be noted that the concepts of "first" and "second" mentioned in this application are used only to distinguish the corresponding content and are not used to limit the order or interdependence.

[0053] It should be noted that the terms "a" and "a plurality of" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0054] Figure 1 is a schematic diagram of a display panel provided in an embodiment of this application, and Figure 2 is a circuit diagram of the pixel circuit and light-emitting element in the display panel shown in Figure 1. Referring to Figures 1 and 2, the display panel includes a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a data writing module 11, a driving module 12 and a compensation module 13; the driving module 12 includes a driving transistor M2; the data writing module 11 is connected between the data signal input terminal Vdata and the first electrode of the driving transistor M2; the compensation module 13 is connected between the gate and the second electrode of the driving transistor M2.

[0055] In addition, the pixel circuit also includes a gate reset module 14, an anode reset module 15, a light emission control module 16, and a storage capacitor Cst; the gate reset module 14 is connected to the gate reset signal terminal Vref1 and the gate of the driving transistor M2. The anode reset module 15 is connected between the anode reset signal terminal Vref2 and the anode of the light emission element 20. The light emission control module 16 includes a first light emission control unit 161 and a second light emission control unit 162; the first light emission control unit 161, the driving module 12, the second light emission control unit 162, and the light emission element 20 are connected in series between the first power signal terminal PVDD and the second power signal terminal PVEE.

[0056] Figure 3 is a timing diagram of a pixel circuit drive in related technologies. Referring to Figures 1-3, the driving process and driving principle of the display panel will be briefly introduced below. The driving process of the pixel circuit 10 may include multiple display frames T, which can be divided into high refresh mode and low refresh mode according to the refresh frequency. In high refresh mode, all display frames T are refresh frames Trefresh; in low refresh mode, the multiple display frames T may include refresh frames Trefresh and hold frames Thold. The refresh frame Trefresh may include a gate reset stage ta, a data writing stage tb, and a light emission stage tc, and the hold frame Thold may include the light emission stage tc.

[0057] During the gate reset phase ta, the gate reset module 14 receives the gate reset control signal S1N, which is at a low level and serves as an enable signal. The gate reset module 14 is then turned on, and the gate reset signal Vref1 is input to the gate of the driving transistor M2 to reset the gate of the driving transistor M2.

[0058] During the data writing phase tb, the data writing module 11 receives the data writing control signal SP, which is currently low, acting as an enable signal, thus turning on the data writing module 11. Simultaneously, the compensation module 13 receives the threshold compensation control signal S2N, which is also low, acting as an enable signal, thus turning on the compensation module 13. The data signal Vdata is input to the gate of the driving transistor M2 through the data writing module 11, the driving module 12, and the compensation module 13, and is stored by the storage capacitor Cst.

[0059] During the light-emitting phase tc, both the first light-emitting control unit 161 and the second light-emitting control unit 162 receive a low-level light-emitting control signal Emit, which serves as an enable signal. Therefore, both the first and second light-emitting control units 161 and 162 are turned on, and the first power supply signal terminal PVDD and the second power supply signal terminal PVEE are turned on. The conduction current is controlled by the driving transistor M2, and the conduction current of the driving transistor M2 is related to its gate-source voltage difference. The driving transistor M2 forms a certain gate-source voltage difference with the first power supply signal terminal PVDD based on the data signal Vdata stored at its gate, thereby controlling the conduction current of the driving transistor M2. In other words, it can provide a corresponding driving current to the light-emitting element 20, enabling the light-emitting element 20 to emit light at the target brightness.

[0060] However, during the light-emitting phase tc, the transistors in the compensation module 13 are controlled by the threshold compensation control signal S2N. Normally, they are in an off state, but because they are typically P-type dual-gate transistors (i.e., including the first transistor M31 and the second transistor M32), the node connecting the two transistors is capacitively coupled to the gate. The threshold compensation control signal S2N received by the gate is at a high level at this time, raising the voltage of the intermediate node. This reduces the gate-source voltage difference of the first transistor M31, causing leakage current in the first transistor M31. This drives the gate of transistor M2, i.e., the potential of the first node N1, to continuously increase within one frame of light emission, resulting in a gradual decrease in the brightness of the light-emitting element 20 during the light-emitting phase tc. When the display panel is driven at a low frequency and the light-emitting time of one frame is long, the brightness decreases significantly, and there are obvious changes in brightness between different display frames. The human eye perceives these changes in brightness as flickering.

[0061] Furthermore, considering that the driving transistor M2 is in a forward bias state during the light-emitting phase tc of multiple display frames (i.e., the voltage of the second node N2 is greater than the voltage of the third node N3), prolonged forward bias will cause the electrical characteristic curve of the driving transistor M2 to drift, affecting the accuracy of the light emission brightness. Referring to Figure 3, the relevant technology will adjust the bias of the driving transistor M2. A bias adjustment phase td is set in the hold frame Thold. The bias adjustment signal VGMP is written to the driving transistor M2 by the data writing transistor M1, so that the voltage of the third node N3 of the driving transistor M2 is greater than or equal to the voltage of the second node N2, and it is in a reverse bias state. This compensates for the forward bias state of the driving transistor M2 during the light-emitting phase tc, stabilizes the electrical characteristics of the driving transistor M2, and ensures the accuracy of the light emission brightness. However, because the third node N3 writes a high-level bias adjustment signal VGMP during the bias adjustment phase td, the gate-source voltage difference of the transistors, especially the second transistor M32, in the compensation module 13, which should be turned off, decreases, which will cause it to be unable to be completely turned off. This will also affect the gate voltage of the driving transistor M2, causing abnormal brightness of the light-emitting element in the display frame and resulting in abnormal screen flickering.

[0062] Figure 4 is a timing diagram of a pixel circuit driving according to an embodiment of this application. Referring to Figures 1, 2 and 4, in order to address the above-mentioned technical problems, in this embodiment of the application, the compensation module 13 is configured to be controlled by a first scan signal S2N; the first scan signal S2N satisfies: V11 < V11'; where V11 is the high-level voltage of the first scan signal S2N in the refresh frame Trefresh, and V11' is the high-level voltage of the first scan signal S2N in the hold frame Thold.

[0063] The compensation module 13 includes a first transistor M31 and a second transistor M32. The first transistor M31 and the second transistor M32 are connected in series between the gate and the second terminal of the driving transistor M2. Both the first transistor M31 and the second transistor M32 can be configured as P-type channel transistors, and their gates receive the first scan signal S2N. As mentioned earlier, when the first scan signal S2N is at a low voltage level, the first transistor M31 and the second transistor M32 are turned on, and the pixel circuit 10 enters the data writing stage tb. When the first scan signal S2N is at a high voltage level, the first transistor M31 and the second transistor M32 are turned off. At this time, the pixel circuit 10 can be in the gate reset stage ta and the light emission stage tc of the refresh frame Trefres, and the bias adjustment stage td and the light emission stage tc of the hold frame Thold. In this embodiment, the high-level voltage of the first scan signal S2N in the refresh frame Trefresh and the hold frame Thold is set differently. Specifically, the high-level voltage of the first scan signal S2N in the refresh frame Trefresh (7.8V in the example) is set lower than the high-level voltage of the first scan signal S2N in the hold frame Thold (8V in the example). On the one hand, this allows the first scan signal S2N to control the first transistor M31 and the second transistor M32 to turn off during the light-emitting phase tc of the refresh frame Trefresh with a relatively lower high-level voltage, thereby reducing the gate-dependent interference at the intermediate node of the two transistors. The coupling effect prevents the voltage of the intermediate node from being raised due to capacitive coupling, thus avoiding leakage current. This prevents the voltage of the gate of the driving transistor M2, i.e., the first node N1, from being affected by leakage current in the first transistor M31, thus affecting the brightness of the light-emitting element 20. On the other hand, it allows the first scan signal S2N to control the first transistor M31 and the second transistor M32 to turn off at a relatively high level during the bias adjustment phase td of the holding frame Thold. This avoids the situation where the first transistor M31 and the second transistor M32 cannot be turned off due to the high-level bias adjustment signal VGMP written to the third node N3, thus preventing abnormal screen flickering.In other words, if the first scan signal S2N uses the same high-level voltage in both the refresh frame Trefresh and the hold frame Thold, for example, both using a high-level voltage of 7.8V, and if the bias adjustment signal VGMP is written through the data writing module 11 in the hold frame Thold, and this bias adjustment signal VGMP is lower than the high-level voltage of the first scan signal S2N (for example, the bias adjustment signal VGMP is 7V), then the third node N3 of the bias adjustment signal VGMP is actually raised, that is, the voltage of the source of the transistor in the compensation module 13 increases. The 7.8V gate voltage and the 7V source voltage cannot generate a sufficient gate-source voltage difference, which will cause the transistor of the compensation module 13 to be unable to turn off in the hold frame Thold. This will cause a more significant change in the voltage of the gate of the driving transistor M2, and a more significant difference between the light emission brightness of the light-emitting element 20 and the target brightness, resulting in abnormal screen flickering.

[0064] To visually demonstrate the display effect and underlying principle of the display panel in the embodiments of this application, corresponding experimental verifications were also conducted in the embodiments of this application.

[0065] First, Figure 5 is a comparison of the display panel brightness under two first scan signals provided in the embodiments of this application. As shown in Figure 5, it illustrates the change curve of the frame brightness of the display panel over time when the compensation module in the pixel circuit of the display panel is turned off using two first scan signals, namely a 6V high-level voltage and an 8V high-level voltage. The base frequency of the display panel is 120Hz, and the example in the figure is a 30Hz low-frequency drive state. That is, in the example in the figure, three hold frames (Thold) are set after each refresh frame (Trefresh) to more clearly reflect the degree of change in frame brightness. Referring to Figures 2 and 5, it can be seen that in multiple display frames, the frame brightness will decrease to varying degrees due to the leakage problem of the compensation module 13. When the pixel circuit 10 is driven by the first scan signal S2N with an 8V high-level voltage and the compensation module 13 is turned off, the frame brightness of the display panel will decrease more significantly, and the decrease will be greater, resulting in obvious brightness changes and flickering. However, when the pixel circuit 10 is driven by the first scan signal S2N with a 6V high-level voltage and the compensation module 13 is turned off, the decrease in frame brightness of the display panel will be slowed down to some extent, meaning the decrease in brightness will no longer be noticeable, thus improving the flickering phenomenon to some extent. This experimental result also proves that by appropriately reducing the high-level voltage of the first scan signal S2N in the refresh frame (Trefresh), the leakage current problem of the compensation module 13 can be reduced, thereby reducing the impact of leakage current on the gate voltage of the driving transistor M2, reducing the brightness changes of the light-emitting element across multiple display frames, and improving the flickering phenomenon of the display panel.

[0066] Figure 6 is a graph showing the relationship between the high-level voltage of the first scan signal and the flickering of the display panel in the refresh frame provided in this embodiment. As shown in Figure 6, the vertical axis represents the flicker value, indicating the brightness ratio during brightness changes, and the horizontal axis represents different high-level voltage values ​​of the first scan signal S2N. As can be seen from Figure 6, within an appropriate range, or in a range where the pixel circuit compensation module can be turned off, the higher the high-level voltage of the first scan signal S2N in the refresh frame Trefresh, the larger its flicker value, indicating a more obvious brightness change and making the flickering phenomenon more easily perceived by the human eye. Conversely, the lower the high-level voltage of the first scan signal S2N in the refresh frame Trefresh, the smaller its flicker value, indicating a less obvious brightness change and making the flickering phenomenon less easily perceived by the human eye. Therefore, in this embodiment, by appropriately reducing the high-level voltage of the first scan signal S2N in the refresh frame Trefresh, the leakage current of the transistor in the compensation module 13 can be reduced, avoiding impact on the gate voltage of the driving transistor M2. This prevents a significant difference between the emitted brightness and the target brightness, thus improving the flickering phenomenon of the display panel.

[0067] Figure 7 is a graph showing the relationship between the high-level voltage of the first scan signal in the hold frame and the flickering of the display panel in an embodiment of this application. It should be noted that in this hold frame (Thold), the pixel circuit of the display panel uses the data writing module 11 to write a bias adjustment signal VGMP to the driving transistor M2 for bias adjustment. As shown in Figure 7, contrary to the pattern of the refresh frame (Trefresh), within an appropriate range, the lower the high-level voltage of the first scan signal S2N in the hold frame (Thold), the larger its flicker value, indicating a more obvious change in brightness and a flickering phenomenon that is more easily perceived by the human eye. Conversely, the higher the high-level voltage of the first scan signal S2N in the hold frame (Thold), the smaller its flicker value, indicating a less obvious change in brightness and a flickering phenomenon that is less easily perceived by the human eye. Therefore, in this embodiment of the application, by appropriately raising the high-level voltage of the first scan signal S2N in the hold frame (Thold), a sufficient gate-source voltage difference can be generated between the gate and source of the transistor in the compensation module to ensure effective turn-off, thereby avoiding abnormal screen flickering caused by the inability of the compensation module to turn off.

[0068] This application also provides a driving method for a display panel. Figure 8 is a flowchart of a driving method for a display panel provided in this application. Referring to Figures 4 and 8, based on the above-mentioned display panel, the driving method of this application may include:

[0069] S110. Control the compensation module using the first scan signal; wherein the first scan signal satisfies: V11 < V11'; wherein V11 is the high-level voltage of the first scan signal in the refresh frame, and V11' is the high-level voltage of the first scan signal in the hold frame.

[0070] This driving method essentially utilizes the first scan signal S2N, which undergoes a high-level voltage change during the refresh frame Trefresh and the hold frame Thold, to control the compensation module 13, i.e., to control the off state of the compensation module 13. As mentioned earlier, setting the high-level voltage of the first scan signal S2N during the refresh frame Trefresh to be lower than the high-level voltage of the first scan signal S2N during the hold frame Thold not only prevents leakage current caused by the voltage of the intermediate node of the dual-gate transistor in the compensation module 13 being raised due to capacitive coupling during the light-emitting phase tc of the refresh frame Trefresh, thus preventing the gate voltage of the driving transistor M2 from affecting the brightness of the light-emitting element 20 due to leakage current from the first transistor M31; it also prevents the first transistor M31 and the second transistor M32 from being unable to be turned off due to the high-level bias adjustment signal VGMP written to the third node N3 during the bias adjustment phase td of the hold frame Thold, thus preventing abnormal screen flickering.

[0071] Referring again to Figure 1, regarding the compensation module in the pixel circuit, the display panel in this embodiment may be provided with a first shift register circuit 31 and a first high-level voltage signal line 41. The first shift register circuit 31 is electrically connected to the first high-level voltage signal line 41. The first high-level voltage signal line 41 is configured to provide a first high-level voltage signal VGH1 to the first shift register circuit 31. The voltage of the first high-level voltage signal VGH1 in the refresh frame Trefresh is less than the voltage in the hold frame Thold. The first shift register circuit 31 is electrically connected to the compensation module 13 to provide a first scan signal S2N to the compensation module 13.

[0072] As those skilled in the art will know, the scanning signal received by the pixel circuit of the display panel is actually provided by the shift register circuit. The multi-level shift register unit provides scanning signals to the multi-line pixel circuit to realize the line-by-line scanning process and complete the display of one display frame. Based on this, in the embodiments of this application, the first scanning signal S2N provided to the compensation module 13 needs to switch between high-level voltage in the refresh frame Trefresh and the hold frame Thold. This can be achieved by the driver chip, which provides a changing high-level voltage signal to the shift register circuit. That is, a changing high-level voltage signal is provided to the first shift register circuit 31 through the first high-level voltage signal line 41. Specifically, the voltage of the first high-level voltage signal VGH1 provided by the first high-level voltage signal line 41 in the refresh frame Trefresh is less than the voltage in the hold frame Thold. In other words, when the driver chip provides the first high-level voltage signal VGH1 to the first shift register circuit 31 through the first high-level voltage signal line 41, it can be designed to output different high-level voltage signals in the refresh frame Trefresh and the hold frame Thold, thereby causing the first shift register circuit 31 to generate a change in the high-level voltage signal when the first scan signal S2N is generated in the refresh frame Trefresh and the hold frame Thold.

[0073] Figure 9 is another pixel circuit driving timing diagram provided in an embodiment of this application. Referring to Figures 4 and 9, in this embodiment of the application, the data writing module 11 may also be configured to be controlled by the second scan signal SP. The first scan signal S2N and the second scan signal SP satisfy: V11 = V12 (as shown in Figure 4), or V11 < V12 (as shown in Figure 9). V12 is the high-level voltage of the second scan signal SP in the refresh frame Trefresh.

[0074] The data writing module 11 includes a third transistor M1. The two poles of the third transistor M1 are respectively connected between the data signal input terminal Vdata and the first pole of the driving transistor M2. The gate of the third transistor M1 receives the second scan signal SP. The third transistor M1 can also be configured as a P-type channel transistor.

[0075] In the embodiment shown in Figure 4, the high-level voltage V11 of the refresh frame Trefresh of the first scan signal S2N and the high-level voltage V12 of the refresh frame Trefresh of the second scan signal SP are equal, both for example, 7.8V. This means that the compensation module 13 and the data writing module 11 use the same high-level voltage for shutdown control in the refresh frame Trefresh without any differentiation. However, considering the possibility that the compensation module 13 may not be able to shut down in the hold frame Thold, the high-level voltage V11' of the first scan signal S2N in the hold frame Thold is set higher, for example, 8V. This ensures that the transistors in the compensation module 13, especially the second transistor M32, can still have a sufficient gate-source voltage difference even when the source of the bias adjustment phase td is written with a high-level voltage signal VGMP. In this way, the P-type second transistor M32 can be effectively shut down, avoiding the problem of abnormal screen flickering in the hold frame Thold.

[0076] In the embodiment shown in Figure 9, the high-level voltage V11 (6V in the example) of the refresh frame Trefresh of the first scan signal S2N is less than the high-level voltage V12 (7.8V in the example) of the refresh frame Trefresh of the second scan signal SP. This means that the problem of leakage current in the refresh frame Trefresh of the compensation module 13 can be given priority. The high-level voltage V11 of the first scan signal S2N in the refresh frame Trefresh is set to be lower than the high-level voltage of the second scan signal SP in the refresh frame Trefresh. That is, on the basis of turning off the compensation module 13 with a relatively lower high-level voltage, the problem of leakage current is avoided by the transistor in the compensation module 13 raising the potential of the intermediate node of the dual-gate transistor due to capacitive coupling.

[0077] Based on the process of the data writing module being configured to be controlled by the second scan signal SP to write data signals or bias signals, referring to Figure 8, the driving method of this application embodiment may further include the following steps:

[0078] S120. Use the second scan signal to control the data writing module; wherein, the first scan signal and the second scan signal satisfy: V11 = V12, or, V11 < V12; wherein, V12 is the high-level voltage of the second scan signal in the refresh frame.

[0079] Figure 10 is another pixel circuit driving timing diagram provided in the embodiment of this application. Referring to Figure 10, optionally, the first scan signal S2N and the second scan signal SP satisfy: V11' > V12.

[0080] Example V11 is 6V, example V11' is 8V, and example V12 is 7.8V. This embodiment not only considers the problem that the compensation module 13 may not be able to turn off in the holding frame Thold by setting the high-level voltage V11' of the first scan signal S2N in the holding frame Thold to be higher, but also considers the problem that the compensation module 13 is prone to leakage in the refresh frame Trefresh by setting the high-level voltage V11 of the first scan signal S2N in the refresh frame Trefresh to be lower than the high-level voltage of the second scan signal SP in the refresh frame Trefresh, that is, to avoid leakage of transistors in the compensation module 13.

[0081] Therefore, in this embodiment, the Trefresh frame can control the leakage current of the compensation module 13, and the Thold frame can effectively prevent the compensation module 13 from being abnormally turned on. This can stabilize the gate potential of the driving transistor M2 in multiple display frames, prevent the gate potential of the driving transistor M2 from changing and affecting the brightness of the light-emitting element 20 and the target brightness, avoid flickering or abnormal screen flickering, and ensure the accuracy and uniformity of the display.

[0082] Referring again to Figures 4, 9 and 10, in this embodiment of the application, the refresh frame Trefresh may include a data writing phase ta, and the hold frame Thold may include a bias adjustment phase td; the data writing module 11 is configured to be controlled by the second scan signal SP, providing a data signal Vdata to the driving transistor M2 during the data writing phase ta, and providing a bias adjustment signal VGMP to the driving transistor M2 during the bias adjustment phase td, wherein VGMP ≥ Vdata.

[0083] As mentioned above, the data writing module 11 is multiplexed as a bias adjustment module during the hold frame Thold. During the hold frame Thold, it writes a bias adjustment signal VGMP to the data signal input terminal Vdata to reverse-bias the driving transistor M2, thereby compensating for the driving transistor M2 which has been in a forward-biased state for a long time. In this embodiment, the bias adjustment signal VGMP is set to be no lower than the data signal Vdata normally written during the refresh frame Trefresh. A high-level voltage signal can be written to the third node N3 to make the voltage of the third node N3 greater than the voltage of the second node N2. Furthermore, the degree of reverse bias of the driving transistor M2 can be adjusted through the higher bias adjustment signal VGMP, thereby effectively adjusting the bias state of the driving transistor M2.

[0084] Referring again to Figures 4 and 10, the data writing module 11 is configured to write a drive signal to the first terminal of the drive transistor M2, and the maximum value of the drive signal is VGMP; where V12 > VGMP + 1V.

[0085] It is understood that the third transistor M1 in the data writing module 11 is a P-type transistor, and the second scan signal SP is responsible for controlling the data writing module 11 to turn off at a high level during the refresh frame Trefresh. Considering that the data writing module 11 needs to be multiplexed as a bias adjustment module during the hold frame Thold, providing a high-level bias adjustment signal VGMP to the drive transistor M2, the drive signal written at the data signal input terminal Vdata of the data writing module 11 is not used for data writing for the entire time; during the bias adjustment phase td, it will transform into a larger bias adjustment signal VGMP. Therefore, when controlling the turn-off of the data writing module 11, the high-level voltage written to its gate needs to take into account the signal written to the source. Setting V12 > VGMP + 1V means that the difference between the high-level voltage controlling the turn-off of the data writing module 11 and the highest voltage signal VGMP written at the data signal input terminal is greater than 1V. This ensures a sufficiently large gate-source voltage difference to turn off the P-type third transistor M1. Based on this, by setting the high-level voltage V11' of the first scan signal S2N in the holding frame Thold to be greater than V12, it can be ensured that the gate of the transistor in the compensation module 13, especially the second transistor M32, has a sufficiently large high-level voltage. Even if the bias adjustment signal VGMP is written to the third node N3 for reverse bias driving transistor M2, it can still make the gate-source voltage difference of the second transistor M32 above 1V, which is greater than its threshold voltage, thereby ensuring that the P-type second transistor M32 is effectively turned off.

[0086] Referring again to Figures 4, 9, and 10, optionally, the second scan signal SP also satisfies: V12 = V12'; where V12' is the high-level voltage of the second scan signal SP in the holding frame Thold. This means that the high-level voltage of the second scan signal SP in the refresh frame and the holding frame does not need to be differentiated. For the third transistor M1 in the data writing module 11, using the same high-level voltage in both the refresh frame Trefresh and the holding frame Thold allows for effective shutdown.

[0087] Regarding the voltage of the scanning signals of the conduction compensation module and the data writing module, in this embodiment of the application, the first scanning signal S2N and the second scanning signal SP may also satisfy: V22≤V21; where V21 is the low-level voltage of the first scanning signal S2N and V22 is the low-level voltage of the second scanning signal SP.

[0088] Setting the low-level voltage of the first scan signal S2N to be no higher than the low-level voltage of the second scan signal SP ensures that the transistors in the compensation module 13 can have an equal or relatively lower gate-source voltage difference, thereby controlling the first P-type transistor M31 and the second transistor M32 to be fully turned on, and effectively writing data signals to the gate of the driving transistor M2.

[0089] Similarly, for the data writing module, the display panel in this embodiment may also be provided with a second shift register circuit 32 and a second high-level voltage signal line 42, wherein the second shift register circuit 32 is electrically connected to the second high-level voltage signal line 42; the second high-level voltage signal line 42 is configured to provide a second high-level voltage signal VGH2 to the second shift register circuit 32; the voltages of the first high-level voltage signal VGH1 and the second high-level voltage signal VGH2 are different for at least a portion of the time. The second shift register circuit 32 is electrically connected to the data writing module 11 to provide a second scan signal SP to the data writing module 11.

[0090] The voltages of the first high-level voltage signal VGH1 and the second high-level voltage signal VGH2 are different for at least a portion of the time, meaning that the voltages are different within the refresh frame Trefresh and / or the hold frame Thold. In this embodiment, the second scan signal SP provided to the data writing module 11 can be differentiated from the first scan signal S2N provided to the compensation module 13. As shown in the embodiments of FIG4, FIG9 and FIG10, the first scan signal S2N is set to a higher high-level voltage in the hold frame Thold and / or a lower high-level voltage in the refresh frame Trefresh, thereby creating a difference from the second scan signal SP. In implementing this differentiated design, the driver chip can provide a second high-level voltage signal VGH2 to the second shift register circuit 32 through the second high-level voltage signal line 42. It is designed to output the same high-level voltage signal in the refresh frame Trefresh and the hold frame Thold, and it is a high-level voltage signal that is different from the first high-level voltage signal VGH1 in the refresh frame Trefresh and / or the hold frame Thold. This causes the second shift register circuit 32 to generate a second scan signal SP in the refresh frame Trefresh and the hold frame Thold.

[0091] The second high-level voltage signal line 42 and the first high-level voltage signal line 41 are responsible for providing different high-level voltage signals to different shift register circuits 32, and these different high-level voltage signals can be provided by the driver chip. Therefore, the second high-level voltage signal line 42 and the first high-level voltage signal line 41 can be connected to different high-level voltage signal output pins of the driver chip to obtain different high-level voltage signals.

[0092] Additionally, as shown in Figure 1, the first shift register circuit 31 and the second shift register circuit 32 are respectively disposed on opposite sides of the display area AA of the display panel. The fact that the first shift register circuit 31 or the second shift register circuit 32 is disposed only on the same side of the display area AA is merely an example of this application. Those skilled in the art can, according to actual needs, simultaneously provide the first shift register circuit 31 on both sides of the display area AA, or simultaneously provide the second shift register circuit 32 on both sides of the display area AA, or simultaneously provide the first shift register circuit 31 and the second shift register circuit 32 on the same side of the display area AA. No limitation is imposed here.

[0093] Figure 11 is a schematic diagram of another display panel structure provided in an embodiment of this application, and Figure 12 is a partial signal timing diagram of different partitions in the display panel shown in Figure 11. Referring to Figures 11 and 12, in an optional embodiment, the display panel may include a first partition AA1 and a second partition AA2. During the same display time, the proportion of refresh frames Trefresh during the operation of the pixel circuit of the first partition AA1 is higher than the proportion of refresh frames Trefresh during the operation of the pixel circuit of the second partition AA2. The first scan signal S2N corresponding to the compensation module 13 of the pixel circuit 10 of the first partition AA1 and the second partition AA2 satisfies: V11_1 > V11_2. Wherein, V11_1 is the high-level voltage of the first scan signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the first partition AA1 in the refresh frame Trefresh, and V11_2 is the high-level voltage of the first scan signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the second partition AA2 in the refresh frame Trefresh.

[0094] As mentioned earlier, the display panel can be set to high refresh rate mode and low refresh rate mode according to the refresh rate. Based on the same principle, different areas of the display panel can also be controlled to achieve different refresh rates, that is, to realize the function of zoned frequency. In this embodiment, the display panel is divided into a first zone AA1 and a second zone AA2. The different proportions of refresh frames Trefresh within the same time indicate that the two zones use different refresh rates. The higher proportion of refresh frames Trefresh in the first zone AA1 indicates that the first zone AA1 is a high refresh rate zone, and the second zone AA2 is a low refresh rate zone. For the low-frequency zone with a lower refresh rate that maintains the brightness of refresh frames Trefresh for a longer period of time, when leakage current occurs in the compensation module 13, causing a slight change in brightness, it will accumulate due to the longer maintenance time, making it easier for the human eye to perceive. Based on this, in this embodiment, the high-level voltage V11_2 of the first scan signal S2N of the second partition AA2 in the refresh frame Trefresh is lower than the high-level voltage V11_1 of the first scan signal S2N of the first partition AA1 in the refresh frame Trefresh. This allows the transistor gate in the compensation module 13 to receive a relatively lower high-level voltage for shutdown control. This enables the compensation module 13 in the low-frequency region to reduce leakage current more effectively and avoids the human eye perceiving changes in brightness caused by leakage current.

[0095] The embodiments of this application also provide specific implementation methods for driving other modules in the pixel circuit, which will be described below with reference to Figures 2, 4, 9 and 10.

[0096] Optionally, the gate reset module 14 is configured to be controlled by the third scan signal S1N; the first scan signal S2N and the third scan signal S1N satisfy: V11 = V13, and / or, V21 = V23; wherein, V11 is the high-level voltage of the first scan signal S2N in the refresh frame Trefresh, V13 is the high-level voltage of the third scan signal S1N in the refresh frame Trefresh, V21 is the low-level voltage of the first scan signal S2N in the refresh frame Trefresh, and V23 is the low-level voltage of the third scan signal S1N in the refresh frame Trefresh.

[0097] The gate reset module 14 may include a fourth transistor M41 and a fifth transistor M42; the fourth transistor M41 and the fifth transistor M42 are connected in series between the gate of the driving transistor M2 and the gate reset signal input terminal Vref1, and the gates of the fourth transistor M41 and the fifth transistor M42 receive the third scan signal S1N; the fourth transistor M41 and the fifth transistor M42 are P-type channel transistors.

[0098] This embodiment indicates that the first scan signal S2N of the drive compensation module 13 and the third scan signal S1N of the drive gate reset module 14 have essentially the same high-level voltage state in the refresh frame Trefresh, that is, they have the same high-level voltage in the refresh frame Trefresh and a lower high-level voltage than the holding frame Thold. This avoids leakage current from the gate reset module 14 in the refresh frame Trefresh due to capacitive coupling, and avoids the problem of abnormal light emission of the light-emitting element 20 due to leakage current from the gate reset module 14.

[0099] The first scan signal and the third scan signal also satisfy: V11' = V13'; where V13' is the high-level voltage of the third scan signal in the holding frame.

[0100] Similarly, this embodiment means that the first scan signal S2N of the drive compensation module 11 and the third scan signal S1N of the drive gate reset module 14 have essentially the same high-level voltage state in the holding frame Thold, that is, they have the same high-level voltage in the holding frame Thold and are higher than the refresh frame Trefresh, so that the gate reset module 14 can be effectively turned off in the holding frame Thold.

[0101] In addition, it should be added that, in order to avoid the influence of leakage current of gate reset module 14 on the brightness of light emission, gate reset module can also be selected as a single transistor design, that is, without the use of dual gate transistor design. Thus, even if the third scan signal S1N is a relatively high high-level voltage when holding frame Thold, the voltage of the intermediate node will not be raised due to the capacitive coupling between the gate and the intermediate node of the dual gate transistor, which can prevent leakage current problem of gate reset module 14 when holding frame Thold.

[0102] Figure 13 is a schematic diagram of another display panel structure provided in an embodiment of this application. Referring to Figure 13, for the gate reset module described above, since the first scan signal S2N of the drive compensation module 13 and the third scan signal S1N of the drive gate reset module 14 can have the same high-level voltage state in the refresh frame Trefresh and the hold frame Thold, the first shift register circuit 31 in the display panel can also be electrically connected to the gate reset module 14 to provide the third scan signal S1N to the gate reset module 14.

[0103] In this embodiment, the first scan signal S2N of the drive compensation module 13 and the third scan signal S1N of the drive gate reset module 14 are set to have the same high-level voltage state in both the refresh frame Trefresh and the hold frame Thold. Therefore, the same shift register circuit, namely the first shift register circuit 31, can be used to simultaneously provide the first scan signal S2N and the third scan signal S1N. It can be understood that since the multi-level shift register unit can output multi-level first scan signals S2N with fixed delay, the first scan signal S2N of other rows can be multiplexed into the third scan signal S1N of this row according to the delay of the first scan signal S2N and the third scan signal S1N required in the same row pixel circuit 1. This is used to control the gate reset module 14 of this row. As a result, there is no need to set up a separate shift register circuit for the gate reset module 14, which greatly reduces the number of shift register circuits and the area of ​​the non-display area where the shift register circuit is located, which helps to realize a narrow bezel design.

[0104] Optionally, the anode reset module 15 is configured to be controlled by the second scan signal SP.

[0105] The anode reset module 15 may include a sixth transistor M5, the two terminals of which are connected between the anode reset signal terminal Vref2 and the anode of the light-emitting element 20, and the gate of the sixth transistor M5 receives the second scan signal SP; the sixth transistor M5 is a P-type channel transistor.

[0106] It can be understood that the anode reset module 15 has the function of resetting the anode of the light-emitting element 20. Before the light-emitting stage tc of multiple display frames, by resetting the anode of the light-emitting element 20, that is, writing a fixed anode reset signal to the anode of the light-emitting element 20, the anode of the light-emitting element 20 can be prevented from maintaining the voltage state of the previous display frame, and the light-emitting brightness of the light-emitting element 20 in the current display frame can be prevented from being affected by the previous display frame.

[0107] In this embodiment, the anode reset module 15 is configured to be controlled by the second scan signal SP, which means that both the data writing module 11 and the anode reset module 15 use the second scan signal SP to control the switch. It can also be understood that during the data writing stage tb, while the data writing module 11 is turned on to write data signals, the anode reset module 15 is also turned on to reset the anode of the light-emitting element 20. The data writing stage tb is also the anode reset stage.

[0108] Regarding the aforementioned anode reset module, since the data writing module 11 and the anode reset module 15 can be controlled by the second scan signal SP, a second shift register circuit 32 and a second high-level voltage signal line 42 can also be provided in the display panel for the anode reset module 15. The second shift register circuit 32 is electrically connected to the second high-level voltage signal line 42. The second high-level voltage signal line 42 is configured to provide a second high-level voltage signal VGH2 to the second shift register circuit 32. The voltages of the first high-level voltage signal VGH1 and the second high-level voltage signal VGH2 are different for at least a portion of the time. The second shift register circuit 32 is also electrically connected to both the data writing module 11 and the anode reset module 15 to provide the second scan signal SP to both modules. Therefore, it is also unnecessary to separately provide a shift register circuit for the anode reset module 15, greatly reducing the number of shift register circuits and the area of ​​the non-display area where the shift register circuits are located, which helps to achieve a narrow bezel design.

[0109] Optionally, the first light-emitting control unit 161 and the second light-emitting control unit 162 are configured to be controlled by the first light-emitting control signal Emit; the second scan signal SP and the first light-emitting control signal Emit satisfy: V12 = V14, and / or, V22 = V24; wherein, V14 is the high-level voltage of the first light-emitting control signal Emit, V22 is the high-level voltage of the second scan signal SP in the refresh frame, and V24 is the low-level voltage of the first light-emitting control signal Emit.

[0110] The first light-emitting control unit 161 includes a seventh transistor M61, and the second light-emitting control unit 162 includes an eighth transistor M62; the two terminals of the seventh transistor M61 are connected between the first power supply signal terminal PVDD and the first terminal of the driving transistor M2; the two terminals of the eighth transistor M62 are connected between the second terminal of the driving transistor M2 and the anode of the light-emitting element 20; the gates of the seventh transistor M61 and the eighth transistor M62 receive the first light-emitting control signal Emit; the seventh transistor M61 and the eighth transistor M62 are P-type channel transistors.

[0111] This embodiment indicates that the first light emission control signal Emit of the driving light emission control module and the second scan signal SP of the driving data writing module 11 have the same level state, which can control the corresponding transistors to turn off and on according to normal high-level voltage and low-level voltage.

[0112] Regarding the aforementioned anode reset module, Figure 14 is a schematic diagram of another display panel structure provided in an embodiment of this application. Referring to Figure 14, in this embodiment, the display panel may further include a third shift register circuit 33 and a third high-level voltage signal line 43. The light-emitting control module 16 is connected to the third shift register circuit 33; the third shift register circuit 33 is electrically connected to the third high-level voltage signal line 43; and the second high-level voltage signal line 42 is electrically connected to the third high-level voltage signal line 43.

[0113] Since the first light-emitting control signal Emit driving the light-emitting control module and the second scan signal SP driving the data writing module 11 can have the same level state, the shift register circuits set by the display panel for the light-emitting control module 16 and the data writing module 11 can use the same high-level voltage. That is, the third high-level voltage signal line 43 corresponding to the third shift register circuit 33 connected to the light-emitting control module 16 can be electrically connected to the second high-level voltage signal line 42 corresponding to the second shift register circuit 32 connected to the data writing module 11, so as to receive the same high-level voltage signal VGH2.

[0114] In other embodiments of this application, an independent shift register circuit may be optionally provided for the gate reset module to improve the driving capability. Figure 15 is a schematic diagram of another display panel provided in an embodiment of this application. Referring to Figure 15, a fourth shift register circuit 34 and a fourth high-level voltage signal line 44 may also be provided in the display panel. The fourth shift register circuit 34 is electrically connected to the gate reset module 14, and the fourth high-level voltage signal line 44 is electrically connected to the first high-level voltage signal line 41.

[0115] As can be seen from the preceding text, since the first scan signal S2N of the driving compensation module 13 and the third scan signal S1N of the driving gate reset module 14 can be set to have the same high-level voltage state in both the refresh frame Trefresh and the hold frame Thold, the shift register circuits set for the compensation module 13 and the gate reset module 14 can use the same high-level voltage. That is, the fourth high-level voltage signal line 44 corresponding to the fourth shift register circuit 34 connected to the gate reset module 14 can be electrically connected to the first high-level voltage signal line 41 corresponding to the first shift register circuit 31 connected to the compensation module 13, so as to receive the same high-level voltage signal VGH1.

[0116] Figure 16 is another pixel circuit driving timing diagram provided in the embodiment of this application. Referring again to Figures 2, 9, 10 and 16, in another embodiment of this application, the compensation module 13 may be configured to be controlled by the first scan signal S2N; the data writing module 11 may be configured to be controlled by the second scan signal SP; the first scan signal S2N and the second scan signal SP satisfy: V11 < V12; where V11 is the high-level voltage of the first scan signal S2N in the refresh frame Trefresh, and V12 is the high-level voltage of the second scan signal SP in the refresh frame Trefresh.

[0117] Similarly, as mentioned above, the high-level voltage V11 (6V in the example) of the refresh frame Trefresh of the first scan signal S2N is less than the high-level voltage V12 (7.8V in the example) of the refresh frame Trefresh of the second scan signal SP. This means that the leakage problem of the compensation module 13 in the refresh frame Trefresh can be given priority. The high-level voltage V11 of the first scan signal S2N in the refresh frame Trefresh is set to be lower than the high-level voltage of the second scan signal SP in the refresh frame Trefresh. That is, on the basis of turning off the compensation module 13 with a relatively lower high-level voltage, the leakage problem caused by the transistor in the compensation module 13 raising the potential of the intermediate node of the dual-gate transistor due to capacitive coupling is avoided.

[0118] As shown in Figures 9, 10, and 16, the gate reset module 14 is controlled by the third scan signal S1N. The third scan signal S1N can have the same high-level voltage state as the first scan signal S2N, as shown in the embodiments of Figures 9 and 10. Alternatively, it can be designed reasonably according to the influence of the gate reset module 14 on the gate of the driving transistor M2, as shown in the embodiment of Figure 16. No limitation is made here.

[0119] Referring again to Figures 9 and 10, optionally, V11 can be set to < V11', where V11' can be 7.8V or 8V. As shown in Figure 10, when V11' > V12, that is, the high-level voltage V11 of the first scan signal S2N in the refresh frame Trefresh is set to be lower than the high-level voltage of the second scan signal SP in the refresh frame Trefresh. This solves the problem of leakage current easily occurring in the compensation module 13 in the refresh frame Trefresh. Simultaneously, the high-level voltage V11' of the first scan signal S2N in the hold frame Thold is also set higher, avoiding the problem that the compensation module 13 might fail to turn off in the hold frame Thold.

[0120] Referring again to Figures 11 and 12, based on the driving timing scheme shown in Figures 9, 10, or 16, in the display panel of this embodiment, the first scan signal S2N corresponding to the compensation module 13 of the pixel circuit 10 of the first partition AA1 and the second partition AA2 can also be set to satisfy: V11_1 > V11_2; where V11_1 is the high-level voltage of the first scan signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the first partition AA1 in the refresh frame Trefresh, and V11_2 is the high-level voltage of the first scan signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the second partition AA2 in the refresh frame Trefresh.

[0121] In this embodiment, the first scan signal S2N of the second partition AA2 is set to be lower than the high-level voltage V11_2 of the refresh frame Trefresh. This allows the transistor gate in the compensation module 13 to receive a relatively lower high-level voltage for shutdown control. This enables the compensation module 13 in the low-frequency region to reduce leakage current more effectively and avoids the human eye perceiving changes in brightness caused by leakage current.

[0122] Based on the same inventive concept, this application also provides a display device. Figure 17 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Referring to Figure 17, the display device includes a display panel 1 and a middle frame 2 as provided in any embodiment of this application. The middle frame 2 is located outside the display panel 1 and provides support for the display panel 1, which will not be described in detail here. Exemplarily, the display device can be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device, and this application does not limit it to such devices.

Claims

1. A display panel, comprising pixel circuitry and light-emitting elements; The pixel circuit includes a data writing module, a driving module, and a compensation module; The driving module includes a driving transistor; The data writing module is connected between the data signal input terminal and the first pole of the driving transistor; The compensation module is connected between the gate and the second electrode of the driving transistor; in, The display panel's screen display process includes display frames, which include refresh frames and hold frames; The compensation module is configured to be controlled by a first scan signal; the first scan signal satisfies: V11 < V11'; where V11 is the high-level voltage of the first scan signal in the refresh frame, and V11' is the high-level voltage of the first scan signal in the hold frame.

2. The display panel according to claim 1, wherein, The data writing module is configured to be controlled by a second scan signal, wherein the first scan signal and the second scan signal satisfy: V11 = V12, or V11 < V12; wherein V12 is the high-level voltage of the second scan signal in the refresh frame.

3. The display panel according to claim 2, wherein, The first scan signal and the second scan signal satisfy: V11' > V12.

4. The display panel according to claim 2, wherein, The data writing module is configured to write a driving signal to the first electrode of the driving transistor, the maximum value of the driving signal being VGMP. Where V12 > VGMP+1V.

5. The display panel according to claim 1, comprising a first partition and a second partition; within the same time period, the proportion of refresh frames during the operation of the pixel circuit of the first partition is higher than the proportion of refresh frames during the operation of the pixel circuit of the second partition; The first scan signal corresponding to the compensation module of the pixel circuit of the first partition and the second partition satisfies: V11_1 > V11_2; in, V11_1 is the high-level voltage of the first scan signal corresponding to the compensation module in the pixel circuit of the first partition in the refresh frame, and V11_2 is the high-level voltage of the first scan signal corresponding to the compensation module in the pixel circuit of the second partition in the refresh frame.

6. The display panel according to claim 2, wherein, The second scan signal also satisfies: V12 = V12'; where V12' is the high-level voltage of the second scan signal in the holding frame.

7. The display panel according to claim 2, wherein, The first scan signal and the second scan signal also satisfy: V22≤V21; Wherein, V21 is the low-level voltage of the first scan signal, and V22 is the low-level voltage of the second scan signal.

8. The display panel according to claim 2, wherein, The compensation module includes a first transistor and a second transistor, which are connected in series between the gate and the second terminal of the driving transistor. The gates of the first transistor and the second transistor receive the first scan signal. The data writing module includes a third transistor, the two terminals of which are respectively connected between the data signal input terminal and the first terminal of the driving transistor, and the gate of the third transistor receives the second scan signal; The first transistor, the second transistor, and the third transistor are all P-channel transistors.

9. The display panel according to claim 1, wherein, The pixel circuit further includes a gate reset module; the gate reset module is connected to the gate reset signal terminal and the gate of the driving transistor; The gate reset module is configured to be controlled by a third scan signal; The first scan signal and the third scan signal satisfy at least one of the following: V11 = V13, or V21 = V23; Wherein, V11 is the high-level voltage of the first scan signal in the refresh frame, V13 is the high-level voltage of the third scan signal in the refresh frame, V21 is the low-level voltage of the first scan signal in the refresh frame, and V23 is the low-level voltage of the third scan signal in the refresh frame.

10. The display panel according to claim 9, wherein, The first scan signal and the third scan signal also satisfy: V11' = V13'; Wherein, V13' is the high-level voltage of the third scan signal in the holding frame.

11. The display panel according to claim 9, wherein, The gate reset module includes a fourth transistor and a fifth transistor; The fourth transistor and the fifth transistor are connected in series between the gate of the driving transistor and the gate reset signal input terminal, and the gates of the fourth transistor and the fifth transistor receive the third scan signal; The fourth and fifth transistors are P-channel transistors.

12. The display panel according to claim 2, wherein, The pixel circuit also includes an anode reset module, which is connected between the anode reset signal terminal and the anode of the light-emitting element; The anode reset module is configured to be controlled by the second scan signal.

13. The display panel according to claim 12, wherein, The anode reset module includes a sixth transistor, the two terminals of which are connected between the anode reset signal terminal and the anode of the light-emitting element, and the gate of the sixth transistor receives the second scan signal; The sixth transistor is a P-channel transistor.

14. The display panel according to claim 2 or 3, wherein, The pixel circuit further includes a light-emitting control module; the light-emitting control module includes a first light-emitting control unit and a second light-emitting control unit; the first light-emitting control unit, the driving module, the second light-emitting control unit, and the light-emitting element are connected in series between the first power signal terminal and the second power signal terminal; The first light-emitting control unit and the second light-emitting control unit are configured to be controlled by the first light-emitting control signal; The second scanning signal and the first light emission control signal satisfy at least one of the following: V12 = V14, or V22 = V24; Wherein, V14 is the high-level voltage of the first light-emitting control signal, V22 is the high-level voltage of the second scanning signal in the refresh frame, and V24 is the low-level voltage of the first light-emitting control signal.

15. The display panel according to claim 14, wherein, The first light-emitting control unit includes a seventh transistor, and the second light-emitting control unit includes an eighth transistor; The two terminals of the seventh transistor are connected between the first power signal terminal and the first terminal of the driving transistor; the two terminals of the eighth transistor are connected between the second terminal of the driving transistor and the anode of the light-emitting element. The gates of the seventh transistor and the eighth transistor receive the first light-emitting control signal; The seventh transistor and the eighth transistor are P-channel transistors.

16. The display panel according to claim 1, wherein, The refresh frame includes a data writing phase, and the hold frame includes an offset adjustment phase; The data writing module is configured to be controlled by a second scan signal, providing a data signal Vdata to the driving transistor during the data writing phase, and providing a bias adjustment signal VGMP to the driving transistor during the bias adjustment phase, wherein VGMP ≥ Vdata.

17. The display panel according to claim 1, further comprising a first shift register circuit and a first high-level voltage signal line, wherein the first shift register circuit is electrically connected to the first high-level voltage signal line; The first high-level voltage signal line is configured to provide a first high-level voltage signal to the first shift register circuit; The voltage of the first high-level voltage signal in the refresh frame is lower than the voltage in the hold frame; the first shift register circuit is electrically connected to the compensation module.

18. The display panel according to claim 17, further comprising a second shift register circuit and a second high-level voltage signal line, wherein the second shift register circuit is electrically connected to the second high-level voltage signal line; The second high-level voltage signal line is configured to provide a second high-level voltage signal to the second shift register circuit; the voltages of the first high-level voltage signal and the second high-level voltage signal are different for at least a portion of the time; the second shift register circuit is electrically connected to the data writing module.

19. The display panel according to claim 18, wherein, The pixel circuit also includes a gate reset module, an anode reset module, and a light emission control module; The gate reset module is electrically connected to the first shift register circuit, and the anode reset module is electrically connected to the second shift register circuit. The display panel also includes a third shift register circuit and a third high-level voltage signal line, and the light-emitting control module is connected to the third shift register circuit; The third shift register circuit is electrically connected to the third high-level voltage signal line; the second high-level voltage signal line is electrically connected to the third high-level voltage signal line.

20. The display panel according to claim 18, wherein, The pixel circuit also includes a gate reset module, an anode reset module, and a light emission control module; The display panel further includes a third shift register circuit, a fourth shift register circuit, a third high-level voltage signal line, and a fourth high-level voltage signal line. The anode reset module is electrically connected to the second shift register circuit, the third shift register circuit is electrically connected to the light-emitting control module, and the fourth shift register circuit is electrically connected to the gate reset module. The third shift register circuit is electrically connected to the third high-level voltage signal line, and the second high-level voltage signal line is electrically connected to the third high-level voltage signal line; The fourth shift register circuit is electrically connected to the fourth high-level voltage signal line, and the first high-level voltage signal line is electrically connected to the fourth high-level voltage signal line.

21. A display panel, comprising pixel circuitry and light-emitting elements; The pixel circuit includes a data writing module, a driving module, and a compensation module; The driving module includes a driving transistor; The data writing module is connected between the data signal input terminal and the first pole of the driving transistor; The compensation module is connected between the gate and the second electrode of the driving transistor; in, The display panel's screen display process includes display frames, and the display frames include refresh frames; The compensation module is configured to be controlled by a first scan signal; the data writing module is configured to be controlled by a second scan signal. The first scan signal and the second scan signal satisfy: V11 < V12; Wherein, V11 is the high-level voltage of the first scan signal in the refresh frame, and V12 is the high-level voltage of the second scan signal in the refresh frame.

22. The display panel according to claim 21, wherein, The display frame also includes a hold frame; The first scan signal also satisfies: V11 < V11'; where V11' is the high-level voltage of the first scan signal in the holding frame.

23. The display panel according to claim 21, comprising a first partition and a second partition; within the same time period, the proportion of refresh frames during the operation of the pixel circuit of the first partition is higher than the proportion of refresh frames during the operation of the pixel circuit of the second partition; The first scan signal corresponding to the compensation module of the pixel circuit of the first partition and the second partition satisfies: V11_1 > V11_2; in, V11_1 is the high-level voltage of the first scan signal corresponding to the compensation module in the pixel circuit of the first partition in the refresh frame, and V11_2 is the high-level voltage of the first scan signal corresponding to the compensation module in the pixel circuit of the second partition in the refresh frame.

24. A method for driving a display panel, wherein, The display panel includes pixel circuitry and light-emitting elements; The pixel circuit includes a data writing module, a driving module, and a compensation module; The driving module includes a driving transistor; The data writing module is connected between the data signal input terminal and the first pole of the driving transistor; The compensation module is connected between the gate and the second electrode of the driving transistor; The display panel's screen display process includes multiple display frames, which include refresh frames and hold frames. The driving method for the display panel includes: The compensation module is controlled using a first scanning signal; wherein the first scanning signal satisfies: V11 < V11'; wherein V11 is the high-level voltage of the first scanning signal in the refresh frame, and V11' is the high-level voltage of the first scanning signal in the hold frame.

25. The driving method according to claim 24, further comprising: The data writing module is controlled by the second scanning signal; wherein the first scanning signal and the second scanning signal satisfy: V11 = V12, or V11 < V12; wherein V12 is the high-level voltage of the second scanning signal in the refresh frame.

26. The driving method according to claim 25, wherein, The first scan signal and the second scan signal also satisfy: V11' > V12.

27. A display device comprising a display panel and a middle frame as described in any one of claims 1-23, the middle frame being located outside the display panel.

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