Data processing circuit and semiconductor memory

Abstract

Embodiments of the present disclosure provide a data processing circuit and a semiconductor memory. The data processing circuit comprises a parallel-to-serial module, configured to receive an initial data signal, perform parallel-to-serial processing on the initial data signal, and generate a data signal to be processed and an auxiliary data signal, wherein the initial data signal is a parallel data signal, the data signal to be processed and the auxiliary data signal are both serial data signals, and the auxiliary data signal is delayed by one unit time interval from the data signal to be processed; a first driving module, configured to receive the data signal to be processed, enhance the driving capability of the data signal to be processed, and output a target data signal to a data port; and a second driving module, configured to receive the data signal to be processed and the auxiliary data signal, and when the potentials of the data signal to be processed and the auxiliary data signal are the same, perform de-emphasis processing on the target data signal. The circuit can reduce the impact of channel loss on signal quality.

Description

Data processing circuits and semiconductor memory

[0001] This application claims priority to Chinese Patent Application No. 202510007689.9, filed on January 2, 2025, entitled “Data Processing Circuit and Semiconductor Memory”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a data processing circuit and a semiconductor memory. Background Technology

[0003] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speed when manufacturing and using devices such as computers. In order to obtain faster data transmission speeds, a series of memory devices and other devices that can transmit data at double data rate (DDR) have emerged, such as DDR4 chips and DDR5 chips.

[0004] In related technologies, compared to DDR4 chips, DDR5 chips have increased the maximum data speed from 3200 megabits per second (Mbps) to 8800 Mbps. However, during data signal transmission, channel loss not only affects signal quality but also limits data speed. Summary of the Invention

[0005] This disclosure relates to providing a data processing circuit and a semiconductor memory.

[0006] In a first aspect, embodiments of this disclosure provide a data processing circuit, the data processing circuit comprising:

[0007] The parallel-to-serial conversion module is used to receive an initial data signal, perform parallel-to-serial conversion on the initial data signal, and generate a data signal to be processed and an auxiliary data signal; wherein, the initial data signal is a parallel data signal, the data signal to be processed and the auxiliary data signal are both serial data signals, and the auxiliary data signal is delayed by one unit time interval compared to the data signal to be processed;

[0008] The first driving module is electrically connected to the data port and the parallel-to-serial conversion module, and is used to receive the data signal to be processed, enhance the driving capability of the data signal to be processed, and output the target data signal to the data port.

[0009] The second driving module is electrically connected to the data port, the parallel-to-serial converter and the first driving module, and is used to receive the data signal to be processed and the auxiliary data signal. When the potentials of the data signal to be processed and the auxiliary data signal are the same, the target data signal is de-emphasized.

[0010] In some embodiments, the parallel-to-serial conversion module includes a first parallel-to-serial conversion module and a second parallel-to-serial conversion module; the initial data signal includes N sub-initial data signals; wherein,

[0011] The first parallel-to-serial converter includes N input terminals and N clock terminals. The i-th input terminal receives the i-th sub-initial data signal, the N-th input terminal receives the N-th sub-initial data signal, the i-th clock terminal receives the i-th clock signal, and the N-th clock terminal receives the N-th clock signal. It is configured to output the signal of the j-th input terminal as 1 bit of data in the data signal to be processed when the signal received at the j-th clock terminal is in an active state.

[0012] The second parallel-to-serial converter includes N input terminals and N clock terminals. The i-th input terminal receives the i-th sub-initial data signal, the N-th input terminal receives the N-th sub-initial data signal, the i-th clock terminal receives the (i+1)-th clock signal, and the N-th clock terminal receives the 1-th clock signal. It is configured to output the signal of the j-th input terminal as 1 bit of data in the auxiliary data signal when the signal received at the j-th clock terminal is in an active state.

[0013] Wherein, the phase difference between the (i+1)th clock signal and the i-th clock signal is 360 degrees / N;

[0014] Where i, j, and N are all positive integers, N>1, 1≤i <N,1≤j≤N。

[0015] In some embodiments, the first parallel-to-serial conversion module includes N main switching units, and the second parallel-to-serial conversion module includes N auxiliary switching units; wherein...

[0016] The input terminal of the j-th main switch unit is connected to the j-th input terminal of the first parallel-to-serial module, and the control terminal is connected to the j-th clock terminal of the first parallel-to-serial module. It is configured to transmit the signal received by the input terminal to the output terminal when the signal received by the control terminal is in an active state. The output terminals of the N main switch units are all connected to the output terminal of the first parallel-to-serial module.

[0017] The input terminal of the j-th auxiliary switch unit is connected to the j-th input terminal of the second parallel-to-serial module, and the control terminal is connected to the j-th clock terminal of the second parallel-to-serial module. It is configured to transmit the signal received by the input terminal to the output terminal when the signal received by the control terminal is in an active state. The output terminals of the N auxiliary switch units are all connected to the output terminal of the second parallel-to-serial module.

[0018] In some embodiments, N=4.

[0019] In some embodiments, each of the main switching units includes a first NAND gate, a first NOR gate, a first PMOS, and a first NMOS; the first input terminal of the first NAND gate is connected to the control terminal of the main switching unit, the second input terminal is connected to the input terminal of the main switching unit, and the output terminal is connected to the gate of the first PMOS; the first input terminal of the first NOR gate is connected to the input terminal of the main switching unit, the signal received at the second input terminal is inverted with the signal at the first input terminal of the first NAND gate, and the output terminal is connected to the gate of the first NMOS; the source of the first PMOS is connected to the power supply terminal, and the drain is connected to the output terminal of the main switching unit; the source of the first NMOS is grounded, and the drain is connected to the output terminal of the main switching unit.

[0020] Each of the sub-switching units includes a second NAND gate, a second NOR gate, a second PMOS, and a second NMOS; the first input terminal of the second NAND gate is connected to the control terminal of the sub-switching unit, the second input terminal is connected to the input terminal of the sub-switching unit, and the output terminal is connected to the gate of the second PMOS; the first input terminal of the second NOR gate is connected to the input terminal of the sub-switching unit, the signal received at the second input terminal is inverted with the signal at the first input terminal of the second NAND gate, and the output terminal is connected to the gate of the second NMOS; the source of the second PMOS is connected to the power supply terminal, and the drain is connected to the output terminal of the sub-switching unit; the source of the second NMOS is grounded, and the drain is connected to the output terminal of the sub-switching unit.

[0021] In some embodiments, the parallel-to-serial converter further includes a first compensation module and a second compensation module; the first compensation module is electrically connected to the output terminal of the first parallel-to-serial converter and is used to enhance the amplitude of the data signal to be processed; the second compensation module is electrically connected to the output terminal of the second parallel-to-serial converter and is used to enhance the amplitude of the auxiliary data signal.

[0022] In some embodiments, the first drive module includes a first control unit and a first driver; wherein...

[0023] The first control unit receives the data signal to be processed and generates a first pull-up control signal and a first pull-down control signal with the same phase, wherein the first pull-up control signal is out of phase with the data signal to be processed;

[0024] The first driver includes a first pull-up unit and a first pull-down unit; the control terminal of the first pull-up unit receives the first pull-up control signal, the first terminal is connected to the power supply terminal, and the second terminal is connected to the data port; the control terminal of the first pull-down unit receives the first pull-down control signal, the first terminal is connected to the data port, and the second terminal is grounded.

[0025] In some embodiments, the second drive module includes a second control unit and a second driver; wherein...

[0026] The second control unit, electrically connected to the parallel-to-serial module and the first drive module, is configured to generate a second pull-down control signal in an active state when both the data signal to be processed and the auxiliary data signal are high; and to generate a second pull-up control signal in an active state when both the data signal to be processed and the auxiliary data signal are low.

[0027] The second driver includes a second pull-up unit and a second pull-down unit; the control terminal of the second pull-up unit receives the second pull-up control signal, the first terminal is connected to the power supply terminal, and the second terminal is connected to the data port; the control terminal of the second pull-down unit receives the second pull-down control signal, the first terminal is connected to the data port, and the second terminal is grounded.

[0028] In some embodiments, the second control unit includes a first OR gate and a first AND gate, the second pull-up unit is composed of a plurality of PMOS transistors, and the second pull-down unit is composed of a plurality of NMOS transistors; wherein...

[0029] The first terminal of the first OR gate receives the data signal to be processed, the second terminal receives the auxiliary data signal, and the output terminal outputs the second pull-up control signal.

[0030] The first terminal of the first AND gate receives the data signal to be processed, the second terminal receives the auxiliary data signal, and the output terminal outputs the second pull-down control signal.

[0031] In some embodiments, the second pull-up control signal includes M sub-signals, and the second pull-down control signal includes M sub-signals; the second pull-up unit includes M pull-up sub-units, and the control terminal of the x-th pull-up sub-unit receives the x-th sub-signal of the second pull-up control signal; the second pull-down unit includes M pull-down sub-units, and the control terminal of the x-th pull-down unit receives the x-th sub-signal of the second pull-down control signal; wherein...

[0032] The second control unit also receives M pull-up adjustment signals and M pull-down adjustment signals, and is configured such that when both the data signal to be processed and the auxiliary data signal are high and the x-th pull-down adjustment signal is active, the x-th sub-signal of the second pull-down control signal is active; and when both the data signal to be processed and the auxiliary data signal are low and the x-th pull-up adjustment signal is active, the x-th sub-signal of the second pull-up control signal is active.

[0033] Where x and M are both positive integers, and 1 ≤ x ≤ M.

[0034] In some embodiments, the second control unit includes a third NOR gate, a fourth NOR gate, M third NAND gates, and M second AND gates; wherein...

[0035] The first input terminal of the third NOR gate receives the data signal to be processed, and the second input terminal receives the auxiliary data signal.

[0036] The first input of the xth third NAND gate is connected to the output of the third NOR gate, the second input receives the xth pull-up adjustment signal, and the output outputs the xth sub-signal of the second pull-up control signal;

[0037] The first input terminal of the fourth NOR gate receives the inverted signal of the data signal to be processed, and the second input terminal receives the inverted signal of the auxiliary data signal;

[0038] The first input terminal of the xth second AND gate is connected to the output terminal of the fourth NOR gate, the second input terminal receives the xth pull-down adjustment signal, and the output terminal outputs the xth sub-signal of the second pull-down control signal.

[0039] In a second aspect, embodiments of this disclosure provide a semiconductor memory that includes the data processing circuitry described in the first aspect.

[0040] This disclosure provides a data processing circuit and a semiconductor memory. The data processing circuit includes a parallel-to-serial converter module for receiving an initial data signal, performing parallel-to-serial conversion on the initial data signal, and generating a data signal to be processed and an auxiliary data signal. The initial data signal is a parallel data signal, while the data signal to be processed and the auxiliary data signal are both serial data signals, with the auxiliary data signal delayed by one unit time interval compared to the data signal to be processed. A first driving module, electrically connected to a data port and the parallel-to-serial converter module, receives the data signal to be processed, enhances the driving capability of the data signal to be processed, and outputs a target data signal to the data port. A second driving module, electrically connected to the data port, the parallel-to-serial converter module, and the first driving module, receives the data signal to be processed and the auxiliary data signal, and performs de-emphasis processing on the target data signal when the potentials of the data signal to be processed and the auxiliary data signal are the same. In this way, the initial data signal is processed into a data signal to be processed and an auxiliary data signal that are separated by a unit time interval. When the potentials of the data signal to be processed and the auxiliary data signal are the same, the target data signal is de-emphasized, so that the target data signal can achieve a good equalization effect under different operating frequencies, process angles and channel conditions. This can reduce the impact of channel loss on signal quality and effectively ensure the speed and transmission quality of the output data. Attached Figure Description

[0041] Figure 1 is a schematic diagram of the composition structure of a data processing circuit provided in an embodiment of this disclosure;

[0042] Figure 2 is a signal timing diagram provided in an embodiment of this disclosure;

[0043] Figure 3 is a schematic diagram of the composition structure of a parallel-to-serial converter module provided in an embodiment of this disclosure;

[0044] Figure 4 is another signal timing diagram provided by an embodiment of this disclosure;

[0045] Figure 5 is a schematic diagram of the composition structure of a first driving module and a second driving module provided in an embodiment of this disclosure;

[0046] Figure 6 is another signal timing diagram provided by an embodiment of this disclosure;

[0047] Figure 7 is a schematic diagram of the composition structure of another first driving module and a second driving module provided in an embodiment of this disclosure;

[0048] Figure 8 is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Embodiments of the present invention

[0049] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0051] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0052] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0053] With the rapid development of semiconductor memory technology, the data speed of memory has also increased. For example, compared with DDR4 chips, the maximum data speed of DDR5 chips has increased from 3200Mbps to 8800Mbps. However, during the transmission of data signals, channel loss not only affects signal quality but also limits data speed.

[0054] In the interface circuit of a memory, the transmitting end is responsible for sending out high-frequency, high-speed signals. However, after transmission through the channel, the high-frequency loss of the channel causes signal energy to diffuse to adjacent symbols, resulting in inter-symbol interference. Therefore, an equalizer is needed to compensate for the high-frequency loss of the channel. To this end, the transmitting end typically uses a method of increasing the amplitude of the high-frequency signal for compensation. This method is also known as pre-emphasis, and it reduces the impact of channel loss on signal quality.

[0055] However, the applicant's extensive research revealed that pre-emphasis amplifies interference signals and is not very effective in eliminating inter-symbol interference caused by channel loss and terminal reflection. Furthermore, due to the influence of the on-die termination (ODT) impedance, the output signal swing can reach its maximum level but not its minimum level without pre-emphasis. Therefore, when pre-emphasis is enabled, the pull-up effect is not significant, while the pull-down effect is significant. This alters the common-mode level of the output signal, affecting signal detection at the receiver, leading to signal distortion, and potentially increasing signal reflection.

[0056] Based on this, this disclosure provides a data processing circuit, which includes a parallel-to-serial converter module for receiving an initial data signal, performing parallel-to-serial conversion on the initial data signal, and generating a data signal to be processed and an auxiliary data signal; wherein the initial data signal is a parallel data signal, and the data signal to be processed and the auxiliary data signal are both serial data signals, and the auxiliary data signal is delayed by one unit time interval compared to the data signal to be processed; a first driving module, electrically connected to the data port and the parallel-to-serial converter module, for receiving the data signal to be processed, enhancing the driving capability of the data signal to be processed, and outputting a target data signal to the data port; and a second driving module, electrically connected to the data port, the parallel-to-serial converter module, and the first driving module, for receiving the data signal to be processed and the auxiliary data signal, and performing de-emphasis processing on the target data signal when the potentials of the data signal to be processed and the auxiliary data signal are the same. In this way, the initial data signal is processed into a data signal to be processed and an auxiliary data signal that are separated by a unit time interval. When the potentials of the data signal to be processed and the auxiliary data signal are the same, the target data signal is de-emphasized, so that the target data signal can achieve a good equalization effect under different operating frequencies, process angles and channel conditions. This can reduce the impact of channel loss on signal quality and effectively ensure the speed and transmission quality of the output data.

[0057] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0058] In one embodiment of this disclosure, referring to FIG1, a schematic diagram of the composition structure of a data processing circuit 10 provided in this embodiment is shown. As shown in FIG1, the data processing circuit 10 may include a parallel-to-serial conversion module 40, a first driving module 20, and a second driving module 30; wherein,

[0059] Parallel-to-serial module 40 is used to receive the initial data signal, perform parallel-to-serial conversion on the initial data signal, and generate a data signal to be processed and an auxiliary data signal; wherein, the initial data signal is a parallel data signal, and the data signal to be processed and the auxiliary data signal are both serial data signals, and the auxiliary data signal is delayed by one unit interval (UI) compared with the data signal to be processed.

[0060] The first driving module 20 is electrically connected to the data port DQ and the parallel-to-serial conversion module 40. It is used to receive the data signal to be processed, enhance the driving capability of the data signal to be processed, and output the target data signal to the data port DQ.

[0061] The second driving module 30 is electrically connected to the data port DQ, the parallel-to-serial conversion module 40 and the first driving module 20. It is used to receive the data signal to be processed and the auxiliary data signal. When the potentials of the data signal to be processed and the auxiliary data signal are the same, the target data signal is de-emphasized.

[0062] It should be noted that, in this embodiment, the data processing circuit 10 can receive an initial data signal, process the initial data signal to generate a target data signal, and output it. This data processing circuit 10 can be applied in a data transmission system and transmit the target data signal to the memory, controller, etc., of the receiving end via a channel. Furthermore, this data processing circuit 10 is primarily used at the transmitting end to improve the quality of the transmitted signal.

[0063] As the operating speed of electronic devices increases, the swing amplitude (SW) of signals transmitted between electronic devices decreases, making signal transmission more susceptible to external noise. Therefore, in the data processing circuit 10 provided in this embodiment, the second driving module 30 performs feed-forward equalization (FFE) on the signal processed by the first driving module 20. This compensates and adjusts the signal before transmission through the channel, altering its driving capability and reducing the impact of channel loss on signal transmission performance. Therefore, in this embodiment, the second driving module 30 can also be referred to as the FFE driving module.

[0064] Referring to the timing diagram in Figure 2, it can be seen that the auxiliary data signal is delayed by 1 UI compared to the data signal to be processed. When the potentials of the data signal to be processed and the auxiliary data signal are the same, the second driving module 30 performs de-emphasis processing on the target data signal. It can be seen that after the target data signal flips from high to low or from low to high, its amplitude remains constant for 1 UI. If the pulse width of the target data signal is greater than 1 UI afterward, the signal after 1 UI can be considered a low-frequency component. The de-emphasis method is to keep the amplitude of the high-frequency signal unchanged, reduce the amplitude of the low-frequency signal, thereby reducing the low-frequency components in the signal and increasing the high-frequency components. By performing de-emphasis processing on the portion of the target data signal output after 1 UI, the high-frequency components within 1 UI remain unchanged, while the low-frequency components after 1 UI are reduced, thus increasing the proportion of high-frequency components, achieving a balancing effect, and reducing the impact of channel loss on signal quality.

[0065] As can be seen from the timing diagram in Figure 2, the second driving module 30 performs de-emphasis processing on both the pull-up and pull-down directions of the target data signal. Furthermore, the de-emphasis amplitude is essentially the same in both directions, ensuring that the common-mode level of the target data signal remains unchanged. Changes in the common-mode level affect signal detection at the receiver, leading to signal distortion and potentially increasing signal reflection. Therefore, the de-emphasis method of this invention aims to maintain a relatively consistent de-emphasis amplitude in both the pull-up and pull-down directions to ensure that the common-mode level of the target data signal does not change.

[0066] The parallel-to-serial converter 40 processes the initial data signal from parallel to serial, generating a high-frequency full-speed signal, including the data signal to be processed and an auxiliary data signal. The auxiliary data signal is delayed by 1 UI compared to the data signal to be processed. It's important to understand that this 1 UI delay is not an absolute delay, but a relative delay, and the delay value differs at different frequencies. This is done to effectively distinguish and de-emphasize low-frequency components at different frequencies, achieving an ideal equalization effect for the signal at various frequencies.

[0067] In some embodiments, referring to FIG3, the parallel-to-serial conversion module 40 includes a first parallel-to-serial conversion module 41 and a second parallel-to-serial conversion module 42; the initial data signal includes N sub-initial data signals; wherein,

[0068] The first parallel-to-serial converter 41 includes N input terminals and N clock terminals. The i-th input terminal receives the i-th sub-initial data signal, the N-th input terminal receives the N-th sub-initial data signal, the i-th clock terminal receives the i-th clock signal, and the N-th clock terminal receives the N-th clock signal. It is configured to output the signal of the j-th input terminal as 1 bit of data in the data signal to be processed when the signal received at the j-th clock terminal is in an active state.

[0069] The second parallel-to-serial converter 42 includes N input terminals and N clock terminals. The i-th input terminal receives the i-th sub-initial data signal, the N-th input terminal receives the N-th sub-initial data signal, the i-th clock terminal receives the (i+1)-th clock signal, and the N-th clock terminal receives the 1-th clock signal. It is configured to output the signal of the j-th input terminal as 1 bit of data in the auxiliary data signal when the signal received at the j-th clock terminal is in an active state.

[0070] Wherein, the phase difference between the (i+1)th clock signal and the i-th clock signal is 360 degrees / N;

[0071] Where i, j, and N are all positive integers, N>1, 1≤i <N,1≤j≤N。

[0072] Understandably, the first parallel-to-serial converter 41 receives N initial data signals through N input terminals and, under the control of N clock signals, converts the parallel N initial data signals into a serial data signal to be processed. The second parallel-to-serial converter 42 also receives N initial data signals through N input terminals and, under the control of N clock signals, converts the parallel N initial data signals into a serial auxiliary data signal. By controlling the clock signals received by the N clock terminals of the first and second parallel-to-serial converters 41 and 42 to have the aforementioned phase difference, the auxiliary data signal is delayed by 1 μs compared to the data signal to be processed.

[0073] In some embodiments, referring to FIG3, N=4. In this case, the first parallel-to-serial module 41 includes four input terminals and four clock terminals. The first input terminal receives the first sub-initial data signal I0, the second input terminal receives the second sub-initial data signal I1, the third input terminal receives the third sub-initial data signal I2, and the fourth input terminal receives the fourth sub-initial data signal I3. The first clock terminal receives the first clock signal ICLK, the second clock terminal receives the second clock signal QCLK, the third clock terminal receives the third clock signal IBCLK, and the fourth clock terminal receives the fourth clock signal QBCLK. The first clock signal ICLK, the second clock signal QCLK, the third clock signal IBCLK, and the fourth clock signal QBCLK are sequentially 90 degrees apart, and their duty cycles are all 25%. The pulse width of each active state is 1UI, and their active pulses do not overlap. In this way, when the clock signal received at each clock terminal is in an active state, the signal received at the corresponding input terminal is output as 1 bit of data in the data signal to be processed, which can realize the conversion of the parallel initial data signal into a serial data signal to be processed.

[0074] The second parallel-to-serial converter 42 includes four input terminals and four clock terminals. The first input terminal receives the first sub-initial data signal I0, the second input terminal receives the second sub-initial data signal I1, the third input terminal receives the third sub-initial data signal I2, and the fourth input terminal receives the fourth sub-initial data signal I3. The first clock terminal receives the second clock signal QCLK, the second clock terminal receives the third clock signal IBCLK, the third clock terminal receives the fourth clock signal QBCLK, and the fourth clock terminal receives the first clock signal ICLK. Thus, when the clock signal received at each clock terminal is valid, the signal received at the corresponding input terminal is output as 1 bit of data in the auxiliary data signal, enabling the conversion of parallel initial data signals into serial auxiliary data signals. The four clock terminals of the first parallel-to-serial converter 41 receive ICLK, QCLK, IBCLK and QBCLK in sequence, respectively. The four clock terminals of the second parallel-to-serial converter 42 receive QCLK, IBCLK, QBCLK and ICLK in sequence, respectively. Since the data output after parallel-to-serial conversion carries the corresponding clock phase information, this setting allows the auxiliary data signal to be delayed by 1UI compared to the data signal to be processed.

[0075] Referring to Figure 4, which illustrates a signal timing diagram according to an embodiment of this disclosure, the first sub-initial data signal I0 may include data D0, D4, D8, and D12; the second sub-initial data signal I1 may include data D1, D5, D9, and D13; the third sub-initial data signal I2 may include data D2, D6, D10, and D14; and the fourth sub-initial data signal I3 may include data D3, D7, D11, and D15. These parallel sub-initial data signals I0, I1, I2, and I3 together constitute the initial data signal. The first clock signal ICLK, the second clock signal QCLK, the third clock signal IBCLK, and the fourth clock signal QBCLK are sequentially 90 degrees apart, and their duty cycles are all 25%. The pulse width of each active state is 1UI, and their active pulses do not overlap. Here, an active state can refer to a signal being in a high-level state.

[0076] Referring to Figures 3 and 4, the four input terminals of the first parallel-to-serial module 41 receive I0, I1, I2 and I3 in sequence, and the four clock terminals receive ICLK, QCLK, IBCLK and QBCLK in sequence. When the clock signal received at each clock terminal is in an active state, the corresponding input terminal receives the signal as 1 bit of data in the data signal to be processed. As shown in Figure 4, the first high-level pulse of the first clock signal ICLK outputs data D0, the second high-level pulse outputs data D4, the third high-level pulse outputs data D8, and the fourth high-level pulse outputs data D12; the first high-level pulse of the second clock signal QCLK outputs data D1, the second high-level pulse outputs data D5, the third high-level pulse outputs data D9, and the fourth high-level pulse outputs data D13; the first high-level pulse of the third clock signal IBCLK outputs data D2, the second high-level pulse outputs data D6, the third high-level pulse outputs data D10, and the fourth high-level pulse outputs data D14; and the first high-level pulse of the fourth clock signal QBCLK outputs data D3, the second high-level pulse outputs data D7, the third high-level pulse outputs data D11, and the fourth high-level pulse outputs data D15. These are combined to form a serial data signal to be processed. The second parallel-to-serial converter 42 has four input terminals that receive I0, I1, I2, and I3 sequentially, and four clock terminals that receive QCLK, IBCLK, QBCLK, and ICLK sequentially. When the clock signal received at each clock terminal is valid, the corresponding input terminal receives the signal as 1 bit of data in the auxiliary data signal. As shown in Figure 4, the first clock terminal of the second parallel-to-serial converter 42 receives the second clock signal QCLK. The first high-level pulse of QCLK outputs data D0, the second high-level pulse outputs data D4, the third high-level pulse outputs data D8, and the fourth high-level pulse outputs data D12. The second clock terminal receives the third clock signal IBCLK. The first high-level pulse of IBCLK outputs data D1, the second high-level pulse outputs data D5, the third high-level pulse outputs data D9, and the fourth high-level pulse outputs data D13. The third clock input receives the fourth clock signal QBCLK. The first high-level pulse of QBCLK outputs data D2, the second high-level pulse outputs data D6, the third high-level pulse outputs data D10, and the fourth high-level pulse outputs data D14. The fourth clock input receives the first clock signal ICLK. The first high-level pulse of ICLK outputs data D3, the second high-level pulse outputs data D7, the third high-level pulse outputs data D11, and the fourth high-level pulse outputs data D15. These are combined to form a serial auxiliary data signal. As shown in Figure 4, since the data output after parallel-to-serial conversion carries the corresponding clock phase information, the auxiliary data signal is delayed by 1UI compared to the data signal to be processed.

[0077] In some embodiments, continuing to refer to FIG3, the first parallel-to-serial conversion module 41 includes N main switch units, and the second parallel-to-serial conversion module 42 includes N auxiliary switch units; wherein...

[0078] The input terminal of the j-th main switch unit is connected to the j-th input terminal of the first parallel-to-serial module 41, and the control terminal is connected to the j-th clock terminal of the first parallel-to-serial module 41. It is configured to transmit the signal received at the input terminal to the output terminal when the signal received at the control terminal is in an effective state. The output terminals of the N main switch units are all connected to the output terminal of the first parallel-to-serial module 41.

[0079] The input terminal of the j-th auxiliary switch unit is connected to the j-th input terminal of the second parallel-to-serial module 42, and the control terminal is connected to the j-th clock terminal of the second parallel-to-serial module 42. It is configured to transmit the signal received at the input terminal to the output terminal when the signal received at the control terminal is in an active state. The output terminals of the N auxiliary switch units are all connected to the output terminal of the second parallel-to-serial module 42.

[0080] As shown in Figure 3, taking N=4 as an example, the first parallel-to-serial conversion module 41 includes four main switch units. The input terminal of the first main switch unit 411 is connected to the first input terminal of the first parallel-to-serial conversion module 41, that is, it receives the first sub-initial data signal I0, and the control terminal is connected to the first clock terminal of the first parallel-to-serial conversion module 41, that is, it receives the first clock signal ICLK; the input terminal of the second main switch unit 412 is connected to the second input terminal of the first parallel-to-serial conversion module 41, that is, it receives the second sub-initial data signal I1, and the control terminal is connected to the second clock terminal of the first parallel-to-serial conversion module 41, that is, it receives the second clock signal QCLK; the third main switch unit... The input terminal of 413 is connected to the third input terminal of the first parallel-to-serial module 41, that is, to receive the third sub-initial data signal I2. The control terminal is connected to the third clock terminal of the first parallel-to-serial module 41, that is, to receive the third clock signal IBCLK. The input terminal of the fourth main switch unit 414 is connected to the fourth input terminal of the first parallel-to-serial module 41, that is, to receive the fourth sub-initial data signal I3. The control terminal is connected to the fourth clock terminal of the first parallel-to-serial module 41, that is, to receive the fourth clock signal QBCLK. The output terminals of the four main switch units are connected together as the output terminal of the first parallel-to-serial module 41, which outputs the serial data signal to be processed.

[0081] The second parallel-to-serial converter 42 includes four sub-switching units. The input terminal of the first sub-switching unit 421 is connected to the first input terminal of the second parallel-to-serial converter 42, i.e., receiving the first sub-initial data signal I0, and its control terminal is connected to the first clock terminal of the second parallel-to-serial converter 42, i.e., receiving the second clock signal QCLK. The input terminal of the second sub-switching unit 422 is connected to the second input terminal of the second parallel-to-serial converter 42, i.e., receiving the second sub-initial data signal I1, and its control terminal is connected to the second clock terminal of the second parallel-to-serial converter 42, i.e., receiving the third clock signal IBCLK. The input terminal of the third sub-switching unit 423 is... The first input terminal of the second parallel-to-serial converter 424 is connected to the third input terminal of the second parallel-to-serial converter 42, which is to receive the third initial data signal I2. The control terminal is connected to the third clock terminal of the second parallel-to-serial converter 42, which is to receive the fourth clock signal QBCLK. The input terminal of the fourth auxiliary switch unit 424 is connected to the fourth input terminal of the second parallel-to-serial converter 42, which is to receive the fourth initial data signal I3. The control terminal is connected to the fourth clock terminal of the second parallel-to-serial converter 42, which is to receive the first clock signal ICLK. The output terminals of the four auxiliary switch units are connected together as the output terminal of the second parallel-to-serial converter 42, which outputs a serial auxiliary data signal.

[0082] In some embodiments, continuing to refer to FIG3, each main switch unit includes a first NAND gate NAND1, a first NOR gate NOR1, a first PMOS (P1), and a first NMOS (N1); the first input terminal of the first NAND gate NAND1 is connected to the control terminal of the main switch unit, the second input terminal is connected to the input terminal of the main switch unit, and the output terminal is connected to the gate of the first PMOS; the first input terminal of the first NOR gate NOR1 is connected to the input terminal of the main switch unit, the signal received at the second input terminal is inverted with the signal at the first input terminal of the first NAND gate NAND1, and the output terminal is connected to the gate of the first NMOS; the source of the first PMOS is connected to the power supply terminal, and the drain is connected to the output terminal of the main switch unit; the source of the first NMOS is grounded, and the drain is connected to the output terminal of the main switch unit;

[0083] Each sub-switching unit includes a second NAND gate NAND2, a second NOR gate NOR2, a second PMOS (P2), and a second NMOS (N2). The first input of the second NAND gate NAND2 is connected to the control terminal of the sub-switching unit, the second input is connected to the input terminal of the sub-switching unit, and the output is connected to the gate of the second PMOS. The first input of the second NOR gate NOR2 is connected to the input terminal of the sub-switching unit, the signal received at the second input is inverted with the signal at the first input terminal of the second NAND gate NAND2, and the output is connected to the gate of the second NMOS. The source of the second PMOS is connected to the power supply terminal, and the drain is connected to the output terminal of the sub-switching unit. The source of the second NMOS is grounded, and the drain is connected to the output terminal of the sub-switching unit.

[0084] As shown in Figure 3, taking N=4 as an example, in the first main switch unit 411, the first input terminal of the first NAND gate NAND1 receives the first clock signal ICLK, and the second input terminal receives the first sub-initial data signal I0; the first input terminal of the first NOR gate NOR1 receives the first sub-initial data signal I0, and the second input terminal receives the inverted signal ICLKB of the first clock signal ICLK. When ICLK is low, ICLKB is high. At this time, NAND1 outputs a high level, NOR1 outputs a low level, P1 and N1 are both turned off, and have no driving effect on the output terminal of the first main switch unit. When ICLK is high, ICLKB is low. If I0 is high, NAND1 and NOR1 output low, P1 is on, N1 is off, and the output of the first main switch unit is pulled high. If I0 is low, NAND1 and NOR1 output high, P1 is off, N1 is on, and the output of the first main switch unit is pulled low. With this configuration, when ICLK is high, the first initial data signal I0 is transmitted to the output of the main switch unit as 1 bit of data in the data signal to be processed. The working principles of the second main switch unit 412, the third main switch unit 413, and the fourth main switch unit 414 are similar and will not be described further. As shown in the waveform diagram in Figure 4, the effective pulses of ICLK, QCLK, IBCLK, and QBCLK do not overlap. Therefore, when one of the main switch units is working and outputting the data signal to be processed, P1 and N1 in the other three main switch units are turned off and do not drive the output. In this way, parallel-to-serial conversion can be performed without affecting the quality of the data signal.

[0085] In the first auxiliary switching unit 421, the first input of the second NAND gate NAND2 receives the second clock signal QCLK, and the second input receives the first sub-initial data signal I0; the first input of the second NOR gate NOR2 receives the first sub-initial data signal I0, and the second input receives the inverted signal QCLKB of the second clock signal QCLK. When QCLK is low, QCLKB is high. At this time, NAND2 outputs a high level, NOR2 outputs a low level, P2 and N2 are both turned off, and have no driving effect on the output of the first auxiliary switching unit. When QCLK is high, QCLKB is low. If I0 is high, NAND2 and NOR2 output low, P2 is on, N2 is off, and the output of the first auxiliary switch unit is pulled high. If I0 is low, NAND2 and NOR2 output high, P2 is off, N2 is on, and the output of the first auxiliary switch unit is pulled low. With this configuration, when QCLK is high, the first initial data signal I0 can be transmitted to the output of the auxiliary switch unit as 1 bit of data in the auxiliary data signal. The operating principles of the second auxiliary switch unit 422, the third auxiliary switch unit 423, and the fourth auxiliary switch unit 424 are similar and will not be described further. As shown in the waveform diagram in Figure 4, the effective pulses of ICLK, QCLK, IBCLK, and QBCLK do not overlap. Therefore, when one of the auxiliary switching units is working and outputs an auxiliary data signal, P2 and N2 in the other three auxiliary switching units are turned off and do not drive the output. In this way, parallel-to-serial conversion can be performed without affecting the quality of the data signal.

[0086] In some embodiments, as shown in FIG3, the parallel-to-serial conversion module 40 further includes a first compensation module 43 and a second compensation module 44; the first compensation module 43 is electrically connected to the output terminal of the first parallel-to-serial conversion module 41 and is used to enhance the amplitude of the data signal to be processed; the second compensation module 44 is electrically connected to the output terminal of the second parallel-to-serial conversion module 42 and is used to enhance the amplitude of the auxiliary data signal. The first compensation module 43 and the second compensation module 44 can be implemented by an odd number of inverters connected in series.

[0087] In some embodiments, as shown in FIG5, the first driving module 20 includes a first control unit 22 and a first driver 21; wherein, the first control unit 22 receives a data signal to be processed and generates a first pull-up control signal and a first pull-down control signal with the same phase, the first pull-up control signal being out of phase with the data signal to be processed; the first driver 21 includes a first pull-up unit 211 and a first pull-down unit 212; the control terminal of the first pull-up unit receives the first pull-up control signal, the first terminal is connected to the power supply terminal, and the second terminal is connected to the data port DQ; the control terminal of the first pull-down unit 212 receives the first pull-down control signal, the first terminal is connected to the data port DQ, and the second terminal is grounded.

[0088] In some embodiments, as shown in FIG5, the first pull-up unit 211 is composed of several PMOS transistors, whose gates receive the first pull-up control signal, whose sources are connected to the power supply terminal, and whose drains are all connected to the data port DQ; the first pull-down unit 212 is composed of several NMOS transistors, whose gates receive the first pull-down control signal, whose sources are grounded, and whose drains are all connected to the data port DQ. The first control unit 22 may include two sets of odd-numbered inverters. The data signal to be processed passes through one set of odd-numbered inverters (5 inverters are shown in FIG5) to generate the first pull-up control signal, and passes through the other set of odd-numbered inverters to generate the first pull-down control signal. A reasonable setting of the size of the odd-numbered inverters can also enhance the driving capability of the first pull-up control signal and the first pull-down control signal. If the data signal to be processed is high, both the first pull-up control signal and the first pull-down control signal are low. The PMOS transistors in the first pull-up unit 211 are all turned on, and the NMOS transistors in the first pull-down unit 212 are all turned off, outputting a high-level target data signal at the data port DQ. If the data signal to be processed is low, both the first pull-up control signal and the first pull-down control signal are high. Several PMOS transistors in the first pull-up unit 211 are turned off, and several NMOS transistors in the first pull-down unit 212 are turned on, outputting a low-level target data signal at the data port DQ. The dimensions of the PMOS transistors in the first pull-up unit 211 and the NMOS transistors in the first pull-down unit 212 can be set according to actual requirements to ensure the driving capability of the target data signal. It is understood that the size and type of the first pull-up unit 211 and the first pull-down unit 212, as well as the logic circuit in the first control unit 22, can be designed according to actual conditions, as long as the target data signal can be output correctly and the driving capability is guaranteed.

[0089] In some embodiments, as shown in FIG5, the second drive module 30 includes a second control unit 32 and a second driver 31; wherein, the second control unit 32 is electrically connected to the parallel-to-serial module 40 and the first drive module 20, and is configured to generate a valid second pull-down control signal when both the data signal to be processed and the auxiliary data signal are at a high level; and to generate a valid second pull-up control signal when both the data signal to be processed and the auxiliary data signal are at a low level; the second driver 31 includes a second pull-up unit 311 and a second pull-down unit 312; the control terminal of the second pull-up unit 311 receives the second pull-up control signal, the first terminal is connected to the power supply terminal, and the second terminal is connected to the data port DQ; the control terminal of the second pull-down unit 312 receives the second pull-down control signal, the first terminal is connected to the data port DQ, and the second terminal is grounded.

[0090] For example, referring to Figure 6, the auxiliary data signal is delayed by 1 UI compared to the data signal to be processed. When both the data signal to be processed and the auxiliary data signal are at a high level, a second pull-down control signal with an effective state is generated. Here, the effective state of the second pull-down control signal is a high level state, which controls the second pull-down unit 312 to work and pull down the target data signal. That is, after the target data signal changes from a low level to a high level by 1 UI, the target data signal is pulled down by a certain amount, which plays a role in de-emphasis. When both the data signal to be processed and the auxiliary data signal are at a low level, a second pull-up control signal with an effective state is generated. Here, the effective state of the second pull-up control signal is a low level state, which controls the second pull-up unit 311 to work and pull up the target data signal. That is, after the target data signal changes from a high level to a low level by 1 UI, the target data signal is pulled up by a certain amount, which plays a role in de-emphasis. This configuration de-emphasizes the portion of the target data signal output after 1 UI, ensuring that the high-frequency components within 1 UI remain unchanged while reducing the low-frequency components after 1 UI. This increases the proportion of high-frequency components, achieving a balancing effect and reducing the impact of channel loss on signal quality.

[0091] In some embodiments, as shown in FIG5, the second control unit 32 includes a first OR gate OR1 and a first AND gate AND1, the second pull-up unit 311 is composed of a plurality of PMOS, and the second pull-down unit 312 is composed of a plurality of NMOS; wherein, the first terminal of the first OR gate OR1 receives the data signal to be processed, the second terminal receives the auxiliary data signal, and the output terminal outputs the second pull-up control signal; the first terminal of the first AND gate AND1 receives the data signal to be processed, the second terminal receives the auxiliary data signal, and the output terminal outputs the second pull-down control signal.

[0092] As shown in Figure 5, the second pull-up unit 311 consists of several PMOS transistors, whose gates receive the second pull-up control signal, their sources are connected to the power supply, and their drains are all connected to the data port DQ. The second pull-down unit 312 consists of several NMOS transistors, whose gates receive the second pull-down control signal, their sources are grounded, and their drains are all connected to the data port DQ. The number and size of the PMOS transistors in the second pull-up unit 311, and the number and size of the NMOS transistors in the second pull-down unit 312, need to be designed according to the de-emphasis amplitude to ensure reasonable de-emphasis and to ensure that the de-emphasis amplitude in the pull-up and pull-down directions is basically the same, thus ensuring that the common-mode level of the target data signal does not change.

[0093] The second pull-up control signal output by the first OR gate OR1 is low only when both the data signal to be processed and the auxiliary data signal received by the first OR gate OR1 are low. At this time, the PMOS in the second pull-up unit 311 is turned on, pulling up the target data signal by a certain amplitude. Similarly, the second pull-down control signal output by the first AND gate AND1 is high only when both the data signal to be processed and the auxiliary data signal received by the first AND gate AND1 are high. At this time, the NMOS in the second pull-down unit 312 is turned on, pulling down the target data signal by a certain amplitude. This configuration de-emphasizes the portion of the target data signal output after 1UI, ensuring that the high-frequency components within 1UI remain unchanged while reducing the low-frequency components after 1UI. This increases the proportion of high-frequency components, achieving a balancing effect and reducing the impact of channel loss on signal quality.

[0094] As shown in Figure 5, both the data signal to be processed and the auxiliary data signal pass through two inverters before reaching the first OR gate (OR1) and the first AND gate (AND1). This configuration enhances the signal driving capability and can also match the delays of different paths. It is understandable that it would be logically reasonable to omit the inverters or to use an even number of inverters here.

[0095] In some embodiments, as shown in FIG7, the second pull-up control signal includes M sub-signals, and the second pull-down control signal includes M sub-signals; the second pull-up unit 311 includes M pull-up sub-units, and the control terminal of the x-th pull-up sub-unit receives the x-th sub-signal of the second pull-up control signal; the second pull-down unit 312 includes M pull-down sub-units, and the control terminal of the x-th pull-down sub-unit receives the x-th sub-signal of the second pull-down control signal; wherein, the second control unit 32 also receives M pull-up adjustment signals and M pull-down adjustment signals, and is configured such that when both the data signal to be processed and the auxiliary data signal are high level and the x-th pull-down adjustment signal is in an active state, the x-th sub-signal of the second pull-down control signal is in an active state; when both the data signal to be processed and the auxiliary data signal are low level and the x-th pull-up adjustment signal is in an active state, the x-th sub-signal of the second pull-up control signal is in an active state.

[0096] Where x and M are both positive integers, and 1 ≤ x ≤ M.

[0097] It should be noted that, compared to the embodiment in Figure 5, the de-emphasis capability of the pull-up and pull-down modules 30 in the embodiment shown in Figure 7 is adjustable. M pull-up adjustment signals and M pull-down adjustment signals are used to control the validity of the state of each sub-signal in the second pull-up control signal and the second pull-down control signal, thereby controlling whether each pull-up sub-unit in the second pull-up unit 311 and each pull-down sub-unit in the second pull-down unit 312 functions, thus controlling the de-emphasis capability of the pull-up and pull-down modules. The M pull-up adjustment signals and M pull-down adjustment signals can be determined through training during testing. The advantage of this is that it ensures that the amplitudes of the pull-up and pull-down are basically consistent during de-emphasis, thus not changing the common-mode level of the target data signal; and it also allows for the determination of the most suitable M pull-up adjustment signals and M pull-down adjustment signals through testing and training under different channel conditions and process angles, enabling the second drive module 30 to achieve the best equalization effect and avoiding over-compensation or under-compensation. After the testing and training process was completed, the most suitable M pull-up adjustment signals and M pull-down adjustment signals were found, which can be fixed by fuses.

[0098] As shown in Figure 7, taking M=3 as an example, the second pull-up control signal includes three sub-signals PU2, PU1, and PU0, and the second pull-down control signal includes three sub-signals PD2, PD1, and PD0; the second pull-up unit 311 includes three pull-up sub-units 3111, 3112, and 3113. The control terminal of the first pull-up sub-unit 3111 receives the first sub-signal PU0 of the second pull-up control signal, the control terminal of the second pull-up sub-unit 3112 receives the second sub-signal PU1 of the second pull-up control signal, and the third... The control terminal of pull-up sub-unit 3113 receives the third sub-signal PU2 of the second pull-up control signal; the second pull-down unit 312 includes three pull-down sub-units 3121, 3122, and 3123. The control terminal of the first pull-down sub-unit 3121 receives the first sub-signal PD0 of the second pull-down control signal, the control terminal of the second pull-down sub-unit 3122 receives the second sub-signal PD1 of the second pull-down control signal, and the control terminal of the third pull-down sub-unit 3123 receives the third sub-signal PD2 of the second pull-down control signal. Each pull-up sub-unit includes a PMOS, with its gate receiving the corresponding sub-signal in the second pull-up control signal, its source connected to the power supply terminal, and its drain connected to the data port DQ. Each pull-down sub-unit includes an NMOS, with its gate receiving the corresponding sub-signal in the second pull-down control signal, its source grounded, and its drain connected to the data port DQ.

[0099] The second control unit 32 receives three pull-up adjustment signals, namely Pu_code0, Pu_code1, and Pu_code2; and three pull-down adjustment signals, namely Pd_code0, Pd_code1, and Pd_code2. When both the data signal to be processed and the auxiliary data signal are at a low level, if the first pull-up adjustment signal Pu_code0 is valid, then the first sub-signal PU0 of the second pull-up control signal is valid; if the second pull-up adjustment signal Pu_code1 is valid, then the second sub-signal PU1 of the second pull-up control signal is valid; if the third pull-up adjustment signal Pu_code2 is valid, then the third sub-signal PU2 of the second pull-up control signal is valid. The valid sub-signals control the corresponding pull-up sub-units to work, thus pulling up the target data signal. When both the data signal to be processed and the auxiliary data signal are high, if the first pull-down adjustment signal Pd_code0 is valid, then the first sub-signal PD0 of the second pull-down control signal is valid; if the second pull-down adjustment signal Pd_code1 is valid, then the second sub-signal PD1 of the second pull-down control signal is valid; if the third pull-down adjustment signal Pd_code2 is valid, then the third sub-signal PD2 of the second pull-down control signal is valid. The valid sub-signals control the corresponding pull-down sub-units to work, thus pulling down the target data signal.

[0100] In testing, the number of active pull-up and pull-down sub-units was adjusted by modifying the pull-up adjustment signals Pu_code0, Pu_code1, and Pu_code2, as well as the pull-down adjustment signals Pd_code0, Pd_code1, and Pd_code2. This configuration allows adjustment of the pull-up and pull-down amplitudes during de-emphasis, ensuring that the amplitudes remain essentially consistent and thus preserving the common-mode level of the target data signal. Furthermore, under different channel conditions and process angles, the optimal three pull-up and three pull-down adjustment signals can be determined through testing and training, enabling the second drive module 30 to achieve the best equalization effect and avoiding over-compensation or under-compensation. This reduces the impact of channel loss on signal quality, effectively guaranteeing the speed and transmission quality of the output data.

[0101] In some embodiments, as shown in FIG7, the second control unit 32 includes a third NOR gate NOR3, a fourth NOR gate NOR4, M third NAND gates NAND3, and M second AND gates AND2; wherein, the first input terminal of the third NOR gate NOR3 receives the data signal to be processed, and the second input terminal receives the auxiliary data signal; the first input terminal of the xth third NAND gate NAND3 is connected to the output terminal of the third NOR gate NOR3, the second input terminal receives the xth pull-up adjustment signal, and the output terminal outputs the xth sub-signal of the second pull-up control signal; the first input terminal of the fourth NOR gate NOR4 receives the inverted signal of the data signal to be processed, and the second input terminal receives the inverted signal of the auxiliary data signal; the first input terminal of the xth second AND gate AND2 is connected to the output terminal of the fourth NOR gate NOR4, the second input terminal receives the xth pull-down adjustment signal, and the output terminal outputs the xth sub-signal of the second pull-down control signal. This logic setting allows the xth sub-signal of the second pull-down control signal to be high when both the pending data signal and the auxiliary data signal are high, thereby turning on the corresponding NMOS; and when both the pending data signal and the auxiliary data signal are low, and the xth pull-up adjustment signal is high, the xth sub-signal of the second pull-up control signal to be low, thereby turning on the corresponding PMOS.

[0102] Referring again to Figure 7, taking M=3 as an example, the first input of the third NOR gate NOR3 receives the data signal to be processed through two inverters, and the second input also receives the auxiliary data signal through two inverters, thus increasing the driving capability of the data signal to be processed and the auxiliary data signal. The first inputs of the three NAND gates are all connected to the outputs of the NOR3. The second input of the first NAND3 receives Pu_code0 and outputs PU0; the second input of the second NAND3 receives Pu_code1 and outputs PU1; and the second input of the third NAND3 receives Pu_code2 and outputs PU2. When both the data signal to be processed and the auxiliary data signal are low, the NOR3 outputs a high level. If Pu_code0 is active (high level is valid), the first NAND3 output PU0 is low, corresponding to turning on the PMOS in the first pull-up sub-unit 3111. If Pu_code1 is high, the second NAND3 output PU1 is low, corresponding to turning on the PMOS in the second pull-up sub-unit 3112. If Pu_code2 is high, the third NAND3 output PU2 is low, corresponding to turning on the PMOS in the third pull-up sub-unit 3113. This configuration controls the pull-up capability of the second drive module 30 for the target data signal by adjusting the levels of the pull-up adjustment signals Pu_code0, Pu_code1, and Pu_code2.

[0103] The first input of the fourth NOR gate (NOR4) receives the inverted signal of the data signal to be processed through an inverter, and the second input also receives the inverted signal of the auxiliary data signal through an inverter. The first inputs of the three AND2 gates are all connected to the outputs of the NOR4. The second input of the first AND2 gate receives Pd_code0 and outputs PD0; the second input of the second AND2 gate receives Pd_code1 and outputs PD1; and the second input of the third AND2 gate receives Pd_code2 and outputs PD2. The NOR4 gate outputs a high level when both the data signal to be processed and the auxiliary data signal are high. If Pd_code0 is active (high level is valid), the first AND2 output PD0 is high, corresponding to turning on the NMOS in the first pull-down subunit 3121. If Pd_code1 is high, the second AND2 output PD1 is high, corresponding to turning on the NMOS in the second pull-down subunit 3122. If Pd_code2 is high, the third AND2 output PD2 is high, corresponding to turning on the NMOS in the third pull-down subunit 3123. This configuration controls the pull-down capability of the second drive module 30 for the target data signal by adjusting the levels of the pull-down adjustment signals Pd_code0, Pd_code1, and Pd_code2.

[0104] This embodiment provides a data processing circuit, which includes a parallel-to-serial converter module for receiving an initial data signal, performing parallel-to-serial conversion on the initial data signal, and generating a data signal to be processed and an auxiliary data signal. The initial data signal is a parallel data signal, while the data signal to be processed and the auxiliary data signal are both serial data signals, with the auxiliary data signal delayed by one unit time interval compared to the data signal to be processed. A first driving module, electrically connected to the data port and the parallel-to-serial converter module, receives the data signal to be processed, enhances the driving capability of the data signal to be processed, and outputs a target data signal to the data port. A second driving module, electrically connected to the data port, the parallel-to-serial converter module, and the first driving module, receives the data signal to be processed and the auxiliary data signal, and performs de-emphasis processing on the target data signal when the potentials of the data signal to be processed and the auxiliary data signal are the same. In this way, the initial data signal is processed into a data signal to be processed and an auxiliary data signal that are separated by a unit time interval. When the potentials of the data signal to be processed and the auxiliary data signal are the same, the target data signal is de-emphasized, so that the target data signal can achieve a good equalization effect under different operating frequencies, process angles and channel conditions. This can reduce the impact of channel loss on signal quality and effectively ensure the speed and transmission quality of the output data.

[0105] In another embodiment of this disclosure, referring to FIG8, a schematic diagram of the composition structure of a semiconductor memory 50 provided in an embodiment of this disclosure is shown. As shown in FIG8, the semiconductor memory 50 may include at least the data processing circuit 10 described in any of the foregoing embodiments.

[0106] In some embodiments, the semiconductor memory 50 is a dynamic random access memory (DRAM) chip and conforms to the DDR5 memory specification.

[0107] In this embodiment of the disclosure, since the semiconductor memory 50 includes the aforementioned data processing circuit 10, the semiconductor memory can be adapted to higher memory specifications, such as DDR4 / LPDDR4, DDR5 / LPDDR5, or DDR6 / LPDDR6. By performing de-emphasis processing on the target data signal, the target data signal can achieve a good equalization effect under different operating frequencies, process angles, and channel conditions. This can reduce the impact of channel loss on signal quality and effectively ensure the speed and transmission quality of the output data.

[0108] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0109] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0110] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0111] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0112] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0113] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0114] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A data processing circuit, characterized in that, include: The parallel-to-serial conversion module is used to receive an initial data signal, perform parallel-to-serial conversion on the initial data signal, and generate a data signal to be processed and an auxiliary data signal; wherein, the initial data signal is a parallel data signal, the data signal to be processed and the auxiliary data signal are both serial data signals, and the auxiliary data signal is delayed by one unit time interval compared to the data signal to be processed; The first driving module is electrically connected to the data port and the parallel-to-serial conversion module, and is used to receive the data signal to be processed, enhance the driving capability of the data signal to be processed, and output the target data signal to the data port. The second driving module is electrically connected to the data port, the parallel-to-serial converter and the first driving module, and is used to receive the data signal to be processed and the auxiliary data signal. When the potentials of the data signal to be processed and the auxiliary data signal are the same, the target data signal is de-emphasized.

2. The data processing circuit according to claim 1, characterized in that, The parallel-to-serial conversion module includes a first parallel-to-serial conversion module and a second parallel-to-serial conversion module; the initial data signal includes N sub-initial data signals; wherein... The first parallel-to-serial converter includes N input terminals and N clock terminals. The i-th input terminal receives the i-th sub-initial data signal, the N-th input terminal receives the N-th sub-initial data signal, the i-th clock terminal receives the i-th clock signal, and the N-th clock terminal receives the N-th clock signal. It is configured to output the signal of the j-th input terminal as 1 bit of data in the data signal to be processed when the signal received at the j-th clock terminal is in an active state. The second parallel-to-serial converter includes N input terminals and N clock terminals. The i-th input terminal receives the i-th sub-initial data signal, the N-th input terminal receives the N-th sub-initial data signal, the i-th clock terminal receives the (i+1)-th clock signal, and the N-th clock terminal receives the 1-th clock signal. It is configured to output the signal of the j-th input terminal as 1 bit of data in the auxiliary data signal when the signal received at the j-th clock terminal is in an active state. Wherein, the phase difference between the (i+1)th clock signal and the i-th clock signal is 360 degrees / N; Where i, j, and N are all positive integers, N>1, 1≤i <N,1≤j≤N。 3. The data processing circuit according to claim 2, characterized in that, The first parallel-to-serial conversion module includes N main switch units, and the second parallel-to-serial conversion module includes N auxiliary switch units; wherein, The input terminal of the j-th main switch unit is connected to the j-th input terminal of the first parallel-to-serial module, and the control terminal is connected to the j-th clock terminal of the first parallel-to-serial module. It is configured to transmit the signal received by the input terminal to the output terminal when the signal received by the control terminal is in an active state. The output terminals of the N main switch units are all connected to the output terminal of the first parallel-to-serial module. The input terminal of the j-th auxiliary switch unit is connected to the j-th input terminal of the second parallel-to-serial module, and the control terminal is connected to the j-th clock terminal of the second parallel-to-serial module. It is configured to transmit the signal received by the input terminal to the output terminal when the signal received by the control terminal is in an active state. The output terminals of the N auxiliary switch units are all connected to the output terminal of the second parallel-to-serial module.

4. The data processing circuit according to claim 3, characterized in that, N=4。 5. The data processing circuit according to claim 3, characterized in that, Each of the main switching units includes a first NAND gate, a first NOR gate, a first PMOS, and a first NMOS; the first input terminal of the first NAND gate is connected to the control terminal of the main switching unit, the second input terminal is connected to the input terminal of the main switching unit, and the output terminal is connected to the gate of the first PMOS; the first input terminal of the first NOR gate is connected to the input terminal of the main switching unit, the signal received at the second input terminal is inverted with the signal at the first input terminal of the first NAND gate, and the output terminal is connected to the gate of the first NMOS; the source of the first PMOS is connected to the power supply terminal, and the drain is connected to the output terminal of the main switching unit; the source of the first NMOS is grounded, and the drain is connected to the output terminal of the main switching unit. Each of the sub-switching units includes a second NAND gate, a second NOR gate, a second PMOS, and a second NMOS; the first input terminal of the second NAND gate is connected to the control terminal of the sub-switching unit, the second input terminal is connected to the input terminal of the sub-switching unit, and the output terminal is connected to the gate of the second PMOS; the first input terminal of the second NOR gate is connected to the input terminal of the sub-switching unit, the signal received at the second input terminal is inverted with the signal at the first input terminal of the second NAND gate, and the output terminal is connected to the gate of the second NMOS; the source of the second PMOS is connected to the power supply terminal, and the drain is connected to the output terminal of the sub-switching unit; the source of the second NMOS is grounded, and the drain is connected to the output terminal of the sub-switching unit.

6. The data processing circuit according to claim 2, characterized in that, The parallel-to-serial converter module further includes a first compensation module and a second compensation module; the first compensation module is electrically connected to the output terminal of the first parallel-to-serial converter module and is used to enhance the amplitude of the data signal to be processed; the second compensation module is electrically connected to the output terminal of the second parallel-to-serial converter module and is used to enhance the amplitude of the auxiliary data signal.

7. The data processing circuit according to claim 1, characterized in that, The first drive module includes a first control unit and a first driver; wherein, The first control unit receives the data signal to be processed and generates a first pull-up control signal and a first pull-down control signal with the same phase, wherein the first pull-up control signal is out of phase with the data signal to be processed; The first driver includes a first pull-up unit and a first pull-down unit; the control terminal of the first pull-up unit receives the first pull-up control signal, the first terminal is connected to the power supply terminal, and the second terminal is connected to the data port; the control terminal of the first pull-down unit receives the first pull-down control signal, the first terminal is connected to the data port, and the second terminal is grounded.

8. The data processing circuit according to claim 1, characterized in that, The second drive module includes a second control unit and a second driver; wherein, The second control unit, electrically connected to the parallel-to-serial module and the first drive module, is configured to generate a second pull-down control signal in an active state when both the data signal to be processed and the auxiliary data signal are high; and to generate a second pull-up control signal in an active state when both the data signal to be processed and the auxiliary data signal are low. The second driver includes a second pull-up unit and a second pull-down unit; the control terminal of the second pull-up unit receives the second pull-up control signal, the first terminal is connected to the power supply terminal, and the second terminal is connected to the data port; the control terminal of the second pull-down unit receives the second pull-down control signal, the first terminal is connected to the data port, and the second terminal is grounded.

9. The data processing circuit according to claim 8, characterized in that, The second control unit includes a first OR gate and a first AND gate, the second pull-up unit is composed of several PMOS transistors, and the second pull-down unit is composed of several NMOS transistors; wherein, The first terminal of the first OR gate receives the data signal to be processed, the second terminal receives the auxiliary data signal, and the output terminal outputs the second pull-up control signal. The first terminal of the first AND gate receives the data signal to be processed, the second terminal receives the auxiliary data signal, and the output terminal outputs the second pull-down control signal.

10. The data processing circuit according to claim 8, characterized in that, The second pull-up control signal includes M sub-signals, and the second pull-down control signal includes M sub-signals; the second pull-up unit includes M pull-up sub-units, and the control terminal of the x-th pull-up sub-unit receives the x-th sub-signal of the second pull-up control signal; the second pull-down unit includes M pull-down sub-units, and the control terminal of the x-th pull-down unit receives the x-th sub-signal of the second pull-down control signal; wherein... The second control unit also receives M pull-up adjustment signals and M pull-down adjustment signals, and is configured such that when both the data signal to be processed and the auxiliary data signal are high and the x-th pull-down adjustment signal is active, the x-th sub-signal of the second pull-down control signal is active; and when both the data signal to be processed and the auxiliary data signal are low and the x-th pull-up adjustment signal is active, the x-th sub-signal of the second pull-up control signal is active. Where x and M are both positive integers, and 1 ≤ x ≤ M.

11. The data processing circuit according to claim 10, characterized in that, The second control unit includes a third NOR gate, a fourth NOR gate, M third NAND gates, and M second AND gates; wherein, The first input terminal of the third NOR gate receives the data signal to be processed, and the second input terminal receives the auxiliary data signal. The first input of the xth third NAND gate is connected to the output of the third NOR gate, the second input receives the xth pull-up adjustment signal, and the output outputs the xth sub-signal of the second pull-up control signal; The first input terminal of the fourth NOR gate receives the inverted signal of the data signal to be processed, and the second input terminal receives the inverted signal of the auxiliary data signal; The first input terminal of the xth second AND gate is connected to the output terminal of the fourth NOR gate, the second input terminal receives the xth pull-down adjustment signal, and the output terminal outputs the xth sub-signal of the second pull-down control signal.

12. A semiconductor memory, characterized in that, The semiconductor memory includes the data processing circuitry as described in any one of claims 1-11.

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