Semiconductor structure and image sensor

Abstract

Embodiments of the present disclosure relates to the field of image sensors, and provide a semiconductor structure and an image sensor. The semiconductor structure may at least comprise: a substrate; an epitaxial layer located on the substrate; a first opening passing through the epitaxial layer and entering the substrate; a first structure located in the first opening; and a second structure located below the first structure and electrically connected to the first structure.

Description

A semiconductor structure and an image sensor

[0001] Cross-referencing

[0002] This application claims priority to Chinese Patent Application No. 202510007696.9, filed on January 2, 2025, entitled “A Semiconductor Structure and Image Sensor”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of image sensors, and more particularly to a semiconductor structure and an image sensor. Background Technology

[0004] CMOS image sensors are the core component of modern image capture technology. They combine low-power logic circuits with high-quality pixel technology to convert external light signals into digital electrical signals. However, driven by the demands for high resolution and miniaturization, maintaining the connectivity and stability between the various components has become a pressing technical challenge. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and an image sensor that at least improve the connectivity and structural stability of a CMOS image sensor.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, comprising: a semiconductor structure characterized in that it includes:

[0007] Base;

[0008] Epitaxial layer, located on the substrate;

[0009] The first opening penetrates the epitaxial layer and enters the substrate;

[0010] The first structure is located in the first opening;

[0011] The second structure is located below the first structure and is electrically connected to the first structure.

[0012] In some embodiments, the first structure includes a first dielectric layer, a conductive layer, and a filling layer. The first dielectric layer covers only the sidewall of the first opening, the conductive layer covers the first dielectric layer and the bottom of the first opening, the conductive layer is electrically connected to the second structure, and the filling layer at least covers the conductive layer.

[0013] In some embodiments, the substrate includes a dielectric layer and a barrier layer stacked together. The substrate also includes a metal layer located within the dielectric layer. The metal layer includes at least a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer from top to bottom. The fifth metal layer extends in a direction parallel to the substrate to below the first opening. A second structure is located between the fifth metal layer and the first structure. The second structure is electrically connected to the fifth metal layer and the first structure.

[0014] In some embodiments, the projected area of ​​the first structure on the fifth metal layer is not greater than the projected area of ​​the second structure on the fifth metal layer.

[0015] In some embodiments, the second structure is columnar, and both the dielectric layer and the barrier layer are connected to the sidewalls of the second structure.

[0016] In some embodiments, the second structure comprises a connection layer and a conductive structure. The connection layer is located within the dielectric layer, and there may be one or more conductive structures. Adjacent connection layers are electrically connected through the conductive structures. The connection layer includes at least a first connection layer, a second connection layer, a third connection layer, and a fourth connection layer from top to bottom. The conductive structure includes at least a first conductive structure, a second conductive structure, a third conductive structure, and a fourth conductive structure from top to bottom. The first connection layer and the second connection layer are electrically connected through the first conductive structure, the second connection layer and the third connection layer are electrically connected through the second conductive structure, the third connection layer and the fourth connection layer are electrically connected through the third conductive structure, and the fourth connection layer and the fifth metal layer are electrically connected through the fourth conductive structure.

[0017] In some embodiments, the connection layer and the metal layer are located at the same level.

[0018] In some embodiments, the upper surface of the second structure is not lower than the upper surface of the first metal layer.

[0019] In some embodiments, the substrate further includes a transistor having a source, a drain, and a gate, wherein the source and drain are electrically connected to the first metal layer via a first electrical connection structure and a second electrical connection structure, respectively.

[0020] In some embodiments, the epitaxial layer further has an isolation layer, a first barrier layer is further between the epitaxial layer and the substrate, and a first isolation structure is further provided on both sides of the first structure, the first isolation structure extending from the isolation layer to the first barrier layer.

[0021] In some embodiments, the epitaxial layer has a contact pad that extends into the epitaxial layer, and a second isolation structure is also provided on both sides of the contact pad, the second isolation structure extending from the isolation layer to the first barrier layer.

[0022] In some embodiments, the epitaxial layer further has a pixel region, which is isolated by a third isolation structure that extends from the isolation layer into the epitaxial layer.

[0023] In some embodiments, a metal mesh structure is also provided above the pixel area to prevent crosstalk between pixel areas.

[0024] Another aspect of this disclosure provides an image sensor, including:

[0025] A first semiconductor and a second semiconductor, wherein the first semiconductor is located on the second semiconductor, and the first semiconductor is composed of a semiconductor structure according to any one of claims 1-13;

[0026] The first semiconductor includes a substrate and an epitaxial layer located on the substrate;

[0027] The second semiconductor includes a substrate and a structural layer located on the substrate, wherein a bonding layer is provided between the top surface of the structural layer and the bottom surface of the substrate.

[0028] In some embodiments, the structural layer includes a structural conductive layer and a second barrier layer thereon. The image sensor also includes a through-structure that passes through the first semiconductor into the second semiconductor and is electrically connected to the structural conductive layer.

[0029] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by setting a first structure and a second structure, with the second structure located below the first structure and electrically connected to the first structure, the areas that are originally prone to cracks and deformation are filled by the second structure, preventing the generation of cracks and deformation, and improving the structural stability and connection performance of the image sensor. Attached Figure Description

[0030] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 is a planar schematic diagram of an image sensor device;

[0032] Figures 2 and 3 are schematic diagrams of a scanning electron microscope of an image sensor in one embodiment.

[0033] Figure 4 is a schematic diagram of a semiconductor structure disclosed herein.

[0034] Figure 5 is a schematic diagram of another semiconductor structure disclosed herein.

[0035] Figures 6 to 8 are top views of the first and second structures of this disclosure.

[0036] Figure 9 is a schematic diagram of an image sensor disclosed herein.

[0037] Figure 10 is a schematic diagram of another image sensor disclosed herein.

[0038] Figure 11 is a schematic diagram of an image sensor including a through-hole structure according to the present disclosure.

[0039] Figure 12 is a schematic diagram of another image sensor in this disclosure that includes a through-hole structure. Detailed Implementation

[0040] As the background technology indicates, CMOS image sensors are the core component of modern image capture technology. They combine low-power logic circuits with high-quality pixel technology, enabling them to convert external light signals into digital electrical signals. However, driven by the demands for high resolution and miniaturization, maintaining the connectivity between various structures and ensuring structural stability has become a pressing technical challenge.

[0041] This disclosure provides a semiconductor structure and an image sensor. By setting a first structure and a second structure, with the second structure located below the first structure and electrically connected to the first structure, areas prone to cracking and deformation are filled by the second structure, preventing the generation of cracks and deformation, and improving the structural stability and connectivity performance of the image sensor.

[0042] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be achieved even without these technical details and various variations and modifications based on the following embodiments. The disclosure is described in more detail below with reference to the accompanying drawings. The advantages and features of this disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this disclosure.

[0043] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0044] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0045] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0046] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0047] Figure 1 is a planar schematic diagram of an image sensor device;

[0048] Figures 2 and 3 are schematic diagrams of a scanning electron microscope of an image sensor in one embodiment.

[0049] Figure 4 is a schematic diagram of a semiconductor structure disclosed herein.

[0050] Figure 5 is a schematic diagram of another semiconductor structure disclosed herein.

[0051] Figures 6 to 8 are top views of the first and second structures of this disclosure.

[0052] Figure 9 is a schematic diagram of an image sensor disclosed herein.

[0053] Figure 10 is a schematic diagram of another image sensor disclosed herein.

[0054] Figure 11 is a schematic diagram of an image sensor including a through-hole structure according to the present disclosure.

[0055] Figure 12 is a schematic diagram of another image sensor in this disclosure that includes a through-hole structure.

[0056] Referring to Figure 1, the image sensor device includes a pixel region A1 and a peripheral region A2. The peripheral region A2 is located on at least one side of the pixel region A1. Figure 1 shows the peripheral region A2 located around the pixel region A1. Of course, the peripheral region A2 can also be located on two or three sides of the pixel region A1, depending on the specific requirements. The pixel region A1 is the core area of ​​the image sensor, mainly responsible for capturing light and converting light signals into electrical signals. The pixel region A1 mainly includes: a photodiode, a transfer transistor, a reset transistor, a source follower or amplification transistor, and a row select transistor, etc. The peripheral region surrounding the pixel area is primarily responsible for signal processing, control, and interface functions; it mainly includes: readout circuitry, control circuitry, row / column driver circuits, timing and logic circuits, interface circuits, memory circuits, and power management circuits. The peripheral region A2 typically has a BSV (back side via) for signal connection and transmission. Figures 2 and 3 are schematic diagrams of a scanning electron microscope (SEM) of an image sensor in one embodiment. As shown in Figure 2, the image sensor includes multiple metal layers 11, a bottom metal layer 16, a back via 13, and a dielectric layer 12. The dielectric layer 12 fills the spaces between adjacent metal layers and between the metal layers and the back via. However, cracks 14 may exist in the dielectric layer 12 of the image sensor, as shown by the white dashed line in Figure 2. The presence of cracks 14 will affect the stability of the overall structure. In addition, in some cases, it is necessary to electrically connect the back via 13 and the bottom metal layer 16 for analog-to-digital conversion. However, as shown in Figure 2, there may be situations where the back via 13 and the bottom metal layer 16 cannot be electrically connected, resulting in an open circuit and affecting the connection performance between the various structures of the image sensor. As shown in Figure 3, when the back via 13 comes into contact with the bottom metal layer 16, the combined effect of the tensile stress of the back via 13 and the compressive stress of the bottom metal layer 16 may cause deformation of the bottom metal layer 16, forming a hole 15. The presence of the hole 15 further reduces the connection performance and structural stability of the image sensor. To address the above issues, this application provides a semiconductor structure and an image sensor to improve the contact performance and structural stability of the image sensor.

[0057] As shown in Figure 4, a semiconductor structure 1 includes: a substrate 10 and an epitaxial layer 20, the epitaxial layer 20 being located on the substrate 10; the substrate 10 includes a pixel region A1 and a peripheral region A2; a first opening 30', as shown by the dashed box in Figure 4, passes through the epitaxial layer 20 and enters the substrate 10; a first structure 31 is located in the first opening; a second structure 32 is located in the substrate 10, below the first structure 31, and electrically connected to the first structure 31. The first structure 31 includes a first dielectric layer 301, a conductive layer 302, and a filling layer 303. The first dielectric layer 301 only covers the sidewalls of the first opening 30', the conductive layer 302 covers the first dielectric layer 301 and the bottom of the first opening 30', the conductive layer 302 is electrically connected to the second structure 32, and the filling layer 303 at least covers the conductive layer 302; in a specific embodiment, the filling layer 303 includes a first filling layer 3031 and a second filling layer 3032. The first dielectric layer 301 can be made of silicon nitride, silicon oxide, or silicon oxynitride; the conductive layer 302 can be made of tungsten; the filling layer 303 can be made of silicon nitride, silicon oxide, or silicon oxynitride, or it can be a filter material such as a color filter. In a specific embodiment, the first filling layer 3031 can be one or more of silicon nitride, silicon oxide, or silicon oxynitride, and the second filling layer 3032 can be a filter material such as a color filter.

[0058] The substrate 10 includes a dielectric layer 101 and a barrier layer 102 stacked together. The substrate 10 also includes a metal layer M located within the dielectric layer 101. The metal layer M, from top to bottom, includes at least a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and a fifth metal layer M5. The fifth metal layer M5 extends parallel to the substrate 10 to below the first opening 30'. A second structure 32 is located between the fifth metal layer M5 and the first structure 31, and the second structure 32 electrically connects the fifth metal layer M5 and the first structure 31. The metal layer M can be made of copper or tungsten. The barrier layer 102 prevents the diffusion of the metal layer M. The projected area of ​​the first structure 31 on the fifth metal layer M5 is not greater than the projected area of ​​the second structure 32 on the fifth metal layer M5.

[0059] In one specific embodiment, as shown in FIG4, the second structure 32 is columnar, and both the dielectric layer 101 and the barrier layer 102 are connected to the sidewall of the second structure 32. As shown in FIG2 above, cracks 14 may exist in the dielectric layer 12 of the image sensor, and the presence of cracks 14 will affect the stability of the overall structure. Here, the main reasons for the formation of cracks 14 are explained in conjunction with FIG2 and FIG4: the semiconductor structure 1 includes a substrate 10 and an epitaxial layer 20. The material of the epitaxial layer 20 is mainly silicon (Si). The substrate 10 includes a dielectric layer 101 and a barrier layer 102 stacked together. The dielectric layer 101 is mainly made of a low-k dielectric layer. Since Si has a large coefficient of thermal expansion, the low-k dielectric layer has a small coefficient of thermal expansion. Especially after drilling BSV holes, there will be a weak point between the dielectric layer 101 and the barrier layer 102. In the subsequent process, there will be some thermal processes. During the thermal processes, due to the difference in the coefficient of thermal expansion, the weak point will expand further and produce cracks. In this embodiment, a second structure 32 is provided in advance in places where cracks are likely to occur. The presence of the second structure 32 can prevent the weakness from being exposed, thereby preventing the weakness from expanding and causing cracks. In addition, the material of the second structure 32 and the metal layer M in the dielectric layer 101 can be the same, which can prevent the influence caused by the different coefficients of thermal expansion.

[0060] Furthermore, as shown in Figure 3, when the back through-hole 13 contacts the bottom metal layer 16, the combined effect of the tensile stress of the back through-hole 13 and the compressive stress of the bottom metal layer 16 may cause deformation of the bottom metal layer 16, forming a hole 15. The presence of the hole 15 further reduces the connection performance and structural stability of the image sensor. In this embodiment, the second structure 32 is directly disposed above the fifth metal layer M5, and the second structure 32 can be block-shaped. The second structure 32 can generate greater compressive stress, preventing the fifth metal layer M5 from forming holes due to warping deformation, and further improving the stability of the semiconductor structure. In addition, the second structure 32 is located below the first structure 31, so that the first structure 31 can achieve electrical connection with the fifth metal layer M5 through the second structure 32, preventing the occurrence of open circuit. The upper surface of the second structure 32 is not lower than the upper surface of the first metal layer M1, so that the first structure 31 can better connect with the second structure 32; preventing the risk that the first structure 31 and the second structure 32 cannot be connected.

[0061] The substrate 10 also includes a transistor T, which has a source S, a drain D, and a gate G. The source S and drain D are electrically connected to the first metal layer M1 through a first electrical connection structure L1 and a second electrical connection structure L2, respectively. In a specific embodiment, the gate G is also connected to a third electrical connection structure L2. It should be noted that the metal layers in the same layer may not be completely connected due to wiring density, signal isolation, and thermal management. As shown in Figure 4, both the source S and drain D are electrically connected to the first metal layer M1, but since the first metal layer M1 is not continuous, the source and drain can transmit signals through the first metal layer M1 respectively. The epitaxial layer 20 also has an isolation layer 400, which includes a first isolation layer 401 and a second isolation layer 402. The first isolation layer 401 can be a high-k dielectric layer, and the second isolation layer 402 can be an oxide layer. The isolation layer 400 can reduce the dark current of the image sensor. A first barrier layer 1011 is also provided between the epitaxial layer 20 and the substrate 10. A first isolation structure 51 is also provided on both sides of the first structure 31, extending from the isolation layer 400 to the first barrier layer 1011. The epitaxial layer 20 also has a contact pad 61, which includes a pad dielectric layer 601, a pad metal layer 602, and a pad 603. The material of the pad dielectric layer 601 can be the same as that of the first dielectric layer 301, and the material of the pad metal layer 602 can be the same as that of the conductive layer 302. The contact pad 61 extends into the epitaxial layer 20, and the exposed surface of the top of the contact pad 61 can be electrically connected to other leads. By applying a voltage to the contact pad 61, the contact pad 61 is electrically connected to the first structure, the first structure 31 is electrically connected to the second structure 32, and the second structure 32 is then electrically connected to the transistor T through the fifth metal layer M5. That is, the applied voltage is transmitted from the contact pad 61 to the transistor T, and the transistor T then performs a corresponding read operation based on the applied voltage. A second isolation structure 52 is also provided on both sides of the contact pad 61, extending from the isolation layer 400 to the first barrier layer 1011. The epitaxial layer 20 also has a pixel region 60, which is isolated by a third isolation structure 53. The third isolation structure 53 includes a first sub-isolation structure 531 and a second sub-isolation structure 532. The first sub-isolation structure 531 can be one or both of silicon oxide or a high-k dielectric layer, and the second sub-isolation structure 532 can be silicon oxide. The third isolation structure 53 reduces the dark current of the image sensor. The third isolation structure 53 extends from the isolation layer 400 into the epitaxial layer 20. A metal mesh structure 70 is also provided above the pixel region 60, including a mesh structure conductive layer 701 and a cover layer 702. A first fill layer 3031 covers the top and sidewalls of the metal mesh structure 70. The metal mesh structure 70 is used to prevent crosstalk between the pixel regions 60.

[0062] In this embodiment, by pre-setting a second structure 32 in areas prone to cracking, the presence of the second structure 32 prevents weaknesses from being exposed, thereby preventing the expansion of weaknesses and the formation of cracks. Furthermore, the second structure 32 can be made of the same material as the metal layer M in the dielectric layer 101, preventing the effects of different coefficients of thermal expansion. In this embodiment, the second structure 32 is directly disposed above the fifth metal layer M5, and the second structure 32 can be block-shaped. The second structure 32 can generate significant compressive stress, preventing holes formed in the fifth metal layer M5 due to warping deformation, further improving the stability of the semiconductor structure. Additionally, the second structure 32 is located below the first structure 31, allowing the first structure 31 to achieve electrical connection with the fifth metal layer M5 through the second structure 32, preventing open circuits.

[0063] Next, please refer to Figure 5, which is a schematic diagram of another semiconductor structure disclosed herein. The identical parts will not be repeated. The difference between this embodiment and the previous embodiment is that the second structure 32 is composed of a connection layer S and a conductive structure D, as shown by the dotted lines in Figure 5. The connection layer S is located within the dielectric layer 101. There can be one or more conductive structures D, and adjacent connection layers S are electrically connected through conductive structures D. The connection layer S, from top to bottom, includes at least a first connection layer S1, a second connection layer S2, a third connection layer S3, and a fourth connection layer S4. The conductive structure D, from top to bottom, includes at least a first conductive structure D1, a second conductive structure D2, a third conductive structure D3, and a fourth conductive structure D4. The first connection layer S1 and the second connection layer S2 are electrically connected through the first conductive structure D1, the second connection layer S2 and the third connection layer S3 are electrically connected through the second conductive structure D2, the third connection layer S3 and the fourth connection layer S4 are electrically connected through the third conductive structure D3, and the fourth connection layer S4 and the fifth metal layer M5 are electrically connected through the fourth conductive structure D4. The interconnect layer S and the metal layer M are located at the same level. It should be noted that "connecting layer S and metal layer M are at the same level" means that each interconnect layer S and each metal layer M are located within the same dielectric layer 101. For example, the first interconnect layer S1 and the first metal layer M1 are located within the same dielectric layer 101, the second interconnect layer S2 and the second metal layer M2 are located within the same dielectric layer 101, the third interconnect layer S3 and the third metal layer M3 are located within the same dielectric layer 101, and the fourth interconnect layer S4 and the fourth metal layer M4 are located within the same dielectric layer 101. In a specific embodiment, the first interconnect layer S1 and the first metal layer M1 can be deposited and formed in the same step, the second interconnect layer S2 and the second metal layer M2 can be deposited and formed in the same step, the third interconnect layer S3 and the third metal layer M3 can be deposited and formed in the same step, and the fourth interconnect layer S4 and the fourth metal layer M4 can be deposited and formed in the same step. There can be one or more conductive structures D, which can be set as needed. In this embodiment, it is shown that there are two conductive structures D. The first structure 31 is electrically connected to the fifth metal layer M5 through the multi-layered connection layer S and the conductive structure D.

[0064] In this embodiment, the second structure 32 is configured as a connecting layer S and a conductive structure D. The connecting layer S and the metal layer M can be formed in the same deposition process, thus eliminating the weak point between the dielectric layer 101 and the barrier layer 102 after drilling BSV holes, as mentioned earlier. This is because the second structure 32 in this embodiment is deposited layer by layer without a hole-drilling process, preventing weak points. Even with subsequent thermal processes, the weak points will not expand further and cause cracks. The second structure in this embodiment prevents the formation and expansion of weak points and prevents cracking. Furthermore, the fourth connecting layer S4 and the fifth metal layer M5 of the second structure are electrically connected through the fourth conductive structure D4. The low tensile stress of the fourth conductive structure D4 prevents the fifth metal layer M5 from warping and deforming to form holes, further improving the stability of the semiconductor structure. Additionally, the second structure 32 is located below the first structure 31, allowing the first structure 31 to achieve electrical connection with the fifth metal layer M5 through the second structure 32, preventing open circuits.

[0065] Figures 6 to 8 are top views of the first and second structures of this disclosure. In the embodiments of this application, the top view of the first structure 31 can be a polygon or a circle. Specifically, the polygon can be a square, a rectangle, etc., and the top view of the second structure 32 can be a quadrilateral or a circle. In a specific embodiment, as shown in Figure 6, both the first structure 31 and the second structure 32 are quadrilaterals; as shown in Figure 7, both the first structure 31 and the second structure 32 are circles; as shown in Figure 8, the first structure 31 is a quadrilateral and the second structure 32 is a circle. It should be noted that no matter how the shapes of the first structure 31 and the second structure 32 change, the top view area of ​​the second structure 32 is larger than the top view area of ​​the first structure 31. That is, the projected area of ​​the first structure 31 on the fifth metal layer M5 is not greater than the projected area of ​​the second structure 32 on the fifth metal layer M5. The advantage of this setting is that the first structure 31 can land more easily on the second structure 32. That is, the second structure 32 provides more space for the landing of the first structure 31, preventing problems caused by the first structure 31 not being able to fully contact the second structure 32.

[0066] Figure 9 is a schematic diagram of an image sensor disclosed herein. As shown in Figure 9, an image sensor 1000 includes: a first semiconductor 100 and a second semiconductor 200. The first semiconductor 100 is located on the second semiconductor 200. The first semiconductor 100 includes a substrate 10 and an epitaxial layer 20 located on the substrate 10. The second semiconductor 200 includes a substrate 30 and a structural layer 40 located on the substrate. A bonding layer 1001 is provided between the top surface of the structural layer 40 and the bottom surface of the substrate 10. The bonding method of the bonding layer 1001 can be direct bonding or wafer bonding. The structural layer 40 includes a structural conductive layer 2003, and a second barrier layer 2011 is also provided on the structural conductive layer 2003. During the process, both the first barrier layer 1011 and the second barrier layer 2011 are used as etching barrier layers to prevent over-etching from affecting other structures.

[0067] Referring to Figures 4 and 9, the first semiconductor 100 includes: a substrate 10 and an epitaxial layer 20, the epitaxial layer 20 being located on the substrate 10; a first opening 30', as shown by the dashed box in Figure 9, passing through the epitaxial layer 20 and entering the substrate 10; a first structure 31 located in the first opening; and a second structure 32 located in the substrate 10, below the first structure 31, and electrically connected to the first structure 31. The first structure 31 includes a first dielectric layer 301, a conductive layer 302, and a filling layer 303. The first dielectric layer 301 only covers the sidewalls of the first opening 30', the conductive layer 302 covers the first dielectric layer 301 and the bottom of the first opening 30', the conductive layer 302 is electrically connected to the second structure 32, and the filling layer 303 at least covers the conductive layer 302. In a specific embodiment, the filling layer 303 includes a first filling layer 3031 and a second filling layer 3032. The first dielectric layer 301 can be made of silicon nitride, silicon oxide, or silicon oxynitride. The conductive layer 302 can be made of tungsten. The filling layer 303 can be made of silicon nitride, silicon oxide, or silicon oxynitride, or it can be a filter material such as a color filter. In a specific embodiment, the first filling layer 3031 can be one or more of silicon nitride, silicon oxide, or silicon oxynitride, and the second filling layer 3032 can be a filter material such as a color filter. The substrate 10 includes a dielectric layer 101 and a barrier layer 102 stacked together. The substrate 10 also includes a metal layer M, which is located within the dielectric layer 101. The metal layer M includes at least a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and a fifth metal layer M5 from top to bottom. The fifth metal layer M5 extends along a direction parallel to the substrate 10 to below the first opening 30'. The second structure 32 is located between the fifth metal layer M5 and the first structure 31, and the second structure 32 is electrically connected to the fifth metal layer M5 and the first structure 31. The metal layer M can be made of copper or tungsten, and the barrier layer 102 is used to prevent the diffusion of the metal layer M. The projected area of ​​the first structure 31 on the fifth metal layer M5 is not greater than the projected area of ​​the second structure 32 on the fifth metal layer M5.

[0068] In one specific embodiment, as shown in FIG9, the second structure 32 is columnar, and both the dielectric layer 101 and the barrier layer 102 are connected to the sidewalls of the second structure 32. As shown in FIG2 above, cracks 14 may exist in the dielectric layer 12 of the image sensor, and the presence of cracks 14 will affect the stability of the overall structure. Here, the main reasons for the formation of cracks 14 are explained in conjunction with FIG2 and FIG9: the semiconductor structure 1 includes a substrate 10 and an epitaxial layer 20. The material of the epitaxial layer 20 is mainly silicon (Si). The substrate 10 includes a dielectric layer 101 and a barrier layer 102 stacked together. The dielectric layer 101 is mainly a low-k dielectric layer. Since Si has a large coefficient of thermal expansion, the low-k dielectric layer has a small coefficient of thermal expansion. Especially after drilling BSV holes, there will be a weak point between the dielectric layer 101 and the barrier layer 102. In the subsequent process, there will be some thermal processing. During the thermal processing, due to the difference in the coefficient of thermal expansion, the weak point will expand further and produce cracks. In this embodiment, a second structure 32 is provided in advance in places where cracks are likely to occur. The presence of the second structure 32 can prevent the weakness from being exposed, thereby preventing the weakness from expanding and causing cracks. In addition, the material of the second structure 32 and the metal layer M in the dielectric layer 101 can be the same, which can prevent the influence caused by the different coefficients of thermal expansion.

[0069] Furthermore, as shown in Figure 3, when the back through-hole 13 contacts the bottom metal layer 16, the combined effect of the tensile stress of the back through-hole 13 and the compressive stress of the bottom metal layer 16 may cause deformation of the bottom metal layer 16, forming a hole 15. The presence of the hole 15 further reduces the connection performance and structural stability of the image sensor. In this embodiment, the second structure 32 is directly disposed above the fifth metal layer M5, and the second structure 32 can be block-shaped. The second structure 32 can generate greater compressive stress, preventing the fifth metal layer M5 from forming holes due to warping deformation, and further improving the stability of the semiconductor structure. In addition, the second structure 32 is located below the first structure 31, so that the first structure 31 can achieve electrical connection with the fifth metal layer M5 through the second structure 32, preventing the occurrence of open circuit. The upper surface of the second structure 32 is not lower than the upper surface of the first metal layer M1, so that the first structure 31 can better connect with the second structure 32; preventing the risk that the first structure 31 and the second structure 32 cannot be connected.

[0070] The substrate 10 also includes a transistor T, which has a source S, a drain D, and a gate G. The source S and drain D are electrically connected to the first metal layer M1 through a first electrical connection structure L1 and a second electrical connection structure L2, respectively. In one specific embodiment, the gate G is also connected to a third electrical connection structure L2. The epitaxial layer 20 also has an isolation layer 400, which includes a first isolation layer 401 and a second isolation layer 402. The first isolation layer 401 can be a high-k dielectric layer, and the second isolation layer 402 can be an oxide layer. The isolation layer 400 can reduce the dark current of the image sensor. A first barrier layer 1011 is also provided between the epitaxial layer 20 and the first substrate 10. First isolation structures 51 are also provided on both sides of the first structure 31, extending from the isolation layer 400 to the first barrier layer 1011. The epitaxial layer 20 also has contact pads 61, which include a pad dielectric layer 601, a pad metal layer 602, and a pad 603. The material of the pad dielectric layer 601 is the same as that of the first dielectric layer 301, and the material of the pad metal layer 602 can be the same as that of the conductive layer 302. The contact pads 61 extend into the epitaxial layer 20, and the exposed surface of the top of the contact pads 61 can be electrically connected to other leads. By applying a voltage to the contact pads 61, the contact pads 61 are electrically connected to the first structure, the first structure 31 is electrically connected to the second structure 32, and the second structure 32 is then electrically connected to the transistor T through the fifth metal layer M5. That is, the applied voltage is transmitted from the contact pads 61 to the transistor T, and the transistor T then performs a corresponding read operation according to the applied voltage. Second isolation structures 52 are also provided on both sides of the contact pads 61, extending from the isolation layer 400 to the first barrier layer 1011. The epitaxial layer 20 also has a pixel region 60, which is isolated by a third isolation structure 53. The third isolation structure 53 includes a first sub-isolation structure 531 and a second sub-isolation structure 532. The first sub-isolation structure 531 can be one or both of silicon oxide or a high-k dielectric layer, and the second sub-isolation structure 532 can be silicon oxide. The third isolation structure 53 reduces the dark current of the image sensor. The third isolation structure 53 extends from the isolation layer 400 into the epitaxial layer 20. A metal mesh structure 70 is also provided above the pixel region 60. The metal mesh structure 70 includes a mesh structure conductive layer 701 and a capping layer 702. A first filling layer 3031 covers the top and sidewalls of the metal mesh structure 70. The metal mesh structure 70 is used to prevent crosstalk between the pixel regions 60.

[0071] In this embodiment, by pre-setting a second structure 32 in areas of the image sensor that are prone to cracking, the presence of the second structure 32 prevents weaknesses from being exposed, thereby preventing the expansion of weaknesses and the formation of cracks. Furthermore, the second structure 32 can be made of the same material as the metal layer M in the dielectric layer 101, preventing the effects of different coefficients of thermal expansion. In this embodiment, the second structure 32 is directly disposed above the fifth metal layer M5, and the second structure 32 can be block-shaped. The second structure 32 can generate significant compressive stress, preventing holes formed in the fifth metal layer M5 due to warping deformation, further improving the stability of the semiconductor structure. Additionally, the second structure 32 is located below the first structure 31, allowing the first structure 31 to achieve electrical connection with the fifth metal layer M5 through the second structure 32, preventing open circuits.

[0072] Figure 10 is a schematic diagram of another image sensor disclosed herein. As shown in Figure 10, an image sensor 1000 includes: a first semiconductor 100 and a second semiconductor 200. The first semiconductor 100 is located on the second semiconductor 200. The first semiconductor 100 includes a substrate 10 and an epitaxial layer 20 located on the substrate 10. The second semiconductor 200 includes a substrate 30 and a structural layer 40 located on the substrate. A bonding layer 1001 is provided between the top surface of the structural layer 40 and the bottom surface of the substrate 10. The structural layer 40 includes a structural conductive layer 2003, and a second barrier layer 2011 is also provided on the structural conductive layer 2003.

[0073] The same parts will not be repeated. The difference between this embodiment and the previous embodiment is that the first semiconductor 100 includes a second structure 32, which is composed of a connection layer S and a conductive structure D, as shown by the dotted line in FIG10. The connection layer S is located within the dielectric layer 101. There can be one or more conductive structures D. The upper and lower adjacent connection layers S are electrically connected through the conductive structures D. The connection layer S includes at least a first connection layer S1, a second connection layer S2, a third connection layer S3 and a fourth connection layer S4 from top to bottom. The conductive structure D includes at least a first conductive structure D1, a second conductive structure D2, a third conductive structure D3 and a fourth conductive structure D4 from top to bottom. The first connection layer S1 and the second connection layer S2 are electrically connected through the first conductive structure D1. The second connection layer S2 and the third connection layer S3 are electrically connected through the second conductive structure D2. The third connection layer S3 and the fourth connection layer S4 are electrically connected through the third conductive structure D3. The fourth connection layer S4 and the fifth metal layer M5 are electrically connected through the fourth conductive structure D4. The interconnect layer S and the metal layer M are located at the same level. It should be noted that "connect layer S and metal layer M are at the same level" means that each interconnect layer S and each metal layer M are located within the same dielectric layer 101. For example, the first interconnect layer S1 and the first metal layer M1 are located within the same dielectric layer 101, the second interconnect layer S2 and the second metal layer M2 are located within the same dielectric layer 101, the third interconnect layer S3 and the third metal layer M3 are located within the same dielectric layer 101, and the fourth interconnect layer S4 and the fourth metal layer M4 are located within the same dielectric layer 101. In a specific embodiment, the first interconnect layer S1 and the first metal layer M1 can be deposited and formed in the same step, the second interconnect layer S2 and the second metal layer M2 can be deposited and formed in the same step, the third interconnect layer S3 and the third metal layer M3 can be deposited and formed in the same step, and the fourth interconnect layer S4 and the first metal layer M4 can be deposited and formed in the same step. There can be one or more conductive structures D, which can be set as needed. In this embodiment, it is shown that there are two conductive structures D. The first structure 31 is electrically connected to the fifth metal layer M5 through the multi-layered connection layer S and the conductive structure D.

[0074] In this embodiment, the second structure 32 is configured as a connecting layer S and a conductive structure D. The connecting layer S and the metal layer M can be formed in the same deposition process, thus eliminating the weak point between the dielectric layer 101 and the barrier layer 102 after drilling BSV holes, as mentioned earlier. This is because the second structure 32 in this embodiment is deposited layer by layer without a hole-drilling process, preventing weak points. Even with subsequent thermal processes, the weak points will not expand further and cause cracks. The second structure in this embodiment prevents the formation and expansion of weak points and prevents cracking. Furthermore, the fourth connecting layer S4 and the fifth metal layer M5 of the second structure are electrically connected through the fourth conductive structure D4. The low tensile stress of the fourth conductive structure D4 prevents the fifth metal layer M5 from warping and deforming to form holes, further improving the stability of the semiconductor structure. Additionally, the second structure 32 is located below the first structure 31, allowing the first structure 31 to achieve electrical connection with the fifth metal layer M5 through the second structure 32, preventing open circuits.

[0075] Figure 11 is a schematic diagram of an image sensor including a through-hole structure according to the present disclosure. The difference between the embodiment of this application and Figure 9 is that the image sensor 1000 further includes a through-hole structure 80, which is located in the peripheral region A2. The through-hole structure 80 passes through the first semiconductor 100 and enters the second semiconductor 200 and is electrically connected to the structural conductive layer 2003. The through-hole structure 80 can transmit the signal of the first semiconductor 100 to the second semiconductor 200.

[0076] Figure 12 is a schematic diagram of another image sensor including a through-structure according to the present disclosure. The difference between the embodiment of this application and Figure 10 is that the image sensor 1000 further includes a through-structure 80, which is located in the peripheral region A2. The through-structure 80 passes through the first semiconductor 100, enters the second semiconductor 200, and is electrically connected to the structural conductive layer 2003.

[0077] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base (10); An epitaxial layer (20) is located on the substrate (10); The first opening (30') passes through the epitaxial layer (20) and enters the substrate (10); The first structure (31) is located in the first opening (30'); The second structure (32) is located below the first structure (31) and is electrically connected to the first structure (31).

2. The semiconductor structure according to claim 1, characterized in that, The first structure (31) includes a first dielectric layer (301), a conductive layer (302), and a filling layer (303). The first dielectric layer (301) covers only the sidewall of the first opening (30'). The conductive layer (302) covers the first dielectric layer (301) and the bottom of the first opening (30'). The conductive layer (302) is electrically connected to the second structure (32). The filling layer (303) covers at least the conductive layer (302).

3. The semiconductor structure according to claim 1, characterized in that, The substrate (10) includes a dielectric layer (101) and a barrier layer (102) stacked together. The substrate (10) also includes a metal layer (M) located within the dielectric layer (101). The metal layer (M) includes at least a first metal layer (M1), a second metal layer (M2), a third metal layer (M3), a fourth metal layer (M4), and a fifth metal layer (M5) from top to bottom. The fifth metal layer (M5) extends in a direction parallel to the substrate (10) to below the first opening (30'). The second structure (32) is located between the fifth metal layer (M5) and the first structure (31). The second structure (32) is electrically connected to the fifth metal layer (M5) and the first structure (31).

4. The semiconductor structure according to claim 3, characterized in that, The projected area of ​​the first structure (31) on the fifth metal layer (M5) is not greater than the projected area of ​​the second structure (32) on the fifth metal layer (M5).

5. The semiconductor structure according to claim 3, characterized in that, The second structure (32) is columnar, and both the dielectric layer (101) and the barrier layer (102) are connected to the sidewall of the second structure (32).

6. The semiconductor structure according to claim 3, characterized in that, The second structure (32) consists of a connecting layer (S) and a conductive structure (D). The connecting layer (S) is located within the dielectric layer (101). The conductive structure (D) can be one or more, and adjacent connecting layers (S) are electrically connected through the conductive structure (D). The connecting layer (S) includes at least a first connecting layer (S1), a second connecting layer (S2), a third connecting layer (S3), and a fourth connecting layer (S4) from top to bottom. The conductive structure (D) includes at least a first conductive structure (D1), a second conductive structure (D2), and a third conductive structure (D3) from top to bottom. 2) Third conductive structure (D3) and fourth conductive structure (D4); the first connecting layer (S1) and the second connecting layer (S2) are electrically connected through the first conductive structure (D1), the second connecting layer (S2) and the third connecting layer (S3) are electrically connected through the second conductive structure (D2), the third connecting layer (S3) and the fourth connecting layer (S4) are electrically connected through the third conductive structure (D3), and the fourth connecting layer (S4) and the fifth metal layer (M5) are electrically connected through the fourth conductive structure (D4).

7. The semiconductor structure according to claim 6, characterized in that, The connecting layer (S) and the metal layer (M) are located at the same level.

8. The semiconductor structure according to any one of claims 3-7, characterized in that, The upper surface of the second structure (32) is not lower than the upper surface of the first metal layer (M1).

9. The semiconductor structure according to claim 1, characterized in that, The substrate (10) also includes a transistor (T), which has a source (S), a drain (D), and a gate (G). The source (S) and the drain (D) are electrically connected to the first metal layer (M1) through a first electrical connection structure (L1) and a second electrical connection structure (L2), respectively.

10. The semiconductor structure according to claim 1, characterized in that, The epitaxial layer (20) also has an isolation layer (400), and a first barrier layer (1011) is also provided between the epitaxial layer (20) and the substrate (10). A first isolation structure (51) is also provided on both sides of the first structure (31), and the first isolation structure (51) extends from the isolation layer (400) to the first barrier layer (1011).

11. The semiconductor structure according to claim 1, characterized in that, The epitaxial layer (20) has a contact pad (61) extending into the epitaxial layer (20), and a second isolation structure (52) is provided on both sides of the contact pad (61), the second isolation structure (52) extending from the isolation layer (400) to the first barrier layer (1011).

12. The semiconductor structure according to claim 1, characterized in that, The epitaxial layer (20) also has a pixel region (60), which is isolated by a third isolation structure (53) that extends from the isolation layer (400) into the epitaxial layer (20).

13. The semiconductor structure according to claim 13, characterized in that, A metal mesh structure (70) is also provided above the pixel area (60) to prevent crosstalk between the pixel areas (60).

14. An image sensor, characterized in that, include: A first semiconductor (100) and a second semiconductor (200), wherein the first semiconductor (100) is located on the second semiconductor (200), and the first semiconductor (100) is composed of a semiconductor structure according to any one of claims 1-13; The first semiconductor (100) includes a substrate (10) and an epitaxial layer (20) located on the substrate (10); The second semiconductor (200) includes a substrate (30) and a structural layer (40) located on the substrate (30), wherein a bonding layer (1001) is provided between the top surface of the structural layer (40) and the bottom surface of the substrate (10).

15. The image sensor according to claim 14, characterized in that, The structural layer (40) includes a structural conductive layer (302), and a second barrier layer is also provided on the structural conductive layer (302). The image sensor also includes a through structure that passes through the first semiconductor (100) into the second semiconductor (200) and is electrically connected to the structural conductive layer (302).

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