Memory structure and manufacturing method therefor

By first forming a specific connection between the conductive layer and the storage layer in the memory structure, and then exposing only the top surface of the conductive layer during planarization, the problem of damage to the storage layer during planarization is solved, thus improving the reliability of the device.

WO2026144772A1PCT designated stage Publication Date: 2026-07-09SHANGHAI INTEGRATED CIRCUIT RESEARCH & DEVELOPMENT CENTER CO LTD
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
SHANGHAI INTEGRATED CIRCUIT RESEARCH & DEVELOPMENT CENTER CO LTD
Filing Date
2025-12-02
Publication Date
2026-07-09

AI Technical Summary

Technical Problem

During the planarization process, existing memory structures are prone to depressions or damage in the storage layer, which affects device performance.

Method used

In the memory structure manufacturing method, an electrically connected conductive layer and a storage layer are first formed on the first electrode, with the top surface of the storage layer being lower than the top surface of the conductive layer. Then, an insulating layer is formed on the first dielectric layer and planarized to expose the top surface of the conductive layer, ensuring that the storage layer is not damaged.

Benefits of technology

This method avoids damage to the storage layer during the planarization process, improving the reliability of the device, especially the stability of small-size, low-power memory structures.

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Abstract

The present application provides a memory structure and a manufacturing method therefor. In the manufacturing method for the memory structure, a conductive layer is formed above a first electrode, and a storage layer is formed on one side of the conductive layer, wherein the top surface of the storage layer is lower than the top surface of the conductive layer, and the conductive layer is electrically connected to the first electrode by means of the storage layer; an insulating layer is formed on a first dielectric layer, wherein the insulating layer is located on the side of the storage layer distant from the conductive layer and covers the conductive layer and the storage layer; and the insulating layer is planarized to expose the top surface of the conductive layer, wherein the top surface of the planarized insulating layer is higher than the top surface of the storage layer.
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