Display panel and display module

Abstract

The present application relates to the technical field of display. Disclosed are a display panel and a display module. The display panel comprises: a substrate, a plurality of sub-pixels, and a gate driver on array circuit, wherein the plurality of sub-pixels are located on one side of the substrate and are distributed in a display region; the gate driver on array circuit is located on one side of the substrate and is located in a non-display region; and the gate driver on array circuit comprises a plurality of gate driver on array units and a plurality of connection signal lines, wherein at least one of the plurality of connection signal lines is a target connection signal line, the target connection signal line comprises a first sub-signal line and a second sub-signal line that are stacked, the first sub-signal line is closer to the substrate than the second sub-signal line, and the second sub-signal line overlaps with the first sub-signal line. In the present application, on the basis that the line width of the target connection signal line is not increased, the impedance of the target connection signal line is reduced by means of overlapping the first sub-signal line with the second sub-signal line, such that the signal load can be reduced, thereby ensuring the display effect of the display panel.

Description

Display panel and display module

[0001] This application claims priority to Chinese Patent Application No. 202510012816.4, filed on January 3, 2025, entitled “Display Panel and Display Module”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a display panel and a display module. Background Technology

[0003] With the continuous development of organic light-emitting diode (OLED) technology, the industry has been demanding increasingly narrower bezels for OLED displays in recent years.

[0004] Typically, a display module (i.e., a display screen) may include a display panel and a driving component bonded to the display panel. The display panel has a display area and a non-display area, and includes multiple sub-pixels located in the display area and a gate driver on array (GOA) circuit located in the non-display area. The gate GOA circuit is used to apply driving scan signals (gate signals) to the sub-pixels in the display panel.

[0005] To increase the screen-to-body ratio of the display module, the width of the area in the display panel used to house the GOA circuit needs to be reduced, which necessitates a reduction in the linewidth of the signal lines in the GOA circuit. However, when the linewidth of the signal lines in the GOA circuit is too narrow, the impedance of the signal lines in the GOA circuit is relatively high, resulting in poor stability of the driving scan signal applied by the GOA circuit to the sub-pixels, and consequently, a poor display effect of the display panel. Summary of the Invention

[0006] This application provides a display panel and a display module. It can solve the problem that the bezels of existing display devices are difficult to further narrow. The technical solution is as follows:

[0007] On one hand, a display panel is provided, the display panel having a display area and a non-display area located around the display area; the display panel includes: a substrate, a plurality of sub-pixels, and a gate driving circuit;

[0008] The plurality of sub-pixels are located on one side of the substrate and distributed within the display area;

[0009] The gate driving circuit is located on one side of the substrate and within the non-display area; the gate driving circuit includes: a plurality of gate driving units and a plurality of connection signal lines, one of the gate driving units is electrically connected to a row of the sub-pixels, and at least some of the plurality of gate driving units are connected to each other through the plurality of connection signal lines;

[0010] Among them, at least one of the multiple connection signal lines is a target connection signal line, and the target connection signal line includes: a first sub-signal line and a second sub-signal line stacked together, wherein the first sub-signal line is closer to the substrate than the second sub-signal line, and the second sub-signal line overlaps with the first sub-signal line.

[0011] Optionally, in a direction perpendicular to the extension direction of the target connection signal line and parallel to the substrate, the width of the first sub-signal line is greater than or equal to the width of the second sub-signal line.

[0012] Optionally, the display panel further includes: an insulating protective layer;

[0013] The first sub-signal line is located on the side of the insulating protective layer facing the substrate, and the second sub-signal line is located on the side of the insulating protective layer away from the substrate;

[0014] The insulating protective layer has a cutout area; the orthographic projection of the cutout area on the substrate is located within the orthographic projection of the first sub-signal line on the substrate; and the second sub-signal line overlaps with the first sub-signal line through the cutout area.

[0015] Optionally, for the cutout area between the first sub-signal line and the second sub-signal line distributed in the same target connection signal line, the cutout area includes a cutout groove and / or multiple cutout holes;

[0016] The extension direction of the hollowed-out groove is the same as the extension direction of the target connection signal line; the arrangement direction of the plurality of hollowed-out holes is the same as the extension direction of the target connection signal line.

[0017] Optionally, the insulating protective layer includes: an inorganic insulating layer and an organic insulating layer stacked together, wherein the inorganic insulating layer is closer to the substrate than the organic insulating layer;

[0018] The inorganic insulating layer and the organic insulating layer each have the hollowed-out area.

[0019] Optionally, when the hollowed-out area includes the hollowed-out groove, the hollowed-out groove includes: a first sub-hollowed-out groove penetrating the inorganic insulating layer, and a second sub-hollowed-out groove penetrating the organic insulating layer, wherein the first sub-hollowed-out groove and the second sub-hollowed-out groove are connected.

[0020] The orthographic projection of the second sub-cutout groove on the substrate is located within the orthographic projection of the first sub-cutout groove on the substrate.

[0021] Optionally, in a direction perpendicular to the extension direction of the target connection signal line and parallel to the substrate, the minimum width of the second sub-cutout is smaller than the minimum width of the first sub-cutout.

[0022] Optionally, when the hollow area includes the plurality of hollow holes, the hollow holes include: a first sub-hollow hole penetrating the inorganic insulating layer and a second sub-hollow hole penetrating the organic insulating layer, wherein the first sub-hollow hole and the second sub-hollow hole are connected.

[0023] The orthographic projection of the first sub-hole on the substrate is located within the orthographic projection of the second sub-hole on the substrate.

[0024] Optionally, in a direction perpendicular to the extension direction of the target connection signal line and parallel to the substrate, the minimum width of the second sub-hole is greater than the minimum width of the first sub-hole.

[0025] Optionally, when the hollow area includes the hollow groove and the plurality of hollow holes, the hollow area includes: a hollow groove penetrating the inorganic insulating layer, and a plurality of hollow holes penetrating the organic insulating layer, wherein the hollow groove and the plurality of hollow holes are connected.

[0026] Wherein, the orthographic projection of the cutout groove on the substrate overlaps with the orthographic projection of the plurality of cutout holes on the substrate; in a direction perpendicular to the extension direction of the target connection signal line and parallel to the substrate, the minimum width of the cutout groove is less than the minimum width of the cutout holes.

[0027] Optionally, the inorganic insulating layer has a first ramp portion on the side facing the hollow area; the angle between the ramp surface of the first ramp portion and the side of the inorganic insulating layer facing the substrate is an acute angle; the orthographic projection of the first ramp portion on the substrate is located within the orthographic projection of the first sub-signal line on the substrate;

[0028] And / or, the organic insulating layer has a second ramp portion on the side facing the cutout area; the angle between the ramp surface of the second ramp portion and the side of the organic insulating layer facing the substrate is an acute angle; a portion of the orthographic projection of the second ramp portion on the substrate is located within the orthographic projection of the first sub-signal line on the substrate, and another portion is located outside the orthographic projection of the first sub-signal line on the substrate.

[0029] Optionally, if the line width of the target connection signal line is greater than or equal to the first line width threshold, the cutout area includes the cutout groove;

[0030] When the line width of the target connection signal line is greater than or equal to the second line width threshold and less than the first line width threshold, the cutout area includes the plurality of cutout holes, or the cutout area includes the cutout groove and the plurality of cutout holes;

[0031] When the line width of the target connection signal line is less than the second line width threshold, the cutout area includes the plurality of cutout holes;

[0032] Wherein, the first linewidth threshold is greater than or equal to the second linewidth threshold.

[0033] Optionally, when the line width of the target connection signal line is greater than or equal to the third line width threshold and less than the first line width threshold, the long side direction of the cutout is perpendicular to the extension direction of the target connection signal line.

[0034] When the line width of the target connection signal line is less than the third line width threshold, the long side of the cutout is parallel to the extension direction of the target connection signal line;

[0035] Wherein, the second linewidth threshold is greater than the third linewidth threshold.

[0036] Optionally, the target connection signal line includes at least one of the following: a horizontal drive clock signal line, a clock signal line, and a power signal line.

[0037] On the other hand, a display module is provided, including: any of the display panels described above, and a driving component bonded and connected to the display panel.

[0038] The beneficial effects of the technical solutions provided in this application include at least the following:

[0039] By setting at least one target connection signal line in the connection signal line of the gate driving circuit, the target connection signal line includes a first sub-signal line and a second sub-signal line stacked together. Without increasing the line width of the target connection signal line, the impedance of the target connection signal line can be reduced by connecting the first sub-signal line and the second sub-signal line, thereby reducing the signal load, improving the stability of the driving scan signal applied by the gate driving circuit to the sub-pixel, and ensuring the display effect of the display panel. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0042] Figure 2 is a schematic diagram of the film layer structure of the display panel along A-A' shown in Figure 1;

[0043] Figure 3 is a schematic diagram of the hollow area provided in an embodiment of this application;

[0044] Figure 4 is a schematic diagram of the preparation process of the insulating protective layer provided in the embodiment of this application;

[0045] Figure 5 is a schematic diagram of the film layer structure of another display panel shown in Figure 1 along A-A';

[0046] Figure 6 is a schematic diagram of another hollow area provided in an embodiment of this application;

[0047] Figure 7 is a schematic diagram of the preparation process of another insulating protective layer provided in the embodiment of this application;

[0048] Figure 8 is a schematic diagram of the film layer structure of another display panel in A-A' as shown in Figure 1;

[0049] Figure 9 is a schematic diagram of another hollow area provided in an embodiment of this application;

[0050] Figure 10 is a schematic diagram of the preparation process of another insulating protective layer provided in the embodiments of this application;

[0051] Figure 11 is a schematic diagram of the film layer structure of the display panel along A-A' in another embodiment shown in Figure 1;

[0052] Figure 12 is a schematic diagram of the film layer structure of another display panel in another embodiment shown in Figure 1 along A-A';

[0053] Figure 13 is a schematic diagram of a hollow area as a hollow hole provided in an embodiment of this application;

[0054] Figure 14 is a schematic diagram of another hollow area provided in the embodiment of this application, which is a hollow hole;

[0055] Figure 15 is a schematic diagram of the film structure of the display panel at B-B' shown in Figure 1;

[0056] Figure 16 is a schematic diagram of the structure of the display module provided in this application. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0058] This application provides a display panel. Please refer to Figures 1 and 2. Figure 1 is a structural schematic diagram of the display panel provided in this application embodiment, and Figure 2 is a schematic diagram of the film layer structure of the display panel shown in Figure 1 along A-A'. The display panel 00 has a display area 02 and a non-display area 01 located around the display area 02. The display panel 00 may include: a substrate 10, a plurality of sub-pixels 20, and a gate driving circuit 30.

[0059] Multiple sub-pixels 20 are located on one side of the substrate 10 and distributed within the display area 02.

[0060] The gate driving circuit 30 is located on one side of the substrate 10 and within the non-display area 01. The gate driving circuit 30 may include a plurality of gate driving units 31 and a plurality of connection signal lines 32. One gate driving unit 31 is electrically connected to a row of sub-pixels 20, and at least some of the gate driving units 31 are connected to each other through the plurality of connection signal lines 32.

[0061] Among them, at least one of the multiple connection signal lines 32 is a target connection signal line 320. The target connection signal line 320 may include: a first sub-signal line 321 and a second sub-signal line 322 stacked together. The first sub-signal line 321 is closer to the substrate 10 than the second sub-signal line 322, and the second sub-signal line 322 overlaps with the first sub-signal line 321.

[0062] For example, the gate driving circuit 30 may include multiple cascaded gate driving units 31. The gate driving circuit 30 has two functions: one is an output function, that is, the gate driving circuit 30 can output a gate scan driving signal to the sub-pixel 20. The gate scan driving signal can be used to drive the sub-pixel 20 circuit, thereby achieving the effect of driving the sub-pixel 20 to emit light. The other function is a shift register function. Since the driving circuit includes multiple cascaded gate driving units 31, the multiple gate driving units 31 can adopt a step-by-step shifting method, transmitting shift signals from the first-level gate driving unit 31 downwards. The specific cascading relationship of the multiple gate driving units 31 can be determined by the circuit structure of the gate driving units 31, and this application embodiment does not limit this.

[0063] This embodiment of the application, by setting at least one target connection signal line in the connection signal lines of the gate driving circuit, includes a first sub-signal line and a second sub-signal line stacked together. Without increasing the linewidth of the target connection signal line, the impedance of the target connection signal line can be reduced by overlapping the first and second sub-signal lines, thereby reducing the signal load, improving the stability of the driving scan signal applied by the gate driving circuit to the sub-pixels, and ensuring the display effect of the display panel. Furthermore, the linewidth of the target connection signal line can be further reduced, allowing the gate driving circuit to occupy less space in the non-display area, thus narrowing the non-display area and increasing the screen-to-body ratio of the display mode.

[0064] In some possible implementations, the width of the first sub-signal line 321 is greater than or equal to the width of the second sub-signal line 322 in a direction perpendicular to the extension direction of the target connection signal line 320 and parallel to the substrate 10 (corresponding to the X direction in FIG2).

[0065] To ensure a narrow bezel, the width of the second sub-signal line 322 is less than or equal to the width of the first sub-signal line 321, so that the width of the target connection signal line 320 will not increase, thus ensuring that the width occupied by the gate drive circuit 30 in the non-display area 01 will not increase.

[0066] In some possible implementations, the display panel 00 may also include: an insulating protective layer 40; a first sub-signal line 321 located on the side of the insulating protective layer 40 facing the substrate 10, and a second sub-signal line 322 located on the side of the insulating protective layer 40 away from the substrate 10.

[0067] The insulating protective layer 40 has a cutout area 400; the orthographic projection of the cutout area 400 on the substrate 10 is located within the orthographic projection of the first sub-signal line 321 on the substrate 10; and the second sub-signal line 322 overlaps with the first sub-signal line 321 through the cutout area 400.

[0068] Generally, the connection signal line 32 in the display panel 00 adopts a stacked titanium-aluminum-titanium three-layer metal structure, in which the aluminum metal layer is exposed on the side of the connection signal line 32. In some patterning processes, the aluminum metal layer may react with some etchant, forming a side depression phenomenon (or drilling), which affects the conductivity of the signal line. Therefore, the first sub-signal line 321 is formed before the second sub-signal line 322. In the subsequent processes of the display panel 00, in order to protect the side of the first sub-signal line 321, an insulating protective layer 40 is needed to protect the side of the first sub-signal line 321. In order to ensure the protection effect, the edges of the first sub-signal line 321 also need to be covered. Therefore, an insulating protective layer 40 will exist between the first sub-signal line 321 and the second sub-signal line 322. In order to achieve the overlap between the second sub-signal line 322 and the first sub-signal line 321, the insulating protective layer 40 needs to be provided with a cutout area 400 to achieve the above-mentioned overlap. The orthographic projection of the cutout area 400 on the substrate 10 is located within the orthographic projection of the first sub-signal line 321 on the substrate 10. In other words, the edge of the first sub-signal line 321 is covered by the insulating protective layer 40, and the side of the first sub-signal line 321 is not exposed.

[0069] In some possible implementations, for the cutout area 400 between the first sub-signal line 321 and the second sub-signal line 322 distributed in the same target connection signal line 320, the cutout area 400 may include a cutout groove and / or multiple cutout holes.

[0070] The extension direction of the hollowed-out groove is the same as the extension direction of the target connection signal line 320; the arrangement direction of the multiple hollowed-out holes is the same as the extension direction of the target connection signal line 320.

[0071] In this embodiment, a slot and / or multiple holes can be used to achieve the overlap between the second sub-signal line 322 and the first sub-signal line 321, depending on the width of the target connection signal line 320, so that the second sub-signal line 322 and the first sub-signal line 321 are effectively overlapped, thereby reducing the impedance of the target connection signal line 320.

[0072] In this embodiment of the application, the insulating protective layer 40 between the first sub-signal line 321 and the second sub-signal line 322 may be at least one of an organic insulating layer 42 and an inorganic insulating layer 41.

[0073] In some possible implementations, as shown in Figure 2, the insulating protective layer 40 may include: an inorganic insulating layer 41 and an organic insulating layer 42 stacked together, wherein the inorganic insulating layer 41 is closer to the substrate 10 than the organic insulating layer 42.

[0074] In this embodiment, at least one of the inorganic insulating layer 41 and the organic insulating layer 42 has a cutout region 400. For example, the inorganic insulating layer 41 may be a passivation layer in the display panel 00, and the organic insulating layer 42 may be a first planarization layer in the display panel 00.

[0075] In some possible implementations, please refer to Figures 3 and 4. Figure 3 is a schematic diagram of the hollow area provided in an embodiment of this application, and Figure 4 is a schematic diagram of the preparation process of the insulating protective layer provided in an embodiment of this application. When the hollow area 400 may include a hollow groove, the hollow groove may include: a first sub-hollow groove 411 penetrating the inorganic insulating layer 41, and a second sub-hollow groove 421 penetrating the organic insulating layer 42. The first sub-hollow groove 411 and the second sub-hollow groove 421 are connected.

[0076] The orthographic projection of the second sub-cutout groove 421 on the substrate 10 is located within the orthographic projection of the first sub-cutout groove 411 on the substrate 10.

[0077] For example, as shown in Figure 4, an inorganic insulating layer 41 covering the first sub-signal line 321 is first formed, and the inorganic insulating layer 41 is patterned to form a first sub-cutout groove 411; then an organic insulating layer 42 covering the inorganic insulating layer 41 is formed, and the organic insulating layer 42 is patterned to form a second sub-cutout groove 421.

[0078] Taking the organic insulating layer 42, made of photosensitive organic material, as an example, during the patterning process of the organic insulating layer 42, a photomask can be used to expose the organic insulating layer 42, and then the exposed organic insulating layer 42 can be developed. This transfers the pattern on the photomask onto the organic insulating layer 42, thus achieving the patterning process of the organic insulating layer 42. However, the pattern actually processed on the organic insulating layer 42 deviates from the pattern designed on the photomask by a certain numerical value, which is called CD Bias. In the patterning process of the inorganic insulating layer 41, it cannot be directly formed through the exposure-development process. It is necessary to first transfer the photomask pattern onto the photoresist, and then remove the excess parts through an etching process. Therefore, the CD Bias of the inorganic insulating layer 41 is the sum of the CD Bias generated by the exposure and development of the photoresist and the etching of the inorganic insulating layer 41.

[0079] Furthermore, during the patterning process of the organic insulating layer 42 to form the second sub-groove 421, there is no mask to block the extension direction (Y direction in Figure 4) of the second sub-groove 421 of the organic insulating layer 42, and there is light leakage at the edge. The light path is complex and variable, which leads to enhanced light effect in the X direction. Therefore, by using a photosensitive material as the organic insulating layer 42, the CD Bias of the second sub-groove 421 in the X direction will increase, and may be greater than the CD Bias of the first sub-groove 411 formed on the inorganic insulating layer 41.

[0080] Therefore, the orthographic projection of the second sub-cutout 421 on the substrate 10 needs to be within the orthographic projection of the first sub-cutout 411 on the substrate 10, to ensure that there is enough organic insulating layer 42 to cover the edge of the first sub-signal line 321.

[0081] In some possible implementations, the minimum width of the second sub-groove 421 is smaller than the minimum width of the first sub-groove 411 in a direction perpendicular to the extension direction of the target connection signal line 320 and parallel to the substrate 10 (corresponding to the X direction in Figures 3 and 4).

[0082] As shown in Figure 3, in the exposure process, current optical systems cannot project light onto the photomask and onto the substrate with perfect perpendicularity. The deviation of the light in the vertical direction results in the actual produced organic or inorganic layer pattern boundaries not being perfectly horizontal and vertical, but rather sloped at a certain angle. Therefore, the widths of the second sub-groove 421 and the first sub-groove 411 are gradually changing. To ensure that the orthographic projection of the second sub-groove 421 onto the substrate 10 lies within the orthographic projection of the first sub-groove 411 onto the substrate 10, the minimum width of the second sub-groove 421 must be less than the minimum width of the first sub-groove 411.

[0083] Among some possible implementation methods, please refer to Figures 5 to 7. Figure 5 is a schematic diagram of another film layer structure of the display panel along A-A' as shown in Figure 1. Figure 6 is a schematic diagram of another hollow area provided by an embodiment of this application. Figure 7 is a schematic diagram of the preparation process of another insulating protective layer provided by an embodiment of this application. When the hollow area 400 may include multiple hollow holes, the hollow holes may include: a first sub-hollow hole 412 penetrating the inorganic insulating layer 41, and a second sub-hollow hole 422 penetrating the organic insulating layer 42, wherein the first sub-hollow hole 412 and the second sub-hollow hole 422 are connected.

[0084] The orthographic projection of the first sub-hole 412 on the substrate 10 is located within the orthographic projection of the second sub-hole 422 on the substrate 10.

[0085] For example, as shown in Figure 7, an inorganic insulating layer 41 covering the first sub-signal line 321 is first formed, and the inorganic insulating layer 41 is patterned to form multiple first sub-holes 412; then an organic insulating layer 42 covering the inorganic insulating layer 41 is formed, and the organic insulating layer 42 is patterned to form multiple second sub-holes 422.

[0086] When patterning the second sub-hole 422 on the organic insulating layer 42, the photosensitive organic material is shielded by a mask in the extension direction (Y direction in Figure 7) of the second sub-hole 422, resulting in very little light leakage at the edge. Therefore, the photosensitive material is used as the organic insulating layer 42. The CD bias of the second sub-hole 422 is much smaller than that of the second sub-hole 421, and the CD bias of the second sub-hole 422 is smaller than that of the first sub-hole 421. Therefore, the width of the second sub-hole 422 can be greater than the width of the first sub-hole 421, thus the overlapping area through the second sub-hole 422 is larger.

[0087] In some possible implementations, as shown in Figure 6, the minimum width of the second sub-hole 422 is greater than the minimum width of the first sub-hole 412 in a direction perpendicular to the extension direction of the target connection signal line 320 and parallel to the substrate 10 (corresponding to the X direction in Figure 6).

[0088] Since the widths of the second sub-hole 422 and the first sub-hole 412 are gradually changing, in order to ensure that the orthographic projection of the first sub-hole 412 on the substrate 10 is within the orthographic projection of the second sub-hole 422 on the substrate 10, it is necessary to ensure that the minimum width of the second sub-hole groove 421 is greater than the minimum width of the first sub-hole groove 411.

[0089] Among some possible implementation methods, please refer to Figures 8 to 10. Figure 8 is a schematic diagram of another display panel film layer structure in A-A' shown in Figure 1. Figure 9 is a schematic diagram of another hollow area provided by the embodiment of this application. Figure 10 is a schematic diagram of the preparation process of another insulating protective layer provided by the embodiment of this application. When the hollow area 400 may include a hollow groove 401 and a plurality of hollow holes 402, the hollow area 400 may include: a hollow groove 401 penetrating the inorganic insulating layer 41, and a plurality of hollow holes 402 penetrating the organic insulating layer 42. The hollow groove 401 and the plurality of hollow holes 402 are connected.

[0090] The orthographic projection of the cutout groove 401 on the substrate 10 overlaps with the orthographic projection of the multiple cutout holes 402 on the substrate 10; in the direction perpendicular to the extension direction of the target connection signal line 320 and parallel to the substrate 10 (corresponding to the X direction in Figures 8 to 10), the minimum width of the cutout groove 401 is smaller than the minimum width of the cutout holes 402.

[0091] Since the inorganic insulating layer 41 is generally very thin when etching the cutout groove 401, and the required photoresist thickness is also very thin, the phenomenon of increased CD bias in the X direction due to the lack of obstruction in the Y direction is very small and can be ignored. Therefore, the cutout groove 401 can be formed in the inorganic insulating layer 41. Thus, the cutout area 400 can include a cutout groove 401 penetrating the inorganic insulating layer 41, while multiple cutout holes 402 are formed in the organic insulating layer 42.

[0092] Thus, compared to the hollow area 400 with the first sub-hollow groove 411 and the second sub-hollow groove 421 shown in Figures 5 to 7, the hollow area 400 with the hollow groove 401 and multiple hollow holes 402 shown in Figures 8 to 10 has a larger spatial volume and can provide a better overlapping effect.

[0093] In some possible implementations, as shown in Figures 2, 5 and 8, the inorganic insulating layer 41 has a first ramp portion 413 on the side facing the cutout area 400; the angle between the ramp surface of the first ramp portion 413 and the side of the inorganic insulating layer 41 facing the substrate 10 is an acute angle; the orthographic projection of the first ramp portion 413 on the substrate 10 is located within the orthographic projection of the first sub-signal line 321 on the substrate 10.

[0094] And / or, the organic insulating layer 42 has a second ramp portion 423 on the side facing the cutout area 400; the angle between the ramp surface of the second ramp portion 423 and the side of the organic insulating layer 42 facing the substrate 10 is an acute angle; a portion of the orthographic projection of the second ramp portion 423 on the substrate 10 lies within the orthographic projection of the first sub-signal line 321 on the substrate 10, and another portion lies outside the orthographic projection of the first sub-signal line 321 on the substrate 10. Alternatively, the orthographic projection of the second ramp portion 423 on the substrate 10 may also be within the orthographic projection of the substrate 10.

[0095] As mentioned earlier, the boundary of the organic insulating layer 42 after the actual process is a gradually changing slope, and the ramp distance is positively correlated with the coating thickness. The boundary of the inorganic insulating layer 41 also has a ramp, because this ramp is formed by the etching process. Since the etching reaction is isotropic, the ramp distance is close to the vertical etching depth. The inorganic insulating layer 41 is thinner than the organic insulating layer 42, therefore the ramp distance of the inorganic insulating layer 41 is much smaller than that of the organic insulating layer 42. Because the organic insulating layer 42 has a relatively large thickness (reference value 1.2 μm to 1.7 μm), the second ramp portion 423 can be used to cover the boundary of the first sub-signal line 321, as long as the actual coverage thickness is above 0.5 μm. The inorganic insulating layer 41 has a thinner thickness (reference value 0.3 μm to 0.5 μm), and the first ramp portion 413 needs to avoid the boundary of the first sub-signal line 321. When only the inorganic insulating layer 41 is used as the insulating protective layer 40, the thickness of the inorganic insulating layer 41 can be appropriately increased to more than 0.5 micrometers.

[0096] As shown in Figures 2, 5, and 8, the second ramp portion 423 of the organic insulating layer 42 is generally thicker, which can be used to protect the edge of the first sub-signal line 321. The first ramp portion 413 of the inorganic insulating layer 41 is thinner and needs to avoid covering the edge of the first sub-signal line 321. Therefore, the width a of the edge of the inorganic insulating layer 41 covering the first sub-signal line 321 needs to be greater than the width of the first ramp portion 413, and the width b of the edge of the organic insulating layer 42 covering the first sub-signal line 321 can be smaller than the width of the second ramp portion 423.

[0097] In some possible implementations, please refer to Figures 11 and 12. Figure 11 is a schematic diagram of the film layer structure of the display panel along A-A' in another embodiment shown in Figure 1, and Figure 12 is a schematic diagram of the film layer structure of another display panel along A-A' in another embodiment shown in Figure 1. The insulating protective layer 40 between the first sub-signal line 321 and the second sub-signal line 322 may include only one of the organic insulating layer 42 and the inorganic insulating layer 41.

[0098] As shown in Figure 11, the first sub-signal line 321 can be protected by only the inorganic insulating layer 41. The orthogonal projection of the first ramp portion 413 of the inorganic insulating layer 41 on the substrate 10 is located within the orthogonal projection of the first sub-signal line 321 on the substrate 10.

[0099] For example, the display panel 00 may include an organic insulating layer 42 that covers the inorganic insulating layer 41, but the organic insulating layer 42 is removed in the area near the target connection signal line 320.

[0100] As shown in Figure 12, the first sub-signal line 321 can be protected using only the organic insulating layer 42. A portion of the orthographic projection of the second ramp portion 423 of the organic insulating layer 42 onto the substrate 10 lies within the orthographic projection of the first sub-signal line 321 onto the substrate 10, while the other portion lies outside the orthographic projection of the first sub-signal line 321 onto the substrate 10. Alternatively, the orthographic projection of the second ramp portion 423 onto the substrate 10 can also be within the orthographic projection onto the substrate 10.

[0101] For example, the display panel 00 may not include the inorganic insulating layer 41, and the organic insulating layer 42 may directly cover the substrate 10 and the first sub-signal line 321.

[0102] In this embodiment of the application, for target connection signal lines 320 with different line widths, a corresponding cutout area 400 design is required to achieve the overlap between the second sub-signal line 322 and the first sub-signal line 321. This is based on ensuring that the line width does not increase and that the cutout area 400 does not expose the side of the first sub-signal line 321. The following is a detailed description.

[0103] In some possible implementations, the cutout area 400 may include a cutout slot if the linewidth of the target connection signal line 320 is greater than or equal to a first linewidth threshold.

[0104] When the line width of the target connection signal line 320 is greater than or equal to the second line width threshold and less than the first line width threshold, the cutout area 400 may include multiple cutout holes, or the cutout area 400 may include a cutout groove and multiple cutout holes.

[0105] If the line width of the target connection signal line 320 is less than the second line width threshold, the cutout area 400 may include multiple cutout holes.

[0106] The first linewidth threshold is greater than or equal to the second linewidth threshold. For example, the first linewidth threshold is 9 micrometers and the second linewidth threshold is 7 micrometers.

[0107] For example, as shown in Figure 2, when using the slotted design, an empirical value for the coverage 'a' of the inorganic insulating layer 41 on the first sub-signal line 321 is 1.5 micrometers, and an empirical value for the coverage 'b' of the organic insulating layer 42 on the first sub-signal line 321 is 2.5 micrometers. The width 'c' of the second slot 421 of the organic insulating layer 42 is, based on mass production experience, at least 4 micrometers. Thus, the minimum width 'D' of the first sub-signal line 321 can be obtained as 2b + c = 9 micrometers, which simultaneously satisfies the requirements for edge covering and overlapping of the insulating protective layer 40.

[0108] As shown in Figure 5, when using a scheme with multiple perforations, an empirical value for the coverage 'a' of the inorganic insulating layer 41 on the first sub-signal line 321 is 1.5 micrometers, and an empirical value for the coverage 'b' of the organic insulating layer 42 on the first sub-signal line 321 is 1.35 micrometers. The width 'c' of the second perforation in the organic insulating layer 42, based on mass production experience, is at least 3 micrometers. Thus, the minimum width 'D' of the first sub-signal line 321 can be obtained as 2b + c = 6.7 micrometers.

[0109] As shown in Figure 8, when using the perforated groove 401 and multiple perforated holes 402, an empirical value for the coverage a of the inorganic insulating layer 41 on the first sub-signal line 321 is 1.5 micrometers, and an empirical value for the coverage b of the organic insulating layer 42 on the first sub-signal line 321 is 1.35 micrometers. The width d of the perforated groove 401 of the inorganic insulating layer 41, based on mass production experience, is at least 4 micrometers. Thus, the minimum width D of the first sub-signal line 321 can be obtained as 2a + d = 7 micrometers.

[0110] Therefore, when the line width of the target connection signal line 320 is greater than or equal to the second line width threshold (e.g., 7 micrometers), the cutout area 400 may include multiple cutout holes, or the cutout area 400 may include a cutout groove and multiple cutout holes, i.e., the scheme shown in Figure 5 or Figure 8 is adopted.

[0111] That is, when the linewidth of the target connection signal line 320 is greater than or equal to 9 micrometers, the cutout area 400 may include a cutout slot. When the linewidth of the target connection signal line 320 is greater than or equal to 7 micrometers and less than 9 micrometers, the cutout area 400 may include multiple cutout holes, or the cutout area 400 may include a cutout slot and multiple cutout holes. When the linewidth of the target connection signal line 320 is less than 7 micrometers, the cutout area 400 may include multiple cutout holes.

[0112] Among some possible implementation methods, please refer to Figures 13 and 14. Figure 13 is a schematic diagram of a hollow area as a hollow hole provided by an embodiment of this application; Figure 14 is a schematic diagram of another hollow area as a hollow hole provided by an embodiment of this application. When the hollow area includes multiple hollow holes, the hollow holes can be rectangular, and the hollow holes have a long side x and a short side y. When the line width of the target connection signal line 320 is greater than or equal to the third line width threshold and less than the first line width threshold, the direction of the long side of the hollow hole is perpendicular to the extension direction of the target connection signal line 320 (as shown by the Y direction in Figures 13 and 14).

[0113] When the line width of the target connection signal line 320 is less than the third line width threshold, the long side of the cutout is parallel to the extension direction of the target connection signal line 320.

[0114] The second linewidth threshold is greater than the third linewidth threshold. For example, the third linewidth threshold is 6.7 micrometers.

[0115] When the line width of the target connection signal line 320 is less than the second line width threshold, only a technical solution can be adopted where the cutout area 400 can include multiple cutout holes, i.e., the technical solution shown in Figure 5. When the cutout holes are rectangular, the orientation of the cutout holes can be adjusted according to the line width of the target connection signal line 320, so that when the line width of the target connection signal line 320 is greater than or equal to the third line width threshold and less than the first line width threshold, the density of cutout holes on the target connection signal line 320 is higher, achieving a better overlapping effect.

[0116] For example, as shown in Figures 13 and 14, in Figure 13, the linewidth of one target connection signal line 320 is 7 micrometers, and in Figure 14, the linewidth of another target connection signal line 320 is 6.5 micrometers. The minimum size of the cutout is 3 micrometers × 4 micrometers, and the spacing between the cutouts is equal. Given the same length, when the linewidth of the target connection signal line 320 is greater than or equal to a third linewidth threshold and less than a first linewidth threshold, the long side of the cutout is perpendicular to the extension direction of the target connection signal line 320, allowing for the arrangement of 3 cutouts. However, when the linewidth of the target connection signal line 320 is less than the third linewidth threshold, the long side of the cutout is parallel to the extension direction of the target connection signal line 320, allowing for the arrangement of only 2 cutouts. It is evident that having the short side of the cutout parallel to the extension direction of the signal line, compared to having the long side parallel to the extension direction, allows for the placement of more cutouts, increasing the overlap area. When the long side of the cutout is parallel to the direction of the signal line extension, although the overlap area is smaller, the required line width of the signal line is narrower, which helps to further narrow the width occupied by the gate drive circuit 30.

[0117] In some possible implementations, the target connection signal line 320 may include at least one of the following: a horizontal drive clock signal line, a clock signal line, and a power supply signal line.

[0118] The horizontal drive clock signal line can also be called the GSTV signal line. Clock signal lines are generally designed in pairs, including the GCB signal line and the GCK signal line. The power signal lines can include a high-level signal line (VGH signal line) and a low-level signal line (VGL signal line). The design scheme of the target connection signal line 320 provided in this application embodiment can be applied to any of the above signal lines.

[0119] Please refer to Figure 15, which is a schematic diagram of the film structure of the display panel at B-B' shown in Figure 1. In this embodiment, the display panel may include: a substrate 10, and an active layer 2003, a first gate insulating layer 2004, a first conductive layer (co-layered with the first electrode 2006 and the gate layer 2005 and made of the same material), a passivation layer 2007, a second conductive layer (co-layered with the second electrode 2008 and made of the same material), an interlayer dielectric layer 2100, a third conductive layer 4000, a first planarization layer 6000, a fourth conductive layer 7000, an organic planarization layer 8000, an anode layer 3001, a pixel definition layer 3004, a light-emitting layer 3002, a support layer 3005, a cathode layer 3003, an encapsulation layer 9002, a touch electrode layer 9001, and an organic touch protection layer 9000, all stacked on one side of the substrate 10.

[0120] The active layer 2003, gate layer 2005, first conductive layer, third conductive layer 4000, and fourth conductive layer 7000 are used to form multiple pixel driving circuits 2000 electrically connected to the light-emitting device 3000, as well as various signal lines electrically connected to the pixel driving circuits 2000. The light-emitting device 3000 includes an anode layer 3001, a light-emitting layer 3002, and a cathode layer 3003 stacked together. The pixel driving circuits 2000 can be electrically connected to the anode layer 3001 in the light-emitting device 3000.

[0121] The pixel driving circuit 2000 may include at least two transistors and a storage capacitor. The third conductive layer 4000 may include the drains of the transistors. The first conductive layer may include the gate layer 2005 of the transistors and the first electrode 2006 of the storage capacitor. The second conductive layer may include the second electrode 2008 of the storage capacitor.

[0122] In this embodiment of the application, when the insulating protective layer 40 includes an inorganic insulating layer 41 and an organic insulating layer 42, the first sub-signal line 321 may be disposed in the same layer as one of the first conductive layer or the second conductive layer, the second sub-signal line 322 may be disposed in the same layer as the fourth conductive layer 7000, the inorganic insulating layer 41 may be disposed in the same layer as one of the passivation layer 2007 or the interlayer dielectric layer 2100, and the organic insulating layer 42 may be disposed in the same layer as the first planarization layer 6000.

[0123] When the insulating protective layer 40 only includes the organic insulating layer 42, the first sub-signal line 321 may be disposed in the same layer as one of the first conductive layer, the second conductive layer, or the third conductive layer 4000; the second sub-signal line 322 may be disposed in the same layer as one of the third conductive layer 4000 or the fourth conductive layer 7000. When the first sub-signal line 321 is disposed in the same layer as the third conductive layer 4000, the second sub-signal line 322 is disposed in the same layer as the fourth conductive layer 7000; the organic insulating layer 42 may be disposed in the same layer as the first planarization layer 6000.

[0124] When the insulating protective layer 40 only includes the organic insulating layer 41, the first sub-signal line 321 may be disposed in the same layer as one of the first conductive layer or the second conductive layer; the second sub-signal line 322 may be disposed in the same layer as one of the third conductive layer 4000 or the fourth conductive layer 7000; and the inorganic insulating layer 41 may be disposed in the same layer as one of the passivation layer 2007 or the interlayer dielectric layer 2100.

[0125] In summary, the display panel and display module provided in this application include a substrate, multiple sub-pixels, and a gate driving circuit. By providing at least one target connection signal line in the connection signal lines of the gate driving circuit, and the target connection signal line including a first sub-signal line and a second sub-signal line stacked together, the impedance of the target connection signal line can be reduced by overlapping the first sub-signal line and the second sub-signal line without increasing the linewidth of the target connection signal line. This reduces the signal load, improves the stability of the driving scan signal applied by the gate driving circuit to the sub-pixels, and ensures the display effect of the display panel.

[0126] Please refer to Figure 16, which is a schematic diagram of the structure of the display module provided in this application. The display module may include: the display panel 00 described in any of the above embodiments, and a driving component 50 that is bonded and connected to the display panel 00. The driving component 50 may be electrically connected to the connection signal line 32 described above. The display module may have the technical effects of the display panel 00 described above, which will not be repeated here.

[0127] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0128] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0129] The above description is only one of the possible implementations of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel has a display area and a non-display area located around the display area; the display panel includes: a substrate, a plurality of sub-pixels, and a gate driving circuit; The plurality of sub-pixels are located on one side of the substrate and distributed within the display area; The gate driving circuit is located on one side of the substrate and within the non-display area; the gate driving circuit includes: a plurality of gate driving units and a plurality of connection signal lines, one of the gate driving units is electrically connected to a row of the sub-pixels, and at least some of the plurality of gate driving units are connected to each other through the plurality of connection signal lines; Among them, at least one of the multiple connection signal lines is a target connection signal line, and the target connection signal line includes: a first sub-signal line and a second sub-signal line stacked together, wherein the first sub-signal line is closer to the substrate than the second sub-signal line, and the second sub-signal line overlaps with the first sub-signal line.

2. The display panel according to claim 1, characterized in that, In a direction perpendicular to the extension direction of the target connection signal line and parallel to the substrate, the width of the first sub-signal line is greater than or equal to the width of the second sub-signal line.

3. The display panel according to claim 1, characterized in that, The display panel also includes: an insulating protective layer; The first sub-signal line is located on the side of the insulating protective layer facing the substrate, and the second sub-signal line is located on the side of the insulating protective layer away from the substrate; The insulating protective layer has a cutout area; the orthographic projection of the cutout area on the substrate is located within the orthographic projection of the first sub-signal line on the substrate; and the second sub-signal line overlaps with the first sub-signal line through the cutout area.

4. The display panel according to claim 3, characterized in that, For the hollow area between the first sub-signal line and the second sub-signal line distributed in the same target connection signal line, the hollow area includes a hollow groove and / or multiple hollow holes; The extension direction of the hollowed-out groove is the same as the extension direction of the target connection signal line; the arrangement direction of the plurality of hollowed-out holes is the same as the extension direction of the target connection signal line.

5. The display panel according to claim 4, characterized in that, The insulating protective layer includes: an inorganic insulating layer and an organic insulating layer stacked together, wherein the inorganic insulating layer is closer to the substrate than the organic insulating layer; The inorganic insulating layer and the organic insulating layer each have the hollowed-out area.

6. The display panel according to claim 5, characterized in that, When the hollow area includes the hollow groove, the hollow groove includes: a first sub-hollow groove penetrating the inorganic insulating layer, and a second sub-hollow groove penetrating the organic insulating layer, wherein the first sub-hollow groove and the second sub-hollow groove are connected. The orthographic projection of the second sub-cutout groove on the substrate is located within the orthographic projection of the first sub-cutout groove on the substrate.

7. The display panel according to claim 6, characterized in that, In a direction perpendicular to the extension direction of the target connection signal line and parallel to the substrate, the minimum width of the second sub-cutout is smaller than the minimum width of the first sub-cutout.

8. The display panel according to claim 5, characterized in that, When the hollow area includes the plurality of hollow holes, the hollow holes include: a first sub-hollow hole penetrating the inorganic insulating layer, and a second sub-hollow hole penetrating the organic insulating layer, wherein the first sub-hollow hole and the second sub-hollow hole are connected. The orthographic projection of the first sub-hole on the substrate is located within the orthographic projection of the second sub-hole on the substrate.

9. The display panel according to claim 8, characterized in that, In a direction perpendicular to the extension direction of the target connection signal line and parallel to the substrate, the minimum width of the second sub-hole is greater than the minimum width of the first sub-hole.

10. The display panel according to claim 5, characterized in that, When the hollow area includes the hollow groove and the plurality of hollow holes, the hollow area includes: a hollow groove penetrating the inorganic insulating layer, and a plurality of hollow holes penetrating the organic insulating layer, wherein the hollow groove and the plurality of hollow holes are connected. Wherein, the orthographic projection of the cutout groove on the substrate overlaps with the orthographic projection of the plurality of cutout holes on the substrate; in a direction perpendicular to the extension direction of the target connection signal line and parallel to the substrate, the minimum width of the cutout groove is less than the minimum width of the cutout holes.

11. The display panel according to any one of claims 5-10, characterized in that, The inorganic insulating layer has a first ramp on the side facing the hollow area; the angle between the ramp surface of the first ramp and the side of the inorganic insulating layer facing the substrate is an acute angle. The orthographic projection of the first ramp portion on the substrate is located within the orthographic projection of the first sub-signal line on the substrate; And / or, the organic insulating layer has a second ramp on the side facing the cutout area; the angle between the ramp surface of the second ramp and the side of the organic insulating layer facing the substrate is an acute angle; A portion of the orthographic projection of the second climbing portion onto the substrate lies within the orthographic projection of the first sub-signal line onto the substrate, while another portion lies outside the orthographic projection of the first sub-signal line onto the substrate.

12. The display panel according to any one of claims 4-10, characterized in that, When the line width of the target connection signal line is greater than or equal to the first line width threshold, the cutout area includes the cutout groove; When the line width of the target connection signal line is greater than or equal to the second line width threshold and less than the first line width threshold, the cutout area includes the plurality of cutout holes, or the cutout area includes the cutout groove and the plurality of cutout holes; When the line width of the target connection signal line is less than the second line width threshold, the cutout area includes the plurality of cutout holes; Wherein, the first linewidth threshold is greater than or equal to the second linewidth threshold.

13. The display panel according to claim 12, characterized in that, When the line width of the target connection signal line is greater than or equal to the third line width threshold and less than the first line width threshold, the long side direction of the cutout is perpendicular to the extension direction of the target connection signal line. When the line width of the target connection signal line is less than the third line width threshold, the long side of the cutout is parallel to the extension direction of the target connection signal line; Wherein, the second linewidth threshold is greater than the third linewidth threshold.

14. The display panel according to any one of claims 1-10, characterized in that, The target connection signal line includes at least one of the following: a horizontal drive clock signal line, a clock signal line, and a power signal line.

15. A display module, characterized in that, include: The display panel according to any one of claims 1-14, and the driving component bonded to the display panel.

Images