Semiconductor device and preparation method therefor, solid-state phase shifter, and communication device

Abstract

The present application relates to a semiconductor device and a preparation method therefor, a solid-state phase shifter, and a communication device. The semiconductor device comprises a substrate, a first isolation layer and a second isolation layer, wherein the substrate is provided with at least one trench, and the trench extends from a first semiconductor layer to a third semiconductor layer of the substrate; the first isolation layer comprises a first portion located outside a first trench and a second portion located inside the first trench, the first portion and the second portion being connected to enclose at least one second trench; the second isolation layer is located outside the second trench and covers an opening of the second trench, so that the second portion and at least part of the second isolation layer enclose a closed isolation cavity; and a size L1 of the opening of the at least one second trench in the second direction satisfies: L1≥5μm. The second isolation layer provides a stable and reliable sealing effect for the opening of the trench to reduce the possibility of foreign matters, such as external moisture and dust, entering the trench, so as to improve the isolation effect of the trench, thereby improving the reliability of the semiconductor device.

Description

A semiconductor device and its fabrication method, a solid-state phase shifter, and a communication device.

[0001] This application claims priority to Chinese Patent Application No. 202411998837.X, filed with the State Intellectual Property Office of China on December 31, 2024, entitled "A Semiconductor Device and its Fabrication Method, a Fixed Phase Shifter, and a Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of diode technology, and in particular to a semiconductor device and its fabrication method, a fixed phase shifter, and a communication device. Background Technology

[0003] With the development of science and technology, the application fields of semiconductor devices are becoming increasingly widespread. In order to achieve electrical isolation between adjacent active regions within a semiconductor device, an isolation structure is usually provided on the semiconductor device. Currently, the sealing performance of the isolation structure is poor, and external foreign matter such as moisture can easily enter the isolation structure, affecting the isolation effect and thus affecting the performance of the semiconductor device.

[0004] Application content

[0005] This application provides a semiconductor device and its fabrication method, a solid-state phase shifter, and a communication device, which helps to solve the problem of poor isolation effect of the isolation structure on the semiconductor device in the prior art.

[0006] In a first aspect, embodiments of this application provide a semiconductor device, including a substrate, a first isolation layer, and a second isolation layer. The substrate includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked along a first direction. The second semiconductor layer is located between the first semiconductor layer and the third semiconductor layer. The substrate has at least one first trench, which extends from the first semiconductor layer to the third semiconductor layer. The first isolation layer includes a first portion located outside the first trench and a second portion located inside the first trench. At least a portion of the first portion is located on the side of the first semiconductor layer opposite to the second semiconductor layer. The second portion covers at least a portion of the sidewall of the first trench and at least a portion of the bottom of the first trench. The first portion and the second portion are connected and form at least one second trench. The second trench has an opening on the side of the first trench opposite to the third semiconductor layer along the first direction. The second isolation layer is located outside the second trench and covers the opening. At least a portion of the first portion, the second portion, and at least a portion of the second isolation layer form a sealed isolation cavity. The dimension L1 of the opening of at least one second trench along the second direction satisfies: L1≥5μm.

[0007] In this embodiment, the isolation cavity can prevent external moisture and impurities from entering, and the semiconductor device achieves electrical isolation between adjacent active regions through the isolation cavity. When the dimension L1 of the groove opening of the second groove along the second direction is ≥ 5μm, the dimension of the isolation cavity along the second direction is larger, resulting in better isolation. Moreover, since the isolation cavity is not filled with insulating material, the isolation effect will not decrease due to the insulation material not filling the isolation cavity completely, nor will the sealing performance deteriorate due to the thermal expansion and contraction of the insulating material. This makes the sealing reliability of the isolation cavity high, thereby improving the electrical isolation effect of the isolation cavity.

[0008] In one possible implementation, at least one of the slots has a dimension L1 along the second direction that satisfies: L1≥10μm.

[0009] By further increasing the size of the slot opening of the second tank, a better isolation effect can be achieved. Moreover, the first and second isolation layers are connected by a bonding process, which can effectively seal the slot opening with L1≥10μm, making the electrical isolation performance and withstand voltage performance of the isolation cavity high.

[0010] In one possible implementation, the first isolation layer is bonded to the second isolation layer.

[0011] In this design, the first and second isolation layers are bonded together, improving the stability of their bond and reducing the possibility of separation or gaps at their contact points that could affect the sealing performance of the isolation cavity. This further reduces the likelihood of external contaminants such as moisture and dust entering the isolation cavity, thereby improving its isolation effect and enhancing the reliability of the semiconductor device. Simultaneously, the bonding method between the first and second isolation layers can seal large-sized slots, ensuring a stable and reliable seal between the second isolation layer and the slot opening. This reduces the possibility of gaps between the second isolation layer and the slot opening affecting the sealing performance of the isolation cavity, thus improving its overall isolation effect.

[0012] In one possible implementation, the first semiconductor layer has a first top surface facing away from the second semiconductor layer, the apex of the first trench connecting the sidewall to the first top surface is rounded, and the bottom of the first trench connecting the sidewall to the bottom is rounded.

[0013] Compared to right angles, rounded corners can disperse the electric field, reducing the electric field density at the rounded corners inside the first tank. This prevents leakage current during semiconductor device operation (especially under high voltage), thereby improving the electrical isolation effect of the isolation cavity formed by the first and second isolation layers. Furthermore, when the first isolation layer covers the first tank, the rounded corners of the first tank can also reduce stress concentration in the first isolation layer, improving its reliability, and thus enhancing the electrical isolation reliability of the isolation cavity formed by the first and second isolation layers.

[0014] In one possible implementation, the first portion has a second top surface facing away from the substrate, the apex of the second tank where the sidewall connects to the second top surface is rounded, and the bottom of the second tank where the sidewall connects to the bottom is rounded.

[0015] The sidewall of the opening of the second groove can have a first rounded corner. The first isolation layer with the first rounded corner experiences less stress concentration and higher structural strength at this location. Furthermore, the first rounded corner is located close to the bonding point between the first and second isolation layers. Compared to a right angle, the rounded corner reduces damage to the second isolation layer during bonding, increases the structural strength of the second isolation layer, and thus improves the isolation reliability of the isolation cavity formed by the first and second isolation layers. The second groove has a first bottom and a first sidewall. The junction between the first bottom and the first sidewall has a second rounded corner. The first isolation layer with the second rounded corner experiences less stress concentration and higher structural strength at this location, further improving the isolation reliability of the isolation cavity formed by the first and second isolation layers.

[0016] In one possible implementation, the second isolation layer has a planar structure, with the bottom surface of the second isolation layer facing the substrate flush with the top surface of the first portion facing away from the substrate.

[0017] When the first and second insulating layers are bonded together, the second insulating layer does not enter the second tank, allowing it to have a planar structure and thus higher structural strength. Furthermore, the bottom of the second insulating layer does not extend into the first sidewall of the second tank. Since there is no second insulating layer inside the second tank, there is no insulating material inside. The interior of the second tank is a vacuum or inert gas. Compared to insulating materials, vacuum or inert gas has a lower dielectric constant, reducing dielectric loss.

[0018] In one possible implementation, at least one of the second groove bodies has a minimum dimension L2 along the second direction that satisfies: L2 ≥ 5 μm.

[0019] The minimum dimension L2 of the second groove along the second direction is made to satisfy: L2≥5μm. This ensures the isolation effect of the isolation cavity while making the space occupied by the isolation cavity on the substrate more reasonable, thereby improving the stability of the substrate structure and thus improving the stability of the semiconductor device.

[0020] In one possible implementation, at least one of the second groove bodies has a minimum dimension L2 along the second direction that satisfies: L2 ≥ 10 μm.

[0021] To achieve better isolation, the width of the second groove is further increased.

[0022] In one possible implementation, the cross-section of the second groove along the first direction is any one of a rectangle, U-shape, gourd shape, V-shape, trapezoid, inverted trapezoid, or irregular shape.

[0023] The cross-section of the isolation cavity is designed to meet the different application requirements of semiconductor devices.

[0024] In one possible implementation, the thickness D1 of the first isolation layer satisfies 0.1μm≤D1≤5μm, and / or the thickness D2 of the second isolation layer satisfies 0.1μm≤D2≤5μm.

[0025] Designing the thickness of the first isolation layer 13 to be between 0.1 μm and 5 μm can improve the withstand voltage capability of the semiconductor device while reducing the risk of cracking due to excessive stress, thus improving the reliability of the first isolation layer. This ensures the sealing performance of the isolation cavity, enhances its isolation effect, and reduces the production cost of the semiconductor device 1. Designing the thickness of the second isolation layer to be between 0.1 μm and 5 μm can ensure stable bonding between the first and second isolation layers while improving the stability and reliability of the second isolation layer. This allows the second isolation layer to provide a stable and reliable seal to the slot of the isolation cavity, thereby improving the isolation effect of the isolation cavity.

[0026] In one possible implementation, 0.1μm≤D1≤2μm, and / or, 0.1μm≤D2≤2μm.

[0027] In one possible implementation, the first insulating layer comprises one or more of the following: oxides of aluminum, silicon, and titanium; nitrides of aluminum, silicon, and titanium; oxynitrides of aluminum, silicon, and titanium; oxides of hafnium, lanthanum, and zirconium; and / or the second insulating layer comprises one or more of the following: oxides of aluminum, silicon, and titanium; nitrides of aluminum, silicon, and titanium; oxynitrides of aluminum, silicon, and titanium; oxides of aluminum, silicon, and titanium; oxides of hafnium, lanthanum, and zirconium.

[0028] The above-mentioned materials are used to improve the reliability of the first and second isolation layers, thereby ensuring the isolation effect of the isolation cavity.

[0029] In one possible implementation, the second isolation layer is a laminated structure, and at least two layers in the laminated structure have different stresses.

[0030] To reduce the risk of the second isolation layer breaking, the second isolation layer can be set as a stacked structure of two or more layers, and at least two of the two or more layers in the stacked structure have different internal stresses. In this way, the internal stress inside the second isolation layer can be adjusted by using membrane layers of different materials, so that the internal stress of the second isolation layer is more balanced, thereby reducing the risk of the second isolation layer breaking at the groove position.

[0031] In one possible implementation, the second isolation layer includes at least a first layer and a second layer, wherein one of the first layer and the second layer is a tensile stress material and the other is a compressive stress material.

[0032] In this design, of the two membrane layers constituting the second isolation layer, one layer tends to contract while the other tends to expand. For example, when the first layer is a compressive stress material and the second layer is a tensile stress material, the first layer tends to contract while the second layer tends to expand, causing the overall internal stress of the second isolation layer to tend to be balanced. When the second isolation layer is subjected to external force, the tendency to contract is suppressed by the second layer, and the tendency to expand is suppressed by the first layer. This reduces the risk of permanent deformation or even fracture of the second isolation layer under external force, thereby reducing the risk of fracture at the groove opening of the second groove and improving the isolation reliability of the isolation cavity formed by the first and second isolation layers.

[0033] In one possible implementation, the first layer is silicon nitride, and the second layer is silicon oxide. Silicon nitride is a compressive stress material, and silicon oxide is a tensile stress material. When the second isolation layer includes both the first and second layers, the internal stress of the second isolation layer tends to be balanced, reducing the risk of permanent deformation or even fracture under external force. This reduces the risk of the second isolation layer breaking at the groove opening of the second tank, improving the isolation reliability of the isolation cavity formed by the first and second isolation layers. In another possible implementation, the first layer is Si3N4, the second layer is SiO2, and the thickness D3 of the first layer satisfies: 50nm ≤ D3 ≤ 400nm, and the thickness D4 of the second layer satisfies: 0.4μm ≤ D4 ≤ 4μm.

[0034] Si3N4 is a tensile stress material, and SiO2 is a compressive stress material. The first layer tends to expand, while the second layer tends to contract, thus balancing the overall internal stress of the second isolation layer. This makes the second isolation layer less prone to expansion or contraction under stress. By using materials with different stresses and adjusting their thicknesses, the internal stress of the second isolation layer can be brought close to zero, reducing the risk of fracture and improving the reliability of the isolation cavity.

[0035] In one possible implementation, the second isolation layer includes a first layer and a second layer stacked along a first direction, the first layer being connected to the first isolation layer, and the first layer being made of the same material as the first isolation layer.

[0036] This ensures that the bonding between the first and second isolation layers is homogeneous bonding, which is a type of van der Waals bonding. Van der Waals bonding has a very strong bonding force, achieving a tight bond between the first and second isolation layers. At the same time, it improves the reliability of the contact interface between the first and second isolation layers, making it almost impossible for the first and second isolation layers to separate. As a result, the second isolation layer can reliably seal the opening of the first groove, improving the isolation effect of the first groove.

[0037] In one possible implementation, the second isolation layer comprises silicon oxide and silicon nitride.

[0038] In one possible implementation, the second tank includes a plurality of mutually isolated cavities, and adjacent cavities are separated by a support structure. The second tank has a first bottom, one end of the support structure is connected to the first bottom, and the other end is connected to the second isolation layer.

[0039] The supporting structure supports the second isolation layer, reducing the possibility of the second isolation layer collapsing into the second tank. At the same time, it improves the stability of the second isolation layer structure above the second tank, reducing the possibility of cracking of the second isolation layer above the second tank. This allows the second isolation layer to reliably seal the opening of the second tank, thereby improving the isolation effect of the isolation cavity.

[0040] In one possible implementation, the substrate includes a first region and a second region, the first region being provided with a first metal electrode, and the first tank being disposed in the second region.

[0041] The above design enables the first tank to achieve electrical isolation between adjacent active regions within the semiconductor device, thereby improving the reliability of the semiconductor device.

[0042] In one possible implementation, the projections of the first groove and the second groove along the first direction are both annular, the first groove surrounds the first region, and the dimension L3 of the first region along the second direction satisfies: 50μm≤L3≤200μm.

[0043] Limiting the size of the first region means limiting the size of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer below the first metal electrode, so that the semiconductor device has excellent electrical performance and meets the requirements of impedance and capacitance of the semiconductor device.

[0044] Secondly, embodiments of this application provide a solid-state phase shifter, which includes any of the semiconductor devices described above.

[0045] Thirdly, embodiments of this application provide a communication device, which includes the solid-state phase shifter described above.

[0046] Fourthly, this application provides a method for fabricating a semiconductor device, the method comprising:

[0047] A first substrate is provided, the first substrate comprising a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially, and at least one first trench is formed on the first substrate, such that the first trench extends from the first semiconductor layer to the third semiconductor layer, and the width L4 of the opening of the first trench is greater than 5 μm.

[0048] A first isolation layer is formed on the inner wall surface of the first tank and at least a portion of the surface of the first semiconductor layer. The first isolation layer includes a first portion located outside the first tank and a second portion located inside the first tank. At least a portion of the first portion is located on the side of the first semiconductor layer opposite to the second semiconductor layer. The second portion covers at least a portion of the sidewall of the first tank and at least a portion of the bottom of the first tank. The first portion and the second portion are connected and form at least one second tank. The portion of the first isolation layer outside the first tank has a first surface opposite to the third semiconductor layer.

[0049] A second substrate is provided, and a second isolation layer is formed on the surface of the second substrate, the second isolation layer having a second surface facing away from the second substrate;

[0050] Using the first surface and the second surface as bonding surfaces, the first isolation layer and the second isolation layer are bonded together, the second isolation layer covers the opening of the second groove, and at least a portion of the first part, the second part and at least a portion of the second isolation layer form a sealed isolation cavity;

[0051] At least a portion of the second substrate is removed, a portion of the second isolation layer and a portion of the first portion are removed, exposing a portion of the surface of the first semiconductor layer;

[0052] A first metal electrode is formed on the exposed surface of the first semiconductor layer, and a second metal electrode is formed on the surface of the third semiconductor layer opposite to the second semiconductor layer.

[0053] This embodiment of the application bonds the first and second isolation layers together, improving the stability of their bond and reducing the possibility of separation or gaps at their contact points that could affect the sealing performance of the isolation cavity. This further reduces the possibility of external moisture, dust, and other foreign matter entering the isolation cavity, thereby improving the isolation effect and enhancing the reliability of the semiconductor device. Simultaneously, the bonding method between the first and second isolation layers can seal large-sized slots, ensuring a stable and reliable seal between the second isolation layer and the slot opening, reducing the possibility of gaps between the second isolation layer and the slot opening affecting the sealing performance of the isolation cavity, thus improving the isolation effect. When the slot opening size L1 of the second slot satisfies L1≥5μm, the isolation cavity has a larger width, resulting in better isolation.

[0054] In one possible implementation, the first semiconductor layer has a first top surface facing away from the second semiconductor layer. When at least one first trench is formed on the first substrate, the method for fabricating the semiconductor device specifically includes: applying a first barrier layer to the surface of the first semiconductor layer facing away from the second semiconductor layer and patterning it; etching the surface of the first barrier layer to form the first trench; removing the first barrier layer; and processing the first trench such that the apex corner connecting the sidewall of the first trench to the top surface of the first semiconductor layer is rounded, and the bottom corner connecting the bottom of the first trench to the sidewall is rounded.

[0055] Compared to right angles, rounded corners can disperse the electric field, reducing the electric field density at the rounded corners inside the first tank. This prevents leakage current during semiconductor device operation (especially under high voltage), thereby improving the electrical isolation effect of the isolation cavity formed by the first and second isolation layers. Furthermore, when the first isolation layer covers the first tank, the rounded corners of the first tank can also reduce stress concentration in the first isolation layer, improving its reliability, and thus enhancing the electrical isolation reliability of the isolation cavity formed by the first and second isolation layers.

[0056] In one possible implementation, the first tank is subjected to wet etching or high-temperature annealing in a hydrogen atmosphere, so that the apex corner connecting the sidewall of the first tank to the first top surface is rounded, and the bottom corner connecting the bottom of the first tank to the sidewall is rounded.

[0057] In one possible implementation, before bonding the first isolation layer and the second isolation layer, the preparation method further includes: chemically and mechanically polishing the first surface and the second surface to make the roughness of the first surface less than 0.5 nm, and / or the roughness of the second surface less than 0.5 nm.

[0058] Chemical mechanical polishing can remove contaminants from the first and second surfaces, reducing their roughness and providing a basis for stable and reliable bonding of the first and second isolation layers.

[0059] In one possible implementation, after chemically and mechanically polishing the first surface and the second surface and before bonding the first isolation layer and the second isolation layer, the preparation method further includes: performing plasma surface activation treatment on the first surface and the second surface.

[0060] Plasma surface activation treatment can improve the bonding strength between the first and second surfaces.

[0061] In one possible implementation, when a second substrate is provided and a second isolation layer is formed on the surface of the second substrate, the method for fabricating the semiconductor device includes: forming a second layer on the surface of the second substrate, forming a first layer on the surface of the second layer, wherein one of the first layer and the second layer is a tensile stress material and the other is a compressive stress material, and the second surface is the surface of the first layer away from the second layer.

[0062] In this design, of the two membrane layers constituting the second isolation layer, one layer tends to contract while the other tends to expand. For example, when the first layer is a compressive stress material and the second layer is a tensile stress material, the first layer tends to contract while the second layer tends to expand, causing the overall internal stress of the second isolation layer to tend to be balanced. When the second isolation layer is subjected to external force, the tendency to contract is suppressed by the second layer, and the tendency to expand is suppressed by the first layer. This reduces the risk of permanent deformation or even fracture of the second isolation layer under external force, thereby reducing the risk of fracture at the groove opening of the second groove and improving the isolation reliability of the isolation cavity formed by the first and second isolation layers.

[0063] In one possible implementation, when a portion of the second isolation layer and a portion of the first isolation layer are removed to expose a portion of the surface of the first semiconductor layer, the method for fabricating the semiconductor device includes: applying a second barrier layer to a third surface of the second isolation layer and patterning it, wherein the third surface is a surface of the second isolation layer disposed opposite to the second surface along a first direction; etching one side of the second barrier layer to expose a portion of the surface of the first semiconductor layer; and removing the second barrier layer.

[0064] In one possible implementation, the first isolation layer is formed by a combination of one or more of thermal oxidation, chemical vapor deposition, and atomic layer deposition, and / or the second isolation layer is formed by a combination of one or more of thermal oxidation, chemical vapor deposition, and atomic layer deposition.

[0065] In one possible implementation, when bonding the first isolation layer and the second isolation layer, a nitrogen gas source is used to perform plasma treatment in a vacuum chamber, and the first surface and the second surface are bonded at room temperature.

[0066] In one possible implementation, after bonding the first isolation layer and the second isolation layer, the method for fabricating the semiconductor device further includes: annealing the bonded structure at a temperature of 400°C to 1000°C for a time of 0.5 hours to 12 hours.

[0067] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0068] Figure 1 is a cross-sectional view of a semiconductor device provided in an embodiment of this application;

[0069] Figure 2 is a cross-sectional view of a semiconductor device in a related technology;

[0070] Figure 3 is a schematic diagram showing the volume shrinkage of the insulating material in Figure 2;

[0071] Figure 4a is a cross-sectional view of a semiconductor device 1 provided in another embodiment of this application;

[0072] Figure 4b is a magnified view of part A in Figure 4a.

[0073] Figure 5 is a cross-sectional view of a semiconductor device in an isolation cavity in the related technology;

[0074] Figure 6 is a partial schematic diagram of a semiconductor device in another embodiment of this application;

[0075] Figure 7 is a partial cross-sectional view of the substrate of a semiconductor device provided in an embodiment of this application at the location of the first trench.

[0076] Figure 8a is a partial cross-sectional view of a portion of a semiconductor device 1 provided in an embodiment of this application at the location of the second tank 19;

[0077] Figure 8b is a partial cross-sectional view of a semiconductor device 1 provided in an embodiment of this application at the isolation cavity 17;

[0078] Figure 9 is a partial top view of a semiconductor device provided in an embodiment of this application;

[0079] Figure 10 is a partial top view of a substrate and a first isolation layer in a semiconductor device according to another embodiment of this application;

[0080] Figure 11 is a partial top view of a semiconductor device provided in yet another embodiment of this application;

[0081] Figure 12 is a partial schematic diagram of a semiconductor device in one embodiment of this application;

[0082] Figure 13 is a partial schematic diagram of a semiconductor device in another embodiment of this application;

[0083] Figure 14 is a schematic diagram of a support structure provided in the isolation cavity in one embodiment of this application;

[0084] Figure 15 is a schematic diagram of multiple support structures arranged in an isolation cavity according to an embodiment of this application;

[0085] Figure 16 is a flowchart of a specific embodiment of the method for fabricating the semiconductor device provided in this application;

[0086] Figure 17 is a schematic diagram of the structure formed in step S101 in a specific embodiment;

[0087] Figure 18 is a schematic diagram of the structure formed in step S102 in a specific embodiment;

[0088] Figure 19 is a schematic diagram of the structure formed in step S103 in a specific embodiment;

[0089] Figure 20 is a schematic diagram of the structure formed in step S104 in a specific embodiment;

[0090] Figure 21 is a schematic diagram of the structure formed in step S20 in a specific embodiment;

[0091] Figure 22 is a schematic diagram of the structure formed in step S30 in a specific embodiment;

[0092] Figure 23 is a schematic diagram of the structure formed in step S60 in a specific embodiment;

[0093] Figure 24 is a schematic diagram of the structure formed in step S70 in a specific embodiment;

[0094] Figure 25 is a schematic diagram of the structure formed in step S801 in a specific embodiment;

[0095] Figure 26 is a schematic diagram of the structure formed in step S802 in a specific embodiment;

[0096] Figure 27 is a schematic diagram of the structure formed in step S90 in a specific embodiment;

[0097] Figure 28 is a schematic diagram of the structure formed in step S302 in a specific embodiment;

[0098] Figure 29 is a schematic diagram of the structure formed in step S601 in a specific embodiment;

[0099] Figure 30 is a schematic diagram of the structure formed in step S701 in a specific embodiment;

[0100] Figure 31 is a schematic diagram of the structure formed in step S811 in a specific embodiment;

[0101] Figure 32 is a schematic diagram of the structure formed in step S812 in a specific embodiment;

[0102] Figure 33 is a schematic diagram of the structure formed in step S901 in a specific embodiment.

[0103] Reference numerals: 1-Semiconductor device; 1'-PIN diode; 11, 11'-Substrate; 111-First semiconductor layer; 111a-First top surface; 112-Second semiconductor layer; 113-Third semiconductor layer; 11a-First region; 11b-Second region; 12, 12'-First trench; 121-Third fillet, 122-Fourth fillet; 123-Opening; 124-Second bottom; 125-Second sidewall; 13, 13'-First isolation layer; 131-First fillet; 132-Second fillet; 133-First portion; 133a-Second top surface; 134-Second portion; 135-First surface; 14, 14'-Second isolation layer; 141-First layer; 142-Second layer; 143-Second surface; 144-Third surface; 15-First metal electrode; 16-Second metal electrode; 17-Isolation cavity; 18-Support structure; 19, 19'-Second groove; 191-First bottom; 192-First sidewall; 193-Groove opening; 2-Dielectric layer; 3-Insulating material; 4-Gap; 5-Insulating film; 6-First substrate; 7-Second substrate; 81-First barrier layer; 82-Second barrier layer.

[0104] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Detailed Implementation

[0105] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0106] The present application will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0107] Semiconductor devices can be used in integrated circuits, communication systems, consumer electronics, and other fields. To achieve electrical isolation between adjacent active regions in a semiconductor device, an isolation structure is usually provided on the device. However, the current isolation structure has low sealing performance, and external foreign matter such as moisture can easily enter the isolation structure, affecting its isolation effect and thus impacting the performance of the semiconductor device.

[0108] To address the aforementioned issues, this application provides a semiconductor device, which will be described below using a PIN (positive-intrinsic-negative) diode as an example.

[0109] Figure 1 shows a cross-sectional view of a semiconductor device 1 provided in an embodiment of this application. The semiconductor device 1 includes a substrate 11, which comprises a first semiconductor layer 111, a second semiconductor layer 112, and a third semiconductor layer 113 stacked along a first direction Z. The second semiconductor layer 112 is located between the first semiconductor layer 111 and the third semiconductor layer 113. The second semiconductor layer 112 can be an intrinsic semiconductor layer. The first semiconductor layer 111 and the third semiconductor layer 113 have opposite polarities; that is, one of the first semiconductor layer 111 and the third semiconductor layer 113 is a P-type doped semiconductor layer, and the other is an N-type doped semiconductor layer. The P-type doped semiconductor layer is formed by doping a semiconductor material with a P-type element, which can be a trivalent element such as boron, indium, or gallium. The N-type doped semiconductor layer is formed by incorporating an N-type element into a semiconductor material, which can be a pentavalent element such as phosphorus, arsenic, or antimony.

[0110] In some embodiments, the first semiconductor layer 111 may be a P-type doped semiconductor layer with a high doping concentration (i.e., a P+ doped semiconductor layer), the third semiconductor layer 113 may be an N-type doped semiconductor layer with a high doping concentration (i.e., an N+ doped semiconductor layer), and the second semiconductor layer 112 may be doped with a lower concentration of N-type elements, i.e., the second semiconductor layer 112 may be an N-type doped intrinsic semiconductor layer (i.e., an N- doped intrinsic semiconductor layer), and the doping concentration of the second semiconductor layer 112 is lower than that of the third semiconductor layer 113.

[0111] In other embodiments, the first semiconductor layer 111 may be a highly doped N-type semiconductor layer (i.e., an N+ doped semiconductor layer), and the third semiconductor layer 113 may be a highly doped P-type semiconductor layer (i.e., a P+ doped semiconductor layer). The second semiconductor layer 112 may be doped with a lower concentration of P-type elements, i.e., the second semiconductor layer 112 may be a P-type doped intrinsic semiconductor layer (i.e., a P- doped intrinsic semiconductor layer), and the doping concentration of the second semiconductor layer 112 may be lower than that of the third semiconductor layer 113.

[0112] In the PIN diode structure described above, the second semiconductor layer 112 between the first semiconductor layer 111 and the third semiconductor layer 113 forms an I-region. This allows the PIN diode to have a large junction capacitance and a high reverse breakdown voltage, resulting in good high-frequency performance. The PIN diode has applications including, but not limited to, the following: RF switches (due to their low capacitance and fast switching characteristics, PIN diodes are used in switching circuits in RF communication systems); protection circuits (PIN diodes can be used to protect sensitive electronic components from electrostatic discharge and other transient voltage events); photodetectors (PIN diodes have excellent light response speed, so they are often used at the receiver end of fiber optic communication systems to detect optical signals); modulators (in some cases, PIN diodes can be used as optical modulators to change the intensity of light passing through them to encode information); power control (PIN diodes can also be used in power electronic devices as variable resistors or for phase control); rectifiers (under certain conditions, PIN diodes can also be used as rectifier devices); attenuators (in the microwave and millimeter-wave frequency range, PIN diodes can provide continuous attenuation, suitable for building variable attenuators); and limiters (at the receiver front end, PIN diodes can be used to limit the maximum amplitude of the input signal to prevent overload damage to subsequent stages).

[0113] As shown in Figure 1, a first metal electrode 15, i.e., a pad, is disposed on the side of the first semiconductor layer 111 opposite to the second semiconductor layer 112. The first metal electrode 15 is electrically connected (i.e., ohmic connection) to a portion of the first semiconductor layer 111. A second metal electrode 16 is disposed on the side of the third semiconductor layer 113 opposite to the second semiconductor layer 112. The second metal electrode 16 is electrically connected (i.e., ohmic connection) to the third semiconductor layer 113.

[0114] A first trench 12 is disposed on the substrate 11. The first trench 12 is formed by, but is not limited to, an etching process. The first trench 12 has an opening that communicates with the outside. The first trench 12 extends from the first semiconductor layer 111 to the third semiconductor layer 113 along the first direction Z, and the first trench 12 does not penetrate the third semiconductor layer 113. The first trench 12 is used to electrically isolate adjacent active regions of the semiconductor device 1.

[0115] Wherein, the first direction Z is the thickness direction of the semiconductor device 1, that is, the stacking direction of the first semiconductor layer 111, the second semiconductor layer 112 and the third semiconductor layer 113 of the substrate 11.

[0116] Figure 2 shows a cross-sectional view of a PIN diode 1' in a related art. In this related art, a dielectric layer 2 is disposed on one side of the substrate 11' with a first trench 12'. The dielectric layer 2 can be located on the surface of the first semiconductor layer 111' in the substrate 11' and on the inner wall of the first trench 12'. The dielectric layer 2 can be an insulating material 3 such as silicon oxide or silicon nitride. Since adjacent active regions in the semiconductor device 1 are electrically isolated through the first trench 12', the first trench 12' must not have moisture or other potentially conductive impurities entering it. Therefore, an insulating material 3 is disposed on the side of the dielectric layer 2 facing away from the substrate 11', so that the first trench 12' is filled with the insulating material 3, thereby preventing moisture and other impurities from entering the first trench 12' and affecting the reliability of electrical isolation.

[0117] Specifically, the insulating material 3 can be polyimide adhesive or spin-coated glass. In actual operation, in order to achieve higher withstand voltage performance of the PIN diode 1', the first groove 12' can be set to a larger groove width, for example, greater than 5 micrometers. A larger groove width makes the electrical isolation performance of the first groove 12' better. However, when the groove width is large, the insulating material 3 is difficult to completely fill the entire first groove 12', resulting in a gap 4 between the insulating material 3 and the inner wall of the first groove 12' (i.e., the dielectric layer 2 on the inner wall of the first groove 12').

[0118] Furthermore, the insulating material 3 expands and contracts with temperature changes, as shown in Figure 3, which is a schematic diagram of the volume of the insulating material 3 after shrinkage in Figure 2. When the ambient temperature drops, the volume of the insulating material 3 shrinks, causing the gap 4 between the insulating material 3 and the inner wall of the first tank 12' to further increase. The insulating material 3 itself is also prone to cracking due to temperature changes, and the contact surface between the insulating material 3 and the dielectric layer 2 has poor reliability, making it easy for the insulating material 3 to detach from the dielectric layer 2. This affects the sealing performance of the first tank 12', allowing external moisture, dust, and other foreign matter to easily enter the gap 4 inside the first tank 12', thus causing the isolation function of the first tank 12' to fail and affecting the performance of the PIN diode 1'.

[0119] The embodiments of this application solve the above-mentioned technical problems by forming a sealed isolation cavity between the first isolation layer and the second isolation layer.

[0120] As shown in Figures 4a and 4b, Figure 4a is a cross-sectional view of semiconductor device 1 provided in another embodiment of this application, and Figure 4b is a partially enlarged view of part A in Figure 4a. The following description uses a PIN diode as an example of semiconductor device 1.

[0121] In this embodiment of the application, as shown in FIG4a, the semiconductor device 1 includes a substrate 11. The substrate 11 includes a first semiconductor layer 111, a second semiconductor layer 112, and a third semiconductor layer 113 stacked along a first direction Z. The substrate 11 has a first trench 12 extending from the first semiconductor layer 111 to the third semiconductor layer 113. The semiconductor device 1 also includes a first isolation layer 13. As shown in FIG4b, the first isolation layer 13 includes a second portion 134 located inside the first trench 12 and a first portion 133 located outside the first trench 12, and the first portion 133 is connected to the second portion 134.

[0122] The second portion 134 covers at least a portion of the sidewalls and at least a portion of the bottom of the first tank 12. In some embodiments, the second portion 134 may completely cover the bottom and sidewalls of the first tank 12, thereby isolating the internal cavity of the first tank 12 from the substrate 11 through the second portion 134 of the first isolation layer 13. In some embodiments, the first isolation layer 13 may be a composite film layer, such as comprising a first film layer and a second film layer stacked together, wherein the first film layer in the second portion 134 may completely cover the bottom and sidewalls of the first tank 12, while the second film layer in the second portion 134 may only cover a portion of the bottom of the first tank 12, or only a portion of the sidewalls, or a portion of the bottom and a portion of the sidewalls.

[0123] As shown in Figure 4b, at least a portion of the first portion 133 covers the side of the first semiconductor layer 111 facing away from the second semiconductor layer 112. The first semiconductor layer 111 has a first top surface 111a facing away from the second semiconductor layer 112. In some embodiments, a portion of the first portion 133 covers the first top surface 111a, and another portion of the first portion 133 is located above the first trench 12. That is, a portion of the projection of the first portion 133 along the first direction Z covers the first top surface 111a, and the other portion of the projection of the first portion 133 along the first direction Z is within the first trench 12. In some embodiments, the first top surface 111a of the first semiconductor layer 111 can be completely covered by the first portion 133; in other embodiments, the first top surface 111a of the first semiconductor layer 111 can also be partially covered by the first portion 133.

[0124] In this embodiment, the first part 133 and the second part 134 are connected and form at least one second groove 19. The embodiment shown in Figure 4a illustrates the structure in which the first part 133 and the second part 134 form a second groove 19. The shape and size of the second groove 19 are adapted to the first groove 12, that is, the second part 134 is attached to the inner wall of the first groove 12, and the second groove 19 has a slot 193 on the side opposite to the third semiconductor layer 113 along the first direction Z.

[0125] As shown in Figures 4a and 4b, the semiconductor device 1 further includes a second isolation layer 14, where both the first isolation layer 13 and the second isolation layer 14 are insulating layers. The second isolation layer 14 is located on the side of the first isolation layer 13 facing away from the substrate 11, and is located outside the second trench 19, covering the opening 193 of the second trench 19. At least a portion of the first part 133, the second part 134, and at least a portion of the second isolation layer 14 form a sealed isolation cavity 17. That is, as shown in Figure 4b, the portion of the first part 133 whose projection along the first direction Z is located within the first trench 12 is connected to the second part 134 and the second isolation layer 14, thereby forming a sealed isolation cavity 17.

[0126] The semiconductor device achieves isolation through the isolation cavity 17. That is, the semiconductor device 1 achieves electrical isolation between adjacent active regions through the isolation cavity 17. The sealed isolation cavity 17, formed by the first isolation layer 13 and the second isolation layer 14, can prevent external moisture and impurities from entering. Moreover, compared with related technologies, the isolation cavity 17 is not filled with insulating material, and its sealing performance will not deteriorate due to the thermal expansion and contraction of insulating material. This makes the sealing reliability of the isolation cavity 17 higher, and thus the electrical isolation reliability of the isolation cavity 17 higher.

[0127] In addition, the interior of the second tank 19 is a vacuum or inert gas. Compared with insulating materials, vacuum or inert gas has a lower dielectric constant, which reduces dielectric loss.

[0128] From the perspective of semiconductor device 1 fabrication, the first isolation layer 13 and the second isolation layer 14 in the embodiments of this application are connected by bonding, that is, the first isolation layer 13 and the second isolation layer 14 are directly in contact and form a firm connection under specific conditions. In some embodiments, the first isolation layer 13 and the second isolation layer 14 can be directly bonded together under the action of mechanical force and high temperature. In other embodiments, the first isolation layer and the second isolation layer can also be bonded by other methods, such as hydrogen-assisted bonding, low-temperature bonding, anodic bonding, etc. This application does not limit the specific bonding method of the first isolation layer and the second isolation layer.

[0129] Compared to the method of filling with insulating material in related technologies, the embodiment of this application provides a first isolation layer 13 and a second isolation layer 14 bonded together. This improves the stability of the bond between the first isolation layer 13 and the second isolation layer 14, reduces the possibility of the first isolation layer 13 and the second isolation layer 14 detaching from each other or gaps existing at their contact points, which could affect the sealing performance of the isolation cavity 17. This further reduces the possibility of external moisture, dust, and other foreign matter entering the isolation cavity 17, thereby improving the isolation effect of the isolation cavity 17, ensuring the performance of the semiconductor device 1, and enhancing the reliability of the semiconductor device 1. Simultaneously, the bonding method between the first isolation layer 13 and the second isolation layer 14 can seal large-sized slots. Even if the second isolation layer 14 can reliably seal the slot of the second slot 19, it reduces the possibility of gaps appearing between the second isolation layer 14 and the slot of the second slot 19, which could affect the sealing performance of the isolation cavity 17, thus improving the isolation effect of the isolation cavity 17.

[0130] In addition, in other related technologies, the first isolation layer and the second isolation layer may also be connected by deposition. Please refer to Figure 5, which is a cross-sectional view of the semiconductor device at the isolation cavity in the related technologies. In the related technologies shown in Figure 5, when forming the second isolation layer 14', the second isolation layer 14' can also be deposited on the first isolation layer 13', such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). PVD is a technology that forms a thin film by evaporating a solid material into a gaseous state and then recondensing it on the substrate surface. The CVD process introduces one or more volatile precursor gases containing target elements into a reaction chamber, where a chemical reaction occurs on the substrate surface to generate a solid material and deposit it on the substrate to form a thin film. Based on the characteristics of the deposition process, when the second isolation layer 14' is deposited on the first isolation layer 13', in addition to forming the second isolation layer 14' on the outside of the second tank 19', the second isolation layer 14' will also exist inside the second tank 19', that is, at least a part of the bottom and sidewall of the second tank 19' will be covered by the second isolation layer 14'.

[0131] In this embodiment of the application, as shown in Figures 4a and 4b, when the first isolation layer 13 and the second isolation layer 14 are bonded together, the second isolation layer 14 does not enter the second trench 19, allowing the second isolation layer 14 to have a planar structure, resulting in higher structural strength. Furthermore, the bottom surface of the second isolation layer 14 facing the substrate 11 is flush with the top surface of the first portion 133 facing away from the substrate 11. In other words, the bottom of the second isolation layer 14 does not enter the area of ​​the first sidewall 192 of the second trench 19, and there is no second isolation layer 14 inside the second trench 19. That is, there is no insulating material inside the second trench 19; the interior of the second trench 19 is a vacuum or inert gas. Compared to insulating materials, vacuum or inert gas has a lower dielectric constant, reducing dielectric loss.

[0132] In addition, it can be understood that, as shown in Figure 5, when the second isolation layer 14' is formed by deposition to seal the opening of the second tank 19', only the smaller openings can be sealed, and the larger openings cannot be sealed by deposition.

[0133] In this embodiment of the application, as shown in Figure 4a, the bonding method between the first isolation layer 13 and the second isolation layer 14 can seal large-sized openings. In a specific embodiment, the dimension L1 of the opening of the second tank 19 along the second direction X satisfies: L1≥5μm. For example, L1 can be 5μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, or 100μm, or other values ​​within the above range. When the dimension L1 of the opening of the second tank 19 satisfies L1≥5μm, the width of the isolation cavity 17 is larger, resulting in better isolation. Moreover, when the dimension L1 of the opening 193 of the second tank 19 is ≥5μm, traditional deposition processes may not be able to effectively seal the opening, leading to poor sealing of the isolation cavity and poor electrical isolation performance. The bonding process described in this application can effectively seal the opening of the second groove 19, improving electrical isolation performance while reducing dielectric loss.

[0134] In an optional embodiment, the size L1 of the slot 193 of the second groove 19 along the second direction X satisfies: L1≥10μm. By further increasing the size of the slot 19, a better isolation effect can be achieved. Moreover, the first isolation layer 13 and the second isolation layer 14 are connected by a bonding process, which can effectively seal the slot 193 with L1≥10μm, so that the electrical isolation performance and withstand voltage performance of the isolation cavity 17 are high.

[0135] It should be noted that the second direction X is perpendicular to the first direction Z.

[0136] In summary, the bonding method in the embodiments of this application is substantially different from the deposition method in related technologies.

[0137] Additionally, as shown in Figure 4a, the semiconductor device 1 in this embodiment further includes a first metal electrode 15 and a second metal electrode 16. The first metal electrode 15 is connected to the first semiconductor layer 111, and the second metal electrode 16 is connected to the third semiconductor layer 113. The two metal electrodes provide an interface for the semiconductor device 1 to connect to an external circuit, thereby enabling the application of a bias voltage to control the operating state of the diode. Furthermore, the two metal electrodes also ensure that current can flow smoothly into and out of the diode.

[0138] As shown in Figure 6, which is a partial schematic diagram of the semiconductor device 1 in another embodiment of this application, the cross-section of the isolation cavity 17 along the first direction Z can be rectangular, U-shaped, V-shaped, trapezoidal, inverted trapezoidal, gourd-shaped, or irregular. The minimum dimension L2 of the isolation cavity 17 along the second direction X satisfies: L2 ≥ 5 μm. For example, L2 can be 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, or 100 μm, or other values ​​within the above range. L2 can be regarded as the minimum width of the second groove 19 along the second direction X. If L2 is too small, the isolation cavity 17 will have difficulty playing a reliable isolation role, thereby affecting the reliability of the semiconductor device 1. If L2 is too large, the space occupied by the isolation cavity 17 on the substrate 11 will be too large, which will increase the volume of the semiconductor device 1 and affect the structural stability of the substrate 11, thereby affecting the reliability of the semiconductor device 1. Therefore, by designing the width L2 of the isolation cavity 17 to be between 10μm and 100μm, the isolation effect of the isolation cavity 17 can be guaranteed while making the space occupied by the isolation cavity 17 on the substrate 11 more reasonable, thereby improving the stability of the substrate 11 structure and thus improving the stability of the semiconductor device 1.

[0139] Furthermore, the dimension L1 of the second groove 19 along the second direction X satisfies: L2≥10μm. By further increasing the width of the second groove 19, a better isolation effect can be achieved.

[0140] This application does not specifically limit the cross-sectional shape of the isolation cavity 17. By designing the cross-section of the isolation cavity 17, it is possible to meet the different usage requirements of the semiconductor device 1.

[0141] The isolation cavity 17 can be filled with an inert gas, such as nitrogen, which has a low relative permittivity, enabling the semiconductor device 1 to have better radio frequency performance. Alternatively, the isolation cavity 17 can be filled with a vacuum to reduce radio frequency signal loss and improve the radio frequency performance of the semiconductor device 1.

[0142] Please refer to Figure 7, which is a partial cross-sectional view of the substrate of the semiconductor device 1 provided in an embodiment of this application at the first trench position. In this embodiment, the substrate is provided with a first trench 12. The apex corner where the sidewall of the first trench 12 connects to the first top surface 111a of the first semiconductor layer 111 is rounded, and the bottom corner where the bottom of the first trench 12 connects to the sidewall of the first trench 12 is rounded. That is, the connection between the sidewall of the first trench 12 and the first top surface 111a of the first semiconductor layer 111 is a rounded corner structure, and the connection between the bottom of the first trench 12 and the sidewall of the first trench 12 is a rounded corner structure. Compared with right angles, rounded corners can disperse the electric field, reduce the electric field distribution density inside the first trench 12 at the rounded corner position, thereby avoiding leakage current when the semiconductor device 1 is working (especially when working under high voltage), and thus improving the electrical isolation effect of the isolation cavity 17 formed by the first isolation layer 13 and the second isolation layer 14. In addition, when the first isolation layer 13 covers the first groove 12, the rounded corners of the first groove 12 can also reduce the stress concentration of the first isolation layer 13, improve the reliability of the first isolation layer 13, and thus improve the electrical isolation reliability of the isolation cavity 17 formed by the first isolation layer 13 and the second isolation layer 14.

[0143] Specifically, in the embodiment shown in FIG7, the first tank 12 has an opening 123 along the first direction Z. The sidewall of the opening has a third rounded corner 121. The third rounded corner 121 can reduce the electric field distribution density of the first tank 12 at the opening 123, reduce the risk of leakage current at the location corresponding to the opening 123 of the isolation cavity 17 formed by the first isolation layer 13 and the second isolation layer 14, and improve the structural strength of the first isolation layer 13 and the second isolation layer 14 formed at the opening 123 of the first tank 12.

[0144] In the embodiment shown in Figure 7, the cross-section of the first groove 12 can be rectangular, that is, the first groove 12 has a second bottom 124 and a second sidewall 125. The position where the second bottom 124 and the second sidewall 125 are connected has a fourth rounded corner 122. The fourth rounded corner 122 can reduce the electric field distribution density of the first groove 12 at the bottom, reduce the risk of leakage of the isolation cavity 17 formed by the first isolation layer 13 and the second isolation layer 14 at the bottom, and improve the strength of the first isolation layer 13 formed at the bottom of the first groove 12.

[0145] Please continue to refer to Figures 8a and 8b. Figure 8a is a partial cross-sectional view of a portion of the semiconductor device 1 provided in an embodiment of this application at the location of the second trench 19, and Figure 8b is a partial cross-sectional view of the semiconductor device 1 provided in an embodiment of this application at the isolation cavity 17. When the first isolation layer 13 is formed on the substrate shown in Figure 7, the structure of the first isolation layer 13 can be as shown in Figure 8a. The first semiconductor layer 111 has a first top surface 111a facing away from the second semiconductor layer 112, and the first portion 133 of the first isolation layer 13 has a second top surface 133a on the side facing away from the substrate 11. Because the apex angle connecting the sidewall of the first groove 12 to the first top surface 111a is rounded, and the bottom angle connecting the bottom of the first groove 12 to the sidewall is rounded, the apex angle connecting the sidewall of the second groove 19 to the second top surface 133a is also rounded, and the bottom angle connecting the bottom of the second groove 19 to the sidewall is also rounded. In other words, the connection between the sidewall of the second groove 19 and the second top surface 133a is a rounded corner structure, and the connection between the bottom of the second groove 19 and the sidewall is also a rounded corner structure. The rounded corner structure of the first isolation layer 13 results in less stress concentration and higher structural strength, ultimately improving the isolation reliability of the isolation cavity 17 formed by the first isolation layer 13 and the second isolation layer 14.

[0146] Specifically, in the embodiment shown in FIG8a, the second groove 19 has a groove 193 along the first direction Z. The sidewall of the groove 193 has a first rounded corner 131. The first isolation layer 13 with the first rounded corner 131 has less stress concentration at this position and higher structural strength. Referring to FIG8a and FIG8b, the position of the first rounded corner 131 is close to the bonding position of the first isolation layer 13 and the second isolation layer 14. Compared with a right angle, it can reduce the damage to the second isolation layer 14 during bonding, improve the structural strength of the second isolation layer 14, and thus improve the isolation reliability of the isolation cavity 17 formed by the first isolation layer 13 and the second isolation layer 14.

[0147] In the embodiment shown in Figure 8a, the cross-section of the second groove 19 can be rectangular, that is, the second groove 19 has a first bottom 191 and a first side wall 192. The position where the first bottom 191 and the first side wall 192 are connected has a second rounded corner 132. The first isolation layer 13 with the second rounded corner 132 has less stress concentration at this position and higher structural strength, thereby improving the isolation reliability of the isolation cavity 17 surrounded by the first isolation layer 13 and the second isolation layer 14.

[0148] As shown in FIG9, FIG9 is a partial top view of a semiconductor device 1 provided in an embodiment of the present application. The substrate 11 includes a first region 11a and a second region 11b, a first metal electrode 15 is disposed on the surface of the first region 11a, and a first trench 12 is formed in the second region 11b.

[0149] The projection of the first groove 12 along the first direction Z is annular, and correspondingly, the projection of the second groove 19 along the first direction Z is also annular. Specifically, the cross-sectional shape of the annular first groove 12 along the first direction Z can be triangular, rectangular, U-shaped, gourd-shaped, or irregular, and the cross-sectional shape of the annular second groove 19 along the first direction Z can be triangular, rectangular, U-shaped, gourd-shaped, or irregular. In the embodiment shown in Figure 4a, the cross-sectional shape of the first groove 12 and the second groove 19 along the first direction Z is rectangular, that is, the first groove 12 and the second groove 19 are annular. The following description uses the annular structure of the first groove 12 and the second groove 19 as an example.

[0150] The annular first groove 12 surrounds the first region 11a. The dimension L3 of the first region 11a along the second direction X satisfies: 50μm≤L3≤200μm. For example, L3 can be 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, or 200μm, or other values ​​within the above range. L3 can be understood as the inner diameter of the first groove 12. Please refer to Figure 1. Limiting the dimension of the first region 11a means limiting the dimensions of the first semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer 113 below the first metal electrode 15, so that the semiconductor device 1 has excellent electrical performance and meets the impedance and capacitance requirements of the semiconductor device 1.

[0151] There can be multiple first grooves 12, all surrounding the outer side of the first metal electrode 15. The dimensions of the first grooves 12 can be different, with smaller first grooves 12 located inside larger first grooves 12; that is, the smaller the size of the first groove 12, the closer it is to the first metal electrode 15. By providing multiple first grooves 12, the isolation effect is enhanced.

[0152] As shown in Figure 10, which is a partial top view of the substrate and the first isolation layer in a semiconductor device 1 according to another embodiment of this application. Referring to Figures 4a and 10, the first isolation layer 13 is connected to the outer peripheral surface of the first metal electrode 15, that is, the first isolation layer 13 can be disposed along the circumference of the first metal electrode 15.

[0153] In another embodiment, the first isolation layer 13 surrounds the first metal electrode 15, but the first isolation layer 13 is not connected to the first metal electrode 15.

[0154] As shown in Figure 11, which is a partial top view of a semiconductor device 1 provided in another embodiment of this application, referring to Figures 4a and 11, the second isolation layer 14 is connected to the outer peripheral surface of the first metal electrode 15. That is, the second isolation layer 14 can be disposed along the circumference of the first metal electrode 15. When the semiconductor device 1 is working, a strong electric field is generated around the first metal electrode 15. The connection of both the first isolation layer 13 and the second isolation layer 14 to the first metal electrode 15 can effectively insulate and isolate the outer peripheral surface of the first metal electrode 15, thereby improving the reliability of electrical isolation between adjacent active regions and ensuring the reliability of the semiconductor device 1.

[0155] In another embodiment, the second isolation layer 14 surrounds the first metal electrode 15, and a first portion of the first isolation layer 13 surrounds the first metal electrode, but the second isolation layer 14 and the first portion are not connected to the first metal electrode 15. Please continue to refer to Figures 12 and 13. Figure 12 is a partial schematic diagram of the semiconductor device 1 in one embodiment of this application, and Figure 13 is a partial schematic diagram of the semiconductor device 1 in another embodiment of this application.

[0156] The thickness D1 of the first isolation layer 13 satisfies: 0.1μm≤D1≤5μm. For example, D1 can be 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm or 5μm, or other values ​​within the above range.

[0157] If the thickness D1 of the first isolation layer 13 is too small, it will affect the reliability of the first isolation layer 13. The first isolation layer 13 is easily broken down by the electric field generated on the inner wall of the first tank 12, affecting the withstand voltage capability of the semiconductor device 1 and reducing the isolation effect of the isolation cavity 17 formed by the first isolation layer 13 and the second isolation layer 14. When the thickness D1 of the first isolation layer 13 is too large, the first isolation layer 13 is prone to large stress, which will cause the first isolation layer 13 to crack easily or separate from the inner wall of the first tank 12, thereby reducing the reliability of the first isolation layer 13 and affecting the sealing performance of the isolation cavity 17. At the same time, it also increases the manufacturing cost of the first isolation layer 13, leading to an increase in the production cost of the semiconductor device 1. Therefore, designing the thickness of the first isolation layer 13 to be between 0.1 μm and 2 μm can improve the withstand voltage capability of the semiconductor device 1, reduce the risk of cracking of the first isolation layer 13 due to excessive stress, improve the reliability of the first isolation layer 13, thereby ensuring the sealing performance of the isolation cavity 17, improving the isolation effect of the isolation cavity 17, and reducing the production cost of the semiconductor device 1.

[0158] The thickness D2 of the second isolation layer 14 satisfies: 0.1μm≤D2≤5μm. For example, D2 can be 0.1μm, 0.2μm, 0.4μm, 0.6μm, 0.8μm, 1μm, 1.1μm, 1.3μm, 1.4μm, 1.5μm, 1.7μm, 1.9μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm or 5μm, or of course, values ​​within the above range.

[0159] If the thickness D2 of the second isolation layer 14 is too small, it can easily affect the stability of the connection between the first isolation layer 13 and the second isolation layer 14, making it difficult for the second isolation layer 14 to provide a stable and reliable seal for the opening of the second groove 19, thus affecting the sealing performance of the isolation cavity 17. If the thickness D2 of the second isolation layer 14 is too large, the second isolation layer 14 is prone to large stress, which can easily lead to cracking of the second isolation layer 14, reducing its reliability. At the same time, it can also cause the second isolation layer 14 to collapse into the second groove 19, making it unable to effectively seal the opening of the second groove 19, which also affects the sealing performance of the isolation cavity 17. Therefore, designing the thickness of the second isolation layer 14 to be between 0.1μm and 2μm can improve the stability and reliability of the second isolation layer 14 while ensuring a stable bond between the first isolation layer 13 and the second isolation layer 14, so that the second isolation layer 14 can provide a stable and reliable seal for the opening of the isolation cavity 17, thereby improving the isolation effect of the isolation cavity 17.

[0160] In some embodiments, the first insulating layer 13 comprises one or more of the following: oxides of aluminum, silicon, and titanium; nitrides of aluminum, silicon, and titanium; oxynitrides of aluminum, silicon, and titanium; and oxides of hafnium, lanthanum, and zirconium. For example, the material of the first insulating layer 13 may include one or more of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride. Figures 12 and 13 show a scheme in which the first insulating layer 13 comprises a single-layer structure; for example, the first insulating layer 13 may be a silicon oxide layer.

[0161] The second isolation layer 14 may include one or more of the following: oxides of aluminum, silicon, and titanium; nitrides of aluminum, silicon, and titanium; oxynitrides of aluminum, silicon, and titanium; and oxides of hafnium, lanthanum, and zirconium. For example, the material of the second isolation layer 14 may include one or more of silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride. In the embodiment shown in FIG12, the second isolation layer 14 is a single-layer structure; for example, the second isolation layer 14 may include silicon oxide.

[0162] In the embodiment shown in Figure 12, the thickness D2 of the second isolation layer 14 satisfies 0.1μm≤D2≤5μm, while the width L1 of the groove 193 of the second groove 19 satisfies L1≥5μm. That is, during bonding, the second isolation layer 14 is suspended at the groove 193 position by a large dimension, which leads to a higher risk of the second isolation layer 14 breaking under stress, and a higher risk of it entering the second groove 19 after breaking.

[0163] To reduce the risk of fracture of the second isolation layer 14, the second isolation layer 14 can be configured as a stacked structure of two or more layers, with at least two layers having different stresses. This allows the stress within the second isolation layer 14 to be adjusted through film layers of different materials, resulting in a more balanced stress and thus reducing the risk of fracture at the slot 193. The different stresses in the at least two layers can include different stress directions and / or different stress magnitudes.

[0164] The stress here refers to the internal stress of the thin film, which includes tensile stress and compressive stress. Tensile stress occurs when one side of the cross-section is subjected to a force in the tensile direction from the other side. Compressive stress occurs when one side of the cross-section is subjected to a force in the compressive direction from the other side. Under tensile stress, the thin film tends to shrink; if the tensile stress exceeds the elastic limit of the film, it will rupture. Under compressive stress, the thin film tends to expand towards the surface and bend inwards; when the compressive stress exceeds the elastic limit, it will cause wrinkling. Therefore, compressive stress materials are materials that generate compressive stress internally, and thin films made from compressive stress materials tend to shrink. Tensile stress materials are materials that generate tensile stress internally, and thin films made from tensile stress materials tend to expand or elongate.

[0165] In the embodiment shown in Figure 13, the stacked structure of the second isolation layer 14 includes two layers, namely, the second isolation layer 14 includes a first layer 141 and a second layer 142 made of different materials. The first layer 141 and the second layer 142 are disposed along the first direction Z, and the first layer 141 is located on the side facing the first isolation layer 13, that is, the first layer 141 is used to contact and bond with the first isolation layer 13.

[0166] The first layer 141 and the second layer 142 are configured as membranes with different internal stress directions. For example, one of the first layer 141 and the second layer 142 is a compressive stress material, and the other is a tensile stress material. Therefore, of the two membranes constituting the second isolation layer 14, one layer tends to contract, and the other tends to expand. For example, when the first layer 141 is a compressive stress material and the second layer 142 is a tensile stress material, the first layer 141 tends to contract, and the second layer 142 tends to expand, making the overall internal stress of the second isolation layer 14 tend to be balanced. When the second isolation layer 14 is subjected to external force, the tendency to contract is suppressed by the second layer 142, and the tendency to expand is suppressed by the first layer 141, thereby reducing the risk of permanent deformation or even fracture of the second isolation layer 14 under external force, thus reducing the risk of fracture of the second isolation layer 14 at the groove opening 193 of the second groove 19, and improving the isolation reliability of the isolation cavity 17 formed by the first isolation layer 13 and the second isolation layer 14.

[0167] In one specific embodiment, the material of the first layer 141 can be silicon nitride, and the material of the second layer 142 can be silicon oxide. For example, the material of the first layer 141 includes, but is not limited to, Si3N4, and the material of the second layer 142 includes, but is not limited to, SiO2. Si3N4 is a tensile stress material, and SiO2 is a compressive stress material. That is, the internal stress of the first layer 141 is tensile stress, and the internal stress of the second layer 142 is compressive stress, thereby making the internal stress of the second isolation layer 14 tend to be in equilibrium.

[0168] Furthermore, since the ease with which a material fractures is related to its thickness, the greater the thickness, the less likely it is to fracture. When the tensile stress value of the first layer 141 is lower than the compressive stress value of the second layer 142, the thickness of the first layer 141 can be set to be greater than the thickness of the second layer 142, thereby balancing the internal pressure of the second isolation layer 14, which includes the first layer 141 and the second layer 142. When the tensile stress value of the first layer 141 is higher than the compressive stress value of the second layer 142, the thickness of the first layer 141 can be set to be less than the thickness of the second layer 142, thereby balancing the internal pressure of the second isolation layer 14, which includes the first layer 141 and the second layer 142, making the second isolation layer 14 less prone to permanent deformation or even fracture.

[0169] Therefore, by using materials with different stresses and adjusting the thickness of these materials, the internal stress of the second isolation layer 14 can be brought close to zero, reducing the risk of fracture and improving the reliability of the isolation cavity.

[0170] In one specific embodiment, when the material of the first layer 141 includes Si3N4 and the material of the second layer 142 includes SiO2, the thickness D3 of the first layer 141 satisfies: 50nm ≤ D3 ≤ 400nm, for example, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, or 400nm, or other values ​​within the above range. The thickness D4 of the second layer satisfies: 0.4μm ≤ D4 ≤ 4μm, for example, 0.4μm, 0.5μm, 0.6μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, or 4μm.

[0171] In other embodiments, the material of the second isolation layer 14 includes silicon oxide and silicon nitride. The second isolation layer 14 can be a single-layer structure, for example, it can be silicon oxide, silicon nitride, or silicon oxynitride. The second isolation layer 14 can also be a multilayer stack, for example, it can include a silicon oxide layer and a silicon nitride layer, or it can include a first layer and a second layer, where the first layer is made of at least one of silicon oxide and silicon nitride, and the second layer is made of at least one of silicon oxide and silicon nitride. Therefore, as long as the material of the second isolation layer 14 includes nitrogen, oxygen, and silicon, the atomic ratio of the three elements is not limited, and the number of layers in the second isolation layer 14 is also not limited.

[0172] In some embodiments, the second isolation layer 14 includes a first layer 141 and a second layer 142. The second isolation layer 14 is bonded to the first isolation layer 13 through the first layer 141. The material of the first layer 141 is the same as that of the first isolation layer 13. For example, both the first isolation layer 13 and the first layer 141 are silicon nitride, making the bond between the first isolation layer 13 and the second isolation layer 14 a homogeneous bond. Homogeneous bonding belongs to van der Waals force bonding. Van der Waals force bonding has a very large bonding force, achieving a tight bond between the first isolation layer 13 and the second isolation layer 14. At the same time, it improves the reliability of the contact interface between the first isolation layer 13 and the second isolation layer 14. The first isolation layer 13 and the second isolation layer 14 are almost unlikely to separate or crack, thereby enabling the second isolation layer 14 to reliably seal the opening of the first groove 12 and improve the isolation effect of the first groove 12. In other embodiments, the materials of the first isolation layer 13 and the second isolation layer 14 are different, that is, the first isolation layer 13 and the second isolation layer 14 are heterobonded. The materials of the first isolation layer 13 and the second isolation layer 14 can be selected according to the use needs and process requirements of the semiconductor device 1 to improve the reliability of the semiconductor device 1.

[0173] As shown in Figure 14, Figure 14 is a schematic diagram of a support structure provided in the isolation cavity 17 according to an embodiment of this application. The isolation cavity 17 includes a plurality of mutually isolated cavities 171, and adjacent cavities 171 are separated by a support structure 18. The support structure 18 can be made of a rigid insulating material, such as silicon oxide, silicon nitride, aluminum oxide, or aluminum nitride. One end of the support structure 18 is connected to the first bottom 191 of the second groove 19, and the other end is connected to the second isolation layer 14. The support structure 18 supports the second isolation layer 14, reducing the possibility of the second isolation layer 14 collapsing into the second groove 19. At the same time, it improves the stability of the structure of the second isolation layer 14 above the second groove 19, reducing the possibility of cracking of the second isolation layer 14 above the second groove 19. Thus, the second isolation layer 14 provides a reliable seal to the opening of the second groove 19, thereby improving the isolation effect of the isolation cavity 17.

[0174] As shown in Figure 15, Figure 15 is a schematic diagram of multiple support structures 18 arranged in an isolation cavity 17 according to an embodiment of this application. The support structure 18 is annular to increase the contact area between the support structure 18 and the first isolation layer and the second isolation layer, thereby improving the stability and reliability of the support structure 18.

[0175] In some embodiments, the spacing between adjacent support structures 18 is the same, that is, the support structures 18 can be evenly arranged in the isolation cavity 17 to improve the uniform force on the second isolation layer 14 above the first groove 12, thereby improving the reliability of the support function of the support structure 18.

[0176] In some embodiments, the support structure 18, the first isolation layer 13, and the second isolation layer 14 can be made of the same material, for example, all three are silicon oxide. Choosing the same material increases the reliability of the contact interfaces between the support structure 18 and the first isolation layer 13, and between the support structure 18 and the second isolation layer 14. This reduces the possibility of cracking at the contact interfaces between the support structure 18 and the first and second isolation layers 13 and 14, and also reduces the possibility of the support structure 18 detaching from the first and second isolation layers 13 and 14. This further improves the stability of the support structure 18, ensuring reliable support for the second isolation layer 14, and also enhances the stability of the isolation cavity 17 structure.

[0177] As mentioned above, the embodiments of this application can solve the problem of low sealing performance of the isolation structure of semiconductor devices in related technologies by forming a sealed isolation cavity between the first isolation layer and the second isolation layer, thereby improving the reliability of electrical isolation. The fabrication method of the above-mentioned semiconductor device will be described in detail below.

[0178] In some embodiments, please refer to FIG16, which is a flowchart of the method for fabricating a semiconductor device provided in this application in a specific embodiment. In this embodiment, the method for fabricating a semiconductor device may include the following steps:

[0179] Step S10: Provide a first substrate, and form at least one first groove on the first substrate such that the size of the opening of the first groove along the second direction X is greater than 5 μm.

[0180] Specifically, step S10 may include steps S101, S102 and S103 as described below.

[0181] Please refer to Figures 17-19. Figure 17 is a schematic diagram of the structure formed in step S101 in a specific embodiment, Figure 18 is a schematic diagram of the structure formed in step S102 in a specific embodiment, and Figure 19 is a schematic diagram of the structure formed in step S103 in a specific embodiment.

[0182] S101: As shown in FIG17, a first substrate 6 is provided, the first substrate 6 including a first semiconductor layer 111, a second semiconductor layer 112 and a third semiconductor layer 113 stacked sequentially along the first direction Z.

[0183] The doping types of the first semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer 113 are the same as those in the embodiments described above, and will not be repeated here.

[0184] S102: As shown in FIG18, a first barrier layer 81 is applied to the surface of the first semiconductor layer 111 facing away from the second semiconductor layer 112 and then patterned.

[0185] The first barrier layer 81 can be a photoresist, which acts as a mask covering the surface of the first semiconductor layer 111. The first substrate 6 includes target areas and non-target areas. During the patterning process of the first barrier layer 81, the first barrier layer 81 in the target areas is removed, exposing the first substrate 6 in the target areas, while the first barrier layer 81 in the non-target areas is retained, keeping the first substrate 6 in the non-target areas covered. For example, the first barrier layer 81 in the target areas can be removed using a laser. Therefore, the purpose of patterning the first barrier layer 81 is to define the areas that need to be etched, specifically by covering the areas that do not need to be etched.

[0186] In an alternative embodiment, the first barrier layer 81 may be a silicon oxide mask.

[0187] S103: As shown in FIG19, at least one first trench 12 is formed by etching on the surface of the first barrier layer 81, such that the first trench 12 extends from the first semiconductor layer 111 to the third semiconductor layer 113, and the size L4 of the opening of the first trench 12 along the second direction X is greater than 5μm.

[0188] In an optional embodiment, L4 satisfies the following condition: L4 is greater than 10 μm, and a better isolation effect is achieved by further increasing the width of the first groove 12.

[0189] In some embodiments, the cross-sectional shape of the first groove 12 along the first direction Z can be any one of the following: rectangular, U-shaped, V-shaped, trapezoidal, inverted trapezoidal, etc.

[0190] The etching method can be dry etching. After the first groove 12 is etched, the remaining first barrier layer 81 can be removed to prevent the first barrier layer 81 from affecting subsequent processing.

[0191] In an optional embodiment, step S104 may be included after step S103. Figure 20 is a schematic diagram of the structure formed in step S104 in a specific implementation.

[0192] S104: As shown in Figure 20, the first tank 12 is processed such that the apex corner connecting the sidewall of the first tank 12 to the top surface of the first semiconductor layer 111 is rounded, and the bottom corner connecting the bottom of the first tank 12 to the sidewall is also rounded. After rounding, the rounded corners can disperse the electric field, reducing the electric field density at the rounded corner positions inside the first tank 12, thereby preventing leakage current during semiconductor device operation (especially under high voltage). Furthermore, when the first isolation layer is formed inside the first tank 12, the rounded corners inside the first tank 12 can also reduce stress concentration in the first isolation layer, improving its reliability.

[0193] In the embodiment shown in FIG20, the cross-sectional shape of the first groove 12 along the first direction X is rectangular. After the processing of step S104, a third rounded corner 121 and a fourth rounded corner 122 are formed on the inner wall of the first groove 12.

[0194] In other embodiments, when the first groove 12 has other shapes, the number of rounded corners may also be different from that in FIG20. The number and shape of the rounded corners vary with the shape of the first groove 12. This application does not limit the position and shape of the rounded corners, as long as the sidewall of the first groove 12 can transition with the top surface of the first semiconductor layer 111 and the bottom of the first groove 12 can transition with the sidewall rounded corners.

[0195] Specifically, in step S104, the first tank 12 can be treated by wet etching or high-temperature annealing in a hydrogen atmosphere, so that the top corner where the sidewall of the first tank 12 connects to the top surface of the first semiconductor layer 111 is rounded, and the bottom corner where the bottom of the first tank 12 connects to the sidewall is rounded.

[0196] Along the first direction Z, the first trench 12 is etched laterally (wet etching) to expose part of the surface of the semiconductor substrate. In the embodiment shown in FIG20, when wet etching is used, the etching rate of the opening sidewall position and the bottom and sidewall connection position of the first trench 12 is faster, and the third rounded corner 121 and the fourth rounded corner 122 shown in FIG20 can be formed quickly.

[0197] It should be noted that the first barrier layer 81 can be removed after the formation of the first groove 12, or it can be removed after the corners of the first groove 12 are rounded. For example, when the first barrier layer 81 is photoresist, the photoresist can be removed first, and then the corners of the first groove 12 can be rounded. When the first barrier layer 81 is a silicon oxide mask, the corners of the first groove 12 can be rounded first, and then the silicon oxide mask can be removed. The embodiments of this application do not limit the position of the step of removing the first barrier layer 81 in the entire preparation method.

[0198] Please continue to refer to Figure 16. After step S10, the method for fabricating this semiconductor device further includes the following steps:

[0199] As shown in Figure 21, Figure 21 is a schematic diagram of the structure formed in step S20 in a specific embodiment.

[0200] S20: A first isolation layer 13 is formed on the inner wall surface of the first tank 12 and at least a portion of the surface of the first semiconductor layer 111, the first isolation layer 13 having a first surface 135 facing away from the third semiconductor layer 113.

[0201] In this design, a first portion of the first isolation layer 13 covers at least a portion of the surface of the first semiconductor layer 111, and a second portion of the first isolation layer 13 is located within the first trench, with the first portion and the second portion forming a second trench 19. Furthermore, since the first trench has rounded corners, the portion of the first isolation layer 13 inside the first trench also has rounded corners, meaning that each position of the first isolation layer 13 has a rounded transition.

[0202] In the embodiment shown in Figure 21, the size of the slot 193 of the second groove 19 along the second direction X is L1, satisfying: L1≥10um. In some optional embodiments, 10um≤L1≤100um.

[0203] The structure and effect of the first isolation layer 13 can be found in the embodiments described above, and will not be repeated here.

[0204] In some embodiments, a first isolation layer 13 can be formed on the inner wall surface of the first tank 12 and at least a portion of the surface of the first semiconductor layer 111 using thermal oxidation. By using thermal oxidation to prepare the first isolation layer 13, it can be completely adhered to the inner wall of the first tank 12 and the surface of the first semiconductor layer 111, with minimal separation between the first isolation layer 13 and the inner wall of the first tank 12. This reduces the possibility of separation and avoids gaps between the first isolation layer 13 and the inner wall of the first tank 12. Simultaneously, it improves the uniformity of the first isolation layer 13, reducing the possibility of uneven thickness at different locations.

[0205] In other embodiments, a first isolation layer 13 may be formed on the inner wall surface of the first tank 12 and at least a portion of the surface of the first semiconductor layer 111 using chemical vapor deposition.

[0206] In other embodiments, a first isolation layer 13 may be formed on the inner wall surface of the first tank 12 and at least a portion of the surface of the first semiconductor layer 111 using a combination of various methods including thermal oxidation, chemical vapor deposition, and atomic layer deposition.

[0207] The first isolation layer 13 is made of insulating material, as can be seen in the embodiments described above, and will not be repeated here.

[0208] Please continue to refer to Figure 16. After step S20, the method for fabricating this semiconductor device further includes the following steps:

[0209] As shown in Figure 22, Figure 22 is a schematic diagram of the structure formed in step S30 in a specific embodiment.

[0210] S30: As shown in FIG22, a second substrate 7 is provided, and a second isolation layer 14 is grown on the surface of the second substrate 7. The second isolation layer 14 has a second surface 143, which is located on the side opposite to the second substrate 7 along the first direction Z.

[0211] The second substrate 7 can be a silicon substrate. The second isolation layer 14 can be formed on the second substrate 7 by any one or a combination of thermal oxidation, chemical vapor deposition, or atomic layer deposition. In some embodiments, as shown in FIG22, a monolayer film structure can be formed directly on the surface of the second substrate 7, that is, the second isolation layer 14 is a monolayer structure, for example, the second isolation layer 14 is a silicon nitride layer.

[0212] In addition, the surface of the second substrate 7 is planar, thus making the second isolation layer 14 a planar structure.

[0213] Please continue to refer to Figure 16. After step S30, the method for fabricating this semiconductor device further includes the following steps:

[0214] S40: As shown in Figures 21 and 22, chemical mechanical polishing (CMP) is performed on the first surface 135 and the second surface 143 to make the roughness of the first surface 135 less than 0.5 nm and the roughness of the second surface 143 less than 0.5 nm.

[0215] Chemical mechanical polishing can remove contaminants from the first surface 135 and the second surface 143, reducing the roughness of the first surface 135 and the second surface 143, thus providing a basis for stable and reliable bonding of the first isolation layer 13 and the second isolation layer 14.

[0216] Please continue to refer to Figure 16. After step S40, the method for fabricating this semiconductor device further includes the following steps:

[0217] Step S50: As shown in Figures 21 and 22, the first surface 135 and the second surface 143 are subjected to plasma surface activation treatment.

[0218] Plasma surface activation treatment can improve the bonding strength between the first surface 135 and the second surface 143.

[0219] Please continue to refer to Figure 16. After step S50, the method for fabricating this semiconductor device further includes the following steps:

[0220] As shown in Figure 23, Figure 23 is a schematic diagram of the structure formed in step S60 in a specific embodiment.

[0221] S60: Referring to Figures 21-23, the first isolation layer 13 and the second isolation layer 14 are bonded together using the first surface 135 and the second surface 143 as bonding surfaces.

[0222] As shown in Figure 23, as mentioned above, the first isolation layer 13 can be formed to surround a second groove 19 that is shaped to match the first groove 12. After the first isolation layer 13 and the second isolation layer 14 are bonded together, the second isolation layer 14 covers a first portion of the first isolation layer 13 and covers the opening 193 of the second groove, thereby forming a sealed isolation cavity 17 through a portion of the first isolation layer 13 and a portion of the second isolation layer 14. Both the first isolation layer 13 and the second isolation layer 14 are insulating layers to achieve the isolation function of the isolation cavity 17. The bonding method of the first isolation layer 13 and the second isolation layer 14 can cover a large-sized opening 193. Furthermore, when the first isolation layer 13 and the second isolation layer 14 are connected by bonding, the second isolation layer 14 will not enter the second groove 19, allowing the second isolation layer 14 to have a planar structure. This results in higher structural strength for the second isolation layer 14, reducing the possibility of stress concentration at the corner of the groove opening 193 of the second groove 19, which could lead to cracking of the second isolation layer 14. This, in turn, improves the stability of the second isolation layer 14 and enables it to reliably seal the groove opening 193 of the second groove 19, thereby enhancing the isolation effect of the isolation cavity 17.

[0223] In some embodiments, when the first isolation layer 13 and the second isolation layer 14 are bonded, a nitrogen gas source can be used to perform plasma treatment in a vacuum chamber, and the first surface 135 and the second surface 143 can be bonded at room temperature.

[0224] In addition, after bonding, the bonded structure is annealed at a temperature of 400℃-1000℃ for 0.5 hours to 12 hours to improve the bond strength.

[0225] Please continue to refer to Figure 16. After step S60, the method for fabricating this semiconductor device further includes the following steps:

[0226] As shown in Figure 24, Figure 24 is a schematic diagram of the structure formed in step S70 in a specific embodiment.

[0227] S70: Remove at least a portion of the second substrate to form the structure shown in FIG24.

[0228] Specifically, in the process of removing the second substrate 7, mechanical grinding can be used to thin the second substrate 7. The equipment used in the thinning process employs non-contact thickness monitoring to remove most of the second substrate 7. The remaining second substrate 7 can then be removed by a wet etching process.

[0229] In some embodiments, the second substrate 7 may be completely removed to fully expose the third surface 144 of the second insulating layer 14.

[0230] Please continue to refer to Figure 16. After step S70, the method for fabricating this semiconductor device further includes the following steps:

[0231] S80: Remove a portion of the second isolation layer and a portion of the first isolation layer to expose a portion of the surface of the first semiconductor layer.

[0232] Specifically, step S70 may include steps S801, S802, and S803. Please refer to Figures 25 and 26, where Figure 25 is a schematic diagram of the structure formed in step S801 in one specific embodiment, and Figure 26 is a schematic diagram of the structure formed in step S802 in one specific embodiment.

[0233] As shown in Figure 24, after removing the second substrate 7, the third surface 144 of the second isolation layer 14 is exposed. The third surface 144 is the surface opposite to the second surface 143 along the first direction Z, that is, the third surface 144 is the surface away from the first isolation layer 13.

[0234] S801: As shown in Figures 24 and 25, the second barrier layer 82 is applied to the third surface 144 of the second isolation layer 14 and then patterned.

[0235] The second barrier layer 82 can be photoresist, which acts as a mask covering the third surface 144 of the second isolation layer 14. The third surface 144 includes target and non-target areas. During patterning of the second barrier layer 82, the second barrier layer 82 in the target area is removed, exposing the second isolation layer 14 in that area, while the second barrier layer 82 in the non-target area is retained, keeping the second isolation layer 14 covered. For example, the second barrier layer 82 in the target area can be removed using a laser. Therefore, the purpose of patterning the second barrier layer 82 is to define the areas that need to be etched away, specifically by covering the areas that do not need to be etched away.

[0236] S802, as shown in FIG26, is etched on one side of the second barrier layer 82 to expose a portion of the surface of the first semiconductor layer 111.

[0237] The etching method can be either dry etching or wet etching.

[0238] S803, Remove the second barrier layer 82. This is to prevent the second barrier layer 82 from affecting subsequent processing.

[0239] Please continue to refer to Figure 16. After step S80, the method for fabricating this semiconductor device also includes step S90.

[0240] As shown in Figure 27, Figure 27 is a schematic diagram of the structure formed in step S90 in a specific embodiment.

[0241] S90: A first metal electrode 15 is formed on the exposed surface of the first semiconductor layer 111, and a second metal electrode 16 is formed on the surface of the third semiconductor layer 113 opposite to the second semiconductor layer 112.

[0242] The first metal electrode 15 can be one or a combination of aluminum, copper, gold, titanium, nickel, and silver, and the second metal electrode 16 can be one or a combination of aluminum, copper, gold, titanium, nickel, and silver.

[0243] In some embodiments, the second isolation layer 14 may also be a structure composed of multiple insulating film layers, that is, the above step S30 may specifically include S301 and S302. Please refer to FIG28, which is a schematic diagram of the structure formed in step S302 in a specific embodiment.

[0244] S301: As shown in Figure 28, a second layer 142 is formed on the surface of the second substrate 7.

[0245] S302: As shown in Figure 28, a first layer 141 is formed on the surface of the second layer 142, and one of the first layer 141 and the second layer 142 is a tensile stress material and the other is a compressive stress material. The second surface 143 is the surface of the first layer 141 that is away from the second layer 142.

[0246] The first layer 141 and the second layer 142 are configured as membranes with different internal stress directions. For example, one of the first layer 141 and the second layer 142 is a compressive stress material, and the other is a tensile stress material. Therefore, of the two membranes constituting the second isolation layer 14, one layer tends to contract, and the other tends to expand. For example, when the first layer 141 is a compressive stress material and the second layer 142 is a tensile stress material, the first layer 141 tends to contract, and the second layer 142 tends to expand, making the overall internal stress of the second isolation layer 14 tend to be balanced. When the second isolation layer 14 is subjected to external force, the tendency to contract is suppressed by the second layer 142, and the tendency to expand is suppressed by the first layer 141, thereby reducing the risk of permanent deformation or even fracture of the second isolation layer 14 under external force, thereby reducing the risk of fracture of the second isolation layer 14 at the groove 193 of the second groove 19, and improving the isolation reliability of the isolation cavity 17 surrounded by the first isolation layer 13 and the second isolation layer 14.

[0247] The embodiment shown in Figure 28 differs from that in Figure 22, the second isolation layer 14 is a single-layer structure, while in the embodiment shown in Figure 28, the second isolation layer 14 is a double-layer structure including a first layer 141 and a second layer 142. For example, the first layer 141 can be a silicon nitride layer, specifically Si3N4, and the second layer 142 can be a silicon oxide layer, specifically SiO2. Other aspects of the embodiment shown in Figure 28 are the same as those in the embodiment shown in Figure 22, and will not be repeated here.

[0248] Of course, in other embodiments, the second isolation layer 14 may also be a structure with two or more layers.

[0249] Based on the structure of the second isolation layer 14 as shown in Figure 28, the above step S60 is specifically S601. Referring to Figure 29, Figure 29 is a schematic diagram of the structure formed by S601 in a specific embodiment.

[0250] S601: As shown in FIG29, the first surface of the first isolation layer 13 and the second surface of the first layer 141 are bonded together, so that the first isolation layer 13 and the second isolation layer 14 are bonded together.

[0251] The embodiment shown in Figure 29 differs from the embodiment shown in Figure 23 in that, in the embodiment shown in Figure 23, the second isolation layer 14 is a single-layer structure and the second surface 143 is a single-layer structure surface, while in the embodiment shown in Figure 29, the second isolation layer 14 is a double-layer structure including a first layer 141 and a second layer 142, and the second surface of the second isolation layer 14 is the surface of the first layer 141 that faces away from the second layer 142.

[0252] The other contents of the embodiment shown in Figure 29 are the same as those of the embodiment shown in Figure 23, and will not be repeated here.

[0253] Based on the structure of the second isolation layer 14 as shown in Figure 28, the above step S70 is specifically S701. Referring to Figure 30, Figure 30 is a schematic diagram of the structure formed by S701 in a specific embodiment.

[0254] S701: Remove at least a portion of the second substrate to form the structure shown in FIG30.

[0255] The embodiment shown in Figure 30 differs from the embodiment shown in Figure 24 in that, in the embodiment shown in Figure 24, the second isolation layer 14 is a single-layer structure and the third surface 144 is a single-layer structure surface, while in the embodiment shown in Figure 30, the second isolation layer 14 is a double-layer structure including a first layer 141 and a second layer 142, and the third surface 144 of the second isolation layer 14 is the surface of the first layer 141 that faces away from the second layer 142.

[0256] The other contents of the embodiment shown in Figure 30 are the same as those of the embodiment shown in Figure 24, and will not be repeated here.

[0257] Based on the structure of the second isolation layer 14 as shown in Figure 28, the above step S80 is specifically S810.

[0258] S810: Remove a portion of the second isolation layer and a portion of the first isolation layer to expose a portion of the surface of the first semiconductor layer.

[0259] Specifically, step S710 may include steps S811, S812, and S813. Please refer to Figures 31 and 32, where Figure 31 is a schematic diagram of the structure formed in step S811 in one specific embodiment, and Figure 32 is a schematic diagram of the structure formed in step S812 in one specific embodiment.

[0260] As shown in Figure 30, after removing the second substrate 7, the third surface 144 of the second isolation layer 14 is exposed. The third surface 144 is the surface that faces away from the first isolation layer 13.

[0261] S811: As shown in Figures 30 and 31, the second barrier layer 82 is applied to the third surface 144 of the second isolation layer 14 and then patterned.

[0262] S812: As shown in Figure 32, etching is performed on one side of the second barrier layer 82 to expose a portion of the surface of the first semiconductor layer 111.

[0263] S813: Remove the second blocking layer 82.

[0264] The embodiments shown in Figures 31 and 32 differ from those shown in Figures 25 and 26 in that, in the embodiments shown in Figures 25 and 26, the second isolation layer 14 is a single-layer structure, while in the embodiments shown in Figures 31 and 32, the second isolation layer 14 is a double-layer structure including a first layer 141 and a second layer 142.

[0265] The other contents of the embodiment shown in Figure 31 are the same as those of the embodiment shown in Figure 25, and the other contents of the embodiment shown in Figure 32 are the same as those of the embodiment shown in Figure 26, which will not be repeated here.

[0266] Based on the structure of the second isolation layer 14 as shown in Figure 28, the above step S90 is specifically S901. Referring to Figure 33, Figure 33 is a schematic diagram of the structure formed by S901 in a specific embodiment.

[0267] S901: A first metal electrode 15 is formed on the exposed surface of the first semiconductor layer 111, and a second metal electrode 16 is formed on the surface of the third semiconductor layer 113 that is opposite to the second semiconductor layer 112.

[0268] The embodiment shown in Figure 27 differs from the embodiment shown in Figure 33 in that the second isolation layer 14 in the embodiment shown in Figure 27 is a single-layer structure, while in the embodiment shown in Figure 33, the second isolation layer 14 is a double-layer structure including a first layer 141 and a second layer 142.

[0269] The other contents of the embodiment shown in Figure 27 are the same as those of the embodiment shown in Figure 33, and will not be repeated here.

[0270] In another embodiment, the method for fabricating the semiconductor device provided in this application may include the following steps:

[0271] S201 provides a first substrate on which a three-layer semiconductor structure can be stacked sequentially, with the front side being a polished surface.

[0272] The first and second semiconductor layers can be either P-type heavily doped semiconductor layers (P++ layer) or N-type heavily doped semiconductor layers (N++ layer), and the second semiconductor layer is an intrinsically undoped semiconductor layer (I layer).

[0273] S202, photoresist is applied to the front side of the first substrate and patterned. Using the photoresist as an etch stop layer, dry etching is performed on the front side of the first substrate to form at least one isolation trench. The isolation trench extends from the first semiconductor layer to the third semiconductor layer. The width of the isolation trench is greater than 10 μm. In a preferred embodiment, the width of the isolation trench is 10-100 μm. The width of the opening of the isolation trench is at least greater than 10 μm, and the width of the narrowest part of the isolation trench is not less than 10 μm. The isolation trench can be U-shaped, V-shaped, trapezoidal, or inverted trapezoidal.

[0274] Optionally, it also includes S203, which removes the etched damage layer and smooths the corners of the trench. The method can be wet etching or high-temperature annealing in a hydrogen atmosphere (not limited to this method).

[0275] The wet etching method is as follows: the isolation trench is etched laterally (wet etching) along the surface of the semiconductor substrate to expose part of the surface of the semiconductor substrate; the etching rate is faster at the top and bottom corners of the trench, and the top and bottom corners are arc-shaped.

[0276] S204, using a thermal oxidation process or CVD deposition, forms a first isolation layer on the inner wall surface of the groove and the partially exposed semiconductor substrate surface.

[0277] S205 provides a second substrate, which can be a monocrystalline silicon substrate with a polished front side. A second isolation layer is grown on the surface of the monocrystalline silicon substrate using a thermal oxidation process, CVD, or ALD deposition. The second isolation layer is an insulating dielectric material, such as silicon oxide, silicon nitride, aluminum oxide, or aluminum nitride, preferably a composite layer of silicon oxide and silicon nitride.

[0278] S206, using the second isolation layer surface of the second substrate and the first isolation layer surface of the first substrate as bonding surfaces, the second substrate and the first substrate are bonded together in a vacuum environment at room temperature to form a bonded substrate;

[0279] Optionally, the surfaces of the first and second isolation layers can be plasma-activated before bonding, and then the two surfaces can be bonded together at room temperature to form a bonding substrate. Preferably, N2 is used as the gas source for plasma treatment in a vacuum chamber.

[0280] S207, the bonding substrate is placed in the furnace tube for annealing to improve the bonding strength. The annealing temperature is preferably 400℃-1000℃ and the time is preferably 0.5 hours to 12 hours.

[0281] S208, thinning of the second substrate. For example, a combination of mechanical grinding and wet etching methods can be used for thinning. The thinning process uses non-contact thickness monitoring equipment to remove most of the substrate monocrystalline silicon, and the remaining substrate monocrystalline silicon is removed by wet etching.

[0282] S209, apply photoresist to the front side of the second isolation layer and pattern it. Use the photoresist as an etching barrier layer and perform dry or wet etching on the front side of the second isolation layer to expose the surface of the first substrate.

[0283] S210, a first metal electrode is made on the surface of the exposed substrate, which can be a combination of aluminum, copper, gold, titanium, nickel and silver.

[0284] S211, a second metal electrode is formed on the back side of the first substrate, which may be a combination of aluminum, copper, gold, titanium, nickel and silver.

[0285] This application provides a solid-state phase shifter and a communication device. The solid-state phase shifter has the aforementioned semiconductor device, and the communication device includes the solid-state phase shifter.

[0286] Since semiconductor devices can achieve the above-mentioned technical effects, solid-state phase shifters and communication devices with such semiconductor devices can also achieve the corresponding technical effects, which will not be elaborated here.

[0287] The above are merely specific embodiments of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A substrate, the substrate comprising a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked along a first direction, wherein the second semiconductor layer is located between the first semiconductor layer and the third semiconductor layer; The substrate is provided with at least one first trench, and the first trench extends from the first semiconductor layer to the third semiconductor layer; A first isolation layer, comprising a first portion located outside the first tank and a second portion located inside the first tank, at least a portion of the first portion being located on the side of the first semiconductor layer opposite to the second semiconductor layer, the second portion covering at least a portion of the sidewall of the first tank and at least a portion of the bottom of the first tank, the first portion being connected to the second portion and forming at least one second tank, the second tank having a slot on the side of the first semiconductor layer opposite to the third semiconductor layer along a first direction; A second isolation layer is located outside the second groove and covers the groove opening. At least a portion of the first part, the second part, and at least a portion of the second isolation layer form a sealed isolation cavity. Wherein, at least one of the groove openings of the second groove body has a dimension L1 along the second direction that satisfies: L1≥5μm.

2. The semiconductor device according to claim 1, characterized in that, At least one of the slots has a dimension L1 along the second direction that satisfies: L1 ≥ 10 μm.

3. The semiconductor device according to claim 1, characterized in that, The first isolation layer is bonded to the second isolation layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first semiconductor layer has a first top surface facing away from the second semiconductor layer, the apex of the first trench connecting the sidewall to the first top surface is rounded, and the bottom of the first trench connecting the sidewall to the bottom is rounded.

5. The semiconductor device according to claim 4, characterized in that, The first portion has a second top surface facing away from the substrate, the apex of the second tank where the sidewall connects to the second top surface is rounded, and the bottom of the second tank where the sidewall connects to the bottom is rounded.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The second isolation layer has a planar structure, and the bottom surface of the second isolation layer facing the substrate is flush with the top surface of the first part facing away from the substrate.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, At least one of the second groove bodies has a minimum dimension L2 along the second direction that satisfies: L2≥5μm.

8. The semiconductor device according to claim 7, characterized in that, At least one of the second groove bodies has a minimum dimension L2 along the second direction that satisfies: L2≥10μm.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The cross-section of the second groove along the first direction is any one of the following: rectangular, U-shaped, gourd-shaped, V-shaped, trapezoidal, inverted trapezoidal, or irregular shape.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, The thickness D1 of the first isolation layer satisfies 0.1μm≤D1≤5μm, and / or; The thickness D2 of the second isolation layer satisfies 0.1μm≤D2≤5μm.

11. The semiconductor device according to claim 10, characterized in that, 0.1μm≤D1≤2μm, and / or, 0.1μm≤D2≤2μm.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that, The first isolation layer comprises one or more of the following: oxides of aluminum, silicon, and titanium; nitrides of aluminum, silicon, and titanium; oxynitrides of aluminum, silicon, and titanium; oxides of hafnium, lanthanum, and zirconium; and / or. The second insulating layer comprises one or more of the following: oxides of aluminum, silicon, and titanium; nitrides of aluminum, silicon, and titanium; oxynitrides of aluminum, silicon, and titanium; and oxides of hafnium, lanthanum, and zirconium.

13. The semiconductor device according to claim 12, characterized in that, The second isolation layer is a stacked structure, and at least two layers in the stacked structure have different stresses.

14. The semiconductor device according to claim 13, characterized in that, The second isolation layer includes at least a first layer and a second layer, wherein one of the first layer and the second layer is a tensile stress material and the other is a compressive stress material.

15. The semiconductor device according to claim 14, characterized in that, The first layer is Si3N4, the second layer is SiO2, and the thickness D3 of the first layer satisfies: 50nm≤D3≤400nm, and the thickness D4 of the second layer satisfies: 0.4μm≤D4≤4μm.

16. The semiconductor device according to claim 12, characterized in that, The second isolation layer includes a first layer and a second layer stacked along a first direction, wherein the first layer is connected to the first isolation layer and the first layer is made of the same material as the first isolation layer.

17. The semiconductor device according to claim 12, characterized in that, The second isolation layer comprises silicon oxide and silicon nitride.

18. The semiconductor device according to any one of claims 1 to 17, characterized in that, The second groove includes a plurality of mutually isolated cavities, and adjacent cavities are separated by a support structure. The second groove has a first bottom, one end of the support structure is connected to the first bottom, and the other end is connected to the second isolation layer.

19. The semiconductor device according to any one of claims 1 to 18, characterized in that, The substrate includes a first region and a second region, the first region is provided with a first metal electrode, and the first tank is disposed in the second region with the first metal electrode.

20. The semiconductor device according to claim 19, characterized in that, The projections of the first and second grooves along the first direction are both annular. The first groove surrounds the first region, and the dimension L3 of the first region along the second direction satisfies: 50μm≤L3≤200μm.

21. A solid-state phase shifter, characterized in that, The solid-state phase shifter comprises the semiconductor device according to any one of claims 1 to 20.

22. A communication device, characterized in that, The communication device includes the solid-state phase shifter as described in claim 21.

23. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes: A first substrate is provided, the first substrate comprising a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially, and at least one first trench is formed on the first substrate, such that the first trench extends from the first semiconductor layer to the third semiconductor layer, and the width L4 of the opening of the first trench is greater than 5 μm. A first isolation layer is formed on the inner wall surface of the first tank and at least a portion of the surface of the first semiconductor layer. The first isolation layer includes a first portion located outside the first tank and a second portion located inside the first tank. At least a portion of the first portion is located on the side of the first semiconductor layer opposite to the second semiconductor layer. The second portion covers at least a portion of the sidewall of the first tank and at least a portion of the bottom of the first tank. The first portion and the second portion are connected and form at least one second tank. The portion of the first isolation layer outside the first tank has a first surface opposite to the third semiconductor layer. A second substrate is provided, and a second isolation layer is formed on the surface of the second substrate, the second isolation layer having a second surface facing away from the second substrate; Using the first surface and the second surface as bonding surfaces, the first isolation layer and the second isolation layer are bonded together, the second isolation layer covers the opening of the second groove, and at least a portion of the first part, the second part and at least a portion of the second isolation layer form a sealed isolation cavity; Remove at least a portion of the second substrate; Remove a portion of the second isolation layer and a portion of the first portion to expose a portion of the surface of the first semiconductor layer; A first metal electrode is formed on the exposed surface of the first semiconductor layer, and a second metal electrode is formed on the surface of the third semiconductor layer opposite to the second semiconductor layer.

24. The method for fabricating a semiconductor device according to claim 23, characterized in that, The first semiconductor layer has a first top surface facing away from the second semiconductor layer. When at least one first trench is formed on the first substrate, the method for fabricating the semiconductor device specifically includes: A first barrier layer is coated on the first top surface of the first semiconductor layer and then patterned. The surface of the first barrier layer is etched to form the first groove. Remove the first barrier layer; The first tank is processed such that the apex corner connecting the sidewall of the first tank to the first top surface is rounded, and the bottom corner connecting the bottom of the first tank to the sidewall is rounded.

25. The method for fabricating a semiconductor device according to claim 24, characterized in that, The first tank is subjected to wet etching or high-temperature annealing in a hydrogen atmosphere to make the apex corner where the sidewall of the first tank connects to the first top surface rounded, and the bottom corner where the bottom of the first tank connects to the sidewall rounded.

26. The method for fabricating a semiconductor device according to any one of claims 23 to 25, characterized in that, Before bonding the first isolation layer and the second isolation layer, the fabrication method further includes: The first surface and the second surface are subjected to chemical mechanical polishing to make the roughness of the first surface less than 0.5 nm, and / or the roughness of the second surface less than 0.5 nm.

27. The method for fabricating a semiconductor device according to claim 26, characterized in that, After chemically and mechanically polishing the first surface and the second surface, and before bonding the first isolation layer and the second isolation layer, the preparation method further includes: The first surface and the second surface are subjected to plasma surface activation treatment.

28. The method for fabricating a semiconductor device according to any one of claims 23 to 27, characterized in that, The method for fabricating the semiconductor device includes providing a second substrate and forming a second isolation layer on the surface of the second substrate: A second layer is formed on the surface of the second substrate; A first layer is formed on the surface of the second layer, wherein one of the first layer and the second layer is a tensile stress material and the other is a compressive stress material, and the second surface is the surface of the first layer that is opposite to the second layer.

29. The method for fabricating a semiconductor device according to any one of claims 23 to 28, characterized in that, The method for fabricating the semiconductor device by removing a portion of the second isolation layer and a portion of the first isolation layer to expose a portion of the surface of the first semiconductor layer includes: A second barrier layer is applied to the third surface of the second isolation layer and patterned thereon. The third surface is the surface of the second isolation layer that is disposed opposite to the second surface along the first direction. Etch one side of the second barrier layer to expose a portion of the surface of the first semiconductor layer; Remove the second barrier layer.

30. The method for fabricating a semiconductor device according to any one of claims 23 to 29, characterized in that, The first isolation layer is formed by a combination of one or more of the following methods: thermal oxidation, chemical vapor deposition, and atomic layer deposition; and / or, The second isolation layer is formed by a combination of one or more of the following methods: thermal oxidation, chemical vapor deposition, and atomic layer deposition.

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