Control apparatus, multi-operator control method, hardware scheduler, accelerator, and system

Abstract

A control apparatus, a multi-operator control method, a hardware scheduler, an accelerator, and a computing system. An instruction decoding circuit decodes a plurality of first cache allocation instructions, and then an instruction execution circuit executes the decoded instructions to respectively allocate caches to a plurality of operators from a shared cache pool, such that data can be transmitted between the operators by means of the caches, thereby achieving soft connections and fast data interaction between the operators.

Description

Control device, multi-operator control method, hardware scheduler, accelerator and system

[0001] This application claims priority to Chinese patent application No. 202411999995.7, filed on December 31, 2024, entitled "Control Device, Multi-Operator Control Method, Hardware Scheduler, Accelerator and System", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of data processing, and more specifically, to a control device, a multi-operator control method, a hardware scheduler, an accelerator, and a computing system. Background Technology

[0003] To pursue application flexibility, the industry commonly uses general-purpose processors such as DSPs for data processing in radar signal processing. With the development of radar technology, radar signal processing algorithms have become increasingly complex, and radar signal processor operators have become increasingly diverse. Multi-channel, high-precision radar applications have created a demand for high-performance, low-power processing of echo signals. Mainstream DSP solutions have accelerated the shift towards radar hardware accelerators; however, these accelerators operate sequentially, resulting in a simple processing flow, lack of flexibility, and difficulty in leveraging the performance advantages of each operator. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, embodiments of this disclosure provide a control device for controlling a plurality of specified operators, the plurality of operators being configured to process data to be processed according to a set connection order, the control device comprising:

[0006] An instruction decoding circuit is configured to decode software code, the software code including a plurality of first cache allocation instructions, each first cache allocation instruction including: a first operand, used to indicate the location and size of the cache allocated for the operator; and a second operand, used to indicate the storage space to be written to the first operand;

[0007] The instruction execution circuit, coupled to the instruction decoding circuit, is configured to, in response to a plurality of decoded first cache allocation instructions, write a first operand in each first cache allocation instruction into the storage space indicated by a second operand in the cache allocation instruction, so as to allocate caches for the plurality of operators to use when accessing data.

[0008] The caches allocated to the multiple operators are all from a shared cache pool.

[0009] On the other hand, this disclosure also provides a multi-operator control method applied to a hardware accelerator, the hardware accelerator including a hardware scheduler, a specified number of operators, and a shared cache pool, the control method including:

[0010] The shared cache pool is used to allocate caches for data access to the plurality of operators to form data channels between the plurality of operators, wherein the allocated caches include input caches and / or output caches;

[0011] By scheduling time steps, the multiple operators are started sequentially according to the set connection order to complete the processing of the data to be processed;

[0012] Among the plurality of operators, the output buffer used by the preceding operator at the current time step is the input buffer used by the following operator at the next time step.

[0013] In another aspect, embodiments of this disclosure also provide a hardware scheduler, including a control device and an internal memory, wherein the control device is the control device described in any embodiment of this disclosure, and the internal memory is configured to store software code to be decoded and executed by the control device.

[0014] In another aspect, embodiments of this disclosure also provide a hardware scheduler, including a control device and an internal memory, wherein the memory stores a computer program, and the control device executes the computer program to implement the multi-operator control method described in any embodiment of this disclosure.

[0015] Furthermore, embodiments of this disclosure also provide a hardware accelerator, including a hardware scheduler, a plurality of designated operators, a shared cache pool providing cache space for the operators, and a register set, wherein:

[0016] The hardware scheduler adopts the hardware scheduler described in any embodiment of this disclosure, wherein the cache information allocated to each operator is saved in the register group, and the processed data is stored in external memory;

[0017] The register group is configured to store configuration information for the plurality of operators, the configuration information including information on the cache allocated to the operators;

[0018] The plurality of operators are configured to, upon startup, obtain information about the cache allocated to the operator from the register group; if an input cache is allocated, read the data block to be processed from the input cache and process it; and if an output cache is allocated, write the processed data into the output cache.

[0019] In another aspect, embodiments of this disclosure also provide a computing system, including a processor, memory, and a hardware accelerator, wherein: the processor is configured to load data to be processed stored in the memory into the hardware accelerator; the memory is configured to store the data to be processed and to store data obtained by the hardware accelerator after processing the data to be processed; the hardware accelerator is the hardware accelerator described in any embodiment of this disclosure.

[0020] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the embodiments described in the description, claims, and drawings.

[0021] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0022] Overview of the attached figures

[0023] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0024] Figure 1 is a schematic diagram of an exemplary radar system according to an embodiment;

[0025] Figure 2 is a structural diagram of an exemplary radar system according to an embodiment;

[0026] Figure 3 is a schematic diagram of electromagnetic waves emitted by a radar system according to an embodiment;

[0027] Figure 4 is a schematic diagram of the digital signal processing flow in a radar system according to an embodiment;

[0028] Figure 5 is a schematic diagram of a hardware accelerator in a radar system according to an embodiment. It supports multiple hard-connected operators.

[0029] Figures 6A and 6B are schematic diagrams of the radar system hardware accelerator in two other embodiments, supporting a single operator;

[0030] Figure 7 is a schematic diagram of the structure of a computing system according to an embodiment of the present disclosure, including a hardware accelerator;

[0031] Figures 8A, 8B, 8C, and 8D are schematic diagrams of multiple operators and a shared cache pool specified in four hardware accelerators according to embodiments of this disclosure;

[0032] Figure 9A is a schematic diagram of the cache used by multiple operators in Figure 8B;

[0033] Figure 9B is a schematic diagram of data flow loopback according to an embodiment of this disclosure;

[0034] Figure 10 is a flowchart of a multi-operator control method according to an embodiment of the present disclosure;

[0035] Figures 11A and 11B are schematic diagrams of two startup and synchronization control methods for a hardware accelerator including three operators in a multiple loop process according to an embodiment of the present disclosure.

[0036] Figure 12 is a schematic diagram of a hardware accelerator according to an embodiment of the present disclosure;

[0037] Figure 13 is a schematic diagram of an integrated circuit according to an embodiment of the present disclosure;

[0038] Figure 14 is a schematic diagram of a device using the integrated circuit in Figure 13 according to an embodiment of the present disclosure;

[0039] Figure 15 is a schematic diagram of the data flow between multiple operators and the time-step switching buffer according to an embodiment of the present disclosure;

[0040] Figure 16 is a schematic diagram of a control device according to an embodiment of the present disclosure;

[0041] Figure 17 is a schematic diagram of a hardware scheduler according to an embodiment of the present disclosure;

[0042] Figure 18 is a schematic diagram of the structure of an operator according to an embodiment of the present disclosure;

[0043] Figure 19 is a flowchart of a multi-operator control method according to another embodiment of the present disclosure;

[0044] Figure 20 is a flowchart of a code generation method according to an embodiment of the present disclosure.

[0045] Detailed Explanation

[0046] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in detail, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0047] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0048] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0049] Figure 1 illustrates a radar system 100 applicable to embodiments of this disclosure. Taking a frequency-modulated continuous wave (FMCW) millimeter-wave radar as an example, the radar system 100 includes a radio frequency (RF) chip 110, a transmitting antenna 120, a receiving antenna 130, and a main processing chip 140. The RF chip 110 is configured to generate a detection signal and transmit it through the transmitting antenna array 120. The detection signal can be an FMCW electromagnetic wave signal. The transmitting antennas 120 are connected to the RF chip 110, and multiple antennas can form a transmitting antenna array, configured to transmit the detection signal. The receiving antennas 130 have multiple antennas and are configured to receive the echo signal formed by the reflection of the detection signal from the target (i.e., the detected object, the target object, hereinafter referred to as the target). The main processing chip 140 is connected to the receiving antenna array 130 and the RF chip 110, configured to process the echo signal obtained by the receiving antenna array 130 to obtain information such as the target's distance, velocity, and angle. In one example, the transmitting antenna 121 and the receiving antenna 131 can be integrated with the RF chip 110 to form an RF transceiver chip, which, together with the main processing chip 140, constitutes a radar signal transceiver processing system. In another example, the RF chip 110 and the main processing chip 140 can be integrated into a single SoC chip, enabling the transmission, reception, and processing of RF signals through a single chip. The transmitting and receiving antennas can also be integrated with this SoC chip to form an AiP chip or AoC chip structure, etc.

[0050] The radio frequency chip 110, which is integrated as one unit or set separately, and the main processing chip 140 constitute the integrated circuit in the radar system. The integrated circuit, the transmitting antenna, and the receiving antenna can be set in the carrier, together with the carrier, to form an electromagnetic wave sensor. The electromagnetic wave sensor can be installed in equipment such as a car cabin.

[0051] Figure 2 shows a radar system that can be used in this embodiment. It includes a transmitting antenna 11, a power amplifier 21, a signal generator 23, a receiving antenna 13, a low-noise amplifier 31, a mixer 33, an analog-to-digital converter (ADC module) 41, and a digital signal processor 51. The signal generator 23 can be a millimeter-wave generator implemented with an oscillator. The detection signal generated by the signal generator 23 is amplified by the power amplifier 21 and then transmitted through one or more transmitting antennas 11. The radar system typically transmits a series of chirps in frames. The detection signal transmitted by the FMCW-based radar system can use the sawtooth waveform shown in Figure 3. Each frame includes multiple chirps, and each chirp includes an up-modulation band, a down-modulation band, and a frequency hold band. The period of the chirp signal is Tc. The signal transmission channel of the radar system is composed of devices such as the signal generator 23 and the power amplifier 21.

[0052] The detection signal is reflected and / or refracted by the target to form an echo signal. The receiving antenna 13 amplifies the received echo signal through a low-noise amplifier 31, and then mixes it with the corresponding local oscillator signal in a mixer 33 to obtain an intermediate frequency (IF) signal. There are usually multiple receiving antennas 13. The signal channel of the radar system is composed of components such as the low-noise amplifier 31 and the mixer 33. The IF signal is sampled by an analog-to-digital converter (ADC) 41, and the resulting digital signal is further processed by a digital signal processor 51.

[0053] Figure 4 illustrates an example of digital signal processing. The intermediate frequency (IF) signal is sampled by an analog-to-digital converter (ADC), resulting in a multi-channel digital signal that undergoes 1D-FFT processing. The 1D-FFT processing in this application does not simply refer to performing a distance-dimensional FFT, but can include techniques such as DC removal, windowing, FFT, and Spatial Variant (SVA). The 1D-FFT data obtained after the 1D-FFT processing stage is cached and accumulated to a predetermined number of frames, such as 128 frames, before being processed in the 2D-FFT processing stage. The 2D-FFT processing stage of this application does not only perform Doppler FFT, but may include other data processing methods such as windowing, clutter suppression, and FFT. After the 2D-FFT processing stage, the range and velocity two-dimensional spectrum (RD spectrum) of the digital signal is obtained. Target detection is then performed based on the RD spectrum. The spectral peaks of the target in the range and velocity dimensions can be determined first by constant false alarm rate (CFAR) detection, and then range measurement, velocity measurement, and direction of arrival (DOA) estimation can be performed.

[0054] The aforementioned calculations on the radar echo data to obtain information such as the target's position and angle can be implemented using a radar signal processing chip equipped with a hardware accelerator (as shown in the main processing chip in Figure 1). Such radar signal processing chips generally come in two types:

[0055] One hardware acceleration scheme is a customized acceleration for a specific application, as shown in Figure 5. The hardware accelerator includes multiple operators: DC removal (DC), mainly used for removing the DC component of the signal; windowing (Win), which uses window functions to window the signal, reducing spectral leakage caused by signal truncation; FFT, used to perform a fast Fourier transform on the intermediate frequency signal data after analog-to-digital conversion, converting the time-domain signal into a frequency-domain representation; and SVA, used to apply different weighting methods to pixels at different spatial locations, effectively suppressing sidelobes. These operators are connected serially, processing the data to be processed from the Radar Cube in sequence, and the processing results are then stored in the Radar Cube. The operators can be controlled through configuration registers. This scheme has strong processing capabilities and maximizes the chip's area utilization efficiency for specific applications. However, the operators are hard-connected, and the connection relationships and data interactions between operators cannot be controlled through software. This greatly limits the chip's application. If complex application designs are to be supported, they need to be determined in the early stages of chip design. After the chip design is completed, it can only support relatively fixed data processing flows and is difficult to support new application requirements.

[0056] Another hardware acceleration scheme, adapted to different applications, uses software instructions for data interaction between hardware accelerators, as shown in Figures 6A and 6B. Data to be processed by the hardware accelerator is moved from the Radar Cube via a Direct Memory Access (DMA) controller (DMAI in the figure), and the processing result is then stored back into the Radar Cube via another DMA controller (DMAO in the figure). The internal cache capacity of the hardware accelerator is relatively small, and the data moved in by DMAI supports a single operator. This scheme allows for the combination of hardware accelerators to complete the required functions for different applications, offering good flexibility. However, the frequent data movement leads to higher chip power consumption, reduced computation speed, and lower utilization efficiency of the hardware accelerators.

[0057] Although the above example uses a radar system, other applications that require hardware acceleration also need to effectively address the conflict between the application flexibility of hardware accelerators and high performance and low power consumption.

[0058] To this end, one embodiment of this disclosure provides a hardware accelerator, including a hardware scheduler, a plurality of designated operators, a shared cache pool providing cache space for the operators, and a register set, as shown in FIG7, wherein:

[0059] The hardware scheduler is configured to allocate caches from the shared cache pool to the plurality of operators based on a set connection order to form a data interaction channel between the plurality of operators, save the information of the allocated caches to the register group; and control the plurality of operators to start sequentially according to the set connection order, complete the processing of the loaded data to be processed in a pipeline manner, and store the processed data in external memory.

[0060] The register group is configured to store configuration information for the plurality of operators, the configuration information including information on the cache allocated to the operators;

[0061] The plurality of operators are configured to, upon startup, obtain information about the cache allocated to the operator from the register group; if an input cache is allocated, read the data block to be processed from the input cache and process it; and if an output cache is allocated, write the processed data into the output cache.

[0062] The embodiments disclosed herein and other embodiments control the multiple operators to start sequentially according to a set connection order, which may be achieved by triggering the multiple operators to start sequentially according to a set connection order through a pulse signal or other means.

[0063] Based on the hardware accelerator of this disclosure, users can flexibly select multiple operators (i.e., specified multiple operators) from the hardware accelerator to implement the computing task according to different usage scenarios. Users can not only set parameters for the specified multiple operators, but also configure the connection relationships between the multiple operators and the data flow direction during operation, to adapt to the requirements of different application scenarios for the required operators and processing flow. Furthermore, multiple operators can be controlled to process in parallel in a pipelined manner, maximizing the processing power per unit chip area. This enables systems equipped with this hardware accelerator, such as radar signal processors, to achieve optimal performance in different scenarios.

[0064] The shared cache pool (also written as memory pool) in this embodiment can use storage media such as SRAM, DRAM (eDRAM), and phase-change memory (PCM). To meet the needs of concurrent processing by multiple operators, the shared cache pool can use multi-bank physical memory, that is, memory with multiple independently accessible memory regions that can be accessed simultaneously by different operators.

[0065] In this example, multiple register groups can be set up, with each register group corresponding to a different operator. However, in another example, the register group can be a set of registers shared by multiple operators, or it can include multiple register groups, with at least some of these register groups being shared by multiple operators.

[0066] The multiple operators specified in this embodiment can be some or all of the multiple operators available in the hardware accelerator. The specified multiple operators and their connection order can be reflected in the software code executed by the hardware scheduler. That is, the connection between the multiple operators is a soft connection. The user can generate software code according to the needs of the computing task, and select some or all of the operators available in the hardware accelerator to execute the computing task through the software code (the selected multiple operators are the specified multiple operators). The connection order of the specified multiple operators can be defined by the positional relationship between the caches allocated to the multiple operators in the software code, as well as the order of scheduling instructions sent to the operators. For example, for a specific application, multiple operators are sequentially connected, and the output data of the previous operator is input to the next operator as input data for processing, and finally the result of this application is output. Based on this embodiment, data interaction between multiple operators is carried out through a shared cache pool. That is, in the hardware accelerator, there is at least one multi-bank memory. The storage space of this memory serves as the cache space of the shared cache pool. It is allocated in real time to different operators in the hardware accelerator through software configuration. The input and output data of multiple operators come from this memory. The time-sharing processing of different operators can also be defined by software code.

[0067] Figure 7 illustrates some operators used in this embodiment when applied to a radar system, such as FFT, SVA, CFAR, DoA, etc. This is merely an example, and these operators can be set in different hardware accelerators. The DMA controller in the figure can also be used as an operator (referred to as DMA operator). Under the control of the hardware scheduler, the DMA operator can store the data obtained after processing the data to be processed by multiple operators into memory. This embodiment can support a variety of operators, including but not limited to dedicated hardware acceleration operators defined by chip manufacturers, such as FFT operators, CMB operators, etc., and can also be broadly extended to general-purpose operators, such as using processors such as DSPs, CPUs, DPUs, APUs, etc. as operators. The structure of dedicated hardware acceleration operators can include logic circuits to implement a certain operation, such as CMB operators and SVA operators to implement complex multiplication and addition operations, and can also include auxiliary circuits such as multiplexers, internal lookup tables, internal memory, filters, etc.

[0068] This embodiment describes how operator buffer allocation and scheduling are related to the characteristics of the operators. Some operators, such as FFT and SVA, process the input data to obtain processed data different from the input data. Input and output buffers can be allocated to these operators. However, not all operator processing requires changing the input data; it can also involve passing through data while performing some statistics on the input data, or moving the input data. For example, multiple operators may include a Digital Front End (DFE) operator (described in detail below). Only the output buffer can be allocated to this operator. After the operator starts, it passes the input data to the output buffer and performs statistics on the input data. Similarly, multiple operators may include a DMA operator. Only the input buffer can be allocated to this operator. After the operator starts, it moves the input data to memory. The operators in the hardware accelerator of this embodiment are not limited to the methods listed here, and will not be elaborated further.

[0069] The hardware scheduler (SEQ: sequencer) in this embodiment can be implemented using an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a Microprocessor (MCU), etc. This hardware scheduler can internally set up a cache to load software code written for the current computing task or automatically generated. By executing instructions in the software code, it performs operations such as allocating caches for operators and scheduling operators. The scheduling of operators can be based on scheduling instructions (a set of scheduling instructions includes a start instruction and a synchronization instruction). However, this does not mean that the hardware scheduler must send start and synchronization instructions to every operator. For example, it may not send start and synchronization instructions to DFE operators that pass through data. When a DFE operator detects data input, it can automatically pass the input data through to the output cache and perform statistics simultaneously. The sequential startup of multiple operators described in this paper does not mean that only one operator can be started at a time step in the initial stage, but rather covers the case where DFE operators can pass through data without synchronization.

[0070] In an exemplary embodiment of this disclosure, the hardware scheduler is a hardware scheduler as described in any embodiment of this disclosure (the first hardware scheduler or the second hardware scheduler hereinafter referred to as such); the plurality of operators are operators as described in any embodiment of this disclosure (see below).

[0071] Radar signal processing can be divided into multiple stages, such as 1D-FFT, 2D-FFT, and CFAR, all of which can be accelerated by hardware accelerators. Each stage's corresponding hardware accelerator can be pre-configured with the necessary operators. The function of each operator is determined by dividing the processing flow of that stage. However, operator configuration is not simply based on size; it also considers possible combinations. Even if an operator is large (e.g., with high computational load or many processing steps), it may not need further splitting to meet multiple combination requirements. Conversely, if the components of an operator need to retain the possibility of other combinations, it can be further split into more operators. To adapt to the different needs of various applications, operators in the hardware accelerator can be configured for multiple applications. When executing a computational task for a specific application, multiple relevant operators are specified through software code to execute the task, while some unrelated operators can be disabled.

[0072] In an exemplary embodiment of this disclosure,

[0073] The plurality of operators sequentially include: CQMD operator, FFT operator, and SVA operator; or

[0074] The plurality of operators sequentially include: DC operator, FFT operator, and SVA operator; or

[0075] The plurality of operators sequentially include: CMB operator, STAS operator, HIST operator, CFAR operator, and STAS operator; or

[0076] The plurality of operators include, in sequence: DC operator, FFT operator, SVA operator, and CMB operator.

[0077] As described above, in one example of this embodiment, the specified multiple operators are operators in the 1D-FFT processing stage, which sequentially include the Digital Front End (DFE) operator, the Chirp Quality Monitor Detection (CQMD) operator, the Fast Fourier Transform (FFT) operator, and the Spatial Vector Analysis (SVA) operator, as shown in Figure 8A. The DFE operator is optional.

[0078] As described above, in another example of this embodiment, the specified plurality of operators are operators in the 2D-FFT processing stage, including, in sequence, the DC removal (DC: Direct Current) operator, the FFT operator, and the SVA operator. Figure 8B shows an example of this embodiment, which includes two SVA operators, denoted as SVA1 and SVA3, but in other examples, only one SVA operator may be included. In addition to the above operators, it also includes a DMA operator (denoted as DMAI operator) for loading external data to be processed into the hardware accelerator and a DMA operator (denoted as DMAO operator) for storing data processed by the hardware accelerator into external memory, such as memory.

[0079] As described above, in another example of this embodiment, the specified plurality of operators are operators in the CFAR processing stage, including, in sequence, the Controller of Combination (CMB) operator, the Statistic (STAS) operator, the Histogram (HIST) operator, the CFAR operator, and the STAS operator. Figure 8C shows an example of this embodiment, which, in addition to the above-mentioned operators, also includes two DMA operators, denoted as the DMAI operator and the DMAO operator, respectively.

[0080] The processing performed by the hardware accelerator is not necessarily divided into the 1D-FFT processing stage, 2D-FFT processing stage, and CFAR processing stage as described above. In another example of this embodiment, the specified multiple operators sequentially include the DC operator, FFT operator, SVA operator, and CMB operator, as shown in Figure 8D.

[0081] Depending on the application requirements, other operators can be inserted between the multiple operators in the above example.

[0082] In the above-described exemplary hardware accelerator, the inputs and outputs of the operators are all connected to a shared cache pool (such as a multi-bank memory). All operators have independent cache allocation permissions, which can be implemented through cache allocation instructions in the software code. For example, the hardware scheduler can parse the cache allocation instructions and configure the register group corresponding to the operator, such as the location and size information to be written to the cache.

[0083] Let's take Figure 8B as an example to further explain the data interaction between operators. In the figure, the DC operator, FFT operator, SVA operator, and SVA operator are connected in sequence. These operators all read input data (i.e., the data to be processed by this operator) from the input buffer allocated to them by the shared buffer pool, process the input data, and save the processed data (the data to be processed by the next operator) to the output buffer allocated to them by the shared buffer pool. A more detailed data flow is shown in Figure 9A. Taking the flow of a data block in the data to be processed as an example, DMAI loads the data block from external memory (such as memory) into two areas in the shared cache pool, namely Cache0 or Cache1. Cache0 and Cache1 are allocated as the two output caches of the DMAI operator and the two input caches of the DC operator. The operator can switch the cache used in adjacent time steps. The DC operator reads the data block from Cache0 or Cache1 for processing, and the processed data block is written to Cache2 or Cache3. Cache2 and Cache3 are allocated as the two output caches of the DC operator and the two input caches of the FFT operator. The FFT operator reads the data block from Cache2 or Cache3 for processing, and the processed data block is written to Cache4 or Cache5. Cache5 and Cache6 are allocated as the two output caches of the FFT operator and the two input caches of the SVA1 operator. The subsequent processing of the SVA1 and SVA2 operators is similar. After the SVA2 operator writes the processed data block to Cache8 or Cache9, the DMAO operator stores the processed data block to external memory, thereby completing the processing of the data block. When hardware acceleration is working, data blocks are continuously loaded and processed in parallel according to the process described above.

[0084] Although the hardware accelerator shown in Figure 8B includes a DMA operator, which is scheduled by the hardware scheduler within the accelerator to load external data to be processed into the hardware accelerator or store the data processed by the hardware accelerator externally, in other embodiments, a DMA operator may not be configured, as shown in Figure 8D. In this case, the processing of loading data to be processed into the shared cache pool and storing the data processed by all operators in the shared cache pool externally is performed by the processor, typically implemented using DMA. For example, after the hardware scheduler completes processing the first batch of data blocks, it can notify the processor to retrieve the data from the output cache of the last operator, such as Cache9. Upon receiving the notification, the processor configures the DMA controller, which then moves the data from Cache9 to memory. In this case, the DMA controller is not controlled by the hardware scheduler. It is easy to understand that in other embodiments, the hardware accelerator may also be configured with only one DMA operator, such as only a DMAI operator for loading external data to be processed into the hardware accelerator, or only a DMAO operator for storing the data processed by the hardware accelerator externally, as shown in Figure 8A.

[0085] The DEF operator in Figure 8A passes the input data to the output buffer without needing to allocate an input buffer. Therefore, external data to be processed can be directly loaded into the input of the DFE operator and then passed to the shared buffer pool.

[0086] In addition to the sequential connection of multiple operators, the hardware accelerator of this embodiment also supports multiple connection methods. As shown in FIG9B, operator B can process the input data multiple times, and then operator C reads the data processed by operator B. That is, the data stream can have loopback. When an operator needs to perform multiple processing on a data block, it can also be achieved by reallocating the cache and scheduling by the hardware scheduler. For example, if processing is required twice, after the first processing is completed at the Nth time step, the output cache of the Nth time step can be reconfigured as the input cache of the N+1th time step, and the input cache of the Nth time step can be reconfigured as the output cache of the N+1th time step. At the N+1th time step, operator B processes the data block again. Before the N+2th time step begins, the output cache used by operator B at the N+1th time step is configured as the input cache used by operator C at the N+2th time step. At the N+2th time step, operator C reads data from the configured input cache. Throughout the entire loop processing, one or more loops can be added individually for operators that require loopback, so as to realize the flow of data between adjacent operators.

[0087] Loopback can occur either within a single operator or between multiple operators. In the case of loopback, multiple operators of the same type can be set up. For example, when there are two operators B in Figure 9B, connecting the four operators in the order of operator A, operator B, operator B, and operator C will yield the same processing result.

[0088] In addition to changing the connection relationships of operators, this embodiment can also specify different operators to implement different applications by generating corresponding software code. For example, the dashed line in Figure 9B indicates that the hardware accelerator can omit operator A and only perform cache allocation and scheduling for operators B and C.

[0089] The hardware accelerator scheme of this disclosure can decompose the radar signal processing flow into multiple operators, all of which are connected to a shared memory pool. Data interaction between operators is conducted through the memory pool, and the space allocation of the memory pool and the scheduling of operators are exposed and defined by software instructions, thus being relatively decoupled from the hardware design. Therefore, it has high performance and application flexibility.

[0090] This disclosure also provides a computing system, including a processor, memory, and a hardware accelerator, as shown in FIG7, wherein:

[0091] The processor is configured to load the data to be processed stored in the memory into the hardware accelerator;

[0092] The memory is configured to store data to be processed, and to store data obtained by the hardware accelerator after processing the data to be processed.

[0093] The hardware accelerator is configured to allocate caches to multiple operators based on a set connection order to form a data interaction channel between the multiple operators; and to control the multiple operators to start sequentially according to the set connection order, to complete the processing of the loaded data to be processed in a pipeline manner, and to store the processed data in the memory.

[0094] The hardware accelerator in the computing system of this disclosure can allocate caches to multiple operators based on a set connection order to form a data interaction channel between the multiple operators; and control the multiple operators to start sequentially according to the set connection order to complete the processing of the loaded data to be processed in a pipeline manner. Therefore, users can flexibly select multiple operators according to different computing tasks in different usage scenarios, and set the connection relationship between multiple operators and the data flow direction when multiple operators are working, so as to adapt to the processing flow needs of the computing task.

[0095] As mentioned above, the radar signal processing flow includes multiple stages, each of which can be accelerated by its respective hardware accelerator. Therefore, the computing system in this embodiment, such as the SoC, can have multiple hardware accelerators. For example, a first hardware accelerator can be set up for accelerating the 1D-FFT processing stage, a second hardware accelerator for accelerating the 2D-FFT processing stage, and a third hardware accelerator for accelerating CFAR processing. More accelerators can also be set up to perform other processing such as target recognition and target tracking. Assuming that the parallel use of multiple hardware accelerators is fully considered during the software code development process, this embodiment can support the parallel processing of any number of operators, ensuring the maximum data processing capacity per unit chip area.

[0096] In a hardware accelerator, one or more operators of the same type can be set. Multiple hardware accelerators can be started sequentially. For example, after the first hardware accelerator used to accelerate the 1D-FFT processing stage finishes processing and the processed 1D-FFT data is stored in memory, the 1D-FFT data in memory is loaded into the second hardware accelerator used to accelerate the 2D-FFT processing stage, and the second hardware accelerator is started, and so on.

[0097] The processor in this embodiment can be a general-purpose processor, such as any one or a combination of a central processing unit (CPU), digital signal processor (DSP), data processing unit (DPU), and accelerated processing unit (APU), but it can also be other conventional processors. The processor can also be an integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), discrete logic or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above devices. That is, the processor in the above embodiments can be any processing device or combination of devices that implements the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. When the embodiments of this disclosure are implemented in part in software, instructions for software can be stored in a suitable non-volatile computer-readable storage medium, and one or more processors can be used to execute the instructions in hardware to implement the methods of the embodiments of this disclosure. The processor in FIG7 includes a CPU and a DSP, which are merely exemplary.

[0098] In this embodiment, the memory can be a storage medium such as Static Random-Access Memory (SRAM), Dynamic Random-Access Memory (DRAM), High-Bandwidth Memory (HBM), NAND Flash, etc.

[0099] In this embodiment, assuming that the first operator among multiple operators connected in a set connection order is an operator that passes through input data (such as the DFE operator below), the processor can load the data block to be processed in memory into the input of this operator. If an input buffer is allocated for the first operator, the processor can load the data block to be processed in memory into the input buffer allocated for the first operator from the shared buffer pool.

[0100] In this embodiment, when the processor loads data using DMA, it can control a DMA controller (which may be different from the DMA operator) to load the data to be processed in memory into the hardware accelerator using DMA, such as loading data blocks one by one into the input buffer allocated to the first operator among the plurality of operators, or loading it into the input terminal of the first operator. A data block can be a chirp of data or multiple chirps of data on a distance gate.

[0101] In an exemplary embodiment of this disclosure, the hardware accelerator is the hardware accelerator described in any embodiment of this disclosure, and the computing system is a system-on-a-chip (SoC), which integrates the hardware accelerator, processor and memory into a single SoC.

[0102] In one exemplary embodiment of this disclosure, the system-on-a-chip is a millimeter-wave chip or sensor chip in a radar system, but this disclosure is not limited thereto.

[0103] Although the computing system in this embodiment adopts a SoC architecture, in other embodiments, a separate hardware accelerator can also be used. This hardware accelerator can be implemented using the control chip of the CXL device, and the processor can access the hardware accelerator through the CXL interface. The memory can be a DDR chip on the CXL device connected to the control chip.

[0104] This disclosure also provides a multi-operator control method (to distinguish it from the control method shown in Figure 19, the control method in this embodiment is also referred to as the first control method), applied to a hardware accelerator including multiple operators and a hardware scheduler, as shown in Figure 10, including: scheduling the multiple operators sequentially according to a set connection order through time-step scheduling to complete the processing of the data to be processed, wherein the scheduling of each time step includes:

[0105] Step 100: Send a start signal to the activation operator to trigger the activation operator to start a process once; wherein, the activation operator is the operator among the plurality of operators that needs to be controlled to start a process once in this time step;

[0106] Step 101: In response to the fact that all the activation operators have completed the current processing, the scheduling of this time step ends. If the processing of the data to be processed has not been completed, the scheduling of the next time step continues.

[0107] The method in this embodiment can be executed by a hardware scheduler. The hardware scheduler decodes the start instruction in the software code, sends a start signal to the activation operator by executing the decoded start instruction, and decodes the synchronization instruction. By executing the decoded synchronization instruction, it determines whether all the activation operators have completed their current processing. If all the activation operators have completed their current processing, the scheduling of the current time step ends. As mentioned above, some operators, such as the DFE operator, do not require control signals to start processing and have a very small computational load; these operators may not be scheduled as activation operators.

[0108] This embodiment uses time steps as the scheduling unit. A start signal (e.g., a pulse signal) is sent to the activation operator to trigger it to begin processing once, and the scheduling of the current time step ends after all activation operators have completed their processing. Therefore, synchronous processing of activation operators is achieved in time steps. The control method is simple, but it ensures that the processing of multiple operators is ordered, such as avoiding conflicts where a subsequent operator reads data before a preceding operator has input the data required by the subsequent operator.

[0109] In an exemplary embodiment of this disclosure, the step of scheduling multiple operators sequentially according to a set connection order to complete the processing of the data to be processed by time-step scheduling includes: performing multiple loop control, in which each loop process, through multiple time-step scheduling, controls the multiple operators to complete the processing of multiple data blocks in the data to be processed in a pipeline manner according to a set connection order; wherein, each activated operator completes the processing of one data block in one time step, and after completing the processing of one data block, it issues a processing end signal to notify the hardware scheduler. This embodiment completes the processing of all data to be processed through multiple loop control, and each loop can be scheduled to allow multiple operators to process concurrently in a pipeline manner, thus achieving high efficiency.

[0110] For hardware accelerators, different computing tasks will have different processing flows. The cyclic processing flow specified in the embodiments of this disclosure does not mean that all computing tasks of the hardware accelerator must use such a flow.

[0111] In one example of this embodiment, each loop process includes M time steps, M = m1 + m2 - 1, where m1 is the number of the plurality of operators, m2 is the number of data blocks processed in each loop, m1 ≥ 2, m2 ≥ 2;

[0112] When m < m1, the activation operator for the m-th time step is the first to the m-th operator, where m = 1, 2, ..., M;

[0113] When m1≤m≤m2, the activation operator at the m-th time step is any one of the plurality of operators;

[0114] When m2 < m ≤ M, the activation operator for the m-th time step is the m-m2+1 to m1-th operators.

[0115] An example of a radar system hardware accelerator comprising three operators, as shown in Figure 11A, is illustrated. This hardware accelerator includes a Bandwidth Extension (BWE) operator, an FFT operator, and an SVA operator connected sequentially. The processing of the data to be processed is accomplished through multiple loops. The radar system includes four receiving channels, and the data to be processed comprises data from all four channels. Assuming each channel contains 128 data blocks, the processing can be completed in 128 loops, with each loop processing the corresponding data blocks from the four channels (e.g., these four data blocks may be data from the same chirp).

[0116] The diagram illustrates a pipeline with three operators, showing only the processing of each operator at each time step in the first and second loops. Each row represents an operator, and each column represents a time step. The small squares at the intersection of rows and columns represent the channel number of a data block processed by one operator in a time step. As shown, in the first time step of the first loop, only the BWE operator starts; in the second time step, both the BWE and FFT operators start; in the third and fourth time steps, the BWE, FFT, and SVA operators start; in the fifth time step, the FFT and SVA operators start; and in the sixth time step, the SVA operator starts, thus completing one loop. It can be seen from the diagram that the order and duration of operator startup are the same in each loop. For a single operator, there are two idle time steps between each loop. In another embodiment, there are no idle time steps between two loops, as shown in Figure 11B. In this way, only in the first two time steps of the first loop and the last two time steps of the last loop will there be situations where some operators have not yet started or have already exited processing.

[0117] Taking Figure 11A as an example, in this embodiment, m1 is the number of operators, which is equal to 3, and m2 is the number of data blocks processed in each loop, which is equal to the number of receiving channels, which is 4. Then M = m1 + m2 - 1 = 6, that is, there are 6 time steps in each loop. In each loop:

[0118] When m < m1, the activation operator for the m-th time step is the first to the m-th operators, where m = 1, 2, ..., 6; corresponding to this example, the activation operator for the first time step between the 3rd and 4th time steps is the first operator, i.e., the BWE operator, and the activation operators for the second time step are the first and second operators, i.e., the BWE operator and the FFT operator.

[0119] When m1≤m≤m2, the activation operator at the m-th time step is all the operators among the plurality of operators. In this example, all operators at the 3rd and 4th time steps, namely the BWE operator, FFT operator, and SVA operator, are activation operators.

[0120] When m2 < m ≤ M, the activation operator for the m-th time step is the (m-m2+1)-m1th operator. In this example, the activation operators for the 5th time step are the 2nd and 3rd operators (FFT and SVA), and the activation operator for the 6th time step is the 3rd operator (SVA).

[0121] It is understood that even when m1 and m2 are other values, the determination rules for the activation operator in this embodiment are still satisfied.

[0122] This example allocates four pairs of buffers to each operator, each pair including an input buffer and an output buffer. In each loop, each operator performs four processing steps over four time steps, processing data blocks from four channels respectively. Each processing step uses one of the four allocated buffer pairs, ensuring that the data from the four channels is independent. For operators requiring independent processing of data from each received channel, the number of buffer pairs allocated can be equal to the number of channels in the radar system. For other operators without this requirement, two or more buffer pairs can be allocated. Unless otherwise specified in this application, "channel" refers to the received channel.

[0123] In an exemplary embodiment of this disclosure, the control method further includes: allocating caches for data access to the plurality of operators respectively, wherein the allocated caches include input caches and / or output caches; wherein the caches allocated to the plurality of operators all come from a shared cache pool, and different caches are located in different and independently accessible regions within the shared cache pool; and for adjacent operators, the output cache allocated to the preceding operator for use in the current time step is the input cache allocated to the following operator for use in the next time step. In this application, adjacent operators among the plurality of operators can be determined according to the set connection order of the plurality of operators. From the perspective of data interaction, when the output data of one operator is the input data of another operator, the two operators are adjacent operators, the operator that outputs the data is the preceding operator, and the operator that uses the output data of the preceding operator as input data is the following operator.

[0124] In one example of this embodiment, allocating caches for data access to the plurality of operators includes: before performing the multiple loop control operations, allocating caches for the first processing of each of the plurality of operators, wherein, for adjacent operators among the plurality of operators, the output cache allocated to the preceding operator is the input cache allocated to the following operator. In this example, before starting loop control, caches are allocated to specified operators. The information of the allocated caches includes row information and column information, which can be represented by offset, size, block information, etc. Here, the caches allocated are for the first processing of each operator, not for use in the same time step; therefore, the output cache allocated to the preceding operator is the input cache allocated to the following operator.

[0125] In one example of this embodiment, after allocating caches for the multiple operators to be used during the loop before the loop, the allocation of caches for data access by the multiple operators further includes: reallocating caches for operators that are active in both the previous and next time steps between two adjacent time steps; wherein, for adjacent operators among the multiple operators, the output cache allocated (including reallocation) for the preceding operator in the next time step is different from the input cache allocated for the following operator in the next time step. This example achieves the switching of caches used by operators between multiple or multiple pairs of allocated caches by reallocating caches, and the output cache allocated for the preceding operator in the next time step is different from the input cache allocated for the following operator in the next time step, which can ensure that two operators will not access the same cache simultaneously and cause a conflict. The switching of caches used by operators between multiple or multiple pairs of allocated caches does not necessarily have to be achieved by the hardware scheduler performing the cache reallocation operation; it can also be achieved by the hardware logic of the operator combined with configuration information (such as the total number or total number of allocated caches).

[0126] In one example of this embodiment, for each of the plurality of operators, there are K groups of buffers allocated and reallocated for the preceding operator during the multiple loops, where K ≥ 2. Each group includes an input buffer and / or an output buffer. Starting from the first processing of the operator, with a period of K time steps, the buffer used by the operator in the kth time step of different periods is the same, and the buffer used in different time steps of the same period is different.

[0127] In an exemplary embodiment of this disclosure, the data to be processed is a frame of data obtained by the radar system processing the received radar signal; the plurality of operators include operators in the 1D-FFT processing stage, and a data block in the data to be processed is data obtained by processing a chirp signal received on a channel; or, the plurality of operators include operators in the 2D-FFT processing stage, and a data block in the data to be processed is data at the same range gate in the 1D-FFT data, wherein the 1D-FFT data is data obtained after processing in the 1D-FFT processing stage, including data for multiple chirps.

[0128] An embodiment of this disclosure also provides a hardware scheduler, as shown in FIG12, including a memory 50 and a control device 60. The memory stores software code for controlling multiple operators, and the control device is configured to run the software code to execute the multi-operator control method described in any embodiment of this disclosure (the first control method corresponding to FIG10, and the second control method corresponding to FIG19). The control device can be any device capable of implementing control functions based on software code.

[0129] An embodiment of this disclosure also provides a hardware accelerator, as shown in FIG7, including a hardware scheduler and a plurality of specified operators, wherein: the hardware scheduler adopts the hardware scheduler described in any embodiment of this disclosure.

[0130] In an exemplary embodiment of this disclosure, the hardware accelerator further includes a shared cache pool and a register set that provide cache space for operators; wherein:

[0131] The hardware scheduler controls the plurality of operators by: allocating caches from the shared cache pool for the plurality of operators to use when accessing data, wherein the caches include input caches and / or output caches;

[0132] The register group is configured to store configuration information for the plurality of operators. The configuration information includes information on the cache allocated to the operators, and may also include other information such as parameters configured for the operators.

[0133] The plurality of operators are configured to, upon startup, obtain information about the cache allocated to the operator from the register group; if an input cache is allocated, read the data block to be processed from the input cache and process it; and if an output cache is allocated, write the processed data into the output cache.

[0134] In an exemplary embodiment of this disclosure,

[0135] The plurality of operators sequentially include: CQMD operator, FFT operator, and SVA operator; or

[0136] The plurality of operators sequentially include: DC operator, FFT operator, and SVA operator; or

[0137] The plurality of operators sequentially include: CMB operator, STAS operator, HIST operator, CFAR operator, and STAS operator; or

[0138] The plurality of operators include, in sequence: DC operator, FFT operator, SVA operator, and CMB operator.

[0139] An embodiment of this disclosure also provides an integrated circuit, as shown in FIG13. The integrated circuit includes a radio frequency module 2011, an analog signal processor 2012, and a digital signal processor 2013 connected in sequence, wherein:

[0140] The radio frequency module 2011 is configured to generate and transmit electromagnetic wave signals, and to receive echo signals;

[0141] The analog signal processor 2012 is configured to down-frequency the echo signal to obtain an intermediate frequency signal; and

[0142] The digital signal processor 2013 is configured to perform analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal;

[0143] The digital signal processor includes the hardware accelerator described in any embodiment of this disclosure.

[0144] In an exemplary embodiment of this disclosure, the integrated circuit is a millimeter-wave chip or sensor chip used in a radar system.

[0145] An embodiment of this disclosure also provides an electromagnetic wave sensor, as shown in FIG14, comprising: a carrier 4; an integrated circuit 5 as described in any embodiment of this disclosure, disposed on the carrier 4; and an antenna 6 disposed on the carrier 4, either integrated with the integrated circuit 5 as a single device or disposed separately; wherein the integrated circuit 5 is connected to the antenna 6 and is used to transmit the electromagnetic wave signal and / or receive the echo signal.

[0146] An embodiment of this disclosure also provides an apparatus, including: an apparatus body; and an electromagnetic wave sensor as described in any embodiment of this disclosure, disposed on the apparatus body; wherein the electromagnetic wave sensor is configured to perform target detection and / or communication to provide reference information to the operation of the apparatus body.

[0147] The following describes an exemplary hardware accelerator and corresponding multi-operator control method for implementing the 1D-FFT processing stage.

[0148] The 1D-FFT processing stage primarily involves performing noise compensation on the echo ADC data at the front end, followed by interference detection, Fast Discrete Fourier Transform (FFT), and Spatial Vector Analysis (SVA) to obtain frequency domain data. This data is then moved from the accelerator cache to external memory via DMA. Operators used to implement the 1D-FFT processing stage include: a Digital Front End (DFE) operator for noise compensation; a CQMD operator for interference detection; an FFT operator for performing FFT; an SVA operator for sidelobe suppression; and a DMA operator for storing data in memory. Data exchange between operators is sequential; for each operator, the input data is the data to be processed, and the output data is the processed data.

[0149] In this embodiment, the operator's cache allocation and scheduling are performed as follows:

[0150] DFE operator: It belongs to the data pass-through module and is not controlled by the start instruction and synchronization instruction, but it needs to allocate a buffer to buffer the pass-through data. The DFE operator can pass-through the input data to the output buffer and perform statistics on the input data. The amount of statistical results is very small and can be written to the output buffer or register group for use by subsequent operators.

[0151] CQMD operator: Controlled by start command and synchronization command, it requires a buffer to be allocated for the CQMD operator to read input data and write output data;

[0152] FFT operator: Controlled by start instructions and synchronization instructions, it requires the allocation of input buffers and output buffers for FFT to read input data and write output data;

[0153] SVA operator: Controlled by start and synchronization instructions, it requires the allocation of input and output buffers for SVA to read input data and write output data;

[0154] DMA operator: Controlled by start and synchronization instructions, it requires an input buffer to be allocated for DMA to read input data. DMA moves the input data to the chip's memory and does not require an output buffer.

[0155] In terms of physical cache space, the data flow between operators in this embodiment is sequential. The input data of CQMD is the output data of the DFE operator, the input data of FFT is the output data of CQMD, and the input data of DMA is the output data of SVA. As shown in Figure 13, the cache allocation for each operator is divided into four levels. Each level of cache includes two caches. The first level of cache is the output cache allocated to the DFE operator and the input cache allocated to the CQMD operator; the second level of cache is the output cache allocated to the CQMD operator and the input cache allocated to the FFT operator; the third level of cache is the output cache allocated to the FFT operator and the input cache allocated to the SVA operator; and the fourth level of cache is the output cache allocated to the SVA operator and the input cache allocated to the DMA operator.

[0156] In the time dimension, in this embodiment, when a later operator accesses data in the input buffer, it must be ensured that the data processed by the previous operator has been completely written to the output buffer to avoid access conflicts. To this end, this embodiment divides the time dimension into two alternating time steps (also called time slices or time units). In odd-numbered time steps (time steps 1, 3, 5, ...), the DFE operator processes the ADC data of chirps with odd indices, and writes the output data to DFE Cache0 (DFE output cache 0 / CQMD input cache 0 in the diagram). The CQMD operator is processing data in DFE Cache1 (DFE output cache 1 / CQMD input cache 1 in the diagram), and writes the output data to CQMD Cache1 (CQMD output cache 1 / FFT input cache 1 in the diagram). The FFT operator is processing data in CQMD Cache0 (CQMD output cache 0 / FFT input cache 0 in the diagram), and writes the output data to FFT Cache0 (FFT output cache 0 / SVA input cache 0 in the diagram). The SVA operator is processing data in FFT Cache1 (FFT output cache 1 / SVA input cache 1 in the diagram), and writes the output data to SVA Cache1 (SVA output cache 1 / DMA input cache 1 in the diagram). The DMA operator is processing SVA... The data in Cache0 (SVA output cache 0 / DMA input cache 0 in the diagram) is moved to external memory.

[0157] The data flow for the odd-numbered time steps is shown by the solid arrows in the figure. Similarly, in the even-numbered time steps (the 2nd, 4th, 6th, ... time steps), the dashed arrows in the figure represent the data flow for each operator reading and writing data, which will not be elaborated here.

[0158] Although this embodiment allocates two input buffers and / or two output buffers to each operator, switching between the two input buffers and / or two output buffers at a period of two time steps (odd time steps and even time steps), it is easy to understand that it is also feasible to allocate more than three input buffers and / or two output buffers to each operator, switching between more than three input buffers and / or two output buffers at a period of more than three time steps. For example, when the radar system has four receiving channels, four input buffers and / or four output buffers can be allocated to each operator, switching between the four input buffers and / or four output buffers at a period of four time steps. Data from one receiving channel is processed in each time step. In two adjacent operators in the same time step, the output buffer of the preceding operator is different from the input buffer of the following operator, and there will be no access conflict caused by two operators reading and writing to the same buffer at the same time. It can also realize independent processing of data from multiple channels.

[0159] In time steps where multiple operators are started, the processing bandwidth and processing time of the multiple operators differ, and the upper-level instruction control needs to ensure synchronization of operators within the time step. This embodiment allocates different buffers for operators in odd and even time steps, and for adjacent operators, the output buffer allocated for the preceding operator in the next time step is different from the input buffer allocated for the following operator in the next time step, thereby enabling pipelining and avoiding access conflicts between operators.

[0160] In this embodiment, the hardware scheduler uses a set of scheduling instructions to synchronously schedule operators. Each set of scheduling instructions includes a start instruction and a synchronization instruction. The start instruction controls the operator to begin processing, and the synchronization instruction determines whether the operator has completed its processing. The execution of the synchronization instruction ends when all operators have completed their processing. The time step proposed in this application begins with the execution of the start instruction in a set of scheduling instructions and ends when the execution of the synchronization instruction in that set of scheduling instructions is completed.

[0161] The table below illustrates the scheduling process for multiple operators in the hardware accelerator at each time step, where L1, L2, ..., L... n This represents the first, second, and so on up to the nth time step. Each time step can be divided into a start area (starting operator) and a sync area (synchronization between operators) to ensure the synchronization of different operators. As mentioned earlier, the DFE operator does not need to be controlled by scheduling instructions, so it is not shown in the table.

[0162] As shown in the table above, the start and synchronization instructions for the first time step L1 are sent to the CQMD operator to start it, and the synchronization for this time step ends after the CQMD operator finishes processing (completes processing of all data in the input buffer and writes the processed data to the output buffer). The start and synchronization instructions for the second time step L2 are sent to both the CQMD and FFT operators to start them simultaneously, and the synchronization for this time step ends after both the CQMD and FFT operators have finished processing. The start and synchronization instructions for the third time step L3 are sent to the CQMD, FFT, and SVA operators to start them simultaneously, and the synchronization for this time step ends after all three operators have finished processing. From the fourth time step L4 to the (n-3)th time step L... n-3The start and synchronization instructions for each time step are sent to the CQMD, FFT, SVA, and DMA operators to simultaneously start them. Synchronization for the current time step ends after all three operators have finished processing. The (n-2)th time step L... n-2 The start and synchronization instructions are sent to the FFT operator, SVA operator, and DMA operator to start them simultaneously, and the synchronization of this time step ends after all three operators have finished processing; the (n-1)th time step L n-1 The start and synchronization instructions are sent to both the SVA and DMA operators to start them simultaneously, and the synchronization ends at the current time step after both the SVA and DMA operators have finished processing; in the nth time step L n Both the start command and the synchronization command are sent to the DMA operator to start the DMA operator, and the synchronization of the current time step ends after the DMA operator has finished processing. One cycle of processing is completed in n time steps.

[0163] In this embodiment, the aforementioned n time steps are the time steps taken to obtain the processing result of the input dataset (such as a frame of ADC data) through multiple loop processing. It can be seen that, except for the first three time steps where each operator starts processing sequentially and the last three time steps where each operator exits sequentially, all operators in other time steps process synchronously, starting the next loop before the previous loop is completed. The entire process is pipelined. Taking its application in radar systems as an example, considering the characteristics of radar data processing, an application typically needs to process thousands of data blocks. During the entire processing time, 99% of the time, all operators and buffers are 100% utilized, thus maximizing the chip's processing capacity per unit area.

[0164] In the design of hardware accelerators, it is essential to ensure that the processing time of multiple operators is as consistent as possible in order to maximize resource utilization. In this embodiment, the CQMD, FFT, and SVA operators process approximately the same amount of data per iteration, and their processing time within a time step is consistent. The simple scheduling method employed in this embodiment also demonstrates high efficiency.

[0165] In another embodiment, the n time steps in the table above can be the time steps taken to process n-3 consecutive data blocks in the data to be processed in one loop. For example, when the radar system includes 8 receiving channels, the processing of 8 chirp data received by the 8 receiving channels can be completed in 11 time steps. In this loop, all operators are processed synchronously in the 4th to 8th time steps, and from the 9th time step onwards, the CQMD operator, FFT operator, and SVA operator exit the loop one by one. In the 11th time step, only the DMA operator works. After the 11th time step ends, the next round of loop processing begins. In this embodiment, each loop processing still operates in a pipeline manner, and this application still refers to it as a pipeline operation mode.

[0166] As described above, the multiple operators specified in this embodiment can be soft-connected through software code. Based on the same hardware accelerator, different software codes can be generated when facing different computing tasks. Through cache allocation instructions in the software code, caches are allocated to the specified multiple operators based on the set connection order to form a data interaction channel between operators. Furthermore, data processing in this embodiment can be executed by hardware-accelerated operators, and scheduling instructions can control the multiple operators to start sequentially and process in parallel in a pipeline manner. Therefore, the hardware accelerator of this embodiment has application flexibility, does not require frequent data transfer, and also has good performance and low power consumption, effectively solving the contradiction between application flexibility and high performance and low power consumption of hardware accelerators. The hardware accelerator of this embodiment can be applied not only to radar systems but also to other systems that require the use of hardware accelerators.

[0167] An embodiment of this disclosure also provides a control device (referred to as a first control device to distinguish it from the control device in the embodiments below), for controlling a plurality of operators configured to process data to be processed according to a set connection order, the control device comprising:

[0168] The instruction decoding circuit is configured to decode software code, which includes multiple sets of scheduling instructions. Each set of scheduling instructions includes a start instruction and a synchronization instruction. The start instruction includes operands for indicating which operator needs to be started, and the synchronization instruction includes operands for indicating which operator needs to be synchronized.

[0169] The instruction execution circuit is configured to, in response to a start instruction in a decoded set of scheduling instructions, control the operator indicated by the operand to start a processing operation; and in response to a synchronization instruction in the decoded set of scheduling instructions, determine that all operators indicated by the operands have completed the current processing operation, and then terminate the execution of the synchronization instruction.

[0170] The control device in this embodiment can be the logic control circuit in the aforementioned hardware scheduler. As shown in Figure 16, the instruction decoding circuit 10 reads and decodes the instructions in the software code. The decoded instructions are then converted into corresponding operations by the instruction execution circuit 20, such as sending a start signal, reading or writing registers, etc.

[0171] Here is a set of pseudocode examples of scheduling instructions:

[0172] start_eng_q0 BWE+FFT

[0173] sync_q0 BWE+FFT

[0174] The pseudocode for the start instruction is "start_eng_q0 BWE+FFT". "start_eng_q0" indicates that this instruction is a start instruction, and "BWE+FFT" indicates that the operators to be started are the BWE and FFT operators. The pseudocode for the synchronization instruction is "sync_q0 BWE+FFT". "sync_q0" indicates that this instruction is a synchronization instruction, and "BWE+FFT" indicates that the operators to be synchronized are the BWE and FFT operators. During the execution of the synchronization instruction, the instruction execution circuit monitors the status of the BWE and FFT operators. When it determines that both operators have completed processing (e.g., when it receives a completion signal from either operator), it terminates the execution of the synchronization instruction, and subsequent instructions can then be executed.

[0175] This embodiment decodes multiple sets of scheduling instructions through an instruction decoding circuit and then executes them through an instruction execution circuit. One scheduling can start one or more operators and end after all the started operators have completed processing. Therefore, it can control the operators to complete the processing of the data to be processed step by step in a time step manner, ensuring that the operators connected according to the set connection order process the data blocks in the correct time order, avoiding conflicts such as when the previous operator has not yet outputted the data required by the subsequent operator while the subsequent operator is reading data.

[0176] In an exemplary embodiment of this disclosure, the start instruction includes an opcode and operands represented by a bitmap. Each of the plurality of operators corresponds to one bit in the bitmap, and the value of this bit indicates whether the operator needs to be started. The synchronization instruction includes an opcode and operands represented by a bitmap. Each of the plurality of operators corresponds to one bit in the bitmap, and the value of this bit indicates whether the operator needs to be synchronized. After the start instruction is decoded and executed, a start signal can be generated for each operator that needs to be started. This signal is sent to the operator through a dedicated interface such as a signal line to trigger the operator to begin a processing cycle. The pseudocode mentioned above is not the actual executed instruction; the format of the actual instruction is described here.

[0177] In an exemplary embodiment of this disclosure, a single instruction in the software code is a short instruction of 16 bits, 32 bits, or 64 bits.

[0178] In some situations, 128-bit instructions are used, which have a wide bit width and are not user-friendly for instruction encoding and parsing. Furthermore, for some instructions, 128 bits cannot be fully utilized; for example, the STOP instruction only uses the high 6 bits, resulting in wasted instruction set storage space. This disclosure uses short instructions, such as 32-bit short instructions, which are easier to encode and parse, and improve instruction execution efficiency. It has, but is not limited to, the following advantages: 32 bits can be effectively utilized, avoiding the waste of a large number of bits and saving instruction set storage space; instruction combinations are more flexible, making it easier for users to implement various functions; the hardware implementation of the scheduler is simpler, reducing the possibility of errors; and, short instructions have higher transmission efficiency, reducing the power consumption and running time of the radar signal processor.

[0179] In an exemplary embodiment of this disclosure, the software code decoded by the instruction decoding circuit further includes a loop start instruction and a loop end instruction, wherein the loop start instruction includes an operand representing the number of loop iterations; and the multiple sets of scheduling instructions are located between the loop start instruction and the loop end instruction.

[0180] The instruction execution circuit responds to the decoded software code by performing multiple loop processes, controlling the multiple operators to complete the processing of the data to be processed in a pipeline manner according to a set connection order; wherein, each loop process includes multiple time steps, each time step starts from the execution of the start instruction in a set of scheduling instructions and ends when the execution of the synchronization instruction in the set of scheduling instructions ends, and each operator started in each time step completes the processing of one data block in the data to be processed in that time step.

[0181] The following pseudocode demonstrates an example of loop-related instructions:

[0182] Instructions for reallocating the cache can also be inserted between the above set of scheduling instructions, as explained below.

[0183] In an exemplary embodiment of this disclosure, the loop start instruction and the loop end instruction include M sets of scheduling instructions, and each loop process includes M time steps, M = m1 + m2 - 1, where m1 is the number of the plurality of operators, m2 is the number of data blocks processed in each loop, m1 ≥ 2, m2 ≥ 2;

[0184] When m < m1, the activation operator for the m-th time step is the first to the m-th operator, where m = 1, 2, ..., M;

[0185] When m1≤m≤m2, the activation operator at the m-th time step is any one of the plurality of operators;

[0186] When m2 < m ≤ M, the activation operator for the m-th time step is the (m-m2+1)-m1 operator;

[0187] Among them, the operator to be started in the start instruction of the m-th group of scheduling instructions is the activation operator of the m-th time step.

[0188] This embodiment is used to determine the activation operator (i.e. the operator that needs to be activated) at each time step, as can be seen in the description of the example shown in Figure 11A above.

[0189] In an exemplary embodiment of this disclosure, the software code decoded by the instruction decoding circuit further includes a plurality of cache allocation instructions; the instruction execution circuit, in response to the plurality of cache allocation instructions, allocates caches for the plurality of operators to be used when accessing data.

[0190] The caches allocated to the multiple operators all come from a shared cache pool, and the multiple caches allocated to the multiple operators for use at the same time step are located in different and independently accessible areas of the shared cache pool, so as to avoid access conflicts caused by two operators accessing a cache at the same time.

[0191] The allocated cache includes an input cache and / or an output cache. For adjacent operators among the plurality of operators, the output cache allocated to the preceding operator for use in the current time step is the input cache allocated to the following operator for use in the next time step, thereby forming a data interaction channel between adjacent operators.

[0192] In an exemplary embodiment of this disclosure, the plurality of cache allocation instructions decoded by the instruction decoding circuit include a plurality of first cache allocation instructions located before the loop start instruction. The first cache allocation instruction includes: a first operand, used to indicate the location and size of the cache initially allocated for the operator; and a second operand, used to indicate the storage space to be written to the first operand.

[0193] The instruction execution circuit is further configured to, in response to a plurality of decoded first cache allocation instructions, write a first operand in each first cache allocation instruction into the storage space indicated by a second operand in the cache allocation instruction, so as to allocate cache for the plurality of operators to be used during the first processing.

[0194] The cache space of the shared cache pool can be a storage array, including multiple rows and columns. The aforementioned first cache allocation instruction can be a single instruction or multiple related instructions. In this embodiment, when a single instruction uses a short instruction in the software code, the first cache allocation instruction includes multiple short instructions.

[0195] The first operand, used to indicate the location and size of the cache, can include multiple immediate values ​​to represent the position of the first row, the number of rows, and the position and number of the first column. The position of the first row and the position of the first column can be represented by the index of the first row and the index of the first column, respectively. The number of rows and columns can be represented in various ways. For example, the number of rows can be represented directly by the value of the number of rows, or by the combination of the index of the first row and the index of the last row, or by the size and number of banks (areas, which can be understood as a set of rows) in the row direction. That is, it can be represented by one or more numbers, either directly or indirectly. The second operand, used to indicate the memory space to be written to by the first operand, can be a register address. However, not every immediate value needs to be written to this register address; it is sufficient that the register address to which each immediate value needs to be written can be obtained based on this register address.

[0196] Here is an example of a first cache allocation instruction represented in pseudocode:

[0197] In the pseudocode above, each line represents an instruction. The first line, wr_que0, indicates writing to a register. 0xb00 is the register address, and 29 indicates that 30 numbers are to be written. The first number is written to address 0xb00, the second to address 0xb04, the third to address 0xb08, and so on, jumping sequentially.

[0198] In each line, Wdat represents the written data. The immediate value in line 2 is defined as the position of the first column in the SVA input buffer, with a configured value of 16, indicating that the index of the first column is 16. The immediate value in line 3 is defined as the position of the first row in the SVA input buffer, with a configured value of 0, indicating that the index of the first row is 0. The immediate value in line 4 is defined as the size of the BANK (set of columns) in the column direction of the SVA input buffer, with a configured value of 3, indicating that a BANK in the column direction has 4 columns. The immediate value in line 5 is defined as the size of the BANK in the row direction of the SVA input buffer, with a configured value of 11, indicating that a BANK in the row direction has 12 rows. The immediate value in line 6 is defined as the number of BANKs included in the column direction of the SVA input buffer, with a configured value of 3, indicating that there are 4 BANKs. The immediate value in line 7 is defined as the number of BANKs included in the row direction of the SVA input buffer, with a configured value of 2, indicating that there are 3 BANKs. By combining multiple instructions, the input buffer allocated to the SVA operator has a first column index of 16, a total of 4×4 columns, a first row index of 0, and a total of 12×3 rows. The information for the output buffer allocated to the SVA operator can be configured in the same way.

[0199] In the example above, the multiple instructions used to configure the registers can also be called a parameter set. Each line can be 32 bits, but a single instruction cannot independently implement a specific function.

[0200] In an exemplary embodiment of this disclosure, the plurality of cache allocation instructions decoded by the instruction decoding circuit further includes a second cache allocation instruction located between two adjacent sets of scheduling instructions. The second cache allocation instruction includes: a first operand for indicating the location of the cache to be reallocated for the operator in the next time step; and a second operand for indicating the storage space to be written to by the first operand.

[0201] The instruction execution circuit is further configured to, in response to each decoded second cache allocation instruction, write the first operand therein to the storage space indicated by the second operand therein, to allocate a cache for use in the next time step for an operator using the storage space; wherein, for adjacent operators among the plurality of operators, the output cache allocated for use in the next time step for the preceding operator is different from the input cache allocated for use in the next time step for the following operator.

[0202] This embodiment uses a second buffer allocation instruction between two sets of scheduling instructions to reallocate buffers for operators. This allows operators to switch between multiple buffers, staggering the output buffer used by the operator at the same time step with the input buffer used by the operator at the next time step. This enables two operators to process data in parallel (including reading and writing data), thus working in a pipelined manner to improve efficiency. The two sets of scheduling instructions in this embodiment can be located in different loop processes.

[0203] The second cache allocation instruction can reallocate caches by changing a few parameters based on the cache allocated by the first cache allocation instruction. An example is as follows:

[0204] Wr_que0 [0xb00],0

[0205] Wdat 32 / / CFG_SVA_INP_BBUF_COL_OFFSET

[0206] In the pseudocode above, line 1 `wr_que0` indicates writing to the register, where 0xb00 is the register address and 0 indicates that the number of data to be written is 1. Line 2 `Wdat` indicates writing data; the immediate value to be written is defined as the index of the first column in the SVA operator's input buffer, configured to a value of 32. The information for the other buffers is the same as that allocated by the first buffer instruction and does not need to be reconfigured. Therefore, when reallocating the buffer, simply updating the index of the first column from 16 to 32 is sufficient to determine the location and size of the input buffer reallocated for the SVA operator. The same applies to the reallocation of the output buffer. Setting the reallocation instruction within a loop reduces the number of instructions required.

[0207] In one example of this embodiment, among the multiple sets of scheduling instructions, the second cache allocation instruction between two adjacent sets of scheduling instructions is used to reallocate the cache position for each operator that performed processing in the previous time step and still needs to perform processing in the next time step; for each of the multiple operators, starting from the time step when the operator is first started, with a period of K time steps, the cache allocated by the instruction execution circuit for the operator in the K time steps of the same period is different, and the cache allocated for the operator in the k-th time step of different periods is the same, k = 0, 1, ..., K-1, K ≥ 2.

[0208] Switching the cache used by an operator during a loop does not necessarily require instructions; it can also be achieved through the operator's hardware logic in conjunction with the configured number of caches. In another exemplary embodiment of this disclosure, the first operand in the first cache allocation instruction is further used to indicate the number K of caches used by the operator in the multiple loop processes. This instructs the operator to update the row or column position of the allocated cache step by step, with a period of K time steps, so that the operator uses different caches in the K time steps of the same period and the same cache in the k-th time step of different periods, where k = 0, 1, ..., K-1, K ≥ 2. The "number K of caches" here is equal to the K in "there are K groups of caches allocated and reallocated for the operator" above. When only input caches are allocated to the operator, this number K is the number of input caches; when only output caches are allocated to the operator, this number K is the number of output caches; when input and output caches are allocated to the operator (i.e., allocated in pairs), this number K is the logarithm of input and output caches, i.e., 4 input caches and 4 output caches are allocated in this case.

[0209] For example, in the example of the first allocation instruction mentioned above, another instruction could be added after the last instruction:

[0210] Wdat 3 / / CFG_SVA_BBUF_PPG_NUM

[0211] The immediate value in this pseudocode is defined as the number of buffers allocated by the SVA operator. A configured value of 3 indicates an allocation of 4 buffers. When only the operator's input buffer is allocated, this number refers to 4 buffers; when only the operator's output buffer is allocated, this number refers to 4 buffers; in this example, when allocating both input and output buffers for the SVA operator, this number refers to 4 buffers for both input and output buffers. However, when allocating both input and output buffers, the number of input and output buffers can be allocated separately. The number of buffers configured here equals the number of time steps in one cycle. Based on the above configuration, the SVA operator operates in a cycle of 4 time steps. The buffers used by the 4 time steps in each cycle will cycle sequentially between 4 pairs of buffers. These 4 pairs of buffers can be defined as having the same size and being sequentially connected in the column direction. The operator updates the position of the buffer used in each time step based on the position and size of the first pair of buffers, according to the number of received start signals (which can be counted cyclically using a counter), while keeping the size unchanged, thus reallocating buffers on the operator side. This method eliminates the need for a second buffer allocation instruction, simplifying the software code.

[0212] In an exemplary embodiment of this disclosure, the instruction execution circuit responds to a start instruction in a decoded set of scheduling instructions by sending a start signal to the operator indicated by the operand therein to control the operator therein to start a processing step.

[0213] The operator receiving the scheduling instruction among the plurality of operators is configured to: upon receiving a start signal, read the input data block from the input buffer and process it, and save the processing result to the output buffer; and, in response to the data block obtained after processing (i.e. the processing result) being saved to the output buffer, generate a signal indicating that the current processing is complete to notify the instruction execution circuit.

[0214] In this embodiment, the start signal is transmitted through a dedicated interface, such as the line between the hardware scheduler and the operator. In other embodiments, it can also be implemented through a configuration register, for example, by setting the register to 1 and 0 to generate a pulse signal, and using this pulse signal as a start signal to trigger the corresponding operator start process.

[0215] In an exemplary embodiment of this disclosure, the data to be processed is a frame of data obtained by the radar system from processing received radar signals; the plurality of operators are operators in the 1D-FFT processing stage, and a data block in the data to be processed is data obtained by processing a chirp signal received on a channel (referred to as chirp data); or, the plurality of operators are operators in the 2D-FFT processing stage, and a data block in the data to be processed is data at the same range gate in the 1D-FFT data. In application fields outside of radar, and in different processing stages within a radar system, the amount of data contained in the data blocks to be processed by the operators and the data to be processed, as well as the physical meaning of the data, can be different.

[0216] One embodiment of this disclosure provides a first hardware scheduler, as shown in FIG17, including a control device and an internal memory. The control device includes the control device described in any embodiment of this disclosure, and the internal memory is configured to store software code (or instruction queue) to be decoded and executed by the control device.

[0217] A hardware scheduler may include one or more memories and one or more control devices. The internal memory can use high-speed storage media such as SRAM as a cache. The example shown in Figure 17 includes two memories and two control devices, capable of controlling multiple hardware accelerators simultaneously. Software code in the internal memory of this example can be loaded in several ways: first, by writing to the internal memory via the APB bus; second, by first storing it in memory (see Figure 7) and then moving it from memory to the internal memory via DMA; and third, by the hardware scheduler actively reading the software code from a designated address. A multiplexer can be configured on the transmission paths of these three methods to select the data path used. As shown, the hardware scheduler is connected to the register bank and the shared cache pool, and can read and write to the register bank and the cache. The hardware scheduler can also send start signals to operators and receive done signals from operators. The done signal indicates that the operator has completed its current processing, and the control device can determine whether to end the synchronization instruction based on the done signal.

[0218] One embodiment of this disclosure provides an operator, as shown in FIG18, including a data reading unit, a processing unit, and a data writing unit, wherein:

[0219] The data reading unit is configured to acquire information about the input buffer allocated to the operator, and based on the information about the input buffer, read out the data blocks in the input buffer sequentially and input them into the processing unit;

[0220] The processing unit is configured to process the data block to obtain a processed data block;

[0221] The write data unit is configured to obtain information about the output buffer allocated to the operator, and write the processed data block into the output buffer based on the information about the buffer.

[0222] The operator in this embodiment is an operator that needs to process the input data block, and does not include all types of operators. The operator in this application can also be called a computing engine, computing unit, etc.

[0223] The operator in this embodiment can be applied to a hardware accelerator. Its structure allows data to be passed between operators through a cache, and the information of the allocated cache can be read from the outside. This enables soft connections (configurable connections) and fast data interaction between operators, ensuring processing efficiency. Furthermore, the connection relationship between operators and the design of data flow can be changed according to application needs, improving the application flexibility of the hardware accelerator using the operator.

[0224] In an exemplary embodiment of this disclosure, the operator further includes any one or more of the following interfaces:

[0225] The scheduling interface receives a start signal, which is used as a trigger signal for this operator to begin processing.

[0226] The synchronization interface is used to write the processed data block into the output buffer and then send a signal indicating that the processing is complete.

[0227] As shown in Figure 18, the operator can initiate a processing step (including reading, processing, and writing data) based on a start signal, such as a pulse signal, sent by the hardware scheduler through the scheduling interface. After processing is complete, the operator returns a "done" signal to the hardware scheduler through the synchronization interface to indicate that the processing is finished. The scheduling interface and the synchronization interface can be dedicated interfaces between the hardware scheduler and the operator, such as dedicated lines, or they can be implemented through register configuration.

[0228] In an exemplary embodiment of this disclosure, the read data unit obtains information about the input buffer allocated to the operator from the register set, and the write data unit obtains information about the output buffer allocated to the operator from the register set;

[0229] The aforementioned register set can be used by a single operator or shared by multiple operators. The hardware scheduler can also write operator parameters, statistical data generated during processing, or other configuration information into the corresponding register set, and is not limited to allocating buffers for operators.

[0230] In an exemplary embodiment of this disclosure, the operator further includes a cache update unit;

[0231] The cache update unit is configured to: read from the register group the location and size of the cache initially allocated to the operator, and the number K of caches allocated to the operator, where K ≥ 2; and cyclically count the number of times the scheduling interface receives the start signal, with the count value ranging from 0 to K-1; when the cumulative number of cycles is k, calculate the location of the cache used by the operator in the next time step based on the location and size of the initially allocated cache and the value of k, and update the cache location in the register group to the calculated cache location; where k = 0, 1, ..., K-1, and the calculated cache location is different when the value of k is different.

[0232] In the example shown in Figure 11A, each operator uses 4 caches during the loop. When updating the cache position on the operator side, taking the input cache of the SVA operator as an example, it is assumed that the first column index of the input cache initially allocated to the SVA operator in the register group is 16, and the total number of columns in the column direction of the cache is 16. The SVA operator's cache update unit monitors the number of times the start signal received by the scheduling interface is received. The initial value of k is 0. In the first loop:

[0233] The SVA operator receives the start signal for the first time in the third time step, uses the initially allocated input buffer with the first column index of 16, adds 1 to the value of k to equal 1, and updates the first column index stored in the register group to the new position 16+16=32.

[0234] The SVA operator receives the start signal for the second time in the fourth time step, uses the input buffer with the first column index of 32, adds 1 to the value of k to equal 2, and updates the first column index stored in the register group to 16 + 16 × 2 = 48;

[0235] The SVA operator receives the start signal for the third time in the 5th time step, uses the input buffer with the first column index of 48, adds 1 to the value of k to equal 3, and updates the first column index stored in the register group to 16 + 16 × 3 = 64;

[0236] The SVA operator receives the start signal for the fourth time at the 6th time step, uses the input buffer with the first column index of 64, increments the value of k by 1 to exceed the maximum value and sets it to 0, and updates the first column index stored in the register group to 16 + 16 × 0 = 16.

[0237] The updates to the input buffer are the same in subsequent loops, and the updates to the output buffer are similar, so I will not repeat them here.

[0238] This embodiment updates the cache on the operator side. When the number of caches allocated to the operator is large, it is not necessary to update the cache through many instructions, which can simplify instruction design.

[0239] Another embodiment of this disclosure provides a control device (also referred to as a second control device to distinguish it from the control device in the foregoing embodiments), for controlling a plurality of specified operators, the plurality of operators being configured to process data to be processed according to a set connection order, the control device comprising:

[0240] An instruction decoding circuit is configured to decode software code, the software code including a plurality of first cache allocation instructions, each first cache allocation instruction including: a first operand, used to indicate the location and size of the cache allocated for the operator; and a second operand, used to indicate the storage space to be written to the first operand;

[0241] The instruction execution circuit, coupled to the instruction decoding circuit, is configured to, in response to a plurality of decoded first cache allocation instructions, write a first operand in each first cache allocation instruction into the storage space indicated by a second operand in the cache allocation instruction, so as to allocate caches for the plurality of operators to use when accessing data.

[0242] The caches allocated to the multiple operators are all from a shared cache pool.

[0243] The control device in this embodiment can be the logic control circuit in the aforementioned hardware scheduler. Alternatively, it can adopt the structure shown in Figure 16, where the instruction decoding circuit 10 reads and decodes the instructions in the software code, and the decoded instructions are converted into corresponding operations by the instruction execution circuit 20, such as reading or writing registers, sending a start signal, etc.

[0244] This embodiment decodes multiple first cache allocation instructions through an instruction decoding circuit and then executes them through an instruction execution circuit. It allocates caches to multiple operators from a shared cache pool, enabling data to be passed between operators through the cache. This achieves soft connections (configurable connections) and fast data interaction between operators, ensuring processing efficiency and allowing the connection relationship between operators to be changed according to application needs, thus improving the application flexibility of hardware accelerators using multiple operators.

[0245] In an exemplary embodiment of this disclosure, the first operand in the first cache allocation instruction is used to indicate the location and size of the cache initially allocated to the operator. The cache initially allocated to the operator is the cache used when the operator performs its first processing. The cache includes an input cache and / or an output cache.

[0246] The multiple operators are started sequentially according to a set connection order. For adjacent operators among the multiple operators, the output buffer initially allocated to the preceding operator is the same as the input buffer initially allocated to the following operator.

[0247] The first cache allocation instruction in this embodiment is used to indicate the location and size of the cache initially allocated to the operator. The cache can be reallocated for the operator during subsequent processing, but this disclosure is not limited to this. In another embodiment, the initially allocated cache can be used throughout the entire computational task performed by the operator. In this case, for adjacent operators, when the preceding operator writes the processed data to the output cache, the following operator can pause processing. After the preceding operator completes writing the data, it notifies the hardware scheduler or the following operator, which then reads the data from the output cache of the preceding operator (i.e., the input cache of the following operator) for processing. Although parallel processing between operators is not possible, soft connections between operators can still be achieved, improving application flexibility. Furthermore, the cache space occupied is small, making it suitable for situations where cache space is limited.

[0248] In an exemplary embodiment of this disclosure, a single instruction in the software code is a short instruction of 16 bits, 32 bits, or 64 bits. The aforementioned first cache allocation instruction may include multiple short instructions to implement the cache allocation function.

[0249] In an exemplary embodiment of this disclosure, the software code decoded by the instruction decoding circuit further includes multiple sets of scheduling instructions; the instruction execution circuit is further configured to schedule one or more operators in response to each set of decoded scheduling instructions, so that the scheduled operators start and complete one processing of a data block in a time step; wherein each time step starts when a set of scheduling instructions is executed and ends when the execution of the set of scheduling instructions ends.

[0250] This embodiment can be implemented using start and synchronization instructions, similar to the previous embodiments. However, other scheduling methods can also be used. For example, during the design phase, the processing time of multiple operators can be balanced. When generating the software code, a set time margin can be added to the maximum processing time of multiple operators each time, serving as the set time for each time step. Each time step begins when the start instruction is executed and ends after the set time (this function can be implemented by designing a delay instruction). This control method is slightly less efficient but simplifies the control and corresponding hardware circuitry.

[0251] In an exemplary embodiment of this disclosure, the software code decoded by the instruction decoding circuit further includes a loop start instruction and a loop end instruction. The loop start instruction includes an operand representing the number of loop iterations. The first cache allocation instruction is located before the loop start instruction, and the multiple sets of scheduling instructions are located between the loop start instruction and the loop end instruction.

[0252] The instruction execution circuit responds to the decoded software code by performing multiple loop processes, controlling the multiple operators to complete the processing of the data to be processed in a pipeline manner according to a set connection order; each loop process includes multiple time steps, and each operator completes one processing of a data block in the data to be processed in one time step.

[0253] The instructions for looping and scheduling in this embodiment can be an example of loop-related instructions shown in pseudocode above. They can also be modified; for example, the loop start instruction (Lp_start_q0), loop end instruction (lp_end_q0), and start instruction (Start_eng_q0) remain unchanged, but the synchronization instruction (sync_q0) is updated to a delay instruction (delay_q0), and the operand of the delay instruction can be set to the delay time.

[0254] In an exemplary embodiment of this disclosure, the loop start instruction and the loop end instruction include M sets of scheduling instructions, and each loop process includes M time steps, M = m1 + m2 - 1, where m1 is the number of the plurality of operators, m2 is the number of data blocks processed in each loop, m1 ≥ 2, m2 ≥ 2;

[0255] When m < m1, the activation operator for the m-th time step is the first to the m-th operator, where m = 1, 2, ..., M;

[0256] When m1≤m≤m2, the activation operator at the m-th time step is any one of the plurality of operators;

[0257] When m2 < m ≤ M, the activation operator for the m-th time step is the (m-m2+1)-m1 operator;

[0258] Among them, the operator to be started in the start instruction of the m-th group of scheduling instructions is the activation operator of the m-th time step.

[0259] This embodiment can be found in the detailed description above.

[0260] In an exemplary embodiment of this disclosure, the first cache allocation instruction includes a write register instruction and N' write data instructions associated with the write register instruction, wherein the write register instruction is associated with a total of N write data instructions, wherein:

[0261] The write register instruction includes: an opcode, a second operand representing the register address Add, and an operand representing the number of immediate values ​​N, where N ≥ N' ≥ 2;

[0262] The write data instruction includes an opcode and an immediate value. The first operand includes N' immediate values ​​from the N' write data instructions. The N' immediate values ​​from the N' write data instructions include information about the row position, row number, column position, and column number of the cache allocated to the operator.

[0263] The instruction execution circuit writes the first operand in each first cache allocation instruction into the storage space indicated by the second operand in the cache allocation instruction, including: for each of the N' write data instructions, writing the immediate value of the instruction into a register at address Add+n-1 for the operator to read, where n is the sequence number of the instruction in the N write data instructions, indicating that the instruction is the nth instruction under the write register instruction, and 1≤n≤N.

[0264] This embodiment can also use an example of the first cache allocation instruction represented by pseudocode above:

[0265] For detailed explanation, please refer to the aforementioned embodiments, where Wr_que0[0xb00],29 is a write register instruction, and the other instructions are write data instructions. An operator usually needs to configure other parameters besides the cache, and the configuration of these other parameters can also be accomplished through write data instructions. Therefore, the write data instructions for implementing cache allocation mentioned above do not necessarily follow the write register instruction immediately; they can also be separated from the write register instruction by one or more other write data instructions.

[0266] In one example of this embodiment, the N' immediate values ​​in the N' write data instructions also include the number K of caches used by the operator in multiple loops, to instruct the operator to update the row or column position of the allocated cache step by step with a period of K time steps, so that the operator uses different caches in the K time steps of the same period and the same cache in the k-th time step of different periods, k = 0, 1, ..., K-1, K ≥ 2.

[0267] An example of this embodiment is as follows:

[0268] Wdat 3 / / CFG_SVA_BBUF_PPG_NUM

[0269] The instruction has been explained in detail above using the SVA operator as an example, so it will not be repeated here.

[0270] In an exemplary embodiment of this disclosure, the software code decoded by the instruction decoding circuit further includes a second cache allocation instruction located between two adjacent sets of scheduling instructions. The second cache allocation instruction includes: a first operand for indicating the location of the cache to be reallocated for the operator in the next time step; and a second operand for indicating the storage space to be written to by the first operand.

[0271] The instruction execution circuit is further configured to, in response to each decoded second cache allocation instruction, write the first operand therein to the storage space indicated by the second operand therein, so as to allocate a cache for the operator using the storage space to use in the next time step; wherein the caches allocated for the plurality of operators to use in the same time step are located in different and independently accessible regions in the shared cache pool, and for adjacent operators among the plurality of operators, the output cache allocated for the preceding operator to use in the current time step is the input cache allocated for the following operator to use in the next time step.

[0272] This embodiment uses a second buffer allocation instruction between two sets of scheduling instructions to reallocate buffers for operators. This allows operators to switch between multiple buffers, staggering the output buffer used by the operator at the same time step with the input buffer used by the operator at the next time step. This enables two operators to process data in parallel (including reading and writing data), thus working in a pipelined manner to improve efficiency. The two sets of scheduling instructions in this embodiment can be located in different loop processes.

[0273] In one example of this embodiment, among the multiple sets of scheduling instructions, the second cache allocation instruction between two adjacent sets of scheduling instructions is used to reallocate the cache position for each operator that performed processing in the previous time step and still needs to perform processing in the next time step; for each of the multiple operators, starting from the time step when the operator is first started, with a period of K time steps, the cache allocated by the instruction execution circuit for the operator in the K time steps of the same period is different, and the cache allocated for the operator in the k-th time step of different periods is the same, k = 0, 1, ..., K-1, K ≥ 2.

[0274] In an exemplary embodiment of this disclosure, the second cache allocation instruction includes a write register instruction and M write data instructions associated with the write register instruction, where M ≥ 1, wherein:

[0275] The write register instruction includes: an opcode, a second operand representing the register address Add', and an operand representing the number of immediate values ​​M;

[0276] The write data instruction includes an opcode and an immediate value. The first operand includes M immediate values ​​from the M write data instructions. The M immediate values ​​from the M write data instructions include information about the row or column position of the cache reallocated for the operator.

[0277] The instruction execution circuit responds to each second cache allocation instruction by writing the first operand therein into the storage space indicated by the second operand therein, including: for each of the M write data instructions, writing the immediate value therein into a register at address Add'+m-1 for the operator to read, where m is the sequence number of the instruction in the M write data instructions, indicating that the instruction is the m-th instruction under the write register instruction, and 1≥m≤M.

[0278] An example of a second cache allocation instruction (M=1) is as follows:

[0279] Wr_que0 [0xb00],0

[0280] Wdat 32 / / CFG_SVA_INP_BBUF_COL_OFFSET

[0281] The example has been explained in detail above, so it will not be repeated here.

[0282] In an exemplary embodiment of this disclosure, the data to be processed is a frame of data obtained by the radar system processing the received radar signal; the plurality of operators are operators in the 1D-FFT processing stage, and one data block in the data to be processed is data obtained by processing a chirp signal received on a channel; or, the plurality of operators are operators in the 2D-FFT processing stage, and one data block in the data to be processed is data at the same range gate in the 1D-FFT data. Similar to the foregoing embodiments, when the control device of this disclosure is applied to a radar system, it can use a frame of data as the dataset to be processed in a set of multiple loops.

[0283] This disclosure also provides a multi-operator control method (to distinguish it from the control method shown in FIG10, the control method of this embodiment can be called a second control method), applied to a hardware accelerator, the hardware accelerator including a hardware scheduler, a specified number of operators and a shared cache pool, as shown in FIG19, the control method including:

[0284] Step 200: Allocate caches from the shared cache pool for the multiple operators to be used when accessing data, so as to form a data channel between the multiple operators. The allocated caches include input caches and / or output caches.

[0285] Step 201: By scheduling time steps, the multiple operators are started sequentially according to the set connection order to complete the processing of the data to be processed.

[0286] Among the plurality of operators, the output buffer used by the preceding operator at the current time step is the input buffer used by the following operator at the next time step.

[0287] This embodiment allocates caches to multiple operators from a shared cache pool, enabling data transfer between operators through the cache. This achieves soft connections (configurable connections) and rapid data interaction between operators. Furthermore, through time-step scheduling, the multiple operators can be started sequentially according to a set connection order to complete the processing of the data to be processed, ensuring processing efficiency. The connection relationship between operators can be changed according to application needs, improving the application flexibility of hardware accelerators using multiple operators.

[0288] In an exemplary embodiment of this disclosure, the allocation of caches from the shared cache pool for data access by the plurality of operators includes: allocating caches from the shared cache pool for the plurality of operators for the first processing; wherein, for adjacent operators among the plurality of operators, the output cache allocated for the first processing by the preceding operator is the same as the input cache allocated for the first processing by the subsequent operator. In another embodiment, the initially allocated caches can be used throughout the entire computation task performed by the operator. As previously described, further details will not be repeated.

[0289] In an exemplary embodiment of this disclosure, the step of scheduling multiple operators sequentially according to a set connection order to process the data to be processed by time-step scheduling includes: performing multiple loop control to control the multiple operators to process multiple data blocks in the data to be processed in a pipeline manner according to the set connection order; each loop process includes multiple time steps, and each operator completes one processing of one data block in the data to be processed in one time step. The caches allocated to the multiple operators for use in the same time step are located in different and independently accessible areas of the shared cache pool; and for adjacent operators among the multiple operators, the output cache allocated to the preceding operator for use in the current time step is the input cache allocated to the following operator for use in the next time step. This embodiment, through multiple loop control combined with cache allocation, can avoid access conflicts between multiple operators.

[0290] In an exemplary embodiment of this disclosure, each loop process includes M time steps, M = m1 + m2 - 1, where m1 is the number of the plurality of operators, m2 is the number of data blocks processed in each loop, m1 ≥ 2, m2 ≥ 2;

[0291] In each cycle:

[0292] When m < m1, the activation operator for the m-th time step is the first to the m-th operator, where m = 1, 2, ..., M;

[0293] When m1≤m≤m2, the activation operator at the m-th time step is any one of the plurality of operators;

[0294] When m2 < m ≤ M, the activation operator for the m-th time step is the m-m2+1 to m1-th operators.

[0295] This embodiment can be referred to in the related embodiments above.

[0296] In an exemplary embodiment of this disclosure, the method further includes: allocating a number K of buffers to the plurality of operators for use in the multiple loops, to instruct the operators to update the position of the allocated buffers step by step over a period of K time steps, so that the operators use different buffers in the K time steps of the same period, and use the same buffer in the k-th time step of different periods, where k = 0, 1, ..., K-1, K ≥ 2. This embodiment configures the number K of buffers for the operators, enabling switching between K pairs of buffers on the operator side to avoid conflicts. In one example, this number K can be the number of receiving channels of the radar system.

[0297] In an exemplary embodiment of this disclosure, the allocation of caches for data access by the plurality of operators from the shared cache pool includes: reallocating caches for operators that process data in both the previous and next time steps between two adjacent time steps; wherein, for each of the plurality of operators, there are K groups of caches allocated and reallocated for that operator during the multiple loops, where K ≥ 2, and each group includes an input cache and / or an output cache; starting from the first processing of the operator, with a period of K time steps, the operator uses the same cache in the k-th time step of different periods, and uses different caches in different time steps of the same period, k = 0, 1, ..., K-1. This embodiment reallocates caches through instructions, eliminating the need for operators to design circuits to update cache information, thus simplifying hardware design.

[0298] In an exemplary embodiment of this disclosure, the data to be processed is a frame of data obtained by the radar system processing the received radar signal; the plurality of operators are operators in the 1D-FFT processing stage, and a data block in the data to be processed is data obtained by processing a chirp signal received on a channel; or, the plurality of operators are operators in the 2D-FFT processing stage, and a data block in the data to be processed is data at the same range gate in the 1D-FFT data.

[0299] One embodiment of this disclosure provides a second hardware scheduler, including a control device and an internal memory, wherein the control device includes the second control device described in any embodiment of this disclosure, and the internal memory is configured to store software code to be decoded and executed by the control device, as shown in FIG17.

[0300] This disclosure also provides a hardware accelerator, including a hardware scheduler, a specified plurality of operators, a shared cache pool providing cache space for the operators, and a register set, wherein:

[0301] The hardware scheduler adopts the second hardware scheduler described in any embodiment of this disclosure, wherein the cache information allocated to each operator is saved in the register group, and the processed data is stored in external memory;

[0302] The register group is configured to store configuration information for the plurality of operators, the configuration information including information on the cache allocated to the operators;

[0303] The plurality of operators are configured to, upon startup, obtain information about the cache allocated to the operator from the register group; if an input cache is allocated, read the data block to be processed from the input cache and process it; and if an output cache is allocated, write the processed data into the output cache.

[0304] The structure of the hardware accelerator in this embodiment can be seen in Figure 7.

[0305] In an exemplary embodiment of this disclosure, the operator includes:

[0306] The data reading unit is configured to acquire information about the input buffer allocated to the operator, and based on the information about the input buffer, sequentially read out the data blocks in the input buffer and input them into the processing unit;

[0307] The processing unit is configured to process the data block to obtain a processed data block;

[0308] The write data unit is configured to obtain information about the output buffer allocated to the operator, and write the processed data block into the output buffer based on the information about the buffer.

[0309] The scheduling interface is configured to receive a start signal and use it as a trigger signal to begin processing this operator.

[0310] The synchronization interface is configured to send a signal indicating that the processing is complete after the write data unit writes the processed data block into the output buffer.

[0311] The structure of the operator in this embodiment can be seen in Figure 18.

[0312] In one example of this embodiment:

[0313] The read data unit retrieves information about the input buffer allocated to the operator from the register group, and the write data unit retrieves information about the output buffer allocated to the operator from the register group.

[0314] The operator also includes a cache update unit;

[0315] The cache update unit is configured to: read from the register group the location and size of the cache initially allocated to the operator, and the number K of caches allocated to the operator, where K ≥ 2; and cyclically count the number of times the scheduling interface receives the start signal, starting a new cycle after the accumulated count reaches K times in each cycle, and when the accumulated count in each cycle is k times, calculate the location of the cache used by the operator in the next time step based on the location and size of the initially allocated cache and the value of k, and update the cache location in the register group to the calculated cache location; where k = 0, 1, ..., K-1, and the calculated cache location is different when the value of k is different.

[0316] In an exemplary embodiment of this disclosure,

[0317] The plurality of operators sequentially include: CQMD operator, FFT operator, and SVA operator; or

[0318] The plurality of operators sequentially include: DC operator, FFT operator, and SVA operator; or

[0319] The plurality of operators sequentially include: CMB operator, STAS operator, HIST operator, CFAR operator, and STAS operator; or

[0320] The plurality of operators include, in sequence: DC operator, FFT operator, SVA operator, and CMB operator.

[0321] One embodiment of this disclosure also provides a computing system, including a processor, memory, and a hardware accelerator, wherein:

[0322] The processor is configured to load the data to be processed stored in the memory into the hardware accelerator;

[0323] The memory is configured to store data to be processed, and to store data obtained by the hardware accelerator after processing the data to be processed.

[0324] The hardware accelerator employs the hardware accelerator described in any of the disclosed embodiments.

[0325] In an exemplary embodiment of this disclosure, the computing system is a system-on-a-chip, which is a millimeter-wave chip or sensor chip in a radar system.

[0326] One embodiment of this disclosure also provides an automated method for generating operating instructions based on a Radar digital signal processing hardware accelerator.

[0327] The main function of radar digital signal processing is to convert millimeter-wave echo signals from the time domain to the frequency domain using Fast Fourier Transform (FFT) to obtain the energy distribution of the spectrum. Then, noise is removed and suppressed according to algorithms to identify the target and obtain its range, velocity, and angle information. Radar digital signal processing applications vary depending on performance, cost, and application flexibility requirements, resulting in different engineering implementations. These can be broadly categorized as follows:

[0328] First, processing radar digital signals through the CPU is mainly used in scenarios where performance is not critical and development flexibility is high.

[0329] Secondly, radar digital signal processing is performed through the chip's internal DSP, which is mainly used in scenarios with certain processing performance requirements, low cost sensitivity, and a certain degree of development flexibility.

[0330] Third, hardware acceleration: radar digital signal processing is performed through dedicated ASIC circuits, mainly used in application scenarios with high processing performance requirements, high cost sensitivity, and low development flexibility.

[0331] The first and second radar digital signal processing (software processing) solutions offer relatively flexible development. Each node in the processing flow can interact extensively with the CPU or upper-layer applications. However, this requires strong computing power from the DSP / CPU and a high-speed data communication interface between the upper-layer application and the digital signal processing unit. This significantly increases system application costs, and compared to hardware acceleration solutions, the processing speed is slower and power consumption is higher. Future evolution will face challenges due to long DSP and F / W development cycles, making it difficult to meet the high-performance and real-time processing requirements of ADAS.

[0332] The third hardware solution can adapt to different application scenarios by simply configuring the registers of the radar signal processing module, and also by simply configuring the data address of the radar signal processing module. However, the development methods in the field of software development (F / W) are limited, only allowing for simple register and input / output address configuration of the custom logic and DSP; the interaction direction and processing order between data in the radar signal processing module are relatively simple and cannot be optimized through software development or iterative F / W.

[0333] This disclosure proposes an automated method for generating operating instructions for a radar digital signal processing hardware accelerator. It adopts a new software and hardware interaction method, which can define radar-specific micro-instructions, such as 32-bit short instructions. Users can define different instruction sets according to their needs to develop different applications. This not only solves the problem of limited development flexibility of hardware acceleration solutions, but also has the characteristics of high-performance processing, because in actual operation, all instruction sets and data streams are processed through ASIC dedicated circuits.

[0334] Before using the automated generation method of this disclosure, the operators to be designed in the hardware accelerator for radar signals can be determined first. To this end, the hardware required for radar signal processing can be broken down into multiple subdivided operators (engines). Each engine serves as an independent basic radar signal processing function and can be controlled and scheduled by a hardware scheduler. The hardware scheduler can configure registers, read registers, start engines, and synchronize engine operations via instructions. For example, the smallest computational units can be identified based on the computational characteristics required by the radar application, serving as operators in the hardware accelerator, such as FFT, complex multiplication, complex addition, complex subtraction, and real number comparators, to meet possible combination requirements.

[0335] The time between the start and completion of operator execution (improving hardware execution efficiency based on operator processing capabilities). For example, if a computational task is implemented by multiple operators, these operators may work simultaneously at any given moment. When splitting operators, it's also necessary to consider that the amount of data each operator needs to process should be roughly the same within a given time period. If the processing capabilities of these operators are roughly equivalent, they can complete data processing almost simultaneously within this time period, ensuring the highest efficiency of the multiple computing engines. Furthermore, the granularity of operator data interaction and the number of cycles are defined according to different application scenarios. This is related to the number of operators required by the application scenario; more operators require deeper operator splitting and caching.

[0336] After identifying multiple operators, application designers or instruction designers often encounter the following typical problems when they need to call the operators through software:

[0337] The allocation of caches used for data interaction between different operators, including the caches required for input and output data, the size of the caches, etc.

[0338] Synchronization of control commands for data interaction between different operators, including synchronization of start execution and completion commands, to ensure the accuracy of data interaction.

[0339] The foregoing embodiments of this disclosure have proposed solutions for operator cache allocation and scheduling. This embodiment also needs to provide a code generation method and a code generation device to generate software code for hardware accelerator operation. Through software code containing instructions for cache allocation and scheduling, efficient cache allocation and scheduling can be achieved.

[0340] The structure of the computing system to which the software code generated by the method of this embodiment is to be applied is shown in Figure 7, as described in the detailed description of the computing system above.

[0341] The scheduling of each basic radar signal processing function will be controlled by a hardware scheduler. The hardware scheduler supports the sequential scheduling and control of basic radar signal processing functions by executing a piece of software-generated instructions (i.e., the software code mentioned above) according to application requirements.

[0342] Users can define instruction sets to support not only the definition of radar algorithm parameters and calibration for different application scenarios, but also the definition of data flow between hardware acceleration modules, including the computation and data interaction of general-purpose processors (such as DSPs, CPUs, DPUs, and APUs) interspersed within ASIC hardware modules.

[0343] Based on the radar digital signal processing hardware and software architecture, this paper proposes a development tool based on the radar signal processing instruction set and a corresponding automated method for generating software code that can run on hardware accelerators. Users only need to define the data flow relationships between radar digital signal processors visually, and enable / disable / enable key radar signal processing features and calibration parameters to generate a set of hardware scheduling instructions that meet user requirements. For example, a chip may have N engines, but in some applications, only the functionality of M engines (M < N) may be used. Therefore, it can be understood that in a radar signal processing flow, only M key features need to be enabled, and NM engines are disabled in that application.

[0344] This instruction set development tool can address the following issues based on user-defined engine data flow rules:

[0345] Constraints on Engine data interaction size

[0346] Constraining Engine cache allocation conflicts and time-sharing rules

[0347] Constraint Engine Parallel Maximum Processing Problem

[0348] The connection relationship and synchronization issues of Engine data before and after constraints.

[0349] Based on user-defined exemplary application scenarios, the following conditions can be determined:

[0350] I. Determine the number, type, and processing order of the engines used in the data flow.

[0351] II. Determine the configuration register values ​​for each engine based on application requirements.

[0352] Based on the above application requirements, the methods to solve the problems raised above are as follows:

[0353] 1. Engine interaction data size:

[0354] Each engine can uniquely determine the size of the input data, parameters, and output results and the minimum parallelism required for a single run based on the configuration register value (each operator has a startup synchronization configuration; one startup and one synchronization constitute a single run, which is at the operator level). When enabling the engine, a cache of the corresponding size and the minimum parallelism need to be allocated.

[0355] Generally, each operator has parallel requirements for data input and output based on its characteristics, which is the minimum degree of parallelism. The maximum parallel processing of operators is generally between operators, that is, the number of operators being calculated simultaneously at the same time.

[0356] 1. Engine cache allocation conflict:

[0357] In the application process, each engine needs to be allocated physical cache for its input data (some operators' inputs are raw data moved from external storage), parameters, and output results. Depending on the data transfer method between engines, the cache size required by each engine, and the timing of data transfer, the output cache of a preceding engine can serve as the input cache for a subsequent engine. Allocation can be based on the total cache size required by all engines in the entire data stream, combined with the overall physical cache size, to determine if the chip can support the current application's data stream. Generally, a scenario where the total cache size required by all engines exceeds the chip's maximum cache size is considered unsupported.

[0358] In addition to considering cache size, we can also analyze whether the maximum number of parallelisms supported by the chip cache can meet the needs of all engines in the data flow. Parallelism is another dimension to consider besides size.

[0359] 2. Maximum Parallelism Problem in Engines:

[0360] The number of hardware accelerators for a dedicated algorithm is usually determined during the chip design process. When a user proposes an application scenario, it is necessary to analyze the capabilities of each stage (time step) of the data stream. If at least one stage requires repeated iterative calculations or multiple operations, multiple engines are needed for parallel processing to ensure the overall data processing capability.

[0361] For example, if a stage requires two iterations, three operators of the same type can be set up and connected end-to-end to increase parallelism. This depends on whether there are multiple operators of the same type in the hardware design. If so, it's possible, such as ccmb; otherwise, it can only be time-sharing via instructions.

[0362] For example, if a stage requires an operator to compute multiple data blocks before starting the next level operator, then multiple operators of the same type can be set up to compute the data blocks in parallel.

[0363] The instruction set generation scheme needs to consider the number of existing engines of the same type in the chip, and analyze the maximum parallelism of the nodes in combination with the processing capabilities of the engines to ensure the efficiency and legal application of the engines.

[0364] 3. Engine data connection and synchronization issues:

[0365] Data transfer between engines can be either sequential or loopback. Sequential transfer can be further divided into starting a single or multiple times, with the output of the higher-level engine serving as the smallest unit of input for the lower-level engine. Loopback can be divided into switching back across a single engine and switching back across multiple engines. These controls are defined by the instruction set. Some operators require multiple results before starting the next operator, while others only require one. This is an application requirement and is defined by the application developer through instructions.

[0366] One embodiment of this disclosure provides a code generation method, as shown in FIG20, for generating software code that runs on a hardware accelerator. The method includes:

[0367] Step 300: Display the interactive interface of the code generation device and receive the input configuration information through the interactive interface;

[0368] The configuration information includes: information about a plurality of specified operators, information about the connection order set for the plurality of operators, and information about the caches allocated to the plurality of operators respectively; the plurality of operators are some or all of the operators possessed by the hardware accelerator;

[0369] Step 302: Automatically generate software code that runs on the hardware accelerator based on the configuration information.

[0370] The method of this embodiment can be applied to a code generation device (such as a software code development platform), which generates software code (also referred to as code, code segment, instruction set, etc.) used by a hardware accelerator. In this embodiment, for a computing task (corresponding to a specific application scenario), a set of software code can be generated by a code generation device (also referred to as an instruction generation tool) and executed by a hardware scheduler. This can achieve the allocation of caches for operators and the scheduling of operators as in other embodiments of this disclosure.

[0371] This embodiment applies to a software code development platform that supports specifying multiple operators. This does not mean that the development platform does not support specifying a single operator; it simply means that the method in this embodiment focuses on the case of multiple operators.

[0372] The configuration interface in this embodiment can be the SDK (Software Development Kit) platform interface. Through parameter configuration, the software code used by the underlying controller for scheduling can be automatically generated.

[0373] The software code generated in this embodiment can be assembly language code, which, after being compiled into binary code, can be decoded and executed by the hardware scheduler in the hardware accelerator. The pseudocode mentioned above in this application does not need to be the actual generated software code; it is simply used to more conveniently illustrate the software code. The generated software code can be loaded into the hardware scheduler in various ways, as shown in Figure 17 and its description.

[0374] One embodiment of this disclosure, taking a hardware accelerator in a radar system as an example, proposes a method for generating software code for radar signal processing, which enables the application of mining chips to achieve extreme flexibility and performance. The generation method includes:

[0375] Step 1: Display the interactive interface and receive configuration information input by the user through the interactive interface;

[0376] The interactive interface offers several configuration options. Users need to set different types of parameters according to their specific radar digital signal processing application requirements. These configurations include:

[0377] ●Radar application parameter configuration: Basic radar parameter configuration is completed through the user interface, including but not limited to the following aspects:

[0378] ADC sampling frequency

[0379] FMCW waveform

[0380] Number of Chirps per Frame

[0381] Number of receiving antennas

[0382] Number of transmitting antennas

[0383] The basic parameters of the above configuration can be used as engine configuration information and are also related to the size of the cache, which may affect the allocation of the cache.

[0384] ●The engine used in the Radar processing flow:

[0385] RSP hardware accelerators can support commonly used radar digital signal processing engines, including but not limited to:

[0386] Multi-point FFT

[0387] ADC interference detection

[0388] SVA operation

[0389] DC estimate

[0390] Multi-channel parallel complex multiply-accumulate arithmetic unit

[0391] Multi-channel parallel real number multiply-accumulate arithmetic unit

[0392] Peak search

[0393] Commonly used angle resolution (DML) algorithms

[0394] In the radar processing flow setup process, users can define the data flow of the supported engines through a visual interface. This flow includes not only the number of engines used, but also the order of data flow between the engines. Once defined, users can implement the signal processing flow required for radar applications.

[0395] During this configuration process, users can also define the interaction between the external general-purpose processor and the internal engine of the hardware accelerator according to their needs. This data interaction can be performed through the memory shown in Figure 7. The external general-purpose processor includes, but is not limited to, CPUs, DSPs, and DPUs. For example, the hardware scheduler can use DMA to move data processed by the hardware accelerator to memory and notify the CPU; after the CPU completes the calculation of the data moved to memory, it notifies the hardware scheduler to continue subsequent calculations. The CPU can control the interaction between the general-purpose processor and the hardware accelerator any number of times. It is ensured that the hardware accelerator's subsequent data processing is restarted only after the general-purpose processor calculates and updates the relevant RSP_MEM.

[0396] ●Radar-processed data and parameters

[0397] This step mainly defines the types of data that each operator needs to process. The data to be processed includes input data, processed data, and parameters. This information can be used to determine the layout of the operator's output cache, the output cache, and the cache used by the parameters in the shared cache pool, such as position and size.

[0398] Data types may include:

[0399] 1. Data and parameters to be processed (parameters are generally those obtained from calibration, such as angle resolution direction weight parameters), such as:

[0400] ADC data

[0401] FFT processes data

[0402] FFT windowing coefficient

[0403] Peak Search Raw Data

[0404] The direction parameter of Peak search

[0405] DoA antenna calibration parameters

[0406] Complex numbers, real numbers multiplied and added raw data, tffu (raw FFT data)

[0407] Second, the data obtained after processing (i.e., the processing result):

[0408] Interference detection results

[0409] FFT Results - This section may include multidimensional FFT processing results.

[0410] Peak search results

[0411] Raw data from the FFT after Peak search.

[0412] DoA angle result (DoA angle determined after processing)

[0413] Complex numbers, results of multiplication and addition of real numbers

[0414] The processing result here is the result obtained after the hardware accelerator completes the computing task.

[0415] ● Allocate cache and adjust operators

[0416] After the user flow is defined, data interaction between engines throughout the flow is achieved through a cache, which is an area invisible to the user. The code generation device determines and displays the size and / or location of the default cache allocated to each operator based on the application parameters, processing flow, and cache allocation configuration information configured by the user in advance. Users can also adjust the size and / or location of the default cache according to their needs to ensure efficient cache application. When the user makes adjustments, instructions for allocating cache to each operator are generated based on the adjusted cache size and location. At this stage, the physical space allocation of RSP-cache is defined according to the cache physical space description method defined internally by RSP, using parameters such as row, column, offset, bank, and pingpong group (i.e., the number of caches mentioned above) to achieve efficient application of engines and cache.

[0417] ● Operator enabling and characteristic parameters:

[0418] Primarily targeting the algorithm features supported within the engine, this allows users to enable algorithms and configure parameters for a single engine, and can be simply divided into:

[0419] FFT:

[0420] Real number input and complex number input configuration

[0421] Adding a window enables opening and closing.

[0422] …

[0423] Peak Search:

[0424] Peak search algorithm: CA / OS / SO / GO

[0425] Peak search coefficient

[0426] Peak search reference window and mask

[0427] …

[0428] DoA:

[0429] Deconstruction angle grouping method

[0430] Solution angle accuracy

[0431] resolution

[0432] Step two: Based on the configuration information entered by the user through the interactive interface, generate the software code used by the hardware accelerator (the software code that the hardware scheduler decodes and executes).

[0433] After the user configures the above parameters according to application requirements, the code generation device can automatically generate software code (such as binary code) supported by the RSP hardware accelerator. Before generating instructions, the code generation device will check the validity of the user's configuration. If the user's configuration is not supported in any of the following aspects, the code generation device will provide a prompt and suggest that the user make targeted modifications:

[0434] Application parameters not supported by RSP

[0435] RSP_MEM out of bounds

[0436] RSP_CACHE cannot be allocated

[0437] The Engine algorithm does not support...

[0438] …

[0439] F / W Program Instructions and Chip Execution

[0440] The software code output by the code generation device can be loaded into memory or cache accessible by the hardware accelerator, thus enabling interaction with the data and control plane of the hardware accelerator.

[0441] The software code generated by the embodiments of this disclosure can be applied to the hardware accelerator of any of the foregoing embodiments to decode and execute the hardware scheduler therein, thereby realizing functions such as scheduling and cache allocation of specified multiple operators.

[0442] This disclosure proposes a hardware-software interaction mechanism for a radar digital signal processing (RSC) hardware accelerator, and, based on this mechanism and considering the characteristics of RSC applications, provides users with a user-friendly, visualized, customized, and usable method and tools for the hardware accelerator. Based on this, various RSC hardware-software interaction methods can be derived, including but not limited to: Radar digital signal processor-based hardware acceleration units; configuration, cache allocation, and time-sharing scheduling of hardware acceleration units using binary code scheduling; SDK application interfaces for automatically generating software code, interaction methods, and validity checks; and interaction and control methods between general-purpose processors and dedicated hardware accelerators, etc.

[0443] Based on the embodiments of this disclosure, users can not only support the definition and calibration of radar algorithm parameters for different application scenarios through the defined instruction set, but also define the data flow between engines through the instruction set, including the calculation and data interaction of general-purpose processors (including DSP, CPU, DPU, APU, etc.) interspersed in the ASIC hardware module, and can support operators.

[0444] Based on the embodiments of this disclosure, after the user inputs and configures some parameters through the interactive interface, pseudocode can be automatically generated. The pseudocode can then be converted into a single 32-bit binary code using a script and provided to the hardware accelerator.

[0445] The instructions generated by the code generation method of this disclosure can be of the types listed in the table below:

[0446] in:

[0447] The function of Reg_load is to write data to a general-purpose register, and its exemplary format is as follows:

[0448] The above shows the bit allocation corresponding to the reg_load instruction, where bit[31:28] represents the instruction ID; bit

[0027] is used to distinguish the instruction sent to different instruction queues for execution; bit[26:25] is used to select the source of the general-purpose register value, 0 indicates that the value corresponding to address bit[19:0] is written to the general-purpose register, 1 indicates that the immediate value is written to the general-purpose register, and 2 indicates that the address exists in another general-purpose register, the data at the corresponding address is read according to the value of the other general-purpose register, and then the read data is written to the current general-purpose register; bit

[0024] is used to select whether the immediate value is written to the high or low 16 bits of the general-purpose register; bit[23:20] represents the index of the current general-purpose register; bit[19:0] represents the address, the immediate value, or the index of another general-purpose register.

[0449] `reg_write` writes a value to the register corresponding to an address; `reg_load` writes a value or the value of the register corresponding to an address to a general-purpose register.

[0450] The function of reg_read is to read the value of the register corresponding to an address. There are multiple types of operator processing results. The data after operator processing includes two types: one is the data obtained by calculation on the input data, which can be stored in the output buffer; the other is the statistical result of the input data, which is smaller in size, such as the number of valid targets. This statistical result can be stored in a result register, which is usually 32 bits. In this case, the application can obtain these statistical results by reading the register.

[0451] The operand event_idx in the wait instruction can be configured from 0 to 7. When the wait instruction is executed, seq will stop and will not continue to execute subsequent instructions. Only when the CPU configuration ctl_seq_event_set and event_idx are consistent will seq continue to execute subsequent instructions.

[0452] An example of the delay instruction is delay 0x3, which means that the execution of the next instruction will continue after a delay of 3 cycles.

[0453] The pc_clear command is used when the pc (program counter) value needs to be incremented starting from 0.

[0454] General-purpose registers can cache intermediate results or perform simple mathematical operations. After the operation is completed, the value can be assigned to a register corresponding to a given address. This can be achieved using the `reg_store` instruction.

[0455] The rf_op instruction can perform simple calculations on intermediate results during instruction execution and then allocate them to a register.

[0456] The `start_engine` directive is used to start one or more operators, and its exemplary format is shown in the table below:

[0457] Bits [31:28] represent the op_code of the instruction; the hardware scheduler has two instruction queues, and bit

[0027] is used to distinguish whether the instruction is executed in the different instruction queues; bits [26:20] are not currently used, but can be used to expand the number of operators if the number of operators increases; bits [19:0] are a total of 20 bits, corresponding to a maximum of 20 operators, such as fft, cfar, etc. The pseudocode example corresponding to this instruction is as follows:

[0458] start_eng_qn fft

[0459] start_eng_qn fft+cfar.

[0460] The `start_engine` instruction can start a single operator, as in the first pseudocode, or multiple operators simultaneously, as in the second pseudocode. After the pseudocode is written, a script will convert it into binary code instructions that the hardware scheduler can parse. When the hardware scheduler executes this instruction, it sends a start signal to the corresponding operator based on bits [19:0]. This start signal is high for only one clock cycle. When the operator receives the start signal, it will begin working according to the configured register information. This register information includes the range of values ​​the operator can access, such as `col_offset`, `col_size`, `row_offset`, `row_size`, etc. These registers can be configured before the `start_engine` instruction using the `reg_write` instruction, as shown in the following figure:

[0461] The `sync` instruction is used by the instruction scheduler to check whether the corresponding operator has completed its task. If it has, the hardware scheduler continues executing subsequent instructions; otherwise, it waits for the corresponding operator to complete its task. An example format is as follows:

[0462] In the table above, bits [31:28] represent the op_code of the sync instruction, bit

[0027] is used to distinguish whether the instruction is executed in different instruction queues, bits [26:20] are temporarily reserved like the start_eng instruction and can be used for subsequent expansion, and bits [19:0] correspond to a maximum of 20 operators like the start_eng instruction. The pseudocode example for this instruction is as follows:

[0463] sync_qn fft

[0464] sync_qn fft+cfar

[0465] The `sync` instruction can check whether a single operator has completed its work, as shown in the first pseudocode, or it can check whether multiple operators have completed their work, as shown in the second pseudocode. When an operator completes its work, it sends a clock cycle high-level "done" signal to the hardware scheduler. After receiving the "done" signal, `seq` considers that the operator has entered the idle state. When all operators corresponding to bits [19:0] have entered the idle state, the `sync` instruction ends, and the hardware scheduler continues to execute subsequent instructions.

[0466] The generated 32-bit software code (short instruction set) can be considered as firmware stored in the chip. Configuration data has been written to the radar signal processing registers, and the configuration data required for each engine's operation has been configured in the engine's internal registers. This means that the hardware acceleration chip implementing function A has been customized and is ready to run. During chip startup, the on-chip CPU and hardware scheduler (SEQ) each start independently. The 32-bit short instructions are sequentially written to the internal memory (instruction queue 0 or 1) in the SEQ. The controllers in the SEQ retrieve the 32-bit short instructions from their respective queues, decode them, determine their functions, and then execute the corresponding instructions.

[0467] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0468] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0469] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly defined.

[0470] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0471] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A control device, wherein, The control device is used to control a plurality of specified operators configured to process data to be processed according to a set connection order. The control device includes: An instruction decoding circuit is configured to decode software code, the software code including a plurality of first cache allocation instructions, each first cache allocation instruction including: a first operand, used to indicate the location and size of the cache allocated for the operator; and a second operand, used to indicate the storage space to be written to the first operand; The instruction execution circuit, coupled to the instruction decoding circuit, is configured to, in response to a plurality of decoded first cache allocation instructions, write a first operand in each first cache allocation instruction into the storage space indicated by a second operand in the cache allocation instruction, so as to allocate caches for the plurality of operators to use when accessing data. The caches allocated to the multiple operators are all from a shared cache pool.

2. The control device according to claim 1, wherein, The first operand in the first cache allocation instruction is used to indicate the location and size of the cache initially allocated to the operator. The cache initially allocated to the operator is the cache used when the operator performs its first processing. The cache includes an input cache and / or an output cache. The multiple operators are started sequentially according to a set connection order. For adjacent operators among the multiple operators, the output buffer initially allocated to the preceding operator is the same as the input buffer initially allocated to the following operator.

3. The control device according to claim 1 or 2, wherein, The software code contains short instructions of 16 bits, 32 bits, or 64 bits.

4. The control device according to claim 2, wherein, The software code decoded by the instruction decoding circuit also includes multiple sets of scheduling instructions; The instruction execution circuit is further configured to schedule one or more operators in response to each decoded set of scheduling instructions, such that the scheduled operators start and complete one processing of a data block in a time step; wherein each time step begins when a set of scheduling instructions is executed and ends when the execution of that set of scheduling instructions ends.

5. The control device according to claim 4, wherein, The software code decoded by the instruction decoding circuit also includes a loop start instruction and a loop end instruction. The loop start instruction includes an operand representing the number of loop iterations. The first cache allocation instruction is located before the loop start instruction, and the multiple sets of scheduling instructions are located between the loop start instruction and the loop end instruction. The instruction execution circuit responds to the decoded software code by performing multiple loop processes, controlling the multiple operators to complete the processing of the data to be processed in a pipeline manner according to a set connection order; each loop process includes multiple time steps, and each operator completes one processing of a data block in the data to be processed in one time step.

6. The control device according to claim 5, wherein, Between the loop start instruction and the loop end instruction, there are M groups of scheduling instructions. Each loop process includes M time steps, where M = m1 + m2 - 1, m1 is the number of the multiple operators, m2 is the number of data blocks processed in each loop, m1 ≥ 2, and m2 ≥ 2; When m < m1, the active operators in the m-th time step are the 1st to m-th operators, where m = 1, 2, …, M; When m1 ≤ m ≤ m2, the active operators in the m-th time step are all of the multiple operators; When m2 < m ≤ M, the active operators in the m-th time step are the (m - m2 + 1)-th to m1-th operators; Among them, the operator to be started indicated by the start instruction in the m-th group of scheduling instructions is the active operator in the m-th time step.

7. The control device according to claim 5, wherein, The first cache allocation instruction includes a write register instruction and N' write data instructions associated with the write register instruction. The write register instruction is associated with a total of N write data instructions, where: The write register instruction includes: an opcode, the second operand representing the register address Add, and an operand representing the number of immediate numbers N, where N ≥ N' ≥ 2; The write data instruction includes an opcode and an immediate number. The first operand includes N' immediate numbers in the N' write data instructions. The N' immediate numbers in the N' write data instructions include information on the row position, number of rows, column position, and number of columns of the cache allocated for the operator; The instruction execution circuit writes the first operand in each first cache allocation instruction into the storage space indicated by the second operand in the cache allocation instruction, including: for each of the N' write data instructions, writing the immediate number therein into the register with the address Add + n - 1 for the operator to read, where n is the serial number of the instruction in the N write data instructions, indicating that the instruction is the n-th instruction under the write register instruction, and 1 ≤ n ≤ N.

8. The control device according to claim 7, wherein, The N' immediate numbers in the N' write data instructions further include the number K of caches used by the operator in multiple loop processes, to indicate that the operator updates the row position or column position of the allocated cache step by step with a period of K time steps, so that the operator uses different caches in K time steps of the same period and the same cache in the k-th time step of different periods, where k = 0, 1, …, K-1 and K ≥ 2.

9. The control device according to claim 5, wherein, The software code decoded by the instruction decoding circuit further includes a second cache allocation instruction located between two adjacent groups of scheduling instructions. The second cache allocation instruction includes: a first operand for indicating the position of the cache reallocated for the operator to be used in the next time step; a second operand for indicating the storage space into which the first operand is to be written; The instruction execution circuit is further configured to, in response to each decoded second cache allocation instruction, write the first operand therein to the storage space indicated by the second operand therein, so as to allocate a cache for the operator using the storage space to use in the next time step; wherein the caches allocated for the plurality of operators to use in the same time step are located in different and independently accessible regions in the shared cache pool, and for adjacent operators among the plurality of operators, the output cache allocated for the preceding operator to use in the current time step is the input cache allocated for the following operator to use in the next time step.

10. The control device according to claim 9, wherein, In the multiple sets of scheduling instructions, the second buffer allocation instruction between two adjacent sets of scheduling instructions is used to reallocate the buffer position for each operator that was processed in the previous time step and still needs to be processed in the next time step. For each of the plurality of operators, starting from the time step when the operator is first started, with a period of K time steps, the cache allocated by the instruction execution circuit for the operator in the K time steps of the same period is different, while the cache allocated for the operator in the k-th time step of different periods is the same, k = 0, 1, ..., K-1, K ≥ 2.

11. The control device according to claim 9, wherein, The second cache allocation instruction includes a write register instruction and M write data instructions associated with the write register instruction, where M ≥ 1, and: The write register instruction includes: an opcode, a second operand representing the register address Add', and an operand representing the number of immediate values ​​M; The write data instruction includes an opcode and an immediate value. The first operand includes M immediate values ​​from the M write data instructions. The M immediate values ​​from the M write data instructions include information about the row or column position of the cache reallocated for the operator. The instruction execution circuit responds to each second cache allocation instruction by writing the first operand therein into the storage space indicated by the second operand, including: for each of the M write data instructions, writing the immediate value therein into a register at address Add'+m-1 for the operator to read, where m is the sequence number of the instruction in the M write data instructions, indicating that the instruction is the m-th instruction under the write register instruction, 1≤m≤M.

12. The control device according to claim 5, wherein, The data to be processed is a frame of data obtained by the radar system from processing the received radar signal. The plurality of operators are operators in the 1D-FFT processing stage, and one data block in the data to be processed is data obtained by processing a chirp signal received on a channel; or, the plurality of operators are operators in the 2D-FFT processing stage, and one data block in the data to be processed is data at the same distance gate in the 1D-FFT data.

13. A multi-operator control method applied to a hardware accelerator, the hardware accelerator including a hardware scheduler, a specified number of operators, and a shared cache pool, the control method comprising: Allocating caches for the multiple operators to use when accessing data from the shared cache pool respectively to form data channels between the multiple operators, where the allocated caches include input caches and / or output caches; Through step-by-step scheduling, starting the multiple operators in sequence according to a set connection order to complete the processing of the data to be processed; Among them, for adjacent operators among the multiple operators, the output cache used by the previous operator in the current time step is the input cache used by the subsequent operator in the next time step.

14. The control method according to claim 13, wherein: The allocating caches for the multiple operators to use when accessing data from the shared cache pool respectively includes: allocating caches for the multiple operators to use when performing the first processing from the shared cache pool; Among them, for adjacent operators among the multiple operators, the output cache allocated for the previous operator to use when performing the first processing is the input cache allocated for the subsequent operator to use when performing the first processing.

15. The control method according to claim 13 or 14, wherein: The through step-by-step scheduling, starting the multiple operators in sequence according to a set connection order to complete the processing of the data to be processed includes: performing multiple loop controls to control the multiple operators to complete the processing of multiple data blocks in the data to be processed in a pipeline manner according to the set connection order; each loop process includes multiple time steps, and each operator completes one processing of one data block in the data to be processed in one time step; Among them, the caches allocated for the multiple operators to use in the same time step are located in different and independently accessible regions in the shared cache pool; and for adjacent operators among the multiple operators, the output cache allocated for the previous operator to use in the current time step is the input cache allocated for the subsequent operator to use in the next time step.

16. The control method according to claim 15, wherein: Each loop process includes M time steps, M = m1 + m2 - 1, where m1 is the number of the multiple operators, m2 is the number of data blocks processed in each loop, m1 ≥ 2, m2 ≥ 2; In each loop process: When m < m1, the activated operators in the m-th time step are the 1st to the m-th operators, m = 1, 2,..., M; When m1 ≤ m ≤ m2, the activated operators in the m-th time step are all the operators among the multiple operators; When m2 < m ≤ M, the activated operators in the m-th time step are the (m - m2 + 1)-th to the m1-th operators.

17. The control method according to claim 15, wherein: The method further includes: respectively allocating the number K of caches for the multiple operators to use in the multiple loop processes to indicate that the operators update the positions of the allocated caches step by step with a period of K time steps, so that the operators use different caches in the K time steps of the same period and use the same cache in the k-th time step of different periods, k = 0, 1,..., K - 1, K ≥ 2.

18. The control method according to claim 15, wherein: The step of allocating caches from the shared cache pool for the multiple operators to use when accessing data includes: reallocating caches for operators that process data in both the previous and next time steps between two adjacent time steps; For each of the plurality of operators, there are K groups of buffers allocated and reallocated for the operator during the multiple loops, where K ≥ 2. Each group includes an input buffer and / or an output buffer. Starting from the first processing of the operator, with a period of K time steps, the buffer used by the operator in the k-th time step of different periods is the same, and the buffer used in different time steps of the same period is different, where k = 0, 1, ..., K-1.

19. The control method according to claim 15, wherein: The data to be processed is a frame of data obtained by the radar system from processing the received radar signal. The plurality of operators are operators in the 1D-FFT processing stage, and one data block in the data to be processed is data obtained by processing a chirp signal received on a channel; or, the plurality of operators are operators in the 2D-FFT processing stage, and one data block in the data to be processed is data at the same distance gate in the 1D-FFT data.

20. A hardware scheduler, comprising a control unit and internal memory, wherein, The control device is a control device as described in any one of claims 1 to 12, and the internal memory is configured to store the software code to be decoded and executed by the control device.

21. A hardware accelerator, wherein, This includes a hardware scheduler, multiple specified operators, a shared cache pool providing cache space for the operators, and a register set, wherein: The hardware scheduler is the hardware scheduler as described in claim 20, wherein the cache information allocated to each operator is saved in the register group, and the processed data is stored in external memory. The register group is configured to store configuration information for the plurality of operators, the configuration information including information on the cache allocated to the operators; The plurality of operators are configured to, upon startup, obtain information about the cache allocated to the operator from the register group; if an input cache is allocated, read the data block to be processed from the input cache and process it; and if an output cache is allocated, write the processed data into the output cache.

22. The hardware accelerator according to claim 21, wherein: The operator includes: The data reading unit is configured to acquire information about the input buffer allocated to the operator, and based on the information about the input buffer, sequentially read out the data blocks in the input buffer and input them into the processing unit; The processing unit is configured to process the data block to obtain a processed data block; The write data unit is configured to obtain information about the output buffer allocated to the operator, and write the processed data block into the output buffer based on the information about the buffer. The scheduling interface is configured to receive a start signal and use it as a trigger signal to begin processing this operator. The synchronization interface is configured to send a signal indicating that the processing is complete after the write data unit writes the processed data block into the output buffer.

23. The hardware accelerator according to claim 22, wherein: The read data unit retrieves information about the input buffer allocated to the operator from the register group, and the write data unit retrieves information about the output buffer allocated to the operator from the register group. The operator also includes a cache update unit; The cache update unit is configured to: read from the register group the location and size of the cache initially allocated to the operator, and the number K of caches allocated to the operator, where K ≥ 2; and cyclically count the number of times the scheduling interface receives the start signal, starting a new cycle after the accumulated count reaches K times in each cycle, and when the accumulated count in each cycle is k times, calculate the location of the cache used by the operator in the next time step based on the location and size of the initially allocated cache and the value of k, and update the cache location in the register group to the calculated cache location; where k = 0, 1, ..., K-1, and the calculated cache location is different when the value of k is different.

24. The hardware accelerator according to claim 21, wherein: The plurality of operators sequentially include: CQMD operator, FFT operator, and SVA operator; or The plurality of operators sequentially include: DC operator, FFT operator, and SVA operator; or The plurality of operators sequentially include: CMB operator, STAS operator, HIST operator, CFAR operator, and STAS operator; or The plurality of operators include, in sequence: DC operator, FFT operator, SVA operator, and CMB operator.

25. A computing system comprising a processor, memory, and a hardware accelerator, wherein: The processor is configured to load the data to be processed stored in the memory into the hardware accelerator; The memory is configured to store data to be processed, and to store data obtained by the hardware accelerator after processing the data to be processed. The hardware accelerator employs the hardware accelerator described in any one of claims 21 to 24.

26. The integrated circuit according to claim 25, wherein: The computing system is a system-on-a-chip, which is a millimeter-wave chip or sensor chip in a radar system.

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