Interface heat dissipation material preform, manufacturing method therefor, and multi-chip package structure

Abstract

The present application provides an interface heat dissipation material preform, a manufacturing method therefor, and a multi-chip package structure. In the interface heat dissipation material preform, the manufacturing method therefor, and the multi-chip package structure provided in the present application, a plurality of chip fixing areas are formed on a second surface, and at least two of the plurality of chip fixing areas have different thicknesses, so that the interface heat dissipation material preform can simultaneously support at least two types of chips having different thicknesses, thereby adapting to different chip requirements, simplifying the packaging process, shortening assembly time, improving production flexibility, and improving generation efficiency. In addition, the standardized design of the interface heat dissipation material preform facilitates consistency and repeatability of each multi-chip package, thereby reducing variability during production.

Description

Interface heat dissipation material preforms, their preparation methods and multi-chip packaging structures Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to an interface heat dissipation material preform, its preparation method and multi-chip packaging structure. Background Technology

[0002] In multi-chip packaging, the height of the chips varies depending on the design requirements. This variation in chip height results in uneven distances between the top of the chip and the bottom of the heatsink. Therefore, multiple interface thermal management material preforms are needed to accommodate the varying chip heights and achieve multi-chip packaging. However, using multiple interface thermal management material preforms for multi-chip packaging involves multiple pick-and-place processes, leading to a longer production cycle. Summary of the Invention

[0003] In view of this, this application provides an interface heat dissipation material preform, a method for preparing the same, and a multi-chip packaging structure, which can simultaneously package chips of different thicknesses using a single interface heat dissipation material preform, thereby improving the efficiency of chip packaging and shortening the chip packaging cycle.

[0004] Specifically, this application is implemented through the following technical solution:

[0005] The first aspect of this application provides an interface heat dissipation material preform for use in a multi-chip package structure, the multi-chip package structure including multiple chips, the multiple chips including chips of at least two different thicknesses; the interface heat dissipation material preform has a first surface and a second surface disposed back-to-back; wherein...

[0006] The first surface is a plane and is used to bond the heat dissipation cover in the multi-chip package structure;

[0007] The second surface has a plurality of chip fixing regions that match the plurality of chips. Each chip fixing region is used to fix a chip that matches the chip fixing region. The total thickness of each chip fixing region and the chip to be fixed in the chip fixing region is equal to a specified value, and at least two of the plurality of chip fixing regions have different thicknesses, so that the at least two different thicknesses of chips can be fixed simultaneously through the interface heat dissipation material preform.

[0008] The second aspect of this application provides a method for preparing an interface heat dissipation material preform, the method being used to prepare the interface heat dissipation material preform provided in the first aspect of this application; the method includes:

[0009] Prepare an initial part of an interface heat dissipation material; wherein the initial part of the interface heat dissipation material has a first surface and a second surface arranged opposite to each other;

[0010] Multiple chip fixing regions are formed on the second surface; wherein at least two of the multiple chip fixing regions have different thicknesses, and the total thickness of each chip fixing region and the chip to be fixed in the chip fixing region is equal to a specified value.

[0011] A third aspect of this application provides a multi-chip packaging structure, the multi-chip packaging structure including a substrate, multiple chips, an interface heat dissipation material preform as provided in the first aspect of this application, and a heat dissipation cap; wherein...

[0012] The plurality of chips are fixed on the substrate; the plurality of chips include chips of at least two different thicknesses;

[0013] The interface heat dissipation material preform has multiple chip fixing areas that match the multiple chips. The interface heat dissipation material preform is fixed to the multiple chips in such a way that each chip fixing area is directly opposite to its matching chip. The total thickness of each chip fixing area and the chip that matches the chip fixing area is equal to a specified value.

[0014] The heat dissipation cover is fixed to the first surface of the interface heat dissipation material preform by covering the plurality of chips, and the downwardly protruding surrounding portion of the heat dissipation cover contacts the substrate.

[0015] The interface heat dissipation material preform, its preparation method, and multi-chip packaging structure provided in this application form multiple chip fixing regions on a second surface, with at least two of the chip fixing regions having different thicknesses. This allows the interface heat dissipation material preform to support at least two different chip thicknesses simultaneously, adapting to different chip requirements, simplifying the packaging process, reducing assembly time, improving production flexibility, and increasing production efficiency. Furthermore, the standardized design of the interface heat dissipation material preform helps ensure the consistency and repeatability of each multi-chip package, reducing variability during the production process. Attached Figure Description

[0016] Figure 1 is a schematic diagram of Embodiment 1 of the interface heat dissipation material preform provided in this application;

[0017] Figure 2 is a schematic diagram of the multi-chip package structure containing the interface heat dissipation material preform shown in Figure 1.

[0018] Figure 3 is a schematic diagram of Embodiment 2 of the interface heat dissipation material preform provided in this application;

[0019] Figure 4 is a schematic diagram of the multi-chip package structure containing the interface heat dissipation material preform shown in Figure 3.

[0020] Figure 5 is a schematic diagram of Embodiment 3 of the interface heat dissipation material preform provided in this application;

[0021] Figure 6 is a bottom view of the multi-chip package structure containing the interface heat dissipation material preform shown in Figure 5.

[0022] Figure 7 is a schematic diagram of Embodiment 4 of the interface heat dissipation material preform provided in this application;

[0023] Figure 8 is a schematic diagram of an interface heat dissipation material preform provided in an exemplary embodiment of this application;

[0024] Figure 9 is a schematic diagram of Embodiment 5 of the interface heat dissipation material preform provided in this application;

[0025] Figure 10 is a flowchart of an embodiment of the preparation method of the interface heat dissipation material preform provided in this application;

[0026] Figure 11 is a schematic diagram illustrating the implementation principle of preparing an interface heat dissipation material preform according to an exemplary embodiment of this application.

[0027] Explanation of reference numerals in the attached drawings: 11: First surface; 12: Second surface; 121: Chip fixing area; 122: Dividing part; 123: Melting start point control part. Detailed Implementation

[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0029] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0030] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0031] The following specific embodiments are given to illustrate the technical solution of this application in detail.

[0032] Figure 1 is a schematic diagram of Embodiment 1 of the interface heat dissipation material preform provided in this application. Figure 2 is a schematic diagram of the multi-chip package structure in which the interface heat dissipation material preform shown in Figure 1 is located. Please refer to Figures 1 and 2 simultaneously. The interface heat dissipation material preform provided in this embodiment is used in a multi-chip package structure, which includes multiple chips, and the multiple chips include chips of at least two different thicknesses; the interface heat dissipation material preform has a first surface 11 and a second surface 12 arranged back to back; wherein,

[0033] The first surface 11 is a plane and is used to bond the heat dissipation cover in the multi-chip package structure;

[0034] The second surface 12 has a plurality of chip fixing regions 121 that match the plurality of chips. Each chip fixing region 121 is used to fix a chip that matches the chip fixing region 121. The total thickness of each chip fixing region 121 and the chip to be fixed on the chip fixing region 121 is equal to a specified value, and at least two of the plurality of chip fixing regions 121 have different thicknesses, so that the at least two different thicknesses of chips can be fixed simultaneously by the interface heat dissipation material preform.

[0035] Specifically, a multi-chip package structure includes multiple chips. Due to different designs, the thickness of these chips may vary, meaning that the multiple chips include chips of at least two different thicknesses. For example, in the example shown in Figure 2, the multi-chip package structure includes three chips, each with a different thickness; that is, the multi-chip package structure includes chips of three different thicknesses.

[0036] Further, referring to Figures 1 and 2, the interface heat dissipation material preform provided in this embodiment has a first surface 11 and a second surface 12, which are arranged back-to-back. The first surface 11 is a plane used for bonding with a heat dissipation cap in a multi-chip package structure. The second surface 12 is composed of multiple planes of different heights, which together form multiple chip fixing regions 121. For example, in the example shown in Figure 1, the second plane 12 has three planes of different heights, which together form three chip fixing regions 121.

[0037] It should be noted that the bonding method between the first surface 11 and the heat sink is set according to actual needs, and is not limited in this embodiment. For example, the bonding method between the first surface 11 and the heat sink can be thermally conductive adhesive bonding, welding, etc. Furthermore, the number of chip fixing regions 121 included on the second surface 12 matches the number of chips included in the multi-chip package structure, and each chip fixing region 121 is used to fix the chip that matches that chip fixing region 121. It should be noted that if the sum of the thickness of a chip fixing region 121 and the thickness of a chip (i.e., the total thickness) equals a specified value, then the chip fixing region 121 matches the chip.

[0038] Please refer to Figure 2. In the example shown in Figure 2, the multi-chip package structure includes three chips. For ease of explanation, these three chips are referred to as the first chip, the second chip, and the third chip, respectively, from left to right. Furthermore, please refer to Figures 1 and 2 simultaneously. The interface heat dissipation material preform provided in this embodiment includes three chip fixing areas 121. For ease of distinction, these three chip fixing areas 121 are referred to as the first chip fixing area, the second chip fixing area, and the third chip fixing area, respectively.

[0039] Referring to Figure 2, the total thickness of the first chip and its fixing region is equal to a specified value, and the first chip and its fixing region are matched, with the fixing region used to fix the first chip. Similarly, the total thickness of the second chip and its fixing region is equal to a specified value, and the fixing regions are matched, with the fixing region used to fix the second chip. Likewise, the total thickness of the third chip and its fixing region is equal to a specified value, and the fixing region is matched, with the fixing region used to fix the third chip. This interface heat dissipation material preform includes three chip fixing regions 121 of different thicknesses, capable of simultaneously fixing chips of three different thicknesses.

[0040] It should be noted that the specified value is set according to actual needs, and in this embodiment, it is not limited.

[0041] Optionally, in one possible implementation, the interface heat dissipation material preform can be made of any of the following materials: indium, tin, silver, indium alloys, tin alloys, silver alloys, graphite, graphene, and composite materials.

[0042] In another possible implementation, the interface heat dissipation material preform is a preform with an external polymer coating or an external flux coating.

[0043] Specifically, the external polymer coating and external flux coating can provide additional mechanical strength and wear resistance to the interface heat dissipation material preform, prevent it from being chemically corroded, ensure the heat dissipation performance of the interface heat dissipation material preform, and promote welding, making the weld stronger.

[0044] Optionally, in one possible implementation, the thickness difference between any two chip fixing regions with different thicknesses is between 20 μm and 700 μm.

[0045] or,

[0046] The thickness difference between any two chip fixing regions with different thicknesses is less than or equal to 80%B; wherein, B is the thickness value of the chip fixing region with the largest thickness among the plurality of chip fixing regions.

[0047] Specifically, referring to the description above, for example, in the example shown in Figure 1, the thickness of the first chip fixing region is 200 μm, the thickness of the second chip fixing region is 130 μm, and the thickness of the third chip fixing region is 170 μm. Among these three chip fixing regions 121, the chip fixing region 121 with the largest thickness is the first chip fixing region, with a thickness of 200 μm, i.e., B equals 200 μm. In this case, 80%B equals 160 μm. Furthermore, the thickness difference between the first and second chip fixing regions is 70 μm, the thickness difference between the first and third chip fixing regions is 30 μm, and the thickness difference between the second and third chip fixing regions is 40 μm. That is, among these three chip fixing regions 121, the thickness difference between any two chip fixing regions 121 with different thicknesses is between 20 μm and 700 μm; or, the thickness difference between any two chip fixing regions 121 with different thicknesses is less than or equal to 80%B (160 μm).

[0048] Two more specific embodiments are given below to illustrate in detail the interface heat dissipation material preform provided in this application.

[0049] Figure 3 is a schematic diagram of Embodiment 2 of the interface heat dissipation material preform provided in this application, and Figure 4 is a schematic diagram of the multi-chip package structure in which the interface heat dissipation material preform shown in Figure 3 is located.

[0050] Please refer to Figure 4. In the example shown in Figure 4, the multi-chip package structure includes three chips. For ease of explanation, these three chips are referred to as the first chip, the second chip, and the third chip, respectively, from left to right. Furthermore, please refer to Figures 3 and 4 simultaneously. The interface heat dissipation material preform provided in this embodiment includes three chip fixing areas 121. For ease of distinction, these three chip fixing areas 121 are referred to as the first chip fixing area, the second chip fixing area, and the third chip fixing area, respectively.

[0051] Furthermore, the total thickness of the first chip and the first chip fixing region is equal to a specified value, the first chip and the first chip fixing region are matched, and the first chip fixing region is used to fix the first chip; similarly, the total thickness of the second chip and the second chip fixing region is equal to a specified value, the second chip and the second chip fixing region are matched, and the second chip fixing region is used to fix the second chip; similarly, the total thickness of the third chip and the third chip fixing region is equal to a specified value, the third chip and the third chip fixing region are matched, and the third chip fixing region is used to fix the third chip.

[0052] Please refer to Figures 3 and 4. In this embodiment, the first chip and the third chip have the same thickness, and the second chip has a greater thickness than the first chip. Furthermore, the fixing regions of the first chip and the third chip have the same thickness, and the fixing regions of the second chip have a smaller thickness than the fixing regions of the first chip.

[0053] In other words, the interface heat dissipation material preform includes two chip fixing areas 121 with different thicknesses, which can simultaneously fix two types of chips with different thicknesses.

[0054] Furthermore, Figure 5 is a schematic diagram of Embodiment 3 of the interface heat dissipation material preform provided in this application (Figure 5 shows a bottom view of the interface heat dissipation material preform), and Figure 6 is a partial schematic diagram of the multi-chip package structure in which the interface heat dissipation material preform shown in Figure 5 is located. Please refer to Figures 5 and 6 simultaneously. In the example shown in Figure 6, the multi-chip package structure includes four chips, namely chip A, chip B, chip C, and chip D; furthermore, chip A and chip D have the same thickness, while chip A, chip B, and chip C have different thicknesses, that is, the multi-chip package structure includes three chips of different thicknesses.

[0055] Further, please continue to refer to Figure 5. The interface heat dissipation material preform provided in this embodiment includes four chip fixing regions 121, namely: chip fixing region A, chip fixing region B, chip fixing region C and chip fixing region D; wherein, chip fixing region A and chip fixing region D have the same thickness, and chip fixing region A, chip fixing region B and chip fixing region C have different thicknesses.

[0056] Furthermore, the total thickness of chip A and chip fixing region A is equal to a specified value, chip A and chip fixing region A are matched, and chip fixing region A is used to fix chip A; similarly, the total thickness of chip B and chip fixing region B is equal to a specified value, chip B and chip fixing region B are matched, and chip fixing region B is used to fix chip B; similarly, the total thickness of chip C and chip fixing region C is equal to a specified value, chip C and chip fixing region C are matched, and chip fixing region C is used to fix chip C; similarly, the total thickness of chip D and chip fixing region D is equal to a specified value, chip D and chip fixing region D are matched, and chip fixing region D is used to fix chip D.

[0057] As described above, it can be understood that the interface heat dissipation material preform includes four chip fixing areas 121, which can simultaneously fix three types of chips of different thicknesses.

[0058] The interface heat dissipation material preform provided in this embodiment forms multiple chip fixing regions on the second surface, and at least two of the chip fixing regions have different thicknesses. In this way, the interface heat dissipation material preform can support at least two different chip thicknesses at the same time, which can adapt to different chip requirements, simplify the packaging process, reduce assembly time, improve production flexibility, and improve production efficiency. In addition, the standardized design of the interface heat dissipation material preform helps to ensure the consistency and repeatability of each multi-chip package, which can reduce the variability in the production process.

[0059] Specifically, Figure 7 is a schematic diagram of Embodiment 4 of the interface heat dissipation material preform provided in this application. Referring to Figure 7, based on the above embodiments, the interface heat dissipation material preform provided in this embodiment has a dividing part 122 at the junction of two adjacent chip fixing areas. The dividing part 122 divides the two adjacent chip fixing areas 121 so that in the reflow soldering process, the melting starting point of the interface heat dissipation material preform can be controlled by the dividing part 122, and the molten interface heat dissipation material can be divided by the dividing part 122. The dividing part 122 includes at least one of the following forms of dividing part: groove, countersunk groove, through hole array, blind hole array.

[0060] Specifically, a segmentation portion 122 is provided at the boundary between two adjacent chip fixing regions 121. The segmentation portion 122 includes at least one of the following forms: groove, countersunk groove, through-hole array, or blind via array. Thus, in the reflow soldering process, in addition to forming a melting starting point around the outer periphery of the interface heat dissipation material preform, structures such as grooves, countersunk grooves, through-holes, or blind vias can effectively guide the distribution of heat within the interface heat dissipation material preform, thereby forming a melting starting point at the segmentation portion 122. This allows for simultaneous melting of the interface heat dissipation material preform from both the outside and inside, accelerating the melting speed of the interface heat dissipation material preform.

[0061] Furthermore, the dividing section 122 can also divide the adjacent chip fixing area 121, thereby dividing the molten interface heat dissipation material to ensure its reasonable distribution during the reflow soldering process and to prevent the molten interface heat dissipation material from flowing into the chip.

[0062] Optionally, Figure 8 is a schematic diagram of an interface heat dissipation material preform provided by an exemplary embodiment of this application. Figures A to E in Figure 8 show different forms of segmentation. Referring to Figure 8, it can be understood that the interface heat dissipation material preform shown in Figure 8 includes three chip fixing regions 121. For ease of distinction, these three chip fixing regions 121 are respectively referred to as the first chip fixing region, the second chip fixing region, and the third chip fixing region in order from left to right. The first chip fixing region and the second chip fixing region are two adjacent chip fixing regions, and the second chip fixing region and the third chip fixing region are two adjacent chip fixing regions.

[0063] Taking the first chip fixing region and the second chip fixing region as examples, the boundary between two adjacent chip fixing regions may include a first boundary of the first chip fixing region near the second chip fixing region, and / or a second boundary of the second chip fixing region near the first chip fixing region. Therefore, the dividing portion 122 can be provided at the first boundary and / or the second boundary. For example, in Figure A of FIG8, for the first chip fixing region and the second chip fixing region, the dividing portion 122 is provided at the first boundary of the first chip fixing region. As another example, in Figure B of FIG8, for the first chip fixing region and the second chip fixing region, the dividing portion 122 is provided at the second boundary of the second chip fixing region. As yet another example, in Figure C of FIG8, for the first chip fixing region and the second chip fixing region, the dividing portion 122 is provided at both the first boundary of the first chip fixing region and the second boundary of the second chip fixing region.

[0064] It should be noted that the dividing part 122 includes at least one of the following forms of dividing part: groove, countersunk groove, through hole array, blind hole array.

[0065] For example, in Figures A, B, and E of FIG8, each segment 122 includes one type of segment. Further, for example, in Figures C and D of FIG8, each segment includes multiple types of segment. For example, in Figure C of FIG8, two types of segment 122 are provided at the junction of the first chip fixing region and the second chip fixing region, and at the junction of the second chip fixing region and the third chip fixing region. For example, in Figure D of FIG8, two types of segment 122 are provided at the junction of the first chip fixing region and the second chip fixing region, namely, a through-hole array and a groove; three types of segment 122 are provided at the junction of the second chip fixing region and the third chip fixing region, namely, a through-hole array, a groove, and a countersunk groove.

[0066] Further, please continue to refer to Figures D and E in Figure 8. Optionally, in one possible implementation, the length direction of the dividing portion 122 is parallel to the boundary line of the two adjacent chip fixing regions 121, or the angle between the length direction of the dividing portion 122 and the boundary line of the two adjacent chip fixing regions 121 is less than 90°.

[0067] Referring to the preceding description, it can be understood that the dividing portion 1 at the junction of two adjacent chip fixing regions 121 can be one of the following: a groove, a countersunk groove, a through-hole array, or a blind via array, or a combination of any two or more of the following forms. In this embodiment, it is not limited to this. For example, in one embodiment, the dividing portion 122 is in the form of a groove; in another embodiment, the dividing portion 122 is in the form of a combination of groove, through-hole array, and blind via array.

[0068] It should be noted that when the segmentation part 122 is in the form of a through-hole array or a blind-hole array, the number of through holes or blind holes is set according to actual needs, and is not limited in this embodiment.

[0069] Optionally, in one possible implementation, when the dividing portion 122 is a groove or a through-hole array, the width of the groove along the arrangement direction of the two adjacent chip fixing regions 121 (left-right direction as shown in FIG8) or the diameter of each through-hole in the through-hole array is greater than or equal to 20 μm and less than or equal to the spacing between the two adjacent chip fixing regions 121.

[0070] It should be noted that the spacing between two adjacent chip fixing areas 121 refers to the distance between the positions where the chip is actually fixed (the positions covered by the chip) in the above-mentioned arrangement direction.

[0071] In other words, when the dividing portion 122 is in the form of a groove, the width of the groove along the arrangement direction of two adjacent chip fixing regions 121 is within the range of 20 μm and the distance between the two adjacent chip fixing regions 121. That is, the minimum width of the groove is 20 μm and the maximum width is the distance between the two adjacent chip fixing regions 121. Similarly, when the dividing portion 122 is in the form of a through-hole array, the diameter of each through-hole in the through-hole array is within the range of 20 μm and the distance between the two adjacent chip fixing regions 121. That is, the minimum diameter of the through-hole is 20 μm and the maximum diameter is the distance between the two adjacent chip fixing regions 121.

[0072] Optionally, in another possible implementation, when the segment 122 is a slot or a blind via array, the width of the slot along the arrangement direction of the two adjacent chip fixing regions 121 or the diameter of each blind via in the blind via array is greater than or equal to 10 μm and less than or equal to twice the distance between the two adjacent chip fixing regions 121.

[0073] Furthermore, when the dividing portion 122 is in the form of a sink, the width of the sink along the arrangement direction of two adjacent chip fixing regions 121 is within the range of 10 μm and twice the distance between the two adjacent chip fixing regions 121. That is, the minimum width of the sink is 10 μm and the maximum is twice the distance between the two adjacent chip fixing regions 121. Similarly, when the dividing portion 122 is in the form of a blind via array, the diameter of each blind via in the blind via array is within the range of 10 μm and twice the distance between the two adjacent chip fixing regions 121. That is, the minimum width of the sink is 10 μm and the maximum is twice the distance between the two adjacent chip fixing regions 121.

[0074] Optionally, in another possible implementation, when the segment 122 is a groove or a blind hole array, the depth of the groove or the depth of each blind hole in the blind hole array is between 5%A and 95%A; wherein A is the thickness value of the interface heat dissipation material preform at the location of the groove or the blind hole array.

[0075] Preferably, in one embodiment, the depth of the sink or the depth of each blind hole in the blind hole array is between 30%A and 60%A.

[0076] Furthermore, when the segment 122 is in the form of a groove or a blind hole array, the depth of the blind holes in the groove or blind hole array is within 5% to 95% of the thickness of the interface heat dissipation material preform at the location of the groove or blind hole array. That is, the minimum depth of the blind holes in the groove or blind hole array is 5% of the thickness at its location, and the maximum depth is 95% of the thickness at its location. Preferably, the depth of the blind holes in the groove or blind hole array is 30% to 60% of the thickness at its location.

[0077] The interface heat dissipation material preform provided in this embodiment has a dividing portion at the junction of two adjacent chip fixing areas, which divides the two adjacent chip fixing areas. Firstly, during the reflow soldering process, in addition to forming melting start points around the outer periphery of the interface heat dissipation material preform, a melting start point can also be formed at the dividing portion, allowing the interface heat dissipation material preform to be melted simultaneously from both the outside and inside, thus accelerating the melting speed. Secondly, the dividing portion can also divide the molten interface heat dissipation material, ensuring its proper distribution during reflow soldering and preventing the molten interface heat dissipation material from flowing into the chip.

[0078] Figure 9 is a schematic diagram of Embodiment 5 of the interface heat dissipation material preform provided in this application. Referring to Figure 9, based on the above embodiments, the interface heat dissipation material preform provided in this embodiment has a melting start point control part 123 inside each chip fixing area 121, so as to control the melting start point in the reflow soldering process through the melting start point control part 123; wherein, the melting start point control part 123 includes at least one control part of the following form: a groove or a blind via.

[0079] Furthermore, referring to Figure 9, each chip fixing region has a melting start control unit 123. In the reflow soldering process, the melting start control unit 123, in the form of a slot or blind via, can control the melting start point inside the chip fixing region 121. Thus, during the reflow soldering process, the chip fixing region 121 can simultaneously begin melting from the outside, the dividing section 122 between two adjacent chip fixing regions 121, and the melting start control unit 123 inside each chip fixing region 121, thereby accelerating the melting speed of the interface heat dissipation material preform.

[0080] Furthermore, the melting start point control unit 123 can be in the form of a countersunk groove or a blind via. The melting start point control units 123 within each chip fixing area can be the same or different. The size, depth, number, and form of the melting start point control units 123 within each chip fixing area are set according to actual needs, and are not limited in this embodiment. For example, in one embodiment, there are two melting start point control units within a certain chip fixing area, one of which is in the form of a countersunk groove, and the other is in the form of a blind via.

[0081] The interface heat dissipation material preform provided in this embodiment has a melting start point control unit set inside each chip fixing area in the interface heat dissipation material preform. In this way, the melting start point can be controlled by the melting start point control unit during the reflow soldering process, so that the interface heat dissipation material preform can start melting simultaneously from the outside, the dividing part between two adjacent chip fixing areas, and the melting start point control unit inside each chip fixing area, thereby accelerating the melting speed of the interface heat dissipation material preform.

[0082] Corresponding to the aforementioned embodiment of an interface heat dissipation material preform, this application also provides a method for preparing an interface heat dissipation material preform. Figure 10 is a flowchart of an embodiment of the method for preparing an interface heat dissipation material preform provided in this application. Referring to Figure 10, the method for preparing an interface heat dissipation material preform provided in this embodiment is used to prepare any interface heat dissipation material preform provided in the first aspect of this application; the preparation method includes:

[0083] S101. Prepare an initial component of the interface heat dissipation material; wherein the initial component of the interface heat dissipation material has a first surface and a second surface arranged opposite to each other.

[0084] S102. A plurality of chip fixing regions are formed on the second surface; wherein at least two of the plurality of chip fixing regions have different thicknesses, and the total thickness of each chip fixing region and the chip to be fixed on the chip fixing region is equal to a specified value.

[0085] In a specific implementation, for example, in one possible implementation, multiple chip fixing areas can be formed on the second surface by mechanical processing.

[0086] Optionally, in one possible implementation, the second surface can be imprinted using a microimprinting mold; wherein the microimprinting mold has a pattern that matches the plurality of chip fixing regions to form a plurality of chip fixing regions on the second surface.

[0087] Optionally, in one possible implementation, the imprinting of the second surface using a microimprinting mold includes:

[0088] During the imprinting process, the initial part of the interface heat dissipation material is heated to soften it; wherein the heating temperature is less than or equal to 85%C; C is the melting temperature of the initial part of the interface heat dissipation material.

[0089] Optionally, in one possible implementation, heating the initial part of the interface heat dissipation material during the imprinting process includes:

[0090] During the heating process, an inert gas is used to form a protective environment to prevent oxidation of the initial components of the interface heat dissipation material.

[0091] Specifically, Figure 11 is a schematic diagram illustrating the implementation principle of preparing an interface heat dissipation material preform according to an exemplary embodiment of this application. Referring to Figure 11, the second surface can be imprinted using a microimprinting mold; wherein, the microimprinting mold has a pattern matching the plurality of chip fixing regions to form a plurality of chip fixing regions on the second surface.

[0092] Referring to Figure 11, the microimprinting mold includes an upper mold and a lower mold. The lower mold has a pattern that matches multiple chip fixing areas. During imprinting, the upper mold contacts the first surface of the interface heat dissipation material initial part, and the lower mold contacts the second surface. In this way, multiple chip fixing areas that meet the requirements can be imprinted on the second surface. Furthermore, as described above, when imprinting on the second surface, the interface heat dissipation material initial part can be heated in an inert gas environment to soften it and prevent oxidation. Further, the heating temperature of the interface heat dissipation material initial part needs to be less than or equal to 85% of its melting temperature; that is, the maximum heating temperature is 85% of its melting temperature.

[0093] Optionally, the micro-imprinting mold can be a linear pressing mold or a roller mold; in this embodiment, it is not limited to either.

[0094] The method provided in this embodiment is a method for preparing interface heat dissipation material preforms. This method can prepare interface heat dissipation material preforms with different thicknesses, so as to simultaneously encapsulate multiple chips of different thicknesses with a single interface heat dissipation material preform, thereby improving chip packaging efficiency and shortening the chip packaging cycle.

[0095] Optionally, after forming a plurality of chip fixing regions on the second surface, the fabrication method further includes:

[0096] A segment is formed at the junction of two adjacent chip fixing areas; wherein, the segment divides the two adjacent chip fixing areas so that, in the reflow soldering process, the melting starting point of the interface heat dissipation material preform is controlled by the segment and the molten interface heat dissipation material is divided by the segment; the segment includes at least one of the following forms of segment: groove, countersunk groove, through-hole array, blind hole array.

[0097] The method for preparing the interface heat dissipation material preform provided in this embodiment forms a segment at the junction of two adjacent chip fixing regions. In the reflow soldering process, the melting starting point of the interface heat dissipation material preform can be controlled by the segment, so that it melts simultaneously from the outside of the interface heat dissipation material preform and at the junction of two adjacent chip fixing regions, thereby accelerating the melting speed of the interface heat dissipation material preform. Furthermore, the segment can also divide the molten interface heat dissipation material to ensure its reasonable distribution during the reflow soldering process and prevent the molten interface heat dissipation material from flowing into the chip.

[0098] Optionally, after forming a plurality of chip fixing regions on the second surface, the fabrication method further includes:

[0099] A melting start control section is formed inside each chip fixed area to control the melting start point during the reflow soldering process; wherein the melting start control section includes at least one control section of the following form: a slot or a blind via.

[0100] In practice, the segmented portion or the melting start point control portion is formed by a micro-imprinting mold or a cutting mold.

[0101] Referring to Figures 1 and 3, this application also provides a multi-chip packaging structure, which includes a substrate, multiple chips, an interface heat dissipation material preform as provided in the first aspect of this application, and a heat dissipation cap; wherein...

[0102] The plurality of chips are fixed on the substrate; the plurality of chips include chips of at least two different thicknesses;

[0103] The interface heat dissipation material preform has multiple chip fixing areas that match the multiple chips. The interface heat dissipation material preform is fixed to the multiple chips in such a way that each chip fixing area is directly opposite to its matching chip. The total thickness of each chip fixing area and the chip that matches the chip fixing area is equal to a specified value.

[0104] The heat dissipation cover is fixed to the first surface of the interface heat dissipation material preform by covering the plurality of chips, and the downwardly protruding surrounding portion of the heat dissipation cover contacts the substrate.

[0105] The multi-chip packaging structure provided in this embodiment can simultaneously package multiple chips of different thicknesses according to different design needs, reducing the chip packaging pick-up and placement process, improving packaging efficiency, and shortening the production cycle.

[0106] This application also provides an application of the interface heat dissipation material preform as provided in the first aspect of this application, the interface heat dissipation material preform being used in the field of multi-chip packaging.

[0107] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A preform of an interface heat dissipation material, characterized in that, The interface heat dissipation material preform is used in a multi-chip packaging structure, the multi-chip packaging structure including multiple chips, the multiple chips including chips of at least two different thicknesses; the interface heat dissipation material preform has a first surface and a second surface disposed back-to-back; wherein... The first surface is a plane and is used to bond the heat dissipation cover in the multi-chip package structure; The second surface is formed with a plurality of chip fixing regions that match the plurality of chips. Each chip fixing region is used to fix a chip that matches the chip fixing region. The total thickness of each chip fixing region and the chip to be fixed on the chip fixing region is equal to a specified value, and at least two of the plurality of chip fixing regions have different thicknesses, so that the at least two different thicknesses of chips can be fixed simultaneously by the interface heat dissipation material preform. The junction of two adjacent chip fixing areas has a dividing part, which divides the two adjacent chip fixing areas so that, in the reflow soldering process, the dividing part controls the melting start point of the interface heat dissipation material preform and divides the molten interface heat dissipation material; wherein, the dividing part includes at least one of the following forms of dividing part: groove, through-hole array, blind hole array. Each chip has a fixed area with a melting start control section to control the melting start point during the reflow soldering process; wherein the melting start control section includes at least one of the following forms: a countersunk hole or a blind via; When the dividing part is a groove or a through-hole array, the width of the groove along the arrangement direction of the two adjacent chip fixing areas or the diameter of each through-hole in the through-hole array is greater than or equal to 20 μm and less than or equal to the distance between the two adjacent chip fixing areas; When the segment is a blind aperture array, the diameter of each blind aperture in the blind aperture array is greater than or equal to 10 μm and less than or equal to twice the distance between two adjacent chip fixed regions.

2. The interface heat dissipation material preform according to claim 1, characterized in that, When the segment is a blind hole array, the depth of each blind hole in the blind hole array is between 5%A and 95%A; wherein, A is the thickness value of the interface heat dissipation material preform at the location of the blind hole array.

3. The interface heat dissipation material preform according to claim 1, characterized in that, The depth of each blind hole in the blind hole array is between 30%A and 60%A; where A is the thickness of the interface heat dissipation material preform at the location of the blind hole array.

4. The interface heat dissipation material preform according to claim 1, characterized in that, The length direction of the segment is parallel to the boundary line of the two adjacent chip fixing areas, or the angle between the length direction of the segment and the boundary line of the two adjacent chip fixing areas is less than 90°.

5. The interface heat dissipation material preform according to claim 1, characterized in that, The interface heat dissipation material preform is made of any of the following materials: indium, tin, silver, indium alloy, tin alloy, silver alloy, graphite, graphene, and composite materials.

6. The interface heat dissipation material preform according to claim 1, characterized in that, The interface heat dissipation material preform is a preform with an external polymer coating or an external flux coating.

7. The interface heat dissipation material preform according to claim 1, characterized in that, The thickness difference between any two chip fixing regions with different thicknesses is between 20 μm and 700 μm; or, The thickness difference between any two chip fixing regions with different thicknesses is less than or equal to 80%B; wherein, B is the thickness value of the chip fixing region with the largest thickness among the plurality of chip fixing regions.

8. A method for preparing an interface heat dissipation material preform, characterized in that, The preparation method is used to prepare the interface heat dissipation material preform according to any one of claims 1-7; the preparation method includes: Prepare an initial part of an interface heat dissipation material; wherein the initial part of the interface heat dissipation material has a first surface and a second surface arranged opposite to each other; Multiple chip fixing regions are formed on the second surface; wherein at least two of the multiple chip fixing regions have different thicknesses, and the total thickness of each chip fixing region and the chip to be fixed on the chip fixing region is equal to a specified value; After forming multiple chip fixing regions on the second surface, the fabrication method further includes: A dividing section is formed at the junction of two adjacent chip fixing areas; wherein, the dividing section divides the two adjacent chip fixing areas so as to control the melting start point of the interface heat dissipation material preform in the reflow soldering process, and to divide the molten interface heat dissipation material; the dividing section includes at least one of the following forms of dividing section: groove, through-hole array, blind hole array; A melting start control section is formed inside each chip fixed area to control the melting start point during the reflow soldering process; wherein the melting start control section includes at least one control section of the following form: a countersunk hole or a blind via; When the dividing part is a groove or a through-hole array, the width of the groove along the arrangement direction of the two adjacent chip fixing areas or the diameter of each through-hole in the through-hole array is greater than or equal to 20 μm and less than or equal to the distance between the two adjacent chip fixing areas; When the segment is a blind aperture array, the diameter of each blind aperture in the blind aperture array is greater than or equal to 10 μm and less than or equal to twice the distance between two adjacent chip fixed regions.

9. The preparation method according to claim 8, characterized in that, The formation of multiple chip fixing regions on the second surface includes: The second surface is imprinted using a microimprinting mold; wherein the microimprinting mold has a pattern that matches the plurality of chip fixing areas to form a plurality of chip fixing areas on the second surface.

10. The preparation method according to claim 9, characterized in that, The process of imprinting the second surface using a micro-imprinting mold includes: During the imprinting process, the initial part of the interface heat dissipation material is heated to soften it; wherein the heating temperature is less than or equal to 85%C; C is the melting temperature of the initial part of the interface heat dissipation material.

11. The preparation method according to claim 10, characterized in that, The heating of the initial part of the interface heat dissipation material during the imprinting process includes: During the heating process, an inert gas is used to form a protective environment to prevent oxidation of the initial components of the interface heat dissipation material.

12. The preparation method according to claim 8, characterized in that, The segment or the melting start point control part is formed by micro-imprinting mold or cutting mold.

13. A multi-chip packaging structure, characterized in that, The multi-chip packaging structure includes a substrate, multiple chips, an interface heat dissipation material preform as described in any one of claims 1-7, and a heat dissipation cap; wherein... The plurality of chips are fixed on the substrate; the plurality of chips include chips of at least two different thicknesses; The interface heat dissipation material preform has multiple chip fixing areas that match the multiple chips. The interface heat dissipation material preform is fixed to the multiple chips in such a way that each chip fixing area is directly opposite to its matching chip. The total thickness of each chip fixing area and the chip that matches the chip fixing area is equal to a specified value. The heat dissipation cover is fixed to the first surface of the interface heat dissipation material preform by covering the plurality of chips, and the downwardly protruding surrounding portion of the heat dissipation cover contacts the substrate.

14. The use of a preformed interfacial heat dissipation material as described in any one of claims 1-7, characterized in that, The interface heat dissipation material preform is used in the field of multi-chip packaging.

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