Circuit board and computing device

Abstract

Embodiments of the present application provide a circuit board and a computing device. The circuit board comprises a board body, a chip array arranged on the board body, an electrical connector, and a voltage converter; the electrical connector is arranged on the board body and is used for supplying power to the voltage converter; and the voltage converter is arranged on the board body and is used for supplying power to the chip array on the basis of a preset voltage range. In the embodiments of the present application, by integrating the electrical connector and the voltage converter onto the board body of the circuit board, a stable voltage required by the circuit board can be provided therefor without a power module, thereby ensuring the stability and reliability of the circuit board.

Description

Circuit boards and computing devices

[0001] This application claims priority to Chinese Patent Application No. 2025200284933, filed on January 6, 2025, entitled "Circuit Board and Computing Device", the entire contents of which are incorporated herein by reference.

[0002] This application claims priority to Chinese Patent Application No. 202510020839X, filed on January 6, 2025, entitled "Fan Device and Computing Equipment", the entire contents of which are incorporated herein by reference.

[0003] This application claims priority to Chinese Patent Application No. 2025200253598, filed on January 6, 2025, entitled "Fan Device and Computing Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0004] This application relates to the field of computing device technology, and more particularly to a circuit board and a computing device. Background Technology

[0005] Computing devices typically have a separate power supply module. This module is designed and regulated to provide a stable output voltage to the circuit board, meeting its operational requirements. However, the inclusion of a power supply module increases space and weight, as well as circuit complexity and cost. Summary of the Invention

[0006] This application provides a circuit board and a computing device to solve or alleviate one or more technical problems in the prior art.

[0007] As one aspect of the embodiments of this application, this application provides a circuit board, including:

[0008] plate body;

[0009] The chip array is mounted on the board.

[0010] Electrical connectors and voltage converters;

[0011] The electrical connector is located on the board and is used to supply power to the voltage converter. The voltage converter is located on the board and is used to supply power to the chip array according to a preset voltage range.

[0012] In one embodiment, at least a portion of the electrical connector and voltage converter are disposed on a first side of the chip array in a first direction.

[0013] In one embodiment, the chip array includes at least two rows of chip groups, which are spaced apart in a second direction, and each row of chip groups includes a plurality of computing chips spaced apart in a first direction.

[0014] In one embodiment, a row of chipsets adjacent to the electrical connector is a first chipset, and a row of chipsets away from the electrical connector is a second chipset. The electrical connector is disposed on a first side of the first chipset in a first direction and on a side of the first chipset away from the second chipset.

[0015] In one embodiment, the electrical connector has a power input terminal and a power ground terminal. The power input terminal is connected to a second chipset via a voltage converter, and the power ground terminal is connected to a first chipset. Multiple computing chips in the chip array are connected in series.

[0016] In one embodiment, the second side of the first chipset in the first direction is electrically connected to the second side of the second chipset in the first direction, the first side of the first chipset in the first direction is connected to the power supply ground terminal, and the first side of the second chipset in the first direction is connected to the voltage converter.

[0017] In one embodiment, the electrical connector has a signal connection end that is connected to a chip array.

[0018] In one embodiment, the power ground terminal, power input terminal, and signal connection terminal of the electrical connector are arranged in a first direction.

[0019] In one embodiment, the signal connection terminal is connected via a signal line to the side of the first chipset of the chip array opposite to the second chipset, and is connected to the computing chip in the first chipset that is closest to the signal connection terminal.

[0020] In one embodiment, the signal line is connected to the computing chip on one side in the second direction, and connected to an adjacent computing chip on the other side in the second direction.

[0021] In one implementation, the computing chip in the first chipset that is furthest from the signal connection terminal is signal-connected to the computing chip in the second chipset that is closest to the computing chip.

[0022] In one implementation, the number of computing chips in the first chipset of the chip array is odd.

[0023] In one implementation, the number of computing chips in the first chipset of the chip array is greater than the number of computing chips in the second chipset of the chip array.

[0024] In one embodiment, the spacing between two adjacent computing chips in the second chipset of the chip array is greater than the spacing between other adjacent computing chips.

[0025] In one embodiment, the circuit board further includes at least two conductive bars and an intermediate conductive element disposed on the board body. The at least two conductive bars correspond one-to-one with at least two rows of chipsets. One conductive bar is connected to multiple computing chips in a corresponding row of chipsets, and the intermediate conductive element is connected between at least two rows of chipsets.

[0026] In one embodiment, a conductive busbar of a plurality of computing chips connected to a first chipset of a chip array is a first conductive busbar, and a conductive busbar of a plurality of computing chips connected to a second chipset of a chip array is a second conductive busbar.

[0027] The second conductive bus has a power supply input terminal located on a first side of the second chipset in a first direction, and the first conductive bus has a power supply output terminal located on a first side of the first chipset in a first direction. The power supply input terminal of the second conductive bus is connected to a voltage converter, and the power supply output terminal of the second conductive bus is connected to the power ground terminal of an electrical connector.

[0028] In one embodiment, an intermediate conductive element is disposed on a second side of at least two rows of chipsets in a first direction and connected between at least two rows of chipsets.

[0029] In one embodiment, the voltage converter includes a voltage regulation module, which includes a voltage control chip, an input voltage switching element, and an output voltage switching element. The voltage control chip is used to control the on / off state of the input voltage switching element and the output voltage switching element according to a preset voltage range.

[0030] In one embodiment, the input voltage switching element and the output voltage switching element are metal-oxide-semiconductor field-effect transistors.

[0031] In one embodiment, the voltage converter includes a voltage regulator module, which includes an input capacitor element, an output capacitor element, and an inductor element. The input capacitor element is connected between the power input terminal of the electrical connector and the input terminal of the input voltage switching element.

[0032] The input terminal of the inductor is connected to the output terminal of the input voltage switching element and the input terminal of the output voltage switching element, respectively. The output terminal of the inductor is connected to the input terminal of the output capacitor element and the power supply input terminal of the chip array, respectively.

[0033] In one embodiment, the inductor is adjacent to a second chip group of the chip array on a first side in a first direction.

[0034] In one embodiment, the number of input capacitor elements is at least two, the at least two input capacitor elements are connected in parallel, the at least two input capacitor elements are disposed on a first side of the inductor element in a first direction, and the at least two input capacitor elements are spaced apart in a second direction.

[0035] In one embodiment, the number of output capacitor elements is at least two, and the at least two output capacitor elements are connected in parallel. Some of the output capacitor elements are disposed on the side of the second chip group of the chip array away from the first chip group and located on the second side of the inductor element in the first direction; the other part of the output capacitor elements are disposed on the side of the inductor element adjacent to the first chip group in the second direction.

[0036] In one embodiment, the input voltage switching element and the output voltage switching element are disposed within a region defined between the input capacitor element, the inductor element, the output capacitor element, and the voltage control chip.

[0037] In one embodiment, the board body has a clearance notch on one side of the first chipset of the chip array in the second direction, the clearance notch extending from the second side of the board body in the first direction toward the side adjacent to the electrical connector.

[0038] In one embodiment, the ratio of the extension dimension of the plate in the first direction to the extension dimension of the plate in the second direction ranges from 1.5:1 to 3.5:1.

[0039] In one embodiment, the board body is formed with a plurality of fixing holes, including a plurality of first fixing holes located on both sides of the board body in a first direction and a plurality of second fixing holes located between a first chipset and a second chipset of the chip array.

[0040] As another aspect of the present application, the present application provides a computing device including a circuit board of any of the above embodiments.

[0041] In one embodiment, the computing device further includes a control board connected to an electrical connector on the circuit board.

[0042] According to the embodiments of the present application, the circuit board and computing device integrate electrical connectors and voltage converters on the circuit board body, enabling the output of the required stable voltage to the circuit board without adding an additional power supply module, thereby ensuring the stability and reliability of the circuit board.

[0043] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0044] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0045] Figure 1 is a schematic front view of a circuit board provided as an example of an embodiment of this application;

[0046] Figure 2 is a schematic diagram of the three-dimensional structure of a circuit board provided as an example of an embodiment of this application;

[0047] Figure 3 is a schematic diagram of the front view structure of a circuit board provided as an example of an embodiment of this application.

[0048] Explanation of reference numerals in the attached drawings: 21-Circuit board, 211-Electrical connector, 2111-Power input terminal, 2112-Power ground terminal, 2113-Signal connection terminal, 210-Board body, 22-Chipset, 213-Computing chip, 23-First chipset, 24-Second chipset, 25-Conductive bus, 251-First conductive bus, 252-Second conductive bus, 253-Power input terminal, 254-Power output terminal, 26-Intermediate conductive component, 212-Positioning hole, 216-First fixing hole, 217-Second fixing hole, 2201-Avoidance notch; 27-Voltage converter, 271-Input voltage switching element, 272-Output voltage switching element, 273-Voltage control main chip, 274-Voltage control auxiliary chip, 275-Diode, 276-Resistor element, 277-Input capacitor element, 278-Inductor element, 279-Output capacitor element; L1 - First direction, L2 - Second direction, L3 - Power supply line, L4 - Signal line. Detailed Implementation

[0049] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0050] In related technologies, a separate power supply module is used to power the circuit board of the computing device. The power supply module is designed and regulated to provide a stable output voltage to the circuit board, meeting its operating requirements. However, the addition of a power supply module increases space occupation and weight, as well as circuit complexity and cost.

[0051] The present application aims to solve the above problems by providing a circuit board 21, which aims to eliminate the need for a separate power supply module while meeting the power requirements of the circuit board 21.

[0052] Figure 1 is an exemplary front view of the circuit board 21 according to an embodiment of this application; Figure 2 is an exemplary perspective view of the circuit board 21 according to an embodiment of this application; and Figure 3 is an exemplary front view of the circuit board 21 according to an embodiment of this application.

[0053] As shown in Figure 1, the circuit board 21 of this embodiment includes a board body 210, a chip array disposed on the board body 210, an electrical connector 211, and a voltage converter 27. The electrical connector 211 is disposed on the board body 210 and is used to supply power to the voltage converter 27. The voltage converter 27 is disposed on the board body 210 and is used to supply power to the chip array according to a preset voltage range. The circuit board 21 electrically connects the voltage converter 27 to the power supply component via the electrical connector 211. The voltage converter 27 adjusts the voltage input to the power supply component to the voltage required by the circuit board 21, thus eliminating the limitation on the type of power supply component and meeting the power supply requirements of the circuit board 21.

[0054] The power supply component can be the control board of the computing device, which can draw power from the mains. Alternatively, the power supply component can be a power adapter, which can draw power directly from the mains.

[0055] The voltage converter 27 can be a DC-DC converter, such as a switching buck converter that converts a higher DC voltage to a lower DC voltage, an adjustable output voltage converter, or an AC-DC converter, etc., and is not limited thereto. The electrical connector 211 can be a pin header type, a header type, a USB type, etc., and is not limited thereto.

[0056] For example, as shown in FIG1, at least a portion of the electrical connector 211 and the voltage converter 27 are disposed on the first side of the chip array in the first direction L1, which facilitates the arrangement of the power supply line L3 between the electrical connector 211, the voltage converter 27 and the chip array.

[0057] For example, the chip array includes at least two rows of chip groups 22, which are spaced apart in a second direction L2. Each row of chip groups 22 includes a plurality of computing chips 213 spaced apart in a first direction L1 to improve computing performance. In the example shown in FIG1, the chip array includes two rows of chip groups 22. In other examples, the chip array may include three or more rows of chip groups 22.

[0058] In the example shown in Figure 1, the row of chipsets 22 adjacent to the electrical connector 211 is the first chipset 23, and the row of chipsets 22 away from the electrical connector 211 is the second chipset 24. The electrical connector 211 is disposed on the first side of the first chipset 23 in the first direction L1 and is located on the side of the first chipset 23 away from the second chipset 24. That is, the electrical connector 211 is closer to the first side of the first chipset 23 in the first direction L1, which facilitates the connection between the electrical connector 211 and the chip array.

[0059] In an example where the chip array includes two rows of chip groups 22, one row of chip groups 22 adjacent to the electrical connector 211 is the first chip group 23, and the other row of chip groups 22 is the second chip group 24. In an example where the chip array includes two or more rows of chip groups 22, the row of chip groups 22 closest to the electrical connector 211 is the first chip group 23, and the row of chip groups 22 farthest from the electrical connector 211 is the second chip group 24.

[0060] As can be understood, as shown in Figures 1 and 3, the electrical connector 211 has a power input terminal 2111 and a power ground terminal 2112. The power input terminal 2111 is connected to the second chipset 24 via a voltage converter 27, and the power ground terminal 2112 is connected to the first chipset 23. That is, the power ground terminal 2112 is connected to the first chipset 23, which is closer to it, via a power supply line L3, shortening the length of the power supply line L3 connecting the first chipset 23 and the power ground terminal 2112, and reducing the crossing of the power supply line L3 at the ground terminal with other lines.

[0061] In some examples, multiple computing chips 213 in the chip array are connected in series, meaning the entire chip array is powered in series. In other examples, the multiple computing chips 213 in the chip array can be connected in parallel or in a hybrid series-parallel configuration.

[0062] In some examples, each computing chip 213 in the chip array may have the same model number. In other examples, each computing chip 213 in the chip array may have the same size. These are merely examples and do not constitute a limitation of this application. Each computing chip 213 in the chip array may also have the same specifications or functions, etc., and is not limited thereto.

[0063] For example, the second side of the first chipset 23 in the first direction L1 is electrically connected to the second side of the second chipset 24 in the first direction L1 (as shown by the intermediate conductive element 26 in FIG1). That is, when the chip array includes two rows of chipsets 22, the second side of the first chipset 23 in the first direction L1 is directly electrically connected to the second side of the second chipset 24 in the first direction L1. When the chip array includes two or more rows of chipsets 22, the second side of the first chipset 23 in the first direction L1 is electrically connected to the second side of the second chipset 24 in the first direction L1 through the chipset 22 between the first chipset 23 and the second chipset 24, thus realizing the series connection of each computing chip 213 in the chip array.

[0064] For example, referring to Figures 1 to 3, the first chipset 23 is connected to the power ground terminal 2112 on the first side of the first direction L1, and the second chipset 24 is connected to the voltage converter 27 on the first side of the first direction L1. That is, the ends of the first chipset 23 and the second chipset 24 on the same side of the first direction L1, i.e. the first side, serve as the ground terminal and the power supply terminal, respectively. This facilitates the arrangement of the power supply line L3 between the electrical connector 211, the voltage converter 27, and the chip array, increases the compactness of the components on the circuit board 21, and reduces the overall size of the circuit board 21.

[0065] In some examples, the electrical connections of the individual computing chips 213 in the chip array can be made using conductive components (such as conductive copper busbars) to improve current carrying capacity and reduce resistance. Furthermore, the good thermal conductivity of the conductive components allows for effective heat dissipation from the chips.

[0066] In other examples, the electrical connections of each computing chip 213 in the chip array can be made through power supply lines provided on the board 210. This connection method occupies little space and enables miniaturization and high integration of the circuit board 21.

[0067] It should be noted that this is merely an example and does not constitute a limitation on this application. Those skilled in the art will understand that the electrical connections of each computing chip 213 can also be made by combining conductive parts and power supply lines, and are not limited to this.

[0068] In a specific example, as shown in Figure 1, the electrical connections of each computing chip 213 in the chip array are made through conductive elements. The board body 210 is provided with at least two conductive bars 25 and intermediate conductive elements 26. The at least two conductive bars 25 correspond one-to-one with at least two rows of chip groups 22. One conductive bar 25 is connected to multiple computing chips 213 in the corresponding row of chip groups 22. The intermediate conductive elements 26 are connected between at least two rows of chip groups 22. That is, each computing chip 213 in the chip group 22 is connected in series through the conductive bars 25, and the computing chips 213 between chip groups 22 are connected in series through the intermediate conductive elements 26.

[0069] In some examples, the conductive busbar 25 and the intermediate conductive element 26 can be integrally formed. In other examples, the conductive busbar 25 and the intermediate conductive element 26 are separate components. In the examples where the conductive busbar 25 and the intermediate conductive element 26 are separate components, the conductive busbar 25 and the intermediate conductive element 26 may each include an integrally formed conductive sheet or include multiple conductive sheets. In the examples where the conductive busbar 25 includes multiple conductive sheets and / or the intermediate conductive element 26 includes multiple conductive sheets, power supply lines can be provided in the gap areas between the multiple conductive sheets on the plate 210 to connect the multiple conductive sheets.

[0070] The conductive busbar 25, the intermediate conductive component 26 and the plate 210 can be fixed by welding, fasteners or other means, and are not limited to these.

[0071] In some examples, as shown in Figure 3, the voltage converter 27 is connected to the busbar 25 via a power supply line, and the power ground terminal 2112 of the electrical connector 211 is connected to the busbar 25 via a power supply line L3, thereby realizing the electrical connection between the chip array and the voltage converter 27 and the electrical connector 211. In other examples, the power ground terminal 2112 of the voltage converter 27 and the electrical connector 211 are directly connected to each computing chip 213 of the chip array via the power supply line L3.

[0072] In a specific example, as shown in Figures 1 and 3, a conductive bus 25 of the plurality of computing chips 213 connected to the first chipset 23 of the chip array is a first conductive bus 251, and a conductive bus 25 of the plurality of computing chips 213 connected to the second chipset 24 of the chip array is a second conductive bus 252. The second conductive bus 252 has a power supply input terminal 253 located on a first side of the second chipset 24 in a first direction L1, and the first conductive bus 251 has a power supply output terminal 254 located on a first side of the first chipset 23 in the first direction L1. The power supply input terminal 253 of the second conductive bus 252 is connected to a voltage converter 27, and the power supply output terminal 254 of the second conductive bus 252 is connected to the power ground terminal 2112 of the electrical connector 211.

[0073] For example, referring to Figure 1, the intermediate conductive element 26 is disposed on the second side of at least two rows of chipsets 22 in the first direction L1 and connected between the at least two rows of chipsets 22, thereby connecting the second sides of each chipset 22 in series in the first direction L1. At the same time, the intermediate conductive element 26 is arranged separately from the electrical connector 211 and voltage converter 27 on the first side of the first direction L1, making the layout more reasonable and making full use of the space of the board 210.

[0074] For example, as shown in Figure 3, the electrical connector 211 has a signal connection end 2113, which is connected to the chip array. Through the electrical connector 211, data is transmitted between the control board and the computing chip 213 of the chip array, so that the computing chip 213 can perform calculations, analysis and other processing on the data and provide feedback on the data processing results.

[0075] For example, referring to Figure 3, the power ground terminal 2112, power input terminal 2111 and signal connection terminal 2113 of the electrical connector 211 are arranged in the first direction L1 to facilitate the electrical connection between the electrical connector 211 and the voltage converter 27 and the chip array.

[0076] In the example shown in Figure 3, the electrical connector 211 can be a long strip extending along the first direction L1. The electrical connector 211 has two rows of sockets spaced apart along the second direction L2. The two rows of sockets extend along the first direction L1 respectively, and the two rows of pinholes define a power ground terminal 2112, a power input terminal 2111 and a signal connection terminal 2113 arranged sequentially along the first direction L1.

[0077] In other examples, the electrical connector 211 may be a strip extending along the second direction L2, and the electrical connector 211 may be a pin-type or a header-type.

[0078] It should be noted that the above are merely illustrative examples and do not constitute a limitation on this application. Those skilled in the art will understand that the electrical connector 211 can also be a regular shape such as a circle or rectangle, or an irregular shape, and is not limited thereto. The connection method of the electrical connector 211 can also be USB, and is not limited thereto.

[0079] For example, as shown in Figure 3, the signal connection terminal 2113 is connected to the side of the first chipset 23 of the chip array away from the second chipset 24 via the signal line L4, and is connected to the computing chip 213 in the first chipset 23 that is closest to the signal connection terminal 2113. On the one hand, this allows the signal line L4 to avoid the power supply line L3 that connects the first chipset 23 to the power ground terminal 2112, thereby avoiding interference from grounding noise and ensuring the reliability and stability of the signal. On the other hand, it can shorten the length of the signal line L4, reduce signal delay, and simplify wiring design.

[0080] For example, signal line L4 connects computing chip 213 to a computing chip 213 on a first side in the second direction L2, and further connects computing chip 213 to an adjacent computing chip 213 on a second side in the second direction L2, so as to connect the computing chips 213 in the first chipset 23 and the second chipset 24 in series. Referring to Figures 1 and 3, in the first chipset 23, signal line L4 connects the upper side of computing chip 213 (i.e., the side of the second direction L2 away from the second chipset 24) to the rightmost computing chip 213 (i.e., the computing chip 213 closest to the signal connection terminal 2113), connects the lower side of the rightmost computing chip 213 (i.e., the other side in the second direction L2) to the adjacent computing chip 213 on the left, and then connects the upper side of the left computing chip 213 to the next computing chip 213 on the left, and so on, so that signal line L4 connects the computing chips 213 in the first chipset 23 in series. The computing chip 213 at the end of the first chipset 23 (i.e., the leftmost computing chip 213) is then connected to the computing chip 213 in the second chipset 24, and each computing chip 213 in the second chipset 24 is then connected in sequence, thus connecting the second chipset 24 and the first chipset 23 in series.

[0081] In some examples, the computing chip 213 farthest from the signal connection terminal 2113 in the first chipset 23 is signal-connected to the computing chip 213 farthest from the signal connection terminal 2113 in the second chipset 24. That is, the signal line L4 in the first chipset 23 is transmitted from the nearest computing chip 213 to the farthest computing chip 213, and then from the farthest computing chip 213 to the computing chip 213 closest to the farthest computing chip 213 in the second chipset 24, so as to shorten the signal line L4. Referring to Figures 1 and 3, the signal line L4 starts from the rightmost computing chip 213 in the first chipset 23, and is transmitted sequentially to each computing chip 213 on the left, then from the leftmost computing chip 213 to the leftmost computing chip 213 in the second chipset 24, and then sequentially to each computing chip 213 on the right, completing the signal transmission between the first chipset 23 and the second chipset 24.

[0082] In other examples, signal line L4 can be transmitted from a computing chip 213 located in the middle of the first chipset 23, and then sequentially transmitted to adjacent computing chips 213 and computing chips 213 in the second chipset 24.

[0083] It should be noted that the above are merely illustrative examples and do not constitute a limitation on this application. Those skilled in the art will understand that the transmission path of signal line L4 is not limited to the above examples. For example, signal line L4 may first pass through the second chipset 24 and then be transmitted to the first chipset 23, and then be transmitted sequentially from the computing chip 213 of the second chipset 24 to other computing chips 213 at the signal connection terminal 2113. It is not limited to this.

[0084] In some examples, the number of computing chips 213 in the first chipset 23 can be odd. When the number of computing chips 213 in the first chipset 23 is odd, when the signal line L4 is transmitted to the leftmost computing chip 213 of the first chipset 23, it can be led out from the lower side of the computing chip 213 (that is, the side of the computing chip 213 closer to the second chipset 24 in the second direction L2). In this way, the signal line L4 can continue to be transmitted from the lower side of the computing chip 213 to the leftmost computing chip 213 of the second chipset 24, thereby shortening the signal line L4 and ensuring the stability of signal transmission.

[0085] In other examples, the number of computing chips 213 in the first chipset 23 can be an even number.

[0086] The total number of computing chips 213 in the chip array can be determined based on the computing power required by the circuit board 21. Furthermore, the number of computing chips 213 in the first chipset 23 and the number of computing chips 213 in the second chipset 24 can be determined based on the component layout design requirements of the circuit board 21. The number of computing chips 213 in the second chipset 24 can be odd or even; this embodiment does not limit this number.

[0087] In some examples, the number of computing chips 213 in the first chipset 23 is greater than the number of computing chips 213 in the second chipset 24. That is, the first chipset 23, which is closer to the signal connection terminal 2113, has more computing chips 213, while the second chipset 24, which is relatively farther from the signal connection terminal 2113, has fewer computing chips 213. This is to ensure that the signal can be transmitted to more computing chips 213 in the same amount of time, thereby improving the signal transmission efficiency.

[0088] In other examples, the number of computing chips 213 in the first chipset 23 may be the same as the number of computing chips 213 in the second chipset 24.

[0089] It should be noted that the above is merely illustrative and does not constitute a limitation on this application. Those skilled in the art will understand that the number of computing chips 213 in the first chipset 23 may also be less than the number of computing chips 213 in the second chipset 24.

[0090] In some examples, the spacing between two adjacent computing chips 213 in the second chipset 24 is greater than the spacing between other adjacent computing chips 213. For example, referring to FIG1, the spacing between adjacent computing chips 213 on the first side of the first direction L1 in the second chipset 24 is greater than the spacing between adjacent computing chips 213 on the second side of the first direction L1, that is, the spacing between adjacent computing chips 213 on the right side of the second chipset 24 is greater than the spacing between adjacent computing chips 213 on the left side.

[0091] Understandably, when the board 210 reserves the same arrangement space for the first chipset 23 and the second chipset 24, if the number of computing chips 213 in the first chipset 23 is greater than the number of computing chips 213 in the second chipset 24, it is equivalent to reducing the number of chips in the second chipset 24, that is, removing some computing chips 213 in the second chipset 24 and increasing the spacing between some adjacent computing chips 213.

[0092] In the example shown in Figure 1, the spacing between adjacent computing chips 213 in the middle region of the second chipset 24 is greater than the spacing between adjacent computing chips 213 on both sides. This can be understood as follows: if two computing chips 213 are removed from the middle region of the second chipset 24, the spacing between adjacent computing chips 213 in the remaining middle region is equivalent to twice the spacing between other adjacent computing chips 213 and the sum of the sizes of the two computing chips 213 themselves.

[0093] It should be noted that the above is merely illustrative and does not constitute a limitation on this application. Those skilled in the art will understand that the spacing between two adjacent computing chips 213 in the second chipset 24 may be uniform or partially uniform, and is not limited to this.

[0094] Understandably, different electronic components require different operating voltages. When the computing device uses other electronic components, such as the control board, to power the circuit board 21, it needs to use the voltage converter 27 to convert the output voltage of the control board into the voltage required by the circuit board 21.

[0095] As exemplarily shown in Figure 1, the voltage converter 27 includes a voltage regulation module, which comprises a voltage control chip, an input voltage switching element 271, and an output voltage switching element 272. The voltage control chip controls the on / off states of the input voltage switching element 271 and the output voltage switching element 272 according to a preset voltage range. The voltage control chip can monitor the output voltage of the voltage converter 27 in real time to determine whether the actual output voltage is within the preset voltage range. If the output voltage of the voltage converter 27 does not fall within the preset voltage range, the voltage control chip will adjust the on / off times of the input voltage switching element 271 and the output voltage switching element 272 to stabilize the output voltage of the voltage converter 27 and bring it within the preset voltage range, thus meeting the operating requirements of the chip array.

[0096] In some examples, the input voltage switching element 271 and the output voltage switching element 272 can be metal-oxide-semiconductor field-effect transistors, that is, the input voltage switching element 271 is a high-side MOS (Metal Oxide Semiconductor) field-effect transistor and the output voltage switching element 272 is a low-side MOS field-effect transistor, so as to reduce the on-resistance and improve the efficiency of the voltage converter 27.

[0097] In other examples, the input voltage switching element 271 can be an insulated gate bipolar transistor (IGBT) or a bipolar junction transistor (BJT), and the output voltage switching element 272 can be a freewheeling diode, but is not limited to these.

[0098] Understandably, the signal connection terminal 2113 of the electrical connector 211 can output two signals. One signal is transmitted to the chip array, enabling the computing chip 213 to perform calculations and analysis. The other signal is transmitted to the voltage control chip, enabling the voltage control chip to control the input voltage switching element 271 and the output voltage switching element 272.

[0099] For example, the voltage control chip may include a main voltage control chip 273 and a secondary voltage control chip 274. The main voltage control chip 273 is responsible for generating pulse width modulation (PWM) signals to control the on and off states of the input voltage switching element 271 and the output voltage switching element 272. The secondary voltage control chip 274 may include a startup circuit, a bias power supply, and protection circuits to provide auxiliary power management and a stable power supply for the main voltage control chip 273 and other auxiliary circuits.

[0100] The voltage regulation module also includes a resistor element 276 and a diode 275. The resistor element 276 may include a voltage divider resistor, a current monitoring resistor, and a start-up resistor. The voltage regulation module obtains a feedback signal of the output voltage of the voltage converter 27 through the voltage divider resistor. This feedback signal is input to the error amplifier in the voltage control main chip 273, compared with a preset voltage range, and generates an error signal. This error signal is input to the PWM control circuit of the voltage control main chip 273. The PWM control circuit adjusts the duty cycle of the PWM based on the error signal. The duty cycle determines the on-time and off-time of the input voltage switching element 271 and the output voltage switching element 272 to adjust the output voltage of the voltage converter 27 to the preset voltage range. The current sensing resistor monitors the current magnitude through the voltage drop across it, providing a current sensing signal for overcurrent protection and current-mode control. The start-up resistor provides the initial start-up current for the voltage control main chip 273. The diode 275 protects components in the circuit from damage caused by overvoltage or reverse voltage.

[0101] For example, the voltage converter 27 includes a voltage regulator module, which includes an input capacitor element 277, an output capacitor element 279, and an inductor element 278. The input capacitor element 277 is connected between the power input terminal 2111 of the electrical connector 211 and the input terminal of the input voltage switch element 271. The input terminal of the inductor element 278 is connected to the output terminal of the input voltage switch element 271 and the input terminal of the output voltage switch element 272, respectively. The output terminal of the inductor element 278 is connected to the input terminal of the output capacitor element 279 and the power supply input terminal 253 of the chip array, respectively.

[0102] Input capacitor 277 filters the input voltage of electrical connector 211, reducing input voltage ripple. When input voltage switch 271 is turned on, the input voltage provides energy to the chip array and output capacitor 279 through inductor 278. Output capacitor 279 filters the output voltage, reducing output voltage ripple and providing a stable DC output to the chip array. When input voltage switch 271 is turned off and output voltage switch 272 is turned on, the energy stored in inductor 278 is released through input voltage switch 271 to maintain the output voltage. Inductor 278 is responsible for storing energy and smoothing current, reducing transient current changes, and maintaining a continuous current supply.

[0103] To facilitate understanding, the voltage regulation and stabilization process of voltage converter 27 is illustrated below with a specific example.

[0104] Referring to Figures 1 to 3, one end of the input capacitor element 277 is connected to the power input terminal 2111 of the electrical connector 211, and the other end is connected to the drain of the input voltage switch element 271. The source of the input voltage switch element 271 is connected to the drain of the inductor element 278 and the output voltage switch element 272. The gate of the input voltage switch element 271 is connected to the PWM signal output of the voltage control chip. The source of the output voltage switch element 272 is grounded, the drain is connected to the drain of the output voltage switch element 272 and the inductor element 278, and the gate is connected to the PWM output of the voltage control chip. One end of the output capacitor element 279 is connected to the output voltage of the inductor element 278, and the other end is connected to ground. The power supply input terminal of the chip array is connected to the output voltage of the inductor element 278, and the power supply output terminal is connected to ground.

[0105] Initially, input voltage switch 271 is turned on, and output voltage switch 272 is turned off. The input voltage of connector 211 provides current to the output terminal through input capacitor 277, input voltage switch 271, and inductor 278, charging output capacitor 279 and powering the chip array. Simultaneously, the current in inductor 278 increases stepwise, storing energy. During this process, the voltage control chip monitors the output voltage of voltage converter 27, obtains the output voltage signal through feedback circuit, and compares it with a preset voltage range. When the output voltage is lower than the preset voltage range, the voltage control chip increases the duty cycle, extending the on-time of input voltage switch 271; when the output voltage is higher than the preset voltage range, the voltage control chip decreases the duty cycle, shortening the on-time of input voltage switch 271.

[0106] When the PWM signal goes low, the input voltage switch 271 turns off, and the output voltage switch 272 turns on. The energy of the inductor 278 is released through the output voltage switch 272, continuing to supply current to the output terminal, while the current in the inductor 278 gradually decreases. When the PWM signal goes high, the input voltage switch 271 turns on, and the output voltage switch 272 turns off. The input voltage is transmitted to the output terminal through the input voltage switch 271 and the inductor. The input voltage switch 271 and the output voltage switch 272 cycle on and off in this periodic manner, continuously providing a stable output voltage to the chip array and meeting the power supply requirements of the chip array.

[0107] In some examples, referring to Figure 1, the inductor 278 is located adjacent to the first side of the second chipset 24 of the chip array in the first direction L1, which facilitates the connection of the inductor 278 to the power supply input terminal 253 of the second chipset 24 and shortens the power supply line.

[0108] In some examples, referring to Figure 1, the number of input capacitor elements 277 is at least two, and the at least two input capacitor elements 277 are connected in parallel to reduce power supply noise and ripple, thereby improving the filtering effect. At the same time, multiple input capacitor elements 277 can share the current, reducing the current load of each input capacitor element 277 and extending the life of the input capacitor elements 277.

[0109] It is understood that at least two input capacitor elements 277 are disposed on the first side of the inductor element 278 in the first direction L1, and at least two input capacitor elements 277 are spaced apart in the second direction L2, so as to facilitate the connection between the input capacitor elements 277 and the inductor element 278.

[0110] In some examples, referring to Figure 1, the number of output capacitor elements 279 is at least two, and at least two output capacitor elements 279 are connected in parallel to reduce power supply noise and ripple, and improve the filtering effect. Multiple output capacitor elements 279 can share the current, reduce the current load of each output capacitor element 279, and extend the life of the output capacitor elements 279.

[0111] Referring again to Figure 1, some of the output capacitor elements 279 are disposed on the side of the second chip group 24 of the chip array away from the first chip group 23 and on the second side of the inductor element 278 in the first direction L1. Other output capacitor elements 279 are disposed on the side of the inductor element 278 in the second direction L2 adjacent to the first chip group 23, so as to better utilize the space of the circuit board 21.

[0112] In some examples, referring to Figure 1, the number of output voltage switching elements 272 is at least two, and the at least two output voltage switching elements 272 are connected in parallel to reduce conduction losses, reduce the current load of each output voltage switching element 272, thereby reducing the power consumption and heat generation of each output voltage switching element 272, providing a certain degree of redundancy protection, and improving the efficiency and reliability of the voltage converter 27.

[0113] In some examples, the input voltage switching element 271 and the output voltage switching element 272 are located within the area defined between the input capacitor element 277, the inductor element 278, the output capacitor element 279, and the voltage control chip. The distribution of each element is more concentrated, which facilitates the connection of each element and improves the space utilization of the circuit board 21.

[0114] In other examples, the input capacitor element 277, the output capacitor element 279, the input voltage switch element 271, and the output voltage switch element 272 can be freely distributed within the right side region of the plate 210 (the first side region in the first direction L1).

[0115] It should be noted that the above are merely illustrative examples and do not constitute a limitation on this application. Those skilled in the art will understand that the distribution of the above-mentioned components may also be in the upper or lower regions of the plate 210, and is not limited thereto.

[0116] For example, the board body 210 is formed with a plurality of positioning holes 212 and a plurality of fixing holes. The plurality of fixing holes include a plurality of first fixing holes 216 located on one side of the board body 210 in the first direction L1 and a plurality of second fixing holes 217 located between the first chipset 23 and the second chipset 24 of the chip array, which facilitates the positioning and fixing of the board body 210 with other components. For example, the positioning holes 212 can be used to fit with the positioning posts on the heat sink to position the board body 21 with the heat sink and the computing device. The first fixing holes 216 can be used to fix the board body 210 with the heat sink and the housing of the computing device by fasteners. The second fixing holes 217 can be used to fix the board body 210 with the heat sink by fasteners.

[0117] It should be noted that the above are merely examples and do not constitute a limitation on this application. The fixing holes may also be located on both sides of the plate 210 in the second direction L2 or partially on one side in the first direction L1, partially on one side in the second direction L2, etc., and are not limited to these.

[0118] For example, as shown in FIG1, the board body 210 has a clearance notch 2201 on the side adjacent to the first chipset 23 in the second direction L2. The clearance notch 2201 extends from the second side of the board body 210 in the first direction L1 toward the side adjacent to the electrical connector 211. The clearance notch 2201 can be used to avoid other components other than the circuit board 21, such as guide mating parts on the housing of the computing device, which are used for guiding and positioning the bottom shell and cover of the housing during assembly.

[0119] It should be noted that the ratio of the extension dimension of the plate 210 in the first direction L1 to the extension dimension of the plate 210 in the second direction L2 can be set according to the actual design requirements of the computing device.

[0120] For example, the ratio of the extension dimension of the board 210 in the first direction L1 to the extension dimension of the board 210 in the second direction L2 can fall within the range of 1.5:1 to 3.5:1, that is, the length dimension and width dimension of the board 210 meet the aforementioned ratio range, providing suitable space for the arrangement of chip arrays and other electronic components to match the performance and size requirements of computing devices.

[0121] As will be understood by those skilled in the art, the above examples of circuit board 21 can be combined in any way to achieve specific design requirements and functions without departing from the spirit or scope of this application.

[0122] According to another aspect of the embodiments of this application, the embodiments of this application also provide a computing device, including the circuit board 21 of any of the above examples.

[0123] The control board of the computing device can be connected to the electrical connector 211 of the circuit board 21. The output voltage of the control board is converted into an output voltage within a preset range through the voltage converter 27 to meet the power supply requirements of the circuit board 21. This eliminates the need for an additional power supply module, reduces circuit complexity and cost, and shrinks the size and weight of the computing device.

[0124] The circuit board 21 and other components of the computing device in the above embodiments can be derived from various technical solutions that are now and will be known to those skilled in the art, and will not be described in detail here.

[0125] In the description of this specification, it should be understood that the terms "length", "upper", "lower", "front", "rear", "left", "right", "vertical", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0126] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0127] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" can refer to electrical connection or communication; they can be direct connection or indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0128] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0129] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0130] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit board, characterized in that, include: plate body; A chip array is disposed on the board body; Electrical connectors and voltage converters; The electrical connector is disposed on the board and is used to supply power to the voltage converter. The voltage converter is disposed on the board and is used to supply power to the chip array according to a preset voltage range.

2. The circuit board according to claim 1, characterized in that, At least a portion of the electrical connector and the voltage converter are disposed on a first side of the chip array in a first direction.

3. The circuit board according to claim 1, characterized in that, The chip array includes at least two rows of chip groups, which are spaced apart in a second direction, and each row of chip groups includes a plurality of computing chips spaced apart in a first direction.

4. The circuit board according to claim 3, characterized in that, The row of chipsets adjacent to the electrical connector is the first chipset, and the row of chipsets away from the electrical connector is the second chipset. The electrical connector is disposed on the first side of the first chipset in a first direction and is located on the side of the first chipset away from the second chipset.

5. The circuit board according to claim 4, characterized in that, The electrical connector has a power input terminal and a power ground terminal. The power input terminal is connected to the second chipset through the voltage converter, and the power ground terminal is connected to the first chipset. Multiple computing chips in the chip array are connected in series.

6. The circuit board according to claim 5, characterized in that, The first chipset is electrically connected to the second side of the second chipset in the first direction, the first side of the first chipset in the first direction is connected to the power ground terminal, and the second chipset in the first direction is connected to the voltage converter.

7. The circuit board according to any one of claims 1 to 6, characterized in that, The electrical connector has a signal connection end, which is connected to the chip array.

8. The circuit board according to claim 7, characterized in that, The power ground terminal, power input terminal, and signal connection terminal of the electrical connector are arranged in a first direction.

9. The circuit board according to claim 7, characterized in that, The signal connection terminal is connected via a signal line to the side of the first chip group of the chip array that is away from the second chip group, and is connected to the computing chip in the first chip group that is closest to the signal connection terminal.

10. The circuit board according to claim 9, characterized in that, The signal line is connected to the computing chip on one side in the second direction, and connected to an adjacent computing chip on the other side in the second direction.

11. The circuit board according to claim 10, characterized in that, The computing chip in the first chipset that is furthest from the signal connection terminal is connected to the computing chip in the second chipset that is closest to the computing chip.

12. The circuit board according to claim 11, characterized in that, The number of computing chips in the first chipset of the chip array is odd.

13. The circuit board according to claim 12, characterized in that, The number of computing chips in the first chipset of the chip array is greater than the number of computing chips in the second chipset of the chip array.

14. The circuit board according to claim 13, characterized in that, In the second chip group of the chip array, the spacing between two adjacent computing chips is greater than the spacing between other adjacent computing chips.

15. The circuit board according to claim 3, characterized in that, It also includes at least two conductive bars and an intermediate conductive element disposed on the board body. The at least two conductive bars correspond one-to-one with the at least two rows of chipsets. One of the conductive bars is connected to multiple computing chips in a corresponding row of chipsets. The intermediate conductive element is connected between the at least two rows of chipsets.

16. The circuit board according to claim 15, characterized in that, A conductive busbar connected to a plurality of computing chips in a first chip group of the chip array is a first conductive busbar, and a conductive busbar connected to a plurality of computing chips in a second chip group of the chip array is a second conductive busbar; The second conductive bus has a power supply input terminal located on a first side of the second chipset in a first direction, and the first conductive bus has a power supply output terminal located on a first side of the first chipset in a first direction. The power supply input terminal of the second conductive bus is connected to the voltage converter, and the power supply output terminal of the second conductive bus is connected to the power ground terminal of the electrical connector.

17. The circuit board according to claim 15, characterized in that, The intermediate conductive element is disposed on the second side of the at least two rows of chips in the first direction and connected between the at least two rows of chips.

18. The circuit board according to claim 1, characterized in that, The voltage converter includes a voltage regulation module, which includes a voltage control chip, an input voltage switching element, and an output voltage switching element. The voltage control chip is used to control the on / off state of the input voltage switching element and the output voltage switching element according to a preset voltage range.

19. The circuit board according to claim 18, characterized in that, The input voltage switching element and the output voltage switching element are metal-oxide-semiconductor field-effect transistors.

20. The circuit board according to claim 18, characterized in that, The voltage converter includes a voltage regulator module, which includes an input capacitor, an output capacitor, and an inductor. The input capacitor is connected between the power input terminal of the electrical connector and the input terminal of the input voltage switch element. The input terminal of the inductor is connected to the output terminal of the input voltage switch and the input terminal of the output voltage switch, respectively. The output terminal of the inductor is connected to the input terminal of the output capacitor and the power supply input terminal of the chip array, respectively.

21. The circuit board according to claim 20, characterized in that, The inductor is located adjacent to the second chipset of the chip array on the first side in the first direction.

22. The circuit board according to claim 20, characterized in that, The number of input capacitor elements is at least two, the at least two input capacitor elements are connected in parallel, the at least two input capacitor elements are disposed on the first side of the inductor element in the first direction, and the at least two input capacitor elements are spaced apart in the second direction.

23. The circuit board according to claim 20, characterized in that, The number of output capacitor elements is at least two, and the at least two output capacitor elements are connected in parallel. Some of the output capacitor elements are disposed on the side of the second chip group of the chip array away from the first chip group and located on the second side of the inductor element in the first direction; the other part of the output capacitor elements are disposed on the side of the inductor element adjacent to the first chip group in the second direction.

24. The circuit board according to claim 20, characterized in that, The input voltage switching element and the output voltage switching element are disposed within the area defined between the input capacitor element, the inductor element, the output capacitor element, and the voltage control chip.

25. The circuit board according to claim 1, characterized in that, The board has a clearance notch on the side of the board adjacent to the first chip group of the chip array in the second direction, the clearance notch extending from the second side of the board in the first direction toward the side adjacent to the electrical connector.

26. The circuit board according to claim 1, characterized in that, The ratio of the extension dimension of the plate in the first direction to the extension dimension of the plate in the second direction ranges from 1.5:1 to 3.5:

1.

27. The circuit board according to claim 1, characterized in that, The board body has a plurality of fixing holes, including a plurality of first fixing holes located on both sides of the board body in a first direction and a plurality of second fixing holes located between the first chip group and the second chip group of the chip array.

28. A computing device, characterized in that, Includes the circuit board as described in any one of claims 1 to 27.

29. The computing device according to claim 28, characterized in that, It also includes a control board, which is connected to the circuit board via an electrical connector.

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