System and method to use processor performance data to prove correct and intended execution of code and code pathways on an electronic device
The system uses processor performance data to verify correct code execution and detect anomalies, ensuring intended execution and preventing malfunctions or breaches on electronic devices.
WO2026147999A1PCT designated stage Publication Date: 2026-07-09WARNE JAMES FARLEY
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- WARNE JAMES FARLEY
- Filing Date
- 2025-12-30
- Publication Date
- 2026-07-09
AI Technical Summary
Technical Problem
Existing systems struggle to prove correct and intended execution of code and code pathways on electronic devices, leading to potential malfunctions or breaches.
Method used
A system and method that utilizes processor performance data to generate a map representing multiple executions, instrument the code, and analyze performance data to determine the status of the code execution, enabling anomaly detection and remedial actions.
Benefits of technology
Ensures correct and intended execution of code by detecting anomalies and performing remedial actions, thereby preventing malfunctions and breaches.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure US2025061650_09072026_PF_FP_ABST
Abstract
In an embodiment, a first compute device includes a memory and a first processor operatively coupled to the memory. The first processor is configured to send instrumented code to a second compute device that includes a second processor to cause the second processor to execute the instrumented code and generate performance data of the second processor. The instrumented code is generated based on un-instrumented code. The first processor is further configured to determine a status of the instrumented code based on the performance data, where the un-instrumented code has the status of the instrumented code.
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