Array substrate, display substrate and display device

By designing a specific arrangement of bonding pads on the array substrate, staggering the first and second pads, and utilizing the space of the fourth peripheral area to arrange fan-out traces, the problem of achieving a narrow bezel on the bottom side of the display screen is solved, achieving the effects of bezel narrowing and cost reduction.

WO2026153151A1PCT designated stage Publication Date: 2026-07-23BOE TECHNOLOGY GROUP CO LTD +1
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
BOE TECHNOLOGY GROUP CO LTD
Filing Date
2026-01-04
Publication Date
2026-07-23

AI Technical Summary

Technical Problem

When electronic components such as driver chips or flexible circuit boards are bonded to the bottom bezel of a display, it is difficult to achieve a narrow bezel design. Existing technologies require increasing the width and area of ​​the flexible circuit board, which increases the manufacturing difficulty and cost.

Method used

By designing a specific bonding pad arrangement on the array substrate, including the staggered arrangement of multiple first pads and second pads, fan-out traces are arranged using the space of the fourth peripheral area, reducing the bezel width while maintaining electrical connection with the driver chip.

Benefits of technology

This technology enables the narrowing of the bottom bezel of the display screen without increasing the width and area of ​​the flexible circuit board, thereby reducing the manufacturing difficulty and cost.

✦ Generated by Eureka AI based on patent content.

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Abstract

Provided is an array substrate, comprising: a base substrate; a plurality of scan lines extending in a first direction and arranged in a second direction; a plurality of signal lines; a gate driving circuit; and a plurality of bonding pads, comprising a plurality of first pads and a plurality of second pads, wherein the plurality of first pads comprise a plurality of first sub-pads and a plurality of second sub-pads; in a row of the first pads, the plurality of first sub-pads are arranged at intervals in the first direction, and the distance between at least one second sub-pad and a display area in the second direction is different from that between the first sub-pads and the display area; and the second pads comprise a plurality of third sub-pads, one end of each gate signal lead is electrically connected to a corresponding third sub-pad, the other end thereof extends to be electrically connected to the gate driving circuit, and a part of each gate signal lead is located on the side of the plurality of second sub-pads away from the display area.
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