Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a base (100) and at least one first pixel circuit (800), wherein the base (100) comprises a display region (AA), the display region (AA) comprising a first display region (A1); and the at least one first pixel circuit (800) is arranged on the base (100), the orthographic projection of the first pixel circuit (800) on the base (100) is located in the first display region (A1), and the first pixel circuit (800) comprises at least one first transistor (201), the first transistor (201) comprising a first transparent active layer (213) and a first gate (214) arranged in an insulated manner on the side of the first active layer (213) away from the base (100), and the first gate (214) comprising a first light-transmitting conductive layer (229).

Description

Display substrate and its preparation method, display device

[0001] This application claims priority to Chinese Patent Application No. 202510072662.8, filed on January 16, 2025, entitled "Display Substrate and Method for Preparing the Same, Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost.

[0004] The low transmittance of the circuit structure layer of the display substrate, while not affecting the efficiency of the upper light-emitting structure layer, will cause significant loss of the signal required by under-display sensors and cameras. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] This application provides a display substrate, including:

[0007] A substrate, including a display area, the display area including a first display area;

[0008] At least one first pixel circuit is disposed on the substrate, and the orthographic projection of the first pixel circuit on the substrate is located in the first display area;

[0009] The first pixel circuit includes at least one first transistor, the first transistor including a transparent first active layer and a first gate disposed on the side of the first active layer away from the substrate, the first gate including a first light-transmitting conductive layer.

[0010] In some exemplary embodiments, the first transistor further includes a first bottom gate, which is insulated on the side of the first active layer near the substrate, and the first bottom gate includes a second light-transmitting conductive layer.

[0011] In some exemplary embodiments, the first transistor further includes a first source and a first drain, wherein the first source and / or the first drain includes a third transparent conductive layer.

[0012] In some exemplary embodiments, the first pixel circuit includes at least one second transistor, the second transistor including a second gate and a transparent second active layer;

[0013] The second gate is located on the side of the second active layer away from the substrate. The second gate includes a first metal layer and a fourth light-transmitting conductive layer. The fourth light-transmitting conductive layer is located on the side of the first metal layer close to the substrate.

[0014] The orthographic projection of the first metal layer on the substrate lies within the orthographic projection of the fourth transparent conductive layer on the substrate.

[0015] In some exemplary embodiments, the fourth transparent conductive layer and the first transparent conductive layer are made of the same material and are arranged in the same layer.

[0016] In some exemplary embodiments, the second transistor further includes a second bottom gate located on the side of the second active layer near the substrate. The second bottom gate includes a second metal layer and a fifth light-transmitting conductive layer located on the side of the second metal layer near the substrate.

[0017] The orthographic projection of the second metal layer on the substrate lies within the orthographic projection of the fifth light-transmitting conductive layer on the substrate. The fifth light-transmitting conductive layer and the second light-transmitting conductive layer are made of the same material and are arranged in the same layer.

[0018] In some exemplary embodiments, the second active layer includes a first region, a channel region, and a second region arranged sequentially in a first direction, the first direction being parallel to the substrate;

[0019] Both the fourth light-transmitting conductive layer and the first metal layer are configured to extend along a second direction. The first metal layer is centrally disposed on the fourth light-transmitting conductive layer in the first direction. The two ends of the fourth light-transmitting conductive layer in the first direction protrude from the two ends of the first metal layer in the first direction. The second direction is parallel to the substrate and perpendicular to the first direction.

[0020] In some exemplary embodiments, the trench area includes a first auxiliary trench area, a main trench area, and a second auxiliary trench area arranged sequentially in the first direction;

[0021] The orthographic projection of the first metal layer on the substrate is configured to overlap with the orthographic projection of the main channel region on the substrate, but not overlap with the orthographic projections of the first auxiliary channel region and the second auxiliary channel region on the substrate;

[0022] The orthographic projections of the main channel region, the first auxiliary channel region, and the second auxiliary channel region on the substrate all overlap with the orthographic projection of the fourth transparent conductive layer on the substrate.

[0023] In some exemplary embodiments, the first gate further includes a third metal layer located on the side of the first transparent conductive layer away from the substrate, and the orthographic projection of the third metal layer on the substrate is located within the orthographic projection of the first transparent conductive layer on the substrate;

[0024] The orthographic projection area of ​​the first metal layer on the substrate is S1, and the orthographic projection area of ​​the third metal layer on the substrate is S2, where S1 > S2.

[0025] In some exemplary embodiments, the width of the first metal layer is set to D1, the width of the third metal layer is set to D2, D1 > D2, and D1 - D2 ≤ 0.5 μm.

[0026] In some exemplary embodiments, the first active layer and the second active layer are both configured to extend along a first direction, and the first gate and the second gate are both configured to extend along a second direction, wherein the first direction and the second direction are both parallel to the substrate and perpendicular to each other;

[0027] The third metal layer has a dimension of L1 in the second direction, and the first transparent conductive layer has a dimension of L2 in the second direction, where L1 < L2;

[0028] The third metal layer is centrally disposed on the first light-transmitting and conductive layer in the second direction, and the two ends of the first light-transmitting and conductive layer in the second direction respectively protrude from the two ends of the third metal layer in the second direction.

[0029] In some exemplary embodiments, one end of the first transparent conductive layer in the second direction is the first end, and the end of the third metal layer near the first end in the second direction is the second end. The distance between the first end and the second end in the second direction is set to L3, where L3 ≥ 1 μm.

[0030] In some exemplary embodiments, the first pixel circuit includes at least one third transistor, the third transistor including a third gate and a third active layer;

[0031] The material of the third active layer includes polycrystalline silicon;

[0032] The third gate is located on the side of the third active layer away from the substrate. The third gate includes a fourth metal layer and a sixth light-transmitting conductive layer. The sixth light-transmitting conductive layer is located on the side of the fourth metal layer close to the substrate. The orthographic projection of the fourth metal layer on the substrate is located within the orthographic projection of the sixth light-transmitting conductive layer on the substrate.

[0033] In some exemplary embodiments, the first active layer includes a first region, a channel region, and a second region sequentially disposed along a first direction, wherein the channel region includes a third end near the first region and a fourth end near the second region in the first direction, and the first direction is parallel to the substrate;

[0034] The first bottom grid further includes a fifth metal layer, which is located on the side of the second light-transmitting conductive layer away from the substrate, and the orthographic projection of the fifth metal layer on the substrate is located within the orthographic projection of the second light-transmitting conductive layer on the substrate;

[0035] The fifth metal layer is located between the third end and the fourth end in the first direction, and the distance between the fifth metal layer and the third end in the first direction is greater than 0, and the distance between the fifth metal layer and the fourth end in the first direction is greater than 0.

[0036] In some exemplary embodiments, the first display area includes at least one sub-pixel area, the sub-pixel area including a main display area, a high-transmittance trace area and a high-transmittance display area, the high-transmittance display area being located on at least one side of the main display area, the high-transmittance trace area being located between the high-transmittance display area and the main display area, and the orthographic projection of the first transistor on the substrate being located in the high-transmittance display area.

[0037] In some exemplary embodiments, the first pixel circuit further includes a plurality of signal lines, the plurality of signal lines including at least one transparent first signal line, the orthographic projection of the first signal line on the substrate being located in the high-transparency trace area.

[0038] In some exemplary embodiments, the plurality of signal lines include at least one second signal line, the second signal line including a first trace layer and a transparent second trace layer, the first trace layer being located on the side of the second trace layer away from the substrate, and the orthographic projection of the second signal line on the substrate being located in the high-transparency trace area.

[0039] In some exemplary embodiments, a light-emitting structure layer is also included, which includes a plurality of first light-emitting devices and a pixel definition layer;

[0040] The pixel definition layer is provided with a plurality of first pixel openings for arranging a plurality of first light-emitting devices, and the first light-emitting devices are configured to be electrically connected in a one-to-one correspondence with the first pixel circuit;

[0041] The orthographic projection of the first pixel opening onto the substrate is configured to overlap with the main display area and the high-transparency display area;

[0042] Alternatively, the orthographic projection of the first pixel opening onto the substrate is configured to overlap with the main display area but not with the high-transparency display area.

[0043] In some exemplary embodiments, the material of the first transparent conductive layer includes a transparent conductive oxide, wherein the transparent conductive oxide includes indium tin oxide.

[0044] This application provides a method for preparing a display substrate, including:

[0045] At least one first pixel circuit is formed on a substrate, the substrate including a display area, the display area including a first display area; at least one first pixel circuit is disposed on the substrate, the orthographic projection of the first pixel circuit on the substrate is located in the first display area; the first pixel circuit includes at least one first transistor, the first transistor including a transparent first active layer, and a first gate disposed insulated on the side of the first active layer away from the substrate, the first gate including a first light-transmitting conductive layer.

[0046] In some exemplary embodiments, forming at least one first pixel circuit on the substrate includes:

[0047] The first transistor and the second transistor are formed synchronously on the substrate. The second transistor includes a second gate, which includes a first metal layer and a fourth light-transmitting conductive layer. The fourth light-transmitting conductive layer is located on the side of the first metal layer close to the substrate. The orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the fourth light-transmitting conductive layer on the substrate. The fourth light-transmitting conductive layer and the first light-transmitting conductive layer are made of the same material and are arranged in the same layer.

[0048] This application provides a display device including the display substrate described above.

[0049] The display substrate of this application replaces the gate of the oxide thin-film transistor with a transparent conductive material, which can improve the transmittance of the local under-display recognition area, reduce the signal loss required by under-display sensing and imaging components, and is compatible with under-display camera and under-display sensing module integration schemes. The display substrate of this application also uses transparent conductive materials for the source and drain of the oxide thin-film transistor, making the entire oxide thin-film transistor transparent and further improving transmittance. The display substrate of this application may reduce the size of the metal portion of the gate of the oxide thin-film transistor, while minimizing the number of polysilicon thin-film transistors and increasing the number of oxide thin-film transistors, further improving transmittance.

[0050] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0051] Overview of the attached figures

[0052] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0053] Figure 1 is a schematic diagram of a display device;

[0054] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0055] Figure 3 is a schematic cross-sectional view of a display device;

[0056] Figure 4 is a schematic diagram of a display substrate according to an exemplary embodiment of the present invention;

[0057] Figure 5 is a cross-sectional schematic diagram of the circuit structure layer of the display substrate in Figure 4;

[0058] Figure 6 is an equivalent circuit diagram of a first pixel circuit according to this exemplary embodiment;

[0059] Figure 7 is a magnified view of part a in Figure 5;

[0060] Figure 8 is a schematic diagram of the second gate in Figure 7;

[0061] Figure 9 is a first schematic diagram of another first transistor in this exemplary embodiment;

[0062] Figure 10 is a second schematic diagram of another first transistor in this exemplary embodiment;

[0063] Figure 11 is a first schematic diagram of yet another first transistor of this exemplary embodiment;

[0064] Figure 12 is a second schematic diagram of yet another first transistor of this exemplary embodiment;

[0065] Figure 13 is a magnified view of part b in Figure 5;

[0066] Figure 14 is a first fabrication schematic diagram of a display substrate according to this exemplary embodiment;

[0067] Figure 15 is a second fabrication schematic diagram of a display substrate according to an exemplary embodiment of the present invention;

[0068] Figure 16 is a third fabrication schematic diagram of a display substrate according to this exemplary embodiment;

[0069] Figure 17 is a fourth fabrication schematic diagram of a display substrate according to this exemplary embodiment;

[0070] Figure 18 is a fifth fabrication schematic diagram of a display substrate according to this exemplary embodiment;

[0071] Figure 19 is a sixth fabrication schematic diagram of a display substrate according to this exemplary embodiment;

[0072] Figure 20 is a seventh fabrication schematic diagram of a display substrate according to this exemplary embodiment;

[0073] Figure 21 is an eighth fabrication schematic diagram of a display substrate according to this exemplary embodiment;

[0074] Figure 22 is a ninth schematic diagram of the fabrication of a display substrate according to this exemplary embodiment;

[0075] Figure 23 is a tenth schematic diagram of the fabrication of a display substrate according to this exemplary embodiment;

[0076] Figure 24 is a schematic diagram of the eleventh fabrication step of a display substrate according to this exemplary embodiment;

[0077] Figure 25 is a schematic diagram of the twelfth fabrication step of a display substrate according to this exemplary embodiment;

[0078] Figure 26 is a thirteenth schematic diagram of the fabrication of a display substrate according to this exemplary embodiment;

[0079] Figure 27 is a schematic diagram of the fourteenth fabrication step of a display substrate according to this exemplary embodiment.

[0080] Detailed Explanation

[0081] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0082] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0083] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0084] This exemplary embodiment provides a display substrate, including:

[0085] A substrate, including a display area, the display area including a first display area;

[0086] At least one first pixel circuit is disposed on the substrate, and the orthographic projection of the first pixel circuit on the substrate is located in the first display area;

[0087] The first pixel circuit includes at least one first transistor, the first transistor including a transparent first active layer and a first gate disposed on the side of the first active layer away from the substrate, the first gate including a first light-transmitting conductive layer.

[0088] In some exemplary embodiments, the first transistor further includes a first bottom gate, which is insulated on the side of the first active layer near the substrate, and the first bottom gate includes a second light-transmitting conductive layer.

[0089] In some exemplary embodiments, the first transistor further includes a first source and a first drain, wherein the first source and / or the first drain includes a third transparent conductive layer.

[0090] In some exemplary embodiments, the first pixel circuit includes at least one second transistor, the second transistor including a second gate and a transparent second active layer;

[0091] The second gate is located on the side of the second active layer away from the substrate. The second gate includes a first metal layer and a fourth light-transmitting conductive layer. The fourth light-transmitting conductive layer is located on the side of the first metal layer close to the substrate.

[0092] The orthographic projection of the first metal layer on the substrate lies within the orthographic projection of the fourth transparent conductive layer on the substrate.

[0093] In some exemplary embodiments, the fourth transparent conductive layer and the first transparent conductive layer are made of the same material and are arranged in the same layer.

[0094] In some exemplary embodiments, the second transistor further includes a second bottom gate located on the side of the second active layer near the substrate. The second bottom gate includes a second metal layer and a fifth light-transmitting conductive layer located on the side of the second metal layer near the substrate.

[0095] The orthographic projection of the second metal layer on the substrate lies within the orthographic projection of the fifth light-transmitting conductive layer on the substrate. The fifth light-transmitting conductive layer and the second light-transmitting conductive layer are made of the same material and are arranged in the same layer.

[0096] In some exemplary embodiments, the second active layer includes a first region, a channel region, and a second region arranged sequentially in a first direction, the first direction being parallel to the substrate;

[0097] Both the fourth light-transmitting conductive layer and the first metal layer are configured to extend along a second direction. The first metal layer is centrally disposed on the fourth light-transmitting conductive layer in the first direction. The two ends of the fourth light-transmitting conductive layer in the first direction protrude from the two ends of the first metal layer in the first direction. The second direction is parallel to the substrate and perpendicular to the first direction.

[0098] In some exemplary embodiments, the trench area includes a first auxiliary trench area, a main trench area, and a second auxiliary trench area arranged sequentially in the first direction;

[0099] The orthographic projection of the first metal layer on the substrate is configured to overlap with the orthographic projection of the main channel region on the substrate, but not overlap with the orthographic projections of the first auxiliary channel region and the second auxiliary channel region on the substrate;

[0100] The orthographic projections of the main channel region, the first auxiliary channel region, and the second auxiliary channel region on the substrate all overlap with the orthographic projection of the fourth transparent conductive layer on the substrate.

[0101] In some exemplary embodiments, the first gate further includes a third metal layer located on the side of the first transparent conductive layer away from the substrate, and the orthographic projection of the third metal layer on the substrate is located within the orthographic projection of the first transparent conductive layer on the substrate;

[0102] The orthographic projection area of ​​the first metal layer on the substrate is S1, and the orthographic projection area of ​​the third metal layer on the substrate is S2, where S1 > S2.

[0103] In some exemplary embodiments, the width of the first metal layer is set to D1, the width of the third metal layer is set to D2, D1 > D2, and D1 - D2 ≤ 0.5 μm.

[0104] In some exemplary embodiments, the first active layer and the second active layer are both configured to extend along a first direction, and the first gate and the second gate are both configured to extend along a second direction, wherein the first direction and the second direction are both parallel to the substrate and perpendicular to each other;

[0105] The third metal layer has a dimension of L1 in the second direction, and the first transparent conductive layer has a dimension of L2 in the second direction, where L1 < L2;

[0106] The third metal layer is centrally disposed on the first light-transmitting and conductive layer in the second direction, and the two ends of the first light-transmitting and conductive layer in the second direction respectively protrude from the two ends of the third metal layer in the second direction.

[0107] In some exemplary embodiments, one end of the first transparent conductive layer in the second direction is the first end, and the end of the third metal layer near the first end in the second direction is the second end. The distance between the first end and the second end in the second direction is set to L3, where L3 ≥ 1 μm.

[0108] In some exemplary embodiments, the first pixel circuit includes at least one third transistor, the third transistor including a third gate and a third active layer;

[0109] The material of the third active layer includes polycrystalline silicon;

[0110] The third gate is located on the side of the third active layer away from the substrate. The third gate includes a fourth metal layer and a sixth light-transmitting conductive layer. The sixth light-transmitting conductive layer is located on the side of the fourth metal layer close to the substrate. The orthographic projection of the fourth metal layer on the substrate is located within the orthographic projection of the sixth light-transmitting conductive layer on the substrate.

[0111] In some exemplary embodiments, the first active layer includes a first region, a channel region, and a second region sequentially disposed along a first direction, wherein the channel region includes a third end near the first region and a fourth end near the second region in the first direction, and the first direction is parallel to the substrate;

[0112] The first bottom grid further includes a fifth metal layer, which is located on the side of the second light-transmitting conductive layer away from the substrate, and the orthographic projection of the fifth metal layer on the substrate is located within the orthographic projection of the second light-transmitting conductive layer on the substrate;

[0113] The fifth metal layer is located between the third end and the fourth end in the first direction, and the distance between the fifth metal layer and the third end in the first direction is greater than 0, and the distance between the fifth metal layer and the fourth end in the first direction is greater than 0.

[0114] In some exemplary embodiments, the first display area includes at least one sub-pixel area, the sub-pixel area including a main display area, a high-transmittance trace area and a high-transmittance display area, the high-transmittance display area being located on at least one side of the main display area, the high-transmittance trace area being located between the high-transmittance display area and the main display area, and the orthographic projection of the first transistor on the substrate being located in the high-transmittance display area.

[0115] In some exemplary embodiments, the first pixel circuit further includes a plurality of signal lines, the plurality of signal lines including at least one transparent first signal line, the orthographic projection of the first signal line on the substrate being located in the high-transparency trace area.

[0116] In some exemplary embodiments, the material of the first transparent conductive layer includes a transparent conductive oxide, wherein the transparent conductive oxide includes indium tin oxide.

[0117] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels ij, where i and j can be natural numbers. At least one sub-pixel ij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn in unit rows, where n can be a natural number. The scan driver can receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The LED driver can receive clock signals, transmit stop signals, etc., from the timing controller to generate transmit signals to LED signal lines E1, E2, E3, ..., Eo. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0118] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel circuit. The pixel circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is connected to the pixel circuit of the sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.

[0119] In some exemplary embodiments, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In exemplary embodiments, the shape of the sub-pixels may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement, etc., without limitation herein. In some exemplary embodiments, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may be arranged along a straight line, but are not limited thereto; for example, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may be arranged in a non-linear arrangement such as a triangular arrangement. In some exemplary embodiments, a pixel unit P may include four sub-pixels, and the four sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement, without limitation herein.

[0120] Figure 3 is a cross-sectional schematic diagram of a display device, illustrating a structure that achieves full color using a combination of white light and a color filter. As shown in Figure 3, the display device may include: a substrate 100, a circuit structure layer 200 disposed on the substrate 100, a light-emitting structure layer 300 disposed on the side of the circuit structure layer 200 away from the substrate 100, a first encapsulation layer 400 disposed on the side of the light-emitting structure layer 300 away from the substrate 100, a color filter structure layer 500 disposed on the side of the first encapsulation layer 400 away from the substrate 100, a second encapsulation layer 600 disposed on the side of the color filter structure layer 500 away from the substrate 100, and a cover plate layer 700 disposed on the side of the second encapsulation layer 600 away from the substrate 100. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited herein.

[0121] In some exemplary embodiments, the substrate 100 may be a polyimide (PI) substrate, but is not limited thereto; for example, it may be a glass substrate. The circuit structure layer 200 may be fabricated on the substrate 100 using silicon semiconductor processes (e.g., CMOS processes). The circuit structure layer 200 may include multiple circuit units, each of which may include at least a pixel circuit. The pixel circuit is connected to scan signal lines and data signal lines, respectively. The pixel circuit may include multiple transistors and storage capacitors; only one transistor is shown as an example in Figure 3. The transistor may include a gate electrode, a first electrode (S), and a second electrode. The gate electrode, the first electrode, and the second electrode may be connected to corresponding connection electrodes via tungsten-filled vias (i.e., tungsten vias, W-vias), and may be connected to other electrical structures (such as traces) via the connection electrodes.

[0122] In an exemplary embodiment, the light-emitting structure layer 300 may include multiple light-emitting devices. Each light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the second electrode of a transistor via a connecting electrode. The organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to a second power line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0123] In an exemplary embodiment, the first encapsulation layer 400 and the second encapsulation layer 600 can be thin film encapsulation (TFE) to ensure that external moisture cannot enter the light-emitting structure layer. The cover layer 700 can be made of glass or a flexible plastic such as colorless polyimide.

[0124] In an exemplary embodiment, the color filter structure layer 500 may include a black matrix (BM) and color filters (CF). The color filters are respectively disposed in red sub-pixels, green sub-pixels and blue sub-pixels to filter the white light emitted by the light-emitting device into red (R) light, green (G) light and blue (B) light. The black matrix may be located between adjacent color filters.

[0125] The applicant discovered that display devices with under-display sensors and cameras cannot completely solve the fundamental problem of low transmittance in the circuit structure layer. Among the various film layers of the display substrate, the circuit structure layer has the lowest transmittance, only about 10%. While this does not affect the efficiency of the light-emitting structure layer, its low transmittance causes significant signal loss for under-display sensors and cameras. Although some display products use external or internal pixel solutions to alleviate this problem, both significantly degrade display quality and affect the display effect of the under-display recognition area.

[0126] The technical solutions of the embodiments of the present invention will be described in detail below through specific examples.

[0127] Figure 4 is a schematic diagram of a display substrate according to an exemplary embodiment of the present invention, and Figure 5 is a cross-sectional schematic diagram of the circuit structure layer of the display substrate in Figure 4. This exemplary embodiment provides a display substrate, as shown in Figures 4 and 5. The display substrate may include a substrate 100 and at least one first pixel circuit 800. The substrate 100 may include a display area AA, and the display area AA may include a first display area A1. At least one first pixel circuit 800 may be disposed on the substrate 100, and the orthographic projection of the first pixel circuit 800 on the substrate 100 is located in the first display area A1. The first pixel circuit 800 includes at least one first transistor 201. The first transistor 201 includes a transparent first active layer 213 and a first gate 214 insulated on the side of the first active layer 213 away from the substrate 100. The first gate 214 includes a first light-transmitting conductive layer 229. Therefore, in this example, the display substrate uses a transparent conductive material for the first gate 214 of the oxide thin film transistor (first transistor 201), which can improve the transmittance of the local under-display recognition area (i.e., the first display area A1), reduce the loss of signal quantity required by under-display sensing and imaging components, and can be adapted to the integration of under-display camera module and under-display sensing module.

[0128] In some exemplary embodiments, as shown in Figures 4 and 5, the substrate 100 may include a display area AA and a border area BB surrounding the display area AA. The display area AA may include a first display area A1 and a second display area A0. The second display area A0 may surround the first display area A1, but is not limited thereto. For example, the first display area A1 may be located on one side of the second display area A0. The display substrate may have an under-display sensor or an under-display camera, or a device integrating sensing and imaging functions. The orthographic projection of the above-mentioned device on the substrate 100 may be located in the first display area A1. Since light needs to pass through the portion of the display substrate located in the first display area A1, increasing the transmittance of the portion of the display substrate located in the first display area A1 allows more light to reach the under-display sensing and imaging components, reducing the loss of signal required by the under-display sensing and imaging components.

[0129] In some exemplary embodiments, as shown in Figures 4 and 5, the display area AA may include multiple sub-pixel areas arranged in an array, with sub-pixels in the display substrate corresponding to each sub-pixel area. The multiple sub-pixel areas may be evenly distributed in the first display area A1 and the second display area A0, with the sub-pixel area located in the first display area A1 being designated as the first sub-pixel area A1. The display area AA may be a flat region, and the display substrate may have multiple sub-pixels forming a pixel array in the display area AA. These multiple sub-pixels can be configured to display dynamic or still images. The display area AA may be referred to as the active area. In some examples, the display area AA may be rectangular, but this is not a limitation; for example, the display area AA may be circular, elliptical, or other shapes.

[0130] In some exemplary embodiments, as shown in Figures 3, 4, and 5, a sub-pixel may include an electrically connected light-emitting device 301 and a pixel circuit 800. The light-emitting structure layer 300 may be provided with a plurality of light-emitting devices 301 and a pixel definition layer 302, the pixel definition layer 302 having a pixel opening. The light-emitting device 301 of the sub-pixel located in the first display area A1 may be a first light-emitting device (not shown in the figure), the pixel circuit 800 of the sub-pixel located in the first display area A1 may be a first pixel circuit 801, the pixel opening located in the first display area A1 may be a first pixel opening, the first light-emitting device may be arranged corresponding to the first pixel opening, and the first light-emitting device may be connected one-to-one with the first pixel circuit 801.

[0131] Figure 6 is an equivalent circuit diagram of a first pixel circuit according to an exemplary embodiment of the present invention. In some exemplary embodiments, as shown in Figure 6, the first pixel circuit 801 may include seven transistors (transistors T1, T2 to T7), a storage capacitor C, and multiple signal lines (data signal line D, first scan signal line S1, second scan signal line S2, initial signal line INIT, first power supply line VDD, second power supply line VSS, and light emission control signal line E).

[0132] In some exemplary embodiments, as shown in FIG6, the gate electrode of transistor T1 is connected to the second scan signal line S2, the first electrode of transistor T1 is connected to the initial signal line INIT, and the second electrode of transistor T1 is connected to the first node N1. The gate electrode of transistor T2 is connected to the first scan signal line S1, the first electrode of transistor T2 is connected to the third node N3, and the second electrode of transistor T2 is connected to the first node N1. The gate electrode of transistor T3 is connected to the first node N1, the first electrode of transistor T3 is connected to the second node N2, and the second electrode of transistor T3 is connected to the third node N3. The gate electrode of transistor T4 is connected to the first scan signal line S1, the first electrode of transistor T4 is connected to the data signal line D, and the second electrode of transistor T4 is connected to the second node N2. The gate electrode of transistor T5 is connected to the light emission control signal line E, the first electrode of transistor T5 is connected to the first power supply line VDD, and the second electrode of transistor T5 is connected to the second node N2. The gate electrode of transistor T6 is connected to the light-emitting control signal line E, the first terminal of transistor T6 is connected to the third node N3, and the second terminal of transistor T6 is connected to the fourth node N4 (i.e., the first terminal of the light-emitting element). The gate electrode of transistor T7 is connected to the first scan signal line S1 or the reset control signal line Reset, the first terminal of transistor T7 is connected to the initial signal line INIT, and the second terminal of transistor T7 is connected to the fourth node N4. The first terminal of storage capacitor C is connected to the first power supply line VDD, and the second terminal of storage capacitor C is connected to the first node N1.

[0133] In some exemplary embodiments, as shown in Figures 4 and 6, the seven transistors (T1 to T7) can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, transistors T1 to T7 may include both P-type and N-type transistors.

[0134] In some exemplary embodiments, the seven transistors (T1 to T7) can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality. The display substrate in this example can employ LTPO technology.

[0135] In some exemplary embodiments, as shown in Figures 5 and 6, the seven transistors (T1 to T7) can be divided into a first transistor 201, a second transistor 202, and a third transistor 203 according to their materials. The first transistor 201 and the second transistor 202 are both oxide thin-film transistors (TFTs), and the third transistor 203 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. In this example, transistor T3 can be the third transistor 203, i.e., an LTPS thin-film transistor. The other transistors (T1, T2, T4, T5, T6, and T7) can be either the first transistor 201 or the second transistor 202, i.e., transistors (T1, T2, T4, T5, T6, and T7) can be oxide thin-film transistors. However, this is not the only possibility. For example, all seven transistors (T1 to T7) can be oxide thin-film transistors; the seven transistors (T1 to T7) can be divided into the first transistor 201 and the second transistor 202 according to their materials; or all seven transistors (T1 to T7) can be the first transistor 201 or all can be the second transistor 202.

[0136] In some exemplary embodiments, as shown in FIG5, the first active layer 213 of the first transistor 201 serves as the active layer of the transistor, and the material of the first active layer 213 may include an oxide semiconductor material. The first gate 214 of the first transistor 201 may serve as the gate electrode of the transistor, and the first gate 214 may be connected to a first transparent conductive layer 229. The material of the first transparent conductive layer 229 may include a transparent conductive oxide (TCO). In this example, the material of the first transparent conductive layer 229 may be indium tin oxide (ITO), but is not limited to this. For example, it may be indium zinc oxide (IZO) or other conductive transparent oxides. The first transistor 201 further includes a first source 216, a first drain 217, and a first bottom gate 215. The first source 216 and the first drain 217 are electrically connected to the first active layer 213 through vias. The first source 216 can serve as the first electrode of the transistor, and the first drain 217 can serve as the second electrode of the transistor. The material of the first source 216 and / or the first drain 217 includes a transparent conductive material. In this example, both the first source 216 and the first drain 217 include a third light-transmitting conductive layer 253. The material of the third light-transmitting conductive layer 253 can be the same as the material of the first light-transmitting conductive layer 229, but is not limited thereto. For example, the material of the third light-transmitting conductive layer 253 of the first source 216 and the first drain 217 can be different from the material of the first light-transmitting conductive layer 229. The first bottom gate 215 may be transparent. The first bottom gate 215 may include a second light-transmitting conductive layer 215-1. The material of the second light-transmitting conductive layer 215-1 may be the same as that of the first light-transmitting conductive layer 229, and may be indium tin oxide, but is not limited to this; for example, it may be other conductive transparent oxides. The first bottom gate 215 is insulated on the side of the first active layer 213 near the substrate 100. The first bottom gate 215 can serve as another gate of the transistor. Thus, the first gate 214, the first source 216, the first drain 217, and the first bottom gate 215 are all made of transparent materials, resulting in an unobstructed light structure for the entire first transistor 201, and thus, the first transistor 201 has high transmittance.

[0137] Figure 7 is a partially enlarged schematic diagram of point a in Figure 5. In some exemplary embodiments, as shown in Figures 5 and 7, the second transistor 202 may include a transparent second active layer 217, a second gate 218, a second bottom gate 219, a second source 220, and a second drain 221. The second active layer 217 serves as the active layer of the transistor. The material of the second active layer 217 may include an oxide semiconductor material. The material of the second active layer 217 may be the same as that of the first active layer 213 and arranged in the same direction. The second gate 218 may be located on the side of the second active layer 217 away from the substrate 100, and the second gate 218 may serve as the gate electrode of the transistor. The second source 220 and the second drain 221 can be electrically connected to the second active layer 217 through vias. The second source 220 can serve as the first electrode of the transistor, and the second drain 221 can serve as the second electrode of the transistor. The materials of the second source 220 and the second drain 221 can both include metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb).

[0138] In some exemplary embodiments, as shown in Figures 5 and 7, the second gate 218 may include a first metal layer 231 and a fourth light-transmitting conductive layer 232 stacked together. The fourth light-transmitting conductive layer 232 is located on the side of the first metal layer 231 closest to the substrate 100, and the orthographic projection of the first metal layer 231 onto the substrate 100 lies within the orthographic projection of the fourth light-transmitting conductive layer 232 onto the substrate 100. The fourth light-transmitting conductive layer 232 and the first light-transmitting conductive layer 229 are made of the same material and are arranged in the same layer. The material of the first metal layer 231 may include a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb).

[0139] Figure 8 is a schematic diagram of the second gate shown in Figure 7. In some exemplary embodiments, as shown in Figures 5, 7, and 8, the second active layer 217 may include a first region 217-2, a channel region 217-1, and a second region 217-3 arranged sequentially in a first direction. The first metal layer 231 and the fourth transparent conductive layer 232 both extend along a second direction. Both the first and second directions are parallel to the substrate 100, the first direction is perpendicular to the second direction, and the third direction is perpendicular to the substrate 100. The second source 220 can be connected to the first region 217-2 of the second active layer 217 through a via, and the second drain 221 can be connected to the second region 217-3 of the second active layer 217 through a via. The fourth transparent conductive layer 232 is flush with the two ends of the channel region 217-1 in the first direction, that is, the width of the fourth transparent conductive layer 232 is equal to the dimension of the channel region 217-1 in the first direction, the length of the fourth transparent conductive layer 232 can be the dimension of the fourth transparent conductive layer 232 in the second direction, and the width of the fourth transparent conductive layer 232 can be the dimension of the fourth transparent conductive layer 232 in the first direction. The orthographic projection of the first metal layer 231 on the substrate 100 lies within the orthographic projection of the fourth transparent conductive layer 232 on the substrate 100.

[0140] In some exemplary embodiments, as shown in Figures 5, 7 and 8, the channel region 217-1 may include a first auxiliary channel region 217-5, a main channel region 217-4 and a second auxiliary channel region 217-6 arranged sequentially in a first direction. The orthographic projections of the first auxiliary channel region 217-5, the main channel region 217-4 and the second auxiliary channel region 217-6 on the substrate 100 all overlap with the orthographic projections of the fourth light-transmitting conductive layer 232 on the substrate 100. The orthographic projection of the first metal layer 231 on the substrate 100 overlaps with the orthographic projection of the main channel region 217-4 on the substrate 100, but does not overlap with the orthographic projections of the first auxiliary channel region 217-5 and the second auxiliary channel region 217-6 on the substrate 100. The width of the fourth transparent conductive layer 232 can be greater than the width of the first metal layer 231. The width of the first metal layer 231 can be the dimension of the first metal layer 231 in the first direction. The first metal layer 231 is centrally arranged on the fourth transparent conductive layer 232 in the first direction. The fourth transparent conductive layer 232 protrudes from the first metal layer 231 at both ends in the first direction. For example, the fourth transparent conductive layer 232 includes a sixth end 235 and a second end 239 at both ends in the first direction. One end of the first metal layer 231 in the first direction can be a fifth end 237. The sixth end 235 protrudes from the fifth end 237. The distance between the sixth end 235 and the fifth end 237 in the first direction can be D5, where D5 > 0. Therefore, the second gate 218, which is composed of the fourth transparent conductive layer 232 and the first metal layer 231, can improve the control capability of the channel region 217-1 without losing transmittance. Moreover, when the fourth transparent conductive layer 232 does conductor-encapsulate the first region 217-2 and the second region 217-3, it can prevent ions from further diffusing into the channel region 217-2, so that the channel region 217-2 has a strong control compensation capability.

[0141] In some exemplary embodiments, as shown in Figures 5, 7, and 8, the second bottom gate 219 may be located on the side of the second active layer 217 near the substrate 100. The second bottom gate 219 may include a second metal layer 233 and a fifth light-transmitting conductive layer 234 stacked together, with the fifth light-transmitting conductive layer 234 located on the side of the second metal layer 233 near the substrate 100. The fifth light-transmitting conductive layer 234 and the first bottom gate 215 are made of the same material and are arranged in the same layer. The material of the second metal layer 233 may include a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The orthographic projection of the second metal layer 233 onto the substrate 100 lies within the orthographic projection of the fifth light-transmitting conductive layer 234 onto the substrate 100.

[0142] Figure 9 is a first schematic diagram of another first transistor according to this exemplary embodiment, and Figure 10 is a second schematic diagram of another first transistor according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 9 and 10, the first gate 214 includes a third metal layer 238 and a first light-transmitting conductive layer 229 stacked together. The third metal layer 238 is located on the side of the first light-transmitting conductive layer 229 away from the substrate 100, and the orthogonal projection of the third metal layer 238 on the substrate 100 lies within the orthogonal projection of the first light-transmitting conductive layer 229 on the substrate 100. The material of the third metal layer 238 may include a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The addition of the third metal layer 238 to the first gate 214 of this first transistor can enhance the driving capability of the first transistor.

[0143] In some exemplary embodiments, as shown in Figures 9 and 10, both the third metal layer 238 and the first light-transmitting conductive layer 229 extend along the second direction. The length of the third metal layer 238 can be L1, the dimension of the first light-transmitting conductive layer 229 in the second direction, and the length of the first light-transmitting conductive layer 229 can be L2, the length of the third metal layer 238 being less than the length of the first light-transmitting conductive layer 229, i.e., L1 < L2. The third metal layer 238 is centrally disposed on the first light-transmitting conductive layer 229 in the second direction, and the two ends of the first light-transmitting conductive layer 229 protrude from the two ends of the third metal layer 238 in the second direction.

[0144] In some exemplary embodiments, as shown in Figures 9 and 10, the width of the third metal layer 238 may be dimension D2 of the third metal layer 238 in the first direction, and the width of the first light-transmitting conductive layer 229 may be dimension D4 of the first light-transmitting conductive layer 229 in the first direction. The width of the third metal layer 238 is smaller than the width of the first light-transmitting conductive layer 229, i.e., D2 < D4. In this example, the third metal layer 238 is centrally arranged on the first light-transmitting conductive layer 229 in the first direction, such that the two ends of the first light-transmitting conductive layer 229 protrude from the two ends of the third metal layer 238 in the first direction.

[0145] In some exemplary embodiments, as shown in Figures 7 to 10, the orthographic projection area of ​​the first metal layer 231 on the substrate 100 is S1, and the orthographic projection area of ​​the first metal layer 231 on the substrate 100 of the third metal layer 238 is S2, where S1 > S2. The width of the first metal layer 231 is set to D1, and the width of the third metal layer 238 is set to D2, where D1 > D2 and D1 - D2 ≤ 0.5 μm. The dimension (L4) of the first metal layer 231 in the second direction is larger than the dimension (L1) of the third metal layer 238 in the second direction. One end of the first light-transmitting conductive layer 229 in the second direction is designated as the first end 240, and the end of the third metal layer 238 near the first end 240 in the second direction is designated as the second end 239. The distance between the first end 240 and the second end 239 in the second direction is set to L3, where L3 ≥ 1 μm. The edge of the first light-transmitting conductive layer 229 can form a rim relative to the first metal layer 231.

[0146] Figure 11 is a first schematic diagram of another first transistor according to this exemplary embodiment, and Figure 12 is a second schematic diagram of another first transistor according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 5, 11, and 12, the first active layer 213 includes a first region 213-2, a channel region 213-1, and a second region 213-2 sequentially disposed along a first direction. The two ends of the channel region 213-1 in the first direction are flush with the two ends of the first light-transmitting conductive layer 229 in the first direction, respectively. The channel region 213-1 includes a third end 213-4 near the first region 213-2 and a fourth end 213-5 near the second region 213-3 in the first direction. The first bottom gate 215 also includes a fifth metal layer 215-2, which is located on the side of the second light-transmitting conductive layer 215-1 away from the substrate 100. The orthographic projection of the fifth metal layer 215-2 on the substrate 100 is located within the orthographic projection of the second light-transmitting conductive layer on the substrate 100.

[0147] In some exemplary embodiments, as shown in Figures 11 and 12, the fifth metal layer 215-2 is located between the third end 213-4 and the fourth end 213-5 in the first direction, that is, the width (D6) of the fifth metal layer 215-2 is smaller than the length (D7) of the channel region 213-1. The distance between the fifth metal layer 215-2 and the third end 213-4 in the first direction is greater than 0, that is, D8 > 0; the distance between the fifth metal layer 215-2 and the fourth end 213-5 in the first direction is greater than 0, that is, D9 > 0. Thus, the fifth metal layer 215-2 is recessed relative to the channel region 213-1, thereby ensuring the stress performance of the transistor without sacrificing transmittance.

[0148] Figure 13 is a partially enlarged schematic diagram of point b in Figure 5. As shown in Figures 5 and 13, in some exemplary embodiments, the third transistor 203 may include a third gate 223, a third active layer 222, a third bottom gate 224, a third source 225, and a third drain 226. The material of the third active layer 222 includes polysilicon. The third gate 223 is located on the side of the third active layer 222 away from the third active layer 222. The third gate 223 may include a fourth metal layer 241 and a sixth transparent conductive layer 242 stacked together. The sixth transparent conductive layer 242 may be made of a transparent material, and the material of the sixth transparent conductive layer 242 may be the same as the material of the first transparent conductive layer 229. The sixth transparent conductive layer 242 is located on the side of the fourth metal layer 241 closer to the substrate 100. The third bottom gate 224 may be made of a metallic material and is located on the side of the third active layer 222 closer to the substrate 100.

[0149] In some exemplary embodiments, as shown in FIG5, the first pixel circuit 800 further includes a plurality of signal lines 230, including at least one transparent first signal line 227 and at least one second signal line 228. The second signal line 228 includes a first wiring layer 228-1 and a transparent second wiring layer 228-2, with the first wiring layer 228-1 located on the side of the second wiring layer 228-2 away from the substrate 100. The materials of the first signal line 227 and the second wiring layer 228-2 may be transparent conductive materials. A portion of the plurality of signal lines (data signal line D, first scan signal line S1, second scan signal line S2, initial signal line INIT, first power line VDD, second power line VSS, and light emission control signal line E) may be the first signal line 227, and another portion may be the second signal line 228.

[0150] In some exemplary embodiments, as shown in Figures 4 and 5, each sub-pixel region A2 includes a main display region A3, a high-transmittance trace region A5, and a high-transmittance display region A4. The high-transmittance display region A4 is located on at least one side of the main display region A3. In this example, the high-transmittance display region A4 is located on one side of the main display region A3 in a first direction, and the high-transmittance trace region A5 is located between the high-transmittance display region A4 and the main display region A3. The orthographic projection of the first transistor 201 on the substrate 100 is located in the high-transmittance display region A4 to improve the transmittance of the high-transmittance display region A4. The orthographic projections of multiple signal lines 230 on the substrate 100 are located in the high-transmittance trace region A5. For example, the orthographic projection of the first signal line 227 on the substrate 100 is located in the high-transmittance trace region A5.

[0151] In some exemplary embodiments, as shown in Figures 4 and 5, the display substrate has at least two third transistors 203. The orthogonal projection of at least one third transistor 203 onto the substrate 100 is located in the high-transmittance display area A4, and the orthogonal projection of at least one third transistor 203 onto the substrate 100 is located in the main display area A3. The third transistor 203 whose orthogonal projection onto the substrate 100 is located in the high-transmittance display area A4 may be a fourth transistor 203-1, and the third transistor 203 whose orthogonal projection onto the substrate 100 is located in the main display area A3 may be a fifth transistor 203-2.

[0152] In some exemplary embodiments, as shown in Figures 4 and 5, the circuit structure layer 200 further includes a first connection layer 243, a second connection layer 244, a third connection layer 245, and a fourth connection layer 246. The first connection layer 243 can be connected to the third drain 226 of the fourth transistor 203-1 via a via; the second connection layer 244 can be connected to a signal line 230 via a via; the third connection layer 245 and the fourth connection layer 246 can be connected to the third source 225 and the third drain 226 of the fifth transistor 203-2 via vias, respectively. The first connection layer 243 and the second connection layer 244 can be made of metallic materials, and are made of the same material and arranged in the same layer; the third connection layer 245 and the fourth connection layer 246 are made of the same material and are both transparent conductive materials, and are arranged in the same layer as the first source 216 and the first drain 217 of the first transistor 201.

[0153] In some exemplary embodiments, as shown in Figures 3, 4, and 5, the display substrate further includes a light-emitting structure layer 300. The light-emitting structure layer 300 may include a plurality of first light-emitting devices (not shown in the figures) and a pixel definition layer 302. The pixel definition layer 302 has a plurality of first pixel openings (not shown in the figures) for arranging the plurality of first light-emitting devices (not shown in the figures). The plurality of first light-emitting devices are configured to be electrically connected to a first pixel circuit 800 in a one-to-one correspondence. The orthographic projection of the first pixel opening onto the substrate 100 is configured to overlap with the main display area A3 and the high-transparency display area A4, forming an internal pixel. Alternatively, the orthographic projection of the first pixel opening onto the substrate 100 is configured to overlap with the main display area A3 but not with the high-transparency display area A4, forming an external pixel.

[0154] In some exemplary embodiments, as shown in Figures 5, 7, and 13, the circuit structure layer 200 of the display area may include: a first conductive layer disposed on the substrate 100, and a first semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, and a tenth conductive layer arranged sequentially away from the substrate 100. The first conductive layer may include the third bottom gate 224 of the third transistor 203. The first semiconductor layer may include the third active layer 222 of the third transistor 203. The second conductive layer may include the sixth light-transmitting conductive layer 242 of the third transistor 203, and the first signal line 227-1. The third conductive layer may include the fourth metal layer 241 of the third transistor 203. The fourth conductive layer may include the second light-transmitting conductive layer 215-1 of the first transistor 201, the fifth light-transmitting conductive layer 234 of the second transistor 202, and the second trace layer 228-2 of the second signal line 228. The fifth conductive layer may include the second metal layer 233 of the second transistor 202 and the first trace layer 228-1 of the second signal line 228. The second semiconductor layer may include the first active layer 213 of the first transistor 201 and the second active layer 217 of the second transistor 202. The sixth conductive layer may include the first light-transmitting conductive layer 229 of the first transistor 201 and the fourth light-transmitting conductive layer 232 of the second transistor 202, and the first signal line 227-2. The seventh conductive layer may include the first metal layer 231 of the second transistor 202. The eighth conductive layer may include the second source 220 and the second drain 221 of the second transistor 202, and the third source 225 and the third drain 226 of the third transistor 203. The ninth conductive layer may include the first drain 216 and the second drain 217 of the first transistor 201, and the third connection portion 245, the fourth connection portion 246, and the first signal line 227-3. The tenth conductive layer may include the first connection portion 243 and the second connection portion 244. A first insulating layer 204 is provided between the first conductive layer and the first semiconductor layer; a second insulating layer 205 is provided between the first semiconductor layer and the second conductive layer; a third insulating layer 206 is provided between the third conductive layer and the fourth conductive layer; a fourth insulating layer 207 is provided between the fifth conductive layer and the second semiconductor layer; a fifth insulating layer 208 is provided between the second semiconductor layer and the sixth conductive layer; a sixth insulating layer 209 is provided between the seventh conductive layer and the eighth conductive layer; a seventh insulating layer 210 is provided between the eighth conductive layer and the ninth conductive layer; an eighth insulating layer 211 is provided between the ninth conductive layer and the tenth conductive layer; and a ninth insulating layer 212 is provided on the side of the tenth conductive layer away from the substrate 100. The insulating layers can be inorganic or organic. Inorganic insulating layers may be made of inorganic films such as silicon oxide (SiO) or silicon nitride (SiN); organic insulating layers may be made of resin-based materials.

[0155] The following is an illustrative description of the fabrication process of a display substrate. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate 100100 using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0156] In some exemplary embodiments, the process of fabricating the display substrate can yield the display substrate shown in FIG5, specifically including the following steps.

[0157] Step 1: Form the first conductive layer pattern.

[0158] Figure 14 is a first fabrication schematic diagram of a display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 5 and 14, forming the first conductive layer pattern may include:

[0159] A first metal thin film is deposited on the substrate 100 and patterned to form a first conductive layer pattern. The first conductive layer pattern includes a third bottom gate 224 of a third transistor 203. The third bottom gate 224 can be connected to a fixed point signal in the peripheral region to ensure that the hysteresis characteristics of the third transistor 203 are maintained within the acceptable range of the pixel circuit.

[0160] Step 2: Form the pattern of the first semiconductor layer.

[0161] Figure 15 is a second fabrication schematic diagram of a display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 5, 14, and 15, forming the first semiconductor layer pattern may include:

[0162] In the previous step, an insulating material is deposited on the pattern to form a first insulating layer 204. Subsequently, an amorphous silicon thin film is deposited on the first insulating layer 204. The amorphous silicon thin film is crystallized using excimer laser annealing (ELA) technology to form a polycrystalline silicon thin film. The polycrystalline silicon thin film is then patterned to form a first semiconductor layer pattern. The first semiconductor layer pattern may include an undoped third active layer 222 in the third transistor 203.

[0163] Step 3: Form the second conductive layer pattern and the third conductive layer pattern.

[0164] Figure 16 is a third fabrication schematic diagram of a display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 5, 15, and 16, forming the second semiconductor layer pattern and the third conductor layer pattern may include:

[0165] In the previous step, an insulating material is deposited on the pattern to form a second insulating layer 205. Then, an oxide thin film is deposited and patterned to form a second conductive layer pattern. Subsequently, a second metal thin film is deposited and patterned to form a third conductive layer pattern. Next, the second semiconductor layer pattern and the third conductor layer pattern are used as masks to conduct the first and second regions of the undoped third active layer 222. The second conductive layer pattern may include the sixth transparent conductive layer 242 of the third transistor 203 and the first signal line 227-1. The third conductive layer pattern may include the fourth metal layer 241 of the third transistor 203. The sixth transparent conductive layer 242 and the fourth metal layer 241 can constitute the third gate 223 of the third transistor 203.

[0166] Step 4: Form the fourth conductive layer pattern and the fifth conductive layer pattern.

[0167] Figure 17 is a fourth fabrication schematic diagram of a display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 5, 16, and 17, forming the fourth conductive layer pattern and the fifth conductive layer pattern may include:

[0168] In the previous step, an insulating material is deposited on the pattern to form a third insulating layer 206. Then, an oxide thin film is deposited and patterned to form a fourth conductive layer pattern. Subsequently, a third metal thin film is deposited and patterned to form a fifth conductive layer pattern. The fourth conductive layer pattern may include a second transparent conductive layer 215-1 of the first transistor 201, a fifth transparent conductive layer 234 of the second transistor 202, and a second trace layer 228-2 of the second signal line 228. The fifth conductive layer pattern may include a second metal layer 233 of the second transistor 202 and a first trace layer 228-1 of the second signal line 228. The fifth transparent conductive layer 234 and the second metal layer 233 constitute the second bottom gate 219 of the second transistor 202, the first trace layer 228-1 and the second trace layer 228-2 constitute the second signal line 228, and the second transparent conductive layer 215-1 constitutes the first bottom gate 215 of the first transistor 201.

[0169] Step 5: Form the pattern of the second semiconductor layer.

[0170] Figure 18 is a fifth fabrication schematic diagram of a display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 5, 17, and 18, forming the second semiconductor layer pattern may include:

[0171] In the previous step, an insulating material is deposited on the pattern to form a fourth insulating layer 207. Then, an oxide thin film is deposited and a patterning process is performed on the oxide thin film to form a second semiconductor layer pattern. The second semiconductor layer pattern may include an undoped first active layer 213 in the first transistor 201 and an undoped second active layer 217 in the second transistor 202.

[0172] Step 6: Form the sixth conductive layer pattern and the seventh conductive layer pattern.

[0173] Figure 19 is a sixth fabrication schematic diagram of a display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 5, 18, and 19, forming the sixth conductive layer pattern and the seventh conductive layer pattern may include:

[0174] In the previous step, an insulating material is deposited on the pattern to form a fifth insulating layer 208. Then, an oxide thin film is deposited and patterned to form a sixth conductive layer pattern. Subsequently, a fourth metal thin film is deposited and patterned to form a seventh conductive layer pattern. Next, the sixth and seventh conductive layer patterns are used as masks to conduct the first and second regions of the undoped first active layer 213 and second active layer 217. The sixth conductive layer pattern may include the first transparent conductive layer 229 of the first transistor 201, the fourth transparent conductive layer 232 of the second transistor 202, and the first signal line 227-2. The seventh conductive layer pattern may include the first metal layer 231 of the second transistor 202. The fourth transparent conductive layer 232 and the first metal layer 231 constitute the second gate 218 of the second transistor 202, and the first transparent conductive layer 229 constitutes the first bottom gate 214 of the first transistor 201.

[0175] Figure 20 is a seventh fabrication schematic diagram of a display substrate according to an exemplary embodiment of the present invention, Figure 21 is an eighth fabrication schematic diagram of a display substrate according to an exemplary embodiment of the present invention, and Figure 22 is a ninth fabrication schematic diagram of a display substrate according to an exemplary embodiment of the present invention. In some exemplary embodiments, as shown in Figures 20 to 22, during the formation of the sixth conductive layer pattern and the seventh conductive layer pattern, the sixth conductive layer pattern is formed first. During this process, as shown in Figure 20, the first light-transmitting conductive layer 229 of the first transistor 201 and the fourth light-transmitting conductive layer 232 of the second transistor 202 are formed simultaneously. Then, a fourth metal thin film is deposited, and the fourth metal thin film is coated, exposed, developed, and etched to form a first pattern. As shown in Figure 21, the first pattern includes the first metal layer 231 of the second transistor 202 and a first capping layer 247. The first capping layer 247 covers the side of the first light-transmitting conductive layer 229 away from the substrate, and the second gate of the second transistor and the first gate of the first transistor are formed. Subsequently, as shown in Figure 22, using the second gate and the first gate as masks, the first active layer 213 and the second active layer 217 are doped and implanted to form conductors. Finally, a second cover layer 248 is formed through a patterning process. The second cover layer 248 covers the second gate of the second transistor but does not cover the first gate of the first transistor, forming a photoresist protection for the second gate of the second transistor. Then, the first cover layer 247 is etched away.

[0176] Figure 23 is a tenth fabrication schematic diagram of a display substrate according to an exemplary embodiment of the present invention, and Figure 24 is an eleventh fabrication schematic diagram of a display substrate according to an exemplary embodiment of the present invention. In some exemplary embodiments, during the formation of the sixth conductive layer pattern and the seventh conductive layer pattern, as shown in Figure 23, a first oxide thin film 249 and a fourth metal thin film 250 are deposited on the fifth insulating layer 208, respectively. After one etching process, the second gate (i.e., the first metal layer 231 and the fourth light-transmitting conductive layer 231) of the second transistor 202, the first capping layer 247, and the first light-transmitting conductive layer 229 covered by the first capping layer 247 are formed, as shown in Figure 21. Subsequently, as shown in Figure 22, the first active layer 213 and the second active layer 217 are doped and implanted as conductors using the second gate and the first capping layer 247 as masks; or, as shown in Figure 24, a third capping layer 251 is covered on the second gate and the first capping layer 247, and the first active layer 213 and the second active layer 217 are doped and implanted as conductors using the third capping layer 251 as a mask. Finally, a second cover layer 248 is formed through a patterning process. The second cover layer 248 covers the second gate of the second transistor but does not cover the first gate of the first transistor, forming a photoresist protection for the second gate of the second transistor. Then, the first cover layer 247 is etched away.

[0177] Figure 25 is a schematic diagram of the twelfth fabrication step of a display substrate according to this exemplary embodiment. In some exemplary embodiments, during the formation of the sixth and seventh conductive layer patterns, as shown in Figure 20, a first transparent conductive layer 229 and a fourth transparent conductive layer 232 are formed simultaneously. Subsequently, as shown in Figure 25, a fourth capping layer 252 is formed on the first transparent conductive layer 229 and the fourth transparent conductive layer 232 through a patterning process. The fourth capping layer 252 covers the end faces of the first transparent conductive layer 229 and the fourth transparent conductive layer 232 away from the substrate 100. Using the fourth capping layer 252 as a mask, the first active layer 213 and the second active layer 217 are doped and implanted with conductors. Finally, a second capping layer 248 is formed through a patterning process. The second capping layer 248 covers the second gate of the second transistor but does not cover the first gate of the first transistor, forming a photoresist protection for the second gate of the second transistor. Then, the first capping layer 247 is etched away. Finally, a fourth metal thin film is deposited, and the fourth metal thin film is coated, exposed, developed, and etched to form the first metal layer 231 of the second transistor 202.

[0178] Step 7: Form the pattern of the eighth conductive layer.

[0179] Figure 26 is a schematic diagram of the thirteenth fabrication step of a display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 5, 19, and 26, forming the pattern of the eighth conductive layer may include:

[0180] In the previous step, an insulating material is deposited on the pattern to form a sixth insulating layer 209. Subsequently, a fifth metal thin film is deposited and patterned to form an eighth conductive layer pattern. The eighth conductive layer pattern may include the second source 220 and the second drain 221 of the second transistor 202, and the third source 225 and the third drain 226 of the third transistor 203.

[0181] Step 8: Form the pattern of the ninth conductive layer.

[0182] Figure 27 is a schematic diagram of the fourteenth fabrication step of a display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in Figures 5, 26, and 27, forming the ninth conductive layer pattern may include:

[0183] In the previous step, an insulating material is deposited on the pattern to form a seventh insulating layer 210. Subsequently, an oxide thin film is deposited and a patterning process is performed on the oxide thin film to form a ninth conductive layer pattern. The ninth conductive layer pattern may include the first drain 216 and the second drain 217 of the first transistor 201, as well as the third connection portion 245, the fourth connection portion 246, and the first signal line 227-3.

[0184] Step 9: Form the pattern of the tenth conductive layer.

[0185] In some exemplary embodiments, as shown in FIG5 and FIG27, forming the pattern of the tenth conductive layer may include:

[0186] In the previous step, an insulating material is deposited on the pattern to form an eighth insulating layer 211. Subsequently, a sixth metal thin film is deposited and patterned to form a tenth conductive layer pattern. The tenth conductive layer pattern may include a first connecting portion 243 and a second connecting portion 244.

[0187] After the circuit structure layer is completed, the subsequent processes of forming the light-emitting structure layer, encapsulation structure layer, optical structure layer, and cover plate will yield the aforementioned display substrate.

[0188] In some exemplary embodiments, a display device includes the aforementioned display substrate. The display device provided in this disclosure can be applied to electronic devices, which can be mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, in-vehicle displays, or any product or component with display functionality, such as wearable devices, smartwatches, smart bracelets, smart glasses, smart headphones, smart clothing, head-mounted displays, etc.

[0189] In some exemplary embodiments, a method for fabricating a display substrate includes:

[0190] At least one first pixel circuit is formed on a substrate, the substrate including a display area, the display area including a first display area; at least one first pixel circuit is disposed on the substrate, the orthographic projection of the first pixel circuit on the substrate is located in the first display area; the first pixel circuit includes at least one first transistor, the first transistor including a transparent first active layer, and a first gate disposed insulated on the side of the first active layer away from the substrate, the first gate including a first light-transmitting conductive layer.

[0191] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0192] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0193] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0194] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0195] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0196] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0197] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, wherein, include: A substrate, including a display area, the display area including a first display area; At least one first pixel circuit is disposed on the substrate, and the orthographic projection of the first pixel circuit on the substrate is located in the first display area; The first pixel circuit includes at least one first transistor, the first transistor including a transparent first active layer and a first gate disposed on the side of the first active layer away from the substrate, the first gate including a first light-transmitting conductive layer.

2. The display substrate according to claim 1, wherein, The first transistor further includes a first bottom gate, which is insulated on the side of the first active layer near the substrate, and the first bottom gate includes a second transparent conductive layer.

3. The display substrate according to claim 1, wherein, The first transistor further includes a first source and a first drain, wherein the first source and / or the first drain includes a third transparent conductive layer.

4. The display substrate according to claim 2, wherein, The first pixel circuit includes at least one second transistor, the second transistor including a second gate and a transparent second active layer; The second gate is located on the side of the second active layer away from the substrate. The second gate includes a first metal layer and a fourth light-transmitting conductive layer. The fourth light-transmitting conductive layer is located on the side of the first metal layer close to the substrate. The orthographic projection of the first metal layer on the substrate lies within the orthographic projection of the fourth transparent conductive layer on the substrate.

5. The display substrate according to claim 4, wherein, The fourth transparent conductive layer and the first transparent conductive layer are made of the same material and are arranged in the same layer.

6. The display substrate according to claim 4, wherein, The second transistor further includes a second bottom gate located on the side of the second active layer near the substrate. The second bottom gate includes a second metal layer and a fifth light-transmitting conductive layer located on the side of the second metal layer near the substrate. The orthographic projection of the second metal layer on the substrate lies within the orthographic projection of the fifth light-transmitting conductive layer on the substrate. The fifth light-transmitting conductive layer and the second light-transmitting conductive layer are made of the same material and are arranged in the same layer.

7. The display substrate according to claim 4, wherein, The second active layer includes a first region, a channel region, and a second region arranged sequentially in a first direction, the first direction being parallel to the substrate; Both the fourth light-transmitting conductive layer and the first metal layer are configured to extend along a second direction. The first metal layer is centrally disposed on the fourth light-transmitting conductive layer in the first direction. The two ends of the fourth light-transmitting conductive layer in the first direction protrude from the two ends of the first metal layer in the first direction. The second direction is parallel to the substrate and perpendicular to the first direction.

8. The display substrate according to claim 7, wherein, The channel area includes a first auxiliary channel area, a main channel area, and a second auxiliary channel area arranged sequentially in the first direction; The orthographic projection of the first metal layer on the substrate is configured to overlap with the orthographic projection of the main channel region on the substrate, but not overlap with the orthographic projections of the first auxiliary channel region and the second auxiliary channel region on the substrate; The orthographic projections of the main channel region, the first auxiliary channel region, and the second auxiliary channel region on the substrate all overlap with the orthographic projection of the fourth transparent conductive layer on the substrate.

9. The display substrate according to claim 4, wherein, The first gate further includes a third metal layer, which is located on the side of the first transparent conductive layer away from the substrate, and the orthographic projection of the third metal layer on the substrate is located within the orthographic projection of the first transparent conductive layer on the substrate; The orthographic projection area of ​​the first metal layer on the substrate is S1, and the orthographic projection area of ​​the third metal layer on the substrate is S2, where S1 > S2.

10. The display substrate according to claim 9, wherein, The width of the first metal layer is set to D1, and the width of the third metal layer is set to D2, where D1 > D2 and D1 - D2 ≤ 0.5 μm.

11. The display substrate according to claim 9, wherein, The first active layer and the second active layer are both configured to extend along a first direction, and the first gate and the second gate are both configured to extend along a second direction. The first direction and the second direction are both parallel to the substrate and perpendicular to each other. The third metal layer has a dimension of L1 in the second direction, and the first transparent conductive layer has a dimension of L2 in the second direction, where L1 < L2; The third metal layer is centrally disposed on the first light-transmitting and conductive layer in the second direction, and the two ends of the first light-transmitting and conductive layer in the second direction respectively protrude from the two ends of the third metal layer in the second direction.

12. The display substrate according to claim 11, wherein, One end of the first transparent conductive layer in the second direction is the first end, and the end of the third metal layer near the first end in the second direction is the second end. The distance between the first end and the second end in the second direction is set to L3, where L3 ≥ 1 μm.

13. The display substrate according to claim 1, wherein, The first pixel circuit includes at least one third transistor, the third transistor including a third gate and a third active layer; The material of the third active layer includes polycrystalline silicon; The third gate is located on the side of the third active layer away from the substrate. The third gate includes a fourth metal layer and a sixth light-transmitting conductive layer. The sixth light-transmitting conductive layer is located on the side of the fourth metal layer close to the substrate. The orthographic projection of the fourth metal layer on the substrate is located within the orthographic projection of the sixth light-transmitting conductive layer on the substrate.

14. The display substrate according to claim 2, wherein, The first active layer includes a first region, a channel region, and a second region arranged sequentially along a first direction. The channel region includes a third end near the first region and a fourth end near the second region along the first direction. The first direction is parallel to the substrate. The first bottom grid further includes a fifth metal layer, which is located on the side of the second light-transmitting conductive layer away from the substrate, and the orthographic projection of the fifth metal layer on the substrate is located within the orthographic projection of the second light-transmitting conductive layer on the substrate; The fifth metal layer is located between the third end and the fourth end in the first direction, and the distance between the fifth metal layer and the third end in the first direction is greater than 0, and the distance between the fifth metal layer and the fourth end in the first direction is greater than 0.

15. The display substrate according to claim 1, wherein, The first display area includes at least one sub-pixel area, the sub-pixel area includes a main display area, a high-transmittance trace area and a high-transmittance display area, the high-transmittance display area is located on at least one side of the main display area, the high-transmittance trace area is located between the high-transmittance display area and the main display area, and the orthogonal projection of the first transistor on the substrate is located in the high-transmittance display area.

16. The display substrate according to claim 15, wherein, The first pixel circuit also includes multiple signal lines, including at least one transparent first signal line, the orthographic projection of the first signal line on the substrate being located in the high-transparency trace area.

17. The display substrate according to claim 16, wherein, The plurality of signal lines include at least one second signal line, the second signal line including a first trace layer and a transparent second trace layer, the first trace layer being located on the side of the second trace layer away from the substrate, and the orthographic projection of the second signal line on the substrate being located in the high-transparency trace area.

18. The display substrate according to claim 15, wherein, It also includes a light-emitting structure layer, which includes a plurality of first light-emitting devices and a pixel definition layer; The pixel definition layer is provided with a plurality of first pixel openings for arranging a plurality of first light-emitting devices, and the first light-emitting devices are configured to be electrically connected in a one-to-one correspondence with the first pixel circuit; The orthographic projection of the first pixel opening onto the substrate is configured to overlap with the main display area and the high-transparency display area; Alternatively, the orthographic projection of the first pixel opening onto the substrate is configured to overlap with the main display area but not with the high-transparency display area.

19. The display substrate according to any one of claims 1 to 18, wherein, The material of the first transparent conductive layer includes a transparent conductive oxide, and the transparent conductive oxide includes indium tin oxide.

20. A method for preparing a display substrate, wherein, include: At least one first pixel circuit is formed on a substrate, the substrate including a display area, the display area including a first display area; at least one first pixel circuit is disposed on the substrate, the orthographic projection of the first pixel circuit on the substrate is located in the first display area; the first pixel circuit includes at least one first transistor, the first transistor including a transparent first active layer, and a first gate disposed insulated on the side of the first active layer away from the substrate, the first gate including a first light-transmitting conductive layer.

21. The method for preparing a display substrate according to claim 20, wherein, The process of forming at least one first pixel circuit on the substrate includes: The first transistor and the second transistor are formed synchronously on the substrate. The second transistor includes a second gate, which includes a first metal layer and a fourth light-transmitting conductive layer. The fourth light-transmitting conductive layer is located on the side of the first metal layer close to the substrate. The orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the fourth light-transmitting conductive layer on the substrate. The fourth light-transmitting conductive layer and the first light-transmitting conductive layer are made of the same material and are arranged in the same layer.

22. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 19.

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