Channel establishment method, storage medium, display system, and display device

Abstract

Disclosed in the present invention are a channel establishment method, a storage medium, a display system, and a display device. The method comprises: acquiring a level voltage transmitted by a control module on the basis of a first target pin of a first embedded display interface, and controlling a level voltage of a second target pin of a second embedded display interface; and if the level voltage of the second target pin is a high level voltage, establishing, on the basis of a first channel parameter corresponding to the high level voltage, a data transmission channel used for transmitting display data between a timing controller and the control module; or, if the level voltage of the second target pin is a low level voltage, establishing, on the basis of a second channel parameter corresponding to the low level voltage, a data transmission channel used for transmitting display data between the timing controller and the control module. The present invention is compatible with driving modes in which the control module uses different chip types, so that high-refresh-rate display data is transmitted, thereby improving the versatility and reliability of a display device when displaying high-refresh-rate display data.

Description

A method for establishing a channel, a storage medium, a display system, and a display device.

[0001] This application claims priority to Chinese Patent Application No. 202510064776.8, filed on January 15, 2025, entitled "A Channel Establishment Method, Storage Medium, Display System and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of computer technology, and in particular to a channel establishment method, a storage medium, a display system, and a display device. Background Technology

[0003] Nowadays, with the continuous development of display device performance, the resolution and refresh rate of display devices are getting higher and higher. If the refresh rate of large-size display devices is insufficient, problems such as slow touch response and poor smoothness will occur. Therefore, achieving a high refresh rate for large-size display devices is particularly important. Summary of the Invention

[0004] This invention provides a channel establishment method, a storage medium, a display system, and a display device. By establishing a data transmission channel for transmitting high refresh rate display data according to the pin definition of the target pin, it is compatible with the driving methods of different chip types used by the control module to transmit high refresh rate display data, thereby improving the versatility and reliability of the display device in transmitting high refresh rate display data.

[0005] In a first aspect, embodiments of the present invention provide a display system, characterized in that the display system includes a display screen, a timing controller, and a control module, the control module is provided with a first embedded display interface, the timing controller is provided with a second embedded display interface, the display screen is connected to the timing controller, and the first embedded display interface and the second embedded display interface are connected through interface pins;

[0006] The control module is used to control the voltage level of the first target pin of the first embedded display interface based on the type of chip used, and to control the voltage level of the second target pin of the second embedded display interface through the voltage level of the first target pin;

[0007] A timing controller is configured to establish a data transmission channel for transmitting display data between the timing controller and the control module based on the first channel parameter corresponding to the high-level voltage if the voltage level of the second target pin is a high-level voltage; or, a timing controller is configured to establish a data transmission channel for transmitting display data between the timing controller and the control module based on the second channel parameter corresponding to the low-level voltage if the voltage level of the second target pin is a low-level voltage, wherein the number of channels indicated by the second channel parameter is greater than the number of channels indicated by the first channel parameter.

[0008] The display screen is used to receive display data transmitted by the timing controller and output display data. The display data is the display data transmitted by the control module to the second data transmission pin of the second embedded display interface of the timing controller based on the first data transmission pin of the first embedded display interface.

[0009] Through the above technical solution, the control module sets the voltage level of the first target pin according to the chip type, enabling the timing controller to establish a data transmission channel between the timing controller and the control module based on the channel parameters corresponding to the voltage level. This allows for the establishment of a data transmission channel for transmitting high refresh rate display data according to the pin definition of the target pin. Consequently, it is compatible with different chip types using different driving methods of the control module to transmit high refresh rate display data, improving the versatility and reliability of the display device in displaying high refresh rate display data.

[0010] In combination with the first aspect and the above implementation methods, in some possible implementation methods, based on the type of chip used, controlling the voltage level of the first target pin of the first embedded display interface includes:

[0011] The control module is used to determine that the first voltage value of the first target pin of the first embedded display interface is a high-level voltage if the chip type used is a first chip type, control the level voltage of the first target pin based on the first voltage value, and control the level voltage of the second target pin of the second embedded display interface to be a high-level voltage through the level voltage of the first target pin;

[0012] or,

[0013] The control module is configured to determine, if the chip type used is a first chip type, that the first voltage value of the first target pin of the first embedded display interface is a low-level voltage, control the level voltage of the first target pin of the first embedded display interface based on the first voltage value, and control the level voltage of the second target pin of the second embedded display interface to be a low-level voltage through the level voltage of the first target pin.

[0014] Through the above technical solution, the voltage level of the first target pin of the first embedded display interface is controlled according to the chip type used by the control module, and the voltage level of the second target pin of the second embedded display interface is controlled based on the voltage level of the first target pin, so that the timing controller can determine the channel parameters according to the voltage level of the second target pin.

[0015] In combination with the first aspect and the above implementation, in some possible implementations, the timing controller is used to determine that the voltage level of the second target pin is a high voltage level if the second voltage value of the second target pin is greater than or equal to the first voltage threshold.

[0016] The timing controller is also configured to determine that the voltage level of the second target pin is a low voltage level if the second voltage value of the second target pin is less than or equal to the second voltage threshold, wherein the first voltage threshold is greater than the second voltage threshold.

[0017] Combining the first aspect and the above implementation methods, in some possible implementation methods, the first chip type is the type of chip running the Windows system, and the second chip type is the type of chip running the Android system.

[0018] Combining the first aspect and the above implementation methods, in some possible implementation methods, if the data transmission channel is established based on the first channel parameters, then the first to eighth pins of the first embedded display interface are power supply pins;

[0019] Pins 9, 35, 37, 38, 40, 41, 43, 44, 46, 47, 49 and 50 of the first embedded display interface are unconnected pins.

[0020] The tenth pin of the first embedded display interface is the first target pin;

[0021] Pins 12, 16, 17, 20, 23, 26, 29, 32, 34, 36, 39, 42, 45, 48, and 51 of the first embedded display interface are ground pins;

[0022] The eleventh pin of the first embedded display interface is the aging test pin;

[0023] The thirteenth pin of the first embedded display interface is the data write pin, the fourteenth pin is the serial communication data signal transmission pin, and the fifteenth pin is the clock pin;

[0024] Pins 18, 19, 21, 22, 24, 25, 27, and 28 of the first embedded display interface are the first data transmission pins;

[0025] Pins 30 and 31 of the first embedded display interface are the first instruction transmission pins;

[0026] The thirty-third pin of the first embedded display interface is the hot-plug detection pin;

[0027] The first to eighth pins of the second embedded display interface are power supply pins;

[0028] Pins 9, 35, 37, 38, 40, 41, 43, 44, 46, 47, 49 and 50 of the second embedded display interface are unconnected pins.

[0029] The tenth pin of the second embedded display interface is the second target pin;

[0030] Pins 12, 16, 17, 20, 23, 26, 29, 32, 34, 36, 39, 42, 45, 48, and 51 of the second embedded display interface are ground pins;

[0031] The eleventh pin of the second embedded display interface is the aging test pin;

[0032] The thirteenth pin of the second embedded display interface is the data write pin, the fourteenth pin is the serial communication data signal transmission pin, and the fifteenth pin is the clock pin;

[0033] Pins 18, 19, 21, 22, 24, 25, 27, and 28 of the second embedded display interface are the second data transmission pins;

[0034] Pins 30 and 31 of the second embedded display interface are the second instruction transmission pins;

[0035] The thirty-third pin of the second embedded display interface is a hot-plug detection pin.

[0036] Combining the first aspect and the above implementation methods, in some possible implementation methods, if the data transmission channel is established based on the second channel parameters, then the first to eighth pins of the first embedded display interface are power supply pins;

[0037] The ninth pin of the first embedded display interface is an unconnected pin;

[0038] The tenth pin of the first embedded display interface is the first target pin;

[0039] Pins 12, 16, 17, 20, 23, 26, 29, 32, 34, 36, 39, 42, 45, 48, and 51 of the first embedded display interface are ground pins;

[0040] The eleventh pin of the first embedded display interface is the aging test pin;

[0041] The thirteenth pin of the first embedded display interface is the data write pin, the fourteenth pin is the serial communication data signal transmission pin, and the fifteenth pin is the clock pin;

[0042] Pins 18, 19, 21, 22, 24, 25, 27, 28, 37, 38, 40, 41, 43, 44, 46, and 47 of the first embedded display interface are the first data transmission pins;

[0043] Pins 30, 31, 49, and 50 of the first embedded display interface are the first instruction transmission pins;

[0044] The 33rd pin of the first embedded display interface is the hot-plug detection pin, and the 35th pin is the slave hot-plug detection pin.

[0045] The first to eighth pins of the second embedded display interface are power supply pins;

[0046] The ninth pin of the second embedded display interface is an unconnected pin;

[0047] The tenth pin of the second embedded display interface is the second target pin;

[0048] Pins 12, 16, 17, 20, 23, 26, 29, 32, 34, 36, 39, 42, 45, 48, and 51 of the second embedded display interface are ground pins;

[0049] The eleventh pin of the second embedded display interface is the aging test pin;

[0050] The thirteenth pin of the second embedded display interface is the data write pin, the fourteenth pin is the serial communication data signal transmission pin, and the fifteenth pin is the clock pin;

[0051] Pins 18, 19, 21, 22, 24, 25, 27, 28, 37, 38, 40, 41, 43, 44, 46, and 47 of the second embedded display interface are the second data transmission pins;

[0052] Pins 30, 31, 49, and 50 of the second embedded display interface are the second instruction transmission pins;

[0053] The 33rd pin of the second embedded display interface is the hot-plug detection pin, and the 35th pin is the slave hot-plug detection pin.

[0054] Combining the first aspect and the above implementation methods, in some possible implementation methods, the timing controller is used to receive display data transmitted by the control module based on the first data transmission pin in the first embedded display interface based on the second data transmission pin in the second embedded display interface, and transmit the display data to the display screen.

[0055] Through the above technical solution, the timing controller receives the display data transmitted by the control module and outputs the display data to the display screen, so as to realize the transmission and display of display data according to the established data display channel.

[0056] Secondly, embodiments of the present invention provide a channel establishment method, the method being applied to a timing controller in a display system. The display system further includes a control module, the control module having a first embedded display interface, and the timing controller having a second embedded display interface. The first embedded display interface and the second embedded display interface are connected via interface pins. The method includes:

[0057] The acquisition control module controls the level voltage of the second target pin of the second embedded display interface based on the level voltage transmitted by the first target pin of the first embedded display interface, wherein the second target pin is any pin in the second embedded display interface;

[0058] If the voltage level of the second target pin is high, then based on the first channel parameters corresponding to the high voltage, a data transmission channel for transmitting display data is established between the timing controller and the control module; or,

[0059] If the voltage level of the second target pin is low, a data transmission channel for transmitting display data is established between the timing controller and the control module based on the second channel parameters corresponding to the low voltage.

[0060] The number of channels indicated by the second channel parameter is greater than the number of channels indicated by the first channel parameter.

[0061] The above technical solution enables the establishment of a data transmission channel between the control module and the target pin based on the voltage level of the second embedded display interface and the corresponding channel parameters. This allows for the establishment of a data transmission channel for transmitting high refresh rate display data based on the pin definition of the target pin. Consequently, it is compatible with different chip types and driving methods used by the control module to transmit high refresh rate display data, thereby improving the versatility and reliability of the display device in displaying high refresh rate display data.

[0062] Combining the second aspect and the above implementation methods, in some possible implementation methods, a data transmission channel for transmitting display data between the timing controller and the control module is established based on the first channel parameters corresponding to the high-level voltage, including:

[0063] Based on the first channel parameters corresponding to the high-level voltage, set the pin definitions of each interface pin of the second embedded display interface;

[0064] Based on the pins of the second embedded display interface after pin definition, a data transmission channel for transmitting display data is established between the timing controller and the control module.

[0065] The above technical solution enables the definition of each interface pin of the second embedded display interface based on the first channel parameters of the high-level voltage. A data transmission channel between the timing controller and the control module is established based on the defined interface pins, thereby enabling the establishment of the channel between the timing controller and the control module when the voltage level is high, ensuring the accuracy and reliability of data transmission.

[0066] Combining the second aspect and the above implementation methods, in some possible implementation methods, a data transmission channel for transmitting display data between the timing controller and the control module is established based on the second channel parameters corresponding to the low-level voltage, including:

[0067] Based on the second channel parameters corresponding to the low-level voltage, set the pin definitions of each interface pin of the second embedded display interface;

[0068] Based on the pins of the second embedded display interface after pin definition, a data transmission channel for transmitting display data is established between the timing controller and the control module.

[0069] The above technical solution enables the definition of each interface pin of the second embedded display interface based on the second channel parameters at a low voltage level. A data transmission channel between the timing controller and the control module is then established based on the defined interface pins, thereby enabling the establishment of the channel between the timing controller and the control module when the voltage level is low, ensuring the accuracy and reliability of data transmission.

[0070] Combining the second aspect and the above implementation methods, in some possible implementation methods, based on the interface pins of the second embedded display interface after pin definition, a data transmission channel for transmitting display data between the timing controller and the control module is established, including:

[0071] Based on the second data transmission pin and the second instruction transmission pin in the second embedded display interface, the display parameters between the timing controller and the control module are matched to determine the link status data in the display parameters;

[0072] If the link status data indicates that the link between the timing controller and the control module is in a stable state, then the data transmission channel between the timing controller and the control module is established.

[0073] The above technical solution enables the matching of display parameters between the timing controller and the control module, so that when the link between the timing controller and the control module is determined to be in a stable state, the data transmission channel between the timing controller and the control module can be established.

[0074] In conjunction with the second aspect and the above implementation methods, in some possible implementation methods, the display parameters also include performance data, identification data, and configuration data. Based on the second data transmission pin and the second instruction transmission pin in the second embedded display interface, the display parameters between the timing controller and the control module are matched to determine the link status data in the display parameters, including:

[0075] Trigger information is transmitted to the control module via the second instruction transmission pin to trigger the control module to transmit a performance data read request via the first instruction transmission pin.

[0076] In response to a performance data read request transmitted by the control module, performance data is transmitted to the control module based on the second instruction transmission pin;

[0077] In response to the identification data read request transmitted by the control module based on the first instruction transmission pin, the identification data is transmitted to the control module based on the second instruction transmission pin;

[0078] The verification data transmitted by the control module based on the first data transmission pin is obtained based on the second data transmission pin, and the verification data is stored.

[0079] In response to the verification data read request transmitted by the control module based on the first instruction transmission pin, the link status data is returned based on the second instruction transmission pin. The link status data indicates the stability of the link between the timing controller and the control module.

[0080] In conjunction with the second aspect and the above implementation methods, in some possible implementations, the display system further includes a display screen, and after establishing a data transmission channel between the timing controller and the control module for transmitting display data, it also includes:

[0081] The display data transmitted by the control module is obtained based on the data transmission channel. The display data includes at least one frame of video data.

[0082] Determine the display sequence of each video data item in the display data, and use the display sequence control to output each video data item sequentially on the display screen.

[0083] The above technical solution can acquire the display data transmitted by the control module and output the display data according to the display timing of each video data in the display data.

[0084] In combination with the second aspect and the above implementation methods, in some possible implementation methods, before obtaining the display data transmitted by the control module based on the data transmission channel, the following steps are also included:

[0085] In response to the data parameters transmitted by the control module, the clock parameters of the data output are adjusted.

[0086] The above technical solution can synchronize the clocks between the timing controller and the control module, ensuring that the timing controller and the control module maintain clock consistency and ensuring the accuracy and reliability of data transmission.

[0087] Combining the second aspect and the above implementation methods, in some possible implementation methods, each interface pin in the second embedded display interface is clustered based on its pin function to obtain at least one pin group, and the pin group includes interface pins with at least one identical pin function;

[0088] Set up unused pins between each pin group.

[0089] The above technical solution enables the pins of the second embedded display interface to be grouped based on pin functions to obtain pin groups, and empty pins are set between each pin group to prevent the display device from burning out due to the mixed use of timing controllers during the manufacturing process, thereby improving the reliability of the embedded display interface and the safety of the display device.

[0090] Thirdly, embodiments of the present invention provide a display device, the display device comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to execute the steps of the above-described method.

[0091] Fourthly, embodiments of the present invention provide a computer storage medium storing multiple instructions adapted for loading by a processor and executing the steps of the above-described method. Attached Figure Description

[0092] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0093] Figure 1 is a schematic diagram of the system architecture of a display system provided in an embodiment of the present invention;

[0094] Figure 2 is a schematic diagram illustrating an example of an interface definition provided in an embodiment of the present invention;

[0095] Figure 3 is a schematic diagram illustrating an example of an interface definition provided in an embodiment of the present invention;

[0096] Figure 4 is a schematic diagram of a display system provided in an embodiment of the present invention;

[0097] Figure 5 is a schematic diagram of a display system provided in an embodiment of the present invention;

[0098] Figure 6 is a schematic diagram of a display system provided in an embodiment of the present invention;

[0099] Figure 7 is a flowchart illustrating a channel establishment method provided in an embodiment of the present invention;

[0100] Figure 8 is a flowchart illustrating a channel establishment method provided in an embodiment of the present invention;

[0101] Figure 9 is a schematic diagram illustrating an example of matching display parameters provided in an embodiment of the present invention;

[0102] Figure 10 is a schematic diagram illustrating an example of a data transmission channel provided in an embodiment of the present invention;

[0103] Figure 11 is a schematic diagram illustrating an example of output display data provided in an embodiment of the present invention;

[0104] Figure 12 is a schematic diagram illustrating an example of pin grouping provided in an embodiment of the present invention;

[0105] Figure 13 is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0106] To make the features and advantages of the present invention more apparent and understandable, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0107] In related technologies, large-size display devices use the VBO (Video by One) interface for image data transmission to achieve high refresh rate display, instead of the eDP (Embedded DisplayPort) interface. This results in a low image data transmission rate and incompatibility with transmission scenarios of different channels. Therefore, defining the standardization of the eDP interface for large-size high refresh rate display devices is an urgent problem to be solved.

[0108] Please refer to Figure 1, which is a schematic diagram of the system architecture of a display system provided in an embodiment of the present invention. This display system can be applied to display devices, specifically, intelligent interactive flat panels, commercial displays, digital signage, electronic whiteboards, electronic blackboards, monitors, etc. The display system provided in this embodiment includes, but is not limited to, a display screen 10, a control module 20, and a timing controller 30 (T-CON, Timing Controller). The control module 20 is provided with a first embedded display interface 21 (eDP interface), and the timing controller 30 is provided with a second embedded display interface 31. The first embedded display interface 21 and the second embedded display interface 31 can be connected through interface pins, and the interface pins can be connected through a data line (T-CON FFC). The first embedded display interface 21 and the second embedded display interface 31 are 51-pin interfaces.

[0109] The interface definition is shown in Figure 2 or Figure 3. Figure 2 can be the interface definition for the first embedded display interface 21 and the second embedded display interface 31 as four channels. Specifically, the first to eighth pins of the first embedded display interface 21 are power supply pins; the ninth, thirty-fifth, thirty-seventh, thirty-eighth, fortieth, forty-first, forty-third, forty-fourth, forty-sixth, forty-seventh, forty-ninth, and fiftieth pins of the first embedded display interface 21 are unconnected pins; the tenth pin of the first embedded display interface 21 is the first target pin; the twelfth, sixteenth, seventeenth, twentieth, twenty-third, and twenty-fourth pins of the first embedded display interface 21 are... Pins 6, 29, 32, 34, 36, 39, 42, 45, 48, and 51 are ground pins; pin 11 of the first embedded display interface 21 is an aging test pin; pin 13 of the first embedded display interface 21 is a data write pin, pin 14 is a serial communication data signal transmission pin, and pin 15 is a clock pin; pins 18, 19, 21, 22, 24, 25, 27, and 28 of the first embedded display interface 21 are first data transmission pins; pins 30 and 51 of the first embedded display interface 21 are ground pins. Pin 11 is the first instruction transmission pin; pin 33 of the first embedded display interface 21 is the hot-plug detection pin; pins 1 to 8 of the second embedded display interface 31 are power supply pins; pins 9, 35, 37, 38, 40, 41, 43, 44, 46, 47, 49, and 50 of the second embedded display interface 31 are unconnected pins; pin 10 of the second embedded display interface 31 is the second target pin; pins 12, 16, 17, 20, 23, 26, 29, and 30 of the second embedded display interface 31 are... Pins 2, 34, 36, 39, 42, 45, 48, and 51 are ground pins; pin 11 of the second embedded display interface 31 is an aging test pin; pin 13 of the second embedded display interface 31 is a data write pin, pin 14 is a serial communication data signal transmission pin, and pin 15 is a clock pin; pins 18, 19, 21, 22, 24, 25, 27, and 28 of the second embedded display interface 31 are second data transmission pins; pins 30 and 31 of the second embedded display interface 31 are second instruction transmission pins.The thirty-third pin of the second embedded display interface 31 is a hot-plug detection pin.

[0110] Figure 3 shows the interface definition for the first embedded display interface 21 and the second embedded display interface 31 as eight channels.Specifically, pins 1 to 8 of the first embedded display interface 21 are power supply pins; pin 9 of the first embedded display interface 21 is an unconnected pin; pin 10 of the first embedded display interface 21 is the first target pin; pins 12, 16, 17, 20, 23, 26, 29, 32, 34, 36, 39, 42, 45, 48, and 51 of the first embedded display interface 21 are ground pins; pin 11 of the first embedded display interface 21 is an aging test pin; pin 13 of the first embedded display interface 21 is a data write pin; pin 14... The first embedded display interface 21 has the following pins: pin 18, pin 19, pin 21, pin 22, pin 24, pin 25, pin 27, pin 28, pin 37, pin 38, pin 40, pin 41, pin 43, pin 44, pin 46, and pin 47. These are the first data transmission pins. The third, third, forty-ninth, and fiftieth pins are the first instruction transmission pins. The thirty-third pin is the hot-plug detection pin, and the thirty-fifth pin is the slave hot-plug detection pin. Pins: Pins 1 to 8 of the second embedded display interface 31 are power supply pins; Pin 9 of the second embedded display interface 31 is an unconnected pin; Pin 10 of the second embedded display interface 31 is the second target pin; Pins 12, 16, 17, 20, 23, 26, 29, 32, 34, 36, 39, 42, 45, 48, and 51 of the second embedded display interface 31 are ground pins; Pin 11 of the second embedded display interface 31 is an aging test pin; Pin 13 of the second embedded display interface 31 is a data write pin; Pin 14... Pin 15 is the clock pin for serial communication data signal transmission; pins 18, 19, 21, 22, 24, 25, 27, 28, 37, 38, 40, 41, 43, 44, 46, and 47 of the second embedded display interface 31 are the second data transmission pins; pins 30, 31, 49, and 50 of the second embedded display interface 31 are the second instruction transmission pins; pin 33 of the second embedded display interface 31 is the hot-plug detection pin, and pin 35 is the slave hot-plug detection pin.

[0111] The display screen 10 can be a liquid crystal display screen or an OLED (Organic Light-Emitting Diode) display screen with a high refresh rate. The display screen 10 can be a large-size display screen, such as a 100-inch display screen. The timing controller 30 is used to process the display data transmitted from the control module 20 and other signal sources. The timing controller 30 and the display screen 10 can transmit data through P2P (peer-to-peer) and other methods.

[0112] In this embodiment, the control module 20 can be the motherboard of the display system. The motherboard may include a main circuit board and a main chip disposed on the main circuit board, as shown in Figure 4. The main chip type can be a first chip (x86 architecture) running a Windows system. As shown in Figure 5, the main chip type can also be a second chip (ARM (Advanced RISC Machines) architecture) running an Android system. For example, a main chip of the second chip type can be a SOC (System on Chip) chip, etc.

[0113] In other embodiments, as shown in Figure 6, when the main chip is a second chip type running the Android system, the main chip can also be connected to the OPS module to obtain display data transmitted by the OPS module. The OPS module can be a first chip running the Windows system, or it can be another data source device connected to the display system, depending on the actual situation. The main chip and the OPS module can transmit data via an HDMI (High Definition Multimedia Interface) 2.1 interface or an OPS interface, or they can be connected in other ways, depending on the actual situation.

[0114] In this embodiment of the invention, the control module 20 is connected to the first embedded display interface 21, and the timing controller 30 is connected to the second embedded display interface 31. The first embedded display interface 21 and the second embedded display interface 31 are connected through interface pins. The control module 20 controls the voltage level of the first target pin of the first embedded display interface 21 according to the chip type used. If the chip type used by the control module 20 is the first chip type, the first voltage value of the first target pin of the first embedded display interface 21 is determined to be a high-level voltage. Based on the first voltage value, the voltage level of the first target pin is controlled to be a high-level voltage, and the voltage level of the second target pin of the second embedded display interface 31 is controlled to be a high-level voltage through the voltage level of the first target pin. The first target pin can be any pin in the first embedded display interface 21. It should be noted that when determining the first voltage value of the first target pin, the control module 20 determines the interface definition of the first embedded display interface 21 based on the first voltage value, and defines each interface pin of the first embedded display interface 21. If the first voltage value is a high-level voltage, the interface definition in Figure 2 is used to define each interface pin in the first embedded display interface 21. The timing controller 30 determines the first channel parameters corresponding to the high-level voltage detected on the second target pin of the second embedded display interface 31, and defines each interface pin of the second embedded display interface 31 according to the interface definition corresponding to the high-level voltage (as shown in Figure 2). A data transmission channel for transmitting display data is established between the timing controller 30 and the control module 20 based on the first channel parameters.

[0115] The control module 20 can control the voltage level of the first target pin according to the chip type in the following ways: The control module 20 can configure the power supply on the motherboard to provide a high-level voltage to the first target pin via software; alternatively, it can configure the voltage level of the first target pin to be either high or low by default after power-on during factory settings. The specific method of providing voltage to the first target pin can be set according to actual conditions. It should be noted that the timing controller 30 can determine that the voltage level of the second target pin is high by: determining a second voltage value for the second target pin, comparing it with a first voltage threshold; if the second voltage value is greater than or equal to the first voltage threshold, then the voltage level of the second target pin is determined to be high.

[0116] If the control module 20 uses the second chip type, it determines that the first voltage value of the first target pin of the first embedded display interface 21 is a low-level voltage. Based on the first voltage value, it controls the voltage level of the first target pin to be low, and controls the voltage level of the second target pin of the second embedded display interface 31 to be low through the voltage level of the first target pin. It should be noted that when determining the first voltage value of the first target pin, the control module 20 determines the interface definition of the first embedded display interface 21 based on the first voltage value, defining each interface pin of the first embedded display interface 21. If the first voltage value is low, the interface definition in Figure 3 is used to define each interface pin of the first embedded display interface 21. The timing controller 30 determines the second channel parameters corresponding to the low-level voltage based on the low-level voltage detected at the second target pin of the second embedded display interface 31, and defines each interface pin of the second embedded display interface 31 according to the interface definition corresponding to the low-level voltage (as shown in Figure 3). A data transmission channel for transmitting display data between the timing controller 30 and the control module 20 is established based on the second channel parameters. The number of channels indicated by the second channel parameters is greater than the number of channels indicated by the first channel parameters. It should be noted that the timing controller 30 determines that the voltage level of the second target pin is low by: determining a second voltage value for the second target pin; comparing the second voltage value with a second voltage threshold; and if the second voltage value is less than or equal to the second voltage threshold, then determining that the voltage level of the second target pin is low.

[0117] After completing the data transmission channel between the timing controller 30 and the control module 20, the timing controller 30 receives the display data transmitted by the control module 20 based on the first data transmission pin in the first embedded display interface 21 via the second data transmission pin in the second embedded display interface 31, and transmits the display data to the display screen 10. The display screen 10 receives the display data transmitted by the timing controller 30 and outputs the display data.

[0118] Through the above technical solution, the control module sets the voltage level of the first target pin according to the chip type, enabling the timing controller to establish a data transmission channel between the timing controller and the control module for transmitting display data based on the channel parameters corresponding to the voltage level. This allows for the establishment of a data transmission channel for transmitting high refresh rate display data based on the pin definition of the target pin, thus enabling the control module to use different chip types and drive methods to transmit high refresh rate display data, thereby improving the versatility and reliability of the display device in displaying high refresh rate display data.

[0119] Based on the display system shown in Figure 1, the channel establishment method provided by the embodiments of the present invention will be described in detail below with reference to Figure 7. Specifically, the channel establishment method provided by the embodiments of the present invention can be a method for establishing a data transmission channel.

[0120] Please refer to Figure 7, which is a flowchart illustrating a channel establishment method provided by an embodiment of the present invention. As shown in Figure 7, this method is applied to a timing controller and may include the following steps S101-S103.

[0121] S101, Obtain the voltage level transmitted by the control module based on the first target pin of the first embedded display interface, and control the voltage level of the second target pin of the second embedded display interface;

[0122] In one embodiment, the timing controller in the display system can acquire the voltage level transmitted by the control module through the first target pin of the first embedded display interface, determine the second voltage value of the second target pin of the second embedded display interface based on the first voltage value of the voltage level, and control the voltage level of the second target pin based on the second voltage value. The second target pin can be any pin in the second embedded display interface, the first voltage value can be the voltage level transmitted by the control module through the first target pin of the first embedded display interface, and the second voltage value is the same as the first voltage value.

[0123] Specifically, the control module determines the first voltage value based on the chip type used. The chip type can be either a Windows-based chip or an Android-based chip. If the chip type is the first type, the first voltage value can be a high-level voltage; if the chip type is the second type, the first voltage value can be a low-level voltage. It can be understood that the first voltage value for the first chip type can also be a low-level voltage, and the first voltage value for the second chip type can be a high-level voltage; the specific setting can be determined according to the actual situation.

[0124] It should be noted that the specific value of the first voltage can be a voltage value pre-agreed upon by the timing controller and the control module. This first voltage value can be a specific value or a voltage threshold. For example, if a specific value is used, the high-level voltage can be 3.3V, and the low-level voltage can be 0V or the target pin can be grounded. If a voltage threshold is used, a first voltage value greater than or equal to the first voltage threshold can be defined as a high-level voltage, and a first voltage value less than or equal to the second voltage threshold can be defined as a low-level voltage. The first voltage threshold is greater than the second voltage threshold, and the specific values ​​of the first and second voltage thresholds can be set according to the actual situation.

[0125] S102, if the voltage level of the second target pin is a high voltage level, then based on the first channel parameters corresponding to the high voltage level, a data transmission channel for transmitting display data is established between the timing controller and the control module.

[0126] In one embodiment, if the voltage level of the second target pin is a high voltage level, then the first channel parameter corresponding to the high voltage level is determined. The first channel parameter can be a parameter defined by the interface of the second embedded display interface used to indicate the number of channels. A data transmission channel between the timing controller and the control module is established based on the first channel parameter. The data transmission channel can be a channel used to receive display data transmitted by the control module.

[0127] Specifically, when the voltage level of the second target pin is high, it can be determined that the chip type used by the control module is the first chip type driven by X86. The control module defines the pins of each interface in the first embedded display interface based on the first channel parameters of the high voltage level. The timing controller correspondingly uses the first channel parameters to define the pins of each interface in the second embedded display interface, thereby establishing a data transmission channel between the control module and the control module for transmitting display data. The established data transmission channel can be a 4-lane 5.4G or 4-lane 8.1G channel, that is, a channel with 4 channels and a data transmission rate of 5.4Gbps, or a channel with 4 channels and a data transmission rate of 8.1Gbps, thereby enabling the timing controller to obtain the high refresh rate display data transmitted by the control module using the X86 driver chip.

[0128] It is understandable that the channel parameters used by the control module and the embedded display interface in the timing controller are determined based on the voltage level of the target pin, thereby establishing a data transmission channel between the timing controller and the control module. Since the channel parameters include the number of channels for data transmission that characterize the chip type used by the control module, it is compatible with different chip types and driving methods used by the control module. Thus, high refresh rate display data is transmitted according to the established data transmission channel.

[0129] S103, if the voltage level of the second target pin is a low voltage, then based on the second channel parameters corresponding to the low voltage, establish a data transmission channel between the timing controller and the control module for transmitting display data;

[0130] In one embodiment, if the voltage level of the second target pin is low, then the second channel parameter corresponding to the low voltage is determined, and a data transmission channel between the timing controller and the control module is established based on the second channel parameter. The second channel parameter can be an interface-defined parameter used to indicate the number of channels and the second embedded display interface, and the number of channels indicated by the second channel parameter is greater than the number of channels indicated by the first channel parameter.

[0131] Specifically, when the voltage level of the second target pin is low, the chip type used by the control module is determined to be the second chip type. The control module defines the pins of each interface in the first embedded display interface based on the second channel parameters of the low voltage. The timing controller correspondingly uses the second channel parameters to define the pins of each interface in the second embedded display interface, thereby establishing a data transmission channel between the control module and the control module for transmitting display data. The established data transmission channel can be an 8-lane 5.4G channel, that is, a channel with 8 channels and a data transmission rate of 5.4Gbps, thereby enabling the timing controller to obtain high refresh rate display data transmitted by the integrated chip of the control module using the ARM architecture.

[0132] In this embodiment of the invention, a data transmission channel between the second target pin of the second embedded display interface and the control module is established based on the channel parameters corresponding to the level voltage. This enables the establishment of a data transmission channel for transmitting high refresh rate display data according to the pin definition of the target pin. This allows the control module to use different chip types and drive methods to transmit high refresh rate display data, thereby improving the versatility and reliability of the display device in displaying high refresh rate display data.

[0133] Please refer to Figure 8, which is a flowchart illustrating a channel establishment method provided by an embodiment of the present invention. As shown in Figure 8, this method is applied to a timing controller and may include the following steps S201-S207.

[0134] S201, Obtain the voltage level transmitted by the control module based on the first target pin of the first embedded display interface, and control the voltage level of the second target pin of the second embedded display interface;

[0135] In one embodiment, the first embedded display interface 21 and the second embedded display interface 31 are connected via interface pins, which can be connected via a data line (T-CON FFC). The timing controller in the display system can obtain the voltage level transmitted by the control module based on the first target pin of the first embedded display interface, and control the voltage level of the second target pin of the second embedded display interface according to the voltage level. The second target pin can be any pin in the second embedded display interface.

[0136] Specifically, the control module determines the first voltage value of the first target pin of the first embedded display interface based on the chip type used, and sets the voltage level of the first target pin according to the first voltage value. The chip type can be either a first chip type running a Windows system or a second chip type running an Android system. If the chip type is the first chip type, the first voltage value of the first target pin can be the voltage value corresponding to a high-level voltage; if the chip type is the second chip type, the first voltage value of the target pin can be the voltage value corresponding to a low-level voltage. Of course, the correspondence between the high / low level voltage settings and the chip type can be set according to actual needs. For example, if the chip type is the first chip type, the voltage level of the first target pin can be a low-level voltage; if the chip type is the second chip type, the voltage level of the first target pin can be a high-level voltage, and so on.

[0137] Optionally, the control module can obtain the chip identifier corresponding to the chip used, and determine the chip type corresponding to the chip used by the control module based on the chip identifier.

[0138] It should be noted that the specific value of the first voltage can be a voltage value pre-agreed upon by the timing controller and the control module. This first voltage value can be a specific value or a voltage threshold. For example, if a specific value is used, the high-level voltage can be 3.3V, and the low-level voltage can be 0V or the target pin can be grounded. If a voltage threshold is used, a first voltage value greater than or equal to the first voltage threshold can be defined as a high-level voltage, and a first voltage value less than or equal to the second voltage threshold can be defined as a low-level voltage. The first voltage threshold is greater than the second voltage threshold, and the specific values ​​of the first and second voltage thresholds can be set according to the actual situation.

[0139] Specifically, the control module can control the voltage level of the first target pin based on its first voltage value in either software or hardware. Software settings can be used to drive the power supply on the motherboard to supply power to the first target pin based on the first voltage value corresponding to the type of chip used.

[0140] Furthermore, the timing controller can determine the voltage level of the second target pin by: acquiring the second voltage value of the second target pin, comparing the second voltage value with the first voltage threshold and the second voltage threshold respectively; if the second voltage value is greater than or equal to the first voltage threshold, then the voltage level of the second target pin is determined to be a high voltage level; if the second voltage value is less than or equal to the second voltage threshold, then the voltage level of the second target pin is determined to be a low voltage level.

[0141] S202, if the voltage level of the second target pin is a high voltage level, then based on the first channel parameters corresponding to the high voltage level, set the pin definitions of each interface pin of the second embedded display interface;

[0142] In one embodiment, if the voltage level of the second target pin is a high voltage level, the first channel parameter corresponding to the high voltage level is obtained. The first channel parameter can be a parameter used to indicate the number of channels and the interface definition of the second embedded display interface. The pins of each interface in the second embedded display interface are defined according to the first channel parameter, thus completing the pin definition of each interface pin.

[0143] The pin definitions of each interface pin set according to the parameters of the first channel can be found in Figure 2.

[0144] S203, if the voltage level of the second target pin is a low voltage level, then based on the second channel parameters corresponding to the low voltage level, set the pin definitions of each interface pin of the second embedded display interface;

[0145] In one embodiment, if the voltage level of the second target pin is a low voltage level, the second channel parameter corresponding to the low voltage level is obtained. The second channel parameter can be a parameter used to indicate the number of channels and the interface definition of the second embedded display interface. The pins of each interface pin in the second embedded display interface are defined according to the second channel parameter, thus completing the pin definition of each interface pin.

[0146] The pin definitions of each interface pin set according to the second channel parameters can be found in Figure 3.

[0147] S204, based on the second data transmission pin and the second instruction transmission pin in the second embedded display interface, matches the display parameters between the timing controller and the control module, and determines the link status data in the display parameters;

[0148] In one embodiment, after defining the pins of each interface pin in the second embedded display interface, the display parameters between the timing controller and the control module are matched based on the second data transmission pin and the second instruction transmission pin in the second embedded display interface to determine the link status between the timing controller and the control module. The display parameters can be parameters related to the timing controller controlling the display screen to output high refresh rate display data, and parameters related to the control module generating high refresh rate display data. The link status data can characterize the stability of the link between the control module and the timing controller. The second instruction transmission pin can be a pin in the second embedded display interface used for transmitting instructions, and the second data transmission pin can be a pin in the second embedded display interface used for transmitting data.

[0149] Specifically, the display parameters also include performance data, identification data, and configuration data. One feasible way to match the display parameters between the timing controller and the control mode is to transmit trigger information to the control module via the second instruction transmission pin, thereby triggering the control module to transmit a performance data read request via the first instruction transmission pin. The trigger information can be a hot-swap detection pulse, etc., and can be set according to the actual situation. The timing controller responds to a performance data read request transmitted by the control module. In response, it transmits performance data to the control module via a second instruction transmission pin. This performance data can characterize the timing controller's data receiving capability, such as the refresh rate representing the number of images it can receive per second. The timing controller also responds to a recognition data read request transmitted by the control module via a first instruction transmission pin. This recognition data can characterize the display model, resolution, etc., and is transmitted to the control module via a second instruction transmission pin. Furthermore, the timing controller acquires verification data transmitted by the control module via a second data transmission pin and stores this verification data in a register within the timing controller. This verification data verifies whether the timing controller can receive data transmitted by the control module through the link. After transmitting verification data to the timing controller, the control module transmits a verification data read request to the timing controller via a first instruction transmission pin. In response to this request, the timing controller returns link status data via a second instruction transmission pin. This link status data indicates whether the timing controller has stored the verification data, thereby indicating the stability of the link between the timing controller and the control module.

[0150] It is understandable that the interface pins between the first embedded display interface and the second embedded display interface correspond one-to-one. For example, instructions are transmitted between the first instruction transmission pin and the second instruction transmission pin, and data is transmitted between the first data transmission pin and the second data transmission pin. Since the first embedded display interface includes more than one first data transmission pin and the second embedded display interface includes more than one second data transmission pin, the specific first data transmission pin and second data transmission pin used for data transmission can be set according to the actual situation.

[0151] For example, as shown in Figure 9, after the timing controller powers on the second target pin, it generates a hot-plug detection pulse and transmits it to the control module. Upon receiving the pulse, the control module sends a performance data read request to the timing controller, which can be DPCD (DisplayPort Configuration Data). In response, the timing controller transmits its performance data to the control module. The control module determines the video mode based on the performance data to determine the corresponding data type to be generated, such as the refresh rate of the display data. The timing controller also receives an identification data read request from the control module via I2C-over-AUX, which can be EDID (Extended Display Identification Data). In response, the timing controller transmits identification data, representing the display model and other information, to the control module via I2C-over-AUX. I2C-over-AUX can be using I2C (Inter-Integrated Display) on the AUX (Auxiliary) channel. The control module uses the Circuit protocol to transmit data. Based on the identification data, it determines the verification method for the embedded display interface, generates verification data, and transmits the verification data to the timing controller. The timing controller stores the verification data in its registers. After transmitting the verification data to the timing controller, the control module initiates link training by sending a link status read request to the timing controller to determine the stability of the link between the control module and the timing controller. Upon receiving the request from the control module to determine the link status data, the timing controller responds by returning the link status data to the control module. The link status data can indicate whether the timing controller has stored the verification data; for example, "1" can represent stored verification data, and "0" can represent no stored verification data. The specific settings can be configured according to the actual situation. If the link status data indicates that the link is unstable, the control module repeats step 7 until the link status data indicates that the link is in a stable state.

[0152] S205, if the link status data indicates that the link between the timing controller and the control module is in a stable state, then the establishment of the data transmission channel between the timing controller and the control module is completed.

[0153] In one embodiment, if the link status data indicates that the link between the timing controller and the control module is in a stable state, it is determined that the timing controller and the control module can transmit data through the first embedded display interface and the second embedded display interface, and the transmitted data can be successfully received, thus completing the establishment of the data transmission channel between the timing controller and the control module.

[0154] Specifically, if the voltage level of the second target pin is high, it can be determined that the data transmission channel established between the timing controller and the control module based on the first channel parameters is a 4-lane 5.4G or 4-lane 8.1G channel, i.e., a four-channel channel with a transmission rate of 5.4Gbps or 8.1Gbps, thereby enabling the timing controller to acquire high refresh rate display data transmitted by the control module using the x86 driver chip. If the voltage level of the second target pin is low, it can be determined that the data transmission channel established between the timing controller and the control module based on the second channel parameters is an 8-lane 5.4G channel, i.e., an eight-channel channel with a transmission rate of 5.4Gbps, thereby enabling the timing controller to acquire high refresh rate display data transmitted by the control module using the ARM architecture integrated chip.

[0155] For example, as shown in Figure 10, when the timing controller determines that the second voltage value of the second target pin is 3.3V, it establishes a "4-lane 5.4G or 4-lane 8.1G" data transmission channel to transmit data with the control module; when the timing controller determines that the second voltage value of the second target pin is 0V, it establishes an "8-lane 5.4G" data transmission channel to transmit data with the control module. When the control module uses a chip of the second chip type for data transmission, in addition to generating and transmitting display data using the second chip, it can also receive display data transmitted by a chip of the first chip type. The display data is then transmitted to the timing controller through the established "8-lane 5.4G" data transmission channel. The external chip transmitting the display data to the control module can be a chip from another device connected to the display system. This chip transmits data with the second chip type chip in the control module through an HDMI 2.1 interface.

[0156] It is understandable that the channel parameters indicated by the high-level voltage and low-level voltage can be set in a corresponding relationship according to the actual situation. For example, the channel parameter indicated by the high-level voltage is the second channel parameter, and the channel parameter indicated by the low-level voltage is the first channel parameter.

[0157] S206, Obtain display data transmitted by the control module based on the data transmission channel;

[0158] In one embodiment, after establishing a data transmission channel between the timing controller and the control module, display data transmitted by the control module is obtained based on the data transmission channel. The display data may include at least one frame of video data, and the video data may be any frame of image data in the display data.

[0159] Specifically, after the timing controller and the control module establish a data transmission channel, the control module transmits display data to the timing controller through the first embedded display interface and the second embedded display interface.

[0160] Furthermore, before receiving display data from the control module, the control module transmits data parameters to the timing controller to synchronize the clock parameters for data transmission between the timing controller and the control module. Display data parameters can include parameters such as the refresh rate, while clock parameters represent the output duration used by the timing controller and control module during data transmission, enabling the timing controller to output display data to the screen accurately and promptly based on the clock parameters.

[0161] For example, as shown in Figure 9, when the control module in Figure 9 determines that the link state is stable, it sends data parameters to the timing controller. The data parameters can be parameters used to indicate the refresh rate of the display data, such as MSA (Main Stream Attribute) data. The timing controller synchronizes the clock parameters based on the data parameters to accurately output the display data according to the refresh rate of the display data.

[0162] S207, determine the display sequence of each video data in the display data, and use the display sequence control to output each video data in sequence on the display screen;

[0163] In one embodiment, the timing controller acquires display data transmitted by the control module based on the data transmission channel and determines the display timing of each video / video data segment within the display data. The display timing can indicate the output order of each video / video data segment. The timing controller outputs each video / video data segment sequentially based on the display timing and the refresh rate represented by the clock parameters. The preset refresh rate can indicate the display duration and switching rate of the video / video data. The display duration can represent the duration of each frame of video / video data output on the display screen, such as 41.7 milliseconds, and the switching rate can represent the rate at which each video / video data segment is switched, such as 24 frames per second.

[0164] For example, as shown in Figure 11, the display sequence of each video data in the display data is determined. Each video data is output sequentially according to its display sequence, and the video data is switched according to the display parameters, thereby completing the output of display data on the display interface.

[0165] Furthermore, to improve the safety and reliability of each pin in the embedded display interface, a feasible approach is to cluster each interface pin in the second embedded display interface based on its function to obtain at least one pin group. The pin function can be the function performed by the interface pin of the second embedded display interface, such as receiving power voltage from power transmission. The pin group includes at least one interface pin with the same pin function. Empty pins are set between each pin group. Empty pins can be pins that are not connected to circuits or have no pin function, thereby avoiding safety issues caused by mis-insertion when connecting the interface.

[0166] For example, as shown in Figure 12, the first and second pins in the second embedded display interface of Figure 12 are in the same pin group for receiving a +12V power voltage. The fourth pin is the second target pin. An empty third pin is provided between the second target pin and the pin group composed of the first and second pins, thereby preventing the display device from burning out due to the mixed use of timing controllers during the manufacturing process, improving the reliability of the embedded display interface, and thus improving the safety of the display device.

[0167] In this embodiment of the invention, a data transmission channel between the second embedded display interface and the control module is established based on the level voltage of the second target pin and the corresponding channel parameters. This allows for the establishment of a data transmission channel for high refresh rate display data according to the pin definition of the target pin. Furthermore, this ensures compatibility with different chip types and driving methods used by the control module for transmitting high refresh rate display data, improving the versatility and reliability of the display device in displaying high refresh rate data. Further, by matching the display parameters between the timing controller and the control module, a data transmission channel between them is established. Additionally, by outputting the display data transmitted by the control module onto the display screen, high refresh rate display data is displayed. Moreover, by grouping the pins of the embedded display interface based on their functions to obtain pin groups, and by setting unused pins between each pin group, the display device is prevented from burning out due to the mixed use of timing controllers during the manufacturing process, thus improving the reliability of the embedded display interface and the safety of the display device.

[0168] This invention also provides a computer storage medium that can store multiple program instructions. The program instructions are adapted to be loaded by a processor and executed as shown in the embodiments of Figures 1-12 above. For the specific execution process, please refer to the detailed description of the embodiments shown in Figures 1-12, which will not be repeated here.

[0169] Please refer to Figure 13, which is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. As shown in Figure 13, the display device 1000 may include: at least one processor 1001, such as a CPU, at least one network interface 1004, an input / output interface 1003, a memory 1005, and at least one communication bus 1002. The communication bus 1002 is used to realize communication between these components. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be a high-speed RAM memory or a non-volatile memory, such as at least one disk storage device. Optionally, the memory 1005 may also be at least one storage device located remotely from the aforementioned processor 1001. As shown in Figure 13, the memory 1005, as a computer storage medium, may include an operating system, a network communication module, an input / output interface module, and a channel establishment application.

[0170] In the display device 1000 shown in Figure 13, the input / output interface 1003 is mainly used to provide an input interface for the user and to obtain the data input by the user.

[0171] In one embodiment, processor 1001 can be used to invoke a channel creation application stored in memory 1005, and specifically perform the following operations:

[0172] The acquisition control module controls the level voltage of the second target pin of the second embedded display interface based on the level voltage transmitted by the first target pin of the first embedded display interface, wherein the second target pin is any pin in the second embedded display interface;

[0173] If the voltage level of the second target pin is high, then based on the first channel parameters corresponding to the high voltage, a data transmission channel for transmitting display data is established between the timing controller and the control module; or,

[0174] If the voltage level of the second target pin is low, a data transmission channel for transmitting display data is established between the timing controller and the control module based on the second channel parameters corresponding to the low voltage.

[0175] The number of channels indicated by the second channel parameter is greater than the number of channels indicated by the first channel parameter.

[0176] Optionally, when the processor 1001 executes the first channel parameters corresponding to the high-level voltage to establish a data transmission channel between the timing controller and the control module for transmitting display data, it specifically performs the following operations:

[0177] Based on the first channel parameters corresponding to the high-level voltage, set the pin definitions of each interface pin of the second embedded display interface;

[0178] Based on the pins of the second embedded display interface after pin definition, a data transmission channel for transmitting display data is established between the timing controller and the control module.

[0179] Optionally, when the processor 1001 executes the second channel parameters corresponding to the low-level voltage to establish a data transmission channel between the timing controller and the control module for transmitting display data, it specifically performs the following operations:

[0180] Based on the second channel parameters corresponding to the low-level voltage, set the pin definitions of each interface pin of the second embedded display interface;

[0181] Based on the pins of the second embedded display interface after pin definition, a data transmission channel for transmitting display data is established between the timing controller and the control module.

[0182] Optionally, when the processor 1001 executes the interface pins of the second embedded display interface based on the pin definitions to establish a data transmission channel between the timing controller and the control module for transmitting display data, it specifically performs the following operations:

[0183] Based on the second data transmission pin and the second instruction transmission pin in the second embedded display interface, the display parameters between the timing controller and the control module are matched to determine the link status data in the display parameters;

[0184] If the link status data indicates that the link between the timing controller and the control module is in a stable state, then the data transmission channel between the timing controller and the control module is established.

[0185] Optionally, the display parameters also include performance data, identification data, and configuration data. When the processor 1001 executes the second data transmission pin and the second instruction transmission pin in the second embedded display interface to match the display parameters between the timing controller and the control module and determine the link status data in the display parameters, it specifically performs the following operations:

[0186] Trigger information is transmitted to the control module via the second instruction transmission pin to trigger the control module to transmit a performance data read request via the first instruction transmission pin.

[0187] In response to a performance data read request transmitted by the control module, performance data is transmitted to the control module based on the second instruction transmission pin;

[0188] In response to the identification data read request transmitted by the control module based on the first instruction transmission pin, the identification data is transmitted to the control module based on the second instruction transmission pin;

[0189] The verification data transmitted by the control module based on the first data transmission pin is obtained based on the second data transmission pin, and the verification data is stored.

[0190] In response to the verification data read request transmitted by the control module based on the first instruction transmission pin, the link status data is returned based on the second instruction transmission pin. The link status data indicates the stability of the link between the timing controller and the control module.

[0191] Optionally, the display system also includes a display screen. After the processor 1001 establishes a data transmission channel between the timing controller and the control module for transmitting display data, it also performs the following operations:

[0192] The display data transmitted by the control module is obtained based on the data transmission channel. The display data includes at least one frame of video data.

[0193] Determine the display sequence of each video data item in the display data, and use the display sequence control to output each video data item sequentially on the display screen.

[0194] Optionally, before executing the acquisition of display data transmitted by the control module based on the data transmission channel, the processor 1001 also performs the following operations:

[0195] In response to the data parameters transmitted by the control module, the clock parameters of the data output are adjusted.

[0196] Optionally, the processor 1001 also performs the following operations:

[0197] Based on the pin function, each interface pin in the second embedded display interface is clustered to obtain at least one pin group, and the pin group includes at least one interface pin with the same pin function.

[0198] Set up unused pins between each pin group.

[0199] In this embodiment of the invention, a data transmission channel between the second embedded display interface and the control module is established based on the level voltage of the second target pin and the corresponding channel parameters. This allows for the establishment of a data transmission channel for high refresh rate display data according to the pin definition of the target pin. Furthermore, this ensures compatibility with different chip types and driving methods used by the control module for transmitting high refresh rate display data, improving the versatility and reliability of the display device in displaying high refresh rate data. Further, by matching the display parameters between the timing controller and the control module, a data transmission channel between them is established. Additionally, by outputting the display data transmitted by the control module onto the display screen, high refresh rate display data is displayed. Moreover, by grouping the pins of the embedded display interface based on their functions to obtain pin groups, and by setting unused pins between each pin group, the display device is prevented from burning out due to the mixed use of timing controllers during the manufacturing process, thus improving the reliability of the embedded display interface and the safety of the display device.

[0200] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0201] The above description discloses only preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A display system, characterized in that, The display system includes a display screen, a timing controller, and a control module. The control module is provided with a first embedded display interface, the timing controller is provided with a second embedded display interface, the display screen is connected to the timing controller, and the first embedded display interface and the second embedded display interface are connected through interface pins. The control module is used to control the voltage level of the first target pin of the first embedded display interface based on the type of chip used, and to control the voltage level of the second target pin of the second embedded display interface through the voltage level of the first target pin; The timing controller is configured to, if the voltage level of the second target pin is a high voltage level, establish a data transmission channel between the timing controller and the control module for transmitting display data based on the first channel parameter corresponding to the high voltage level; or, if the voltage level of the second target pin is a low voltage level, establish a data transmission channel between the timing controller and the control module for transmitting display data based on the second channel parameter corresponding to the low voltage level, wherein the number of channels indicated by the second channel parameter is greater than the number of channels indicated by the first channel parameter. The display screen is used to receive display data transmitted by the timing controller and output the display data; the display data is the display data transmitted by the control module to the second data transmission pin of the second embedded display interface of the timing controller based on the first data transmission pin of the first embedded display interface.

2. The display system according to claim 1, characterized in that, The step of controlling the voltage level of the first target pin of the first embedded display interface based on the type of chip used includes: The control module is configured to, if the chip type used is a first chip type, determine that the first voltage value of the first target pin of the first embedded display interface is a high-level voltage, control the level voltage of the first target pin based on the first voltage value, and control the level voltage of the second target pin of the second embedded display interface to be a high-level voltage through the level voltage of the first target pin; or, The control module is configured to, if the chip type used is a first chip type, determine that the first voltage value of the first target pin of the first embedded display interface is a low-level voltage, control the level voltage of the first target pin of the first embedded display interface based on the first voltage value, and control the level voltage of the second target pin of the second embedded display interface to be a low-level voltage through the level voltage of the first target pin.

3. The display system according to claim 1, characterized in that, The timing controller is configured to determine that the voltage level of the second target pin is a high-level voltage if the second voltage value of the second target pin is greater than or equal to the first voltage threshold. The timing controller is further configured to determine that the voltage level of the second target pin is a low voltage level if the second voltage value of the second target pin is less than or equal to the second voltage threshold, wherein the first voltage threshold is greater than the second voltage threshold.

4. The display system according to claim 2, characterized in that, The first chip type is a chip type that runs the Windows system, and the second chip type is a chip type that runs the Android system.

5. The display system according to claim 1, characterized in that, If the data transmission channel is established based on the first channel parameters, then the first to eighth pins of the first embedded display interface are power supply pins. The ninth, thirty-fifth, thirty-seventh, thirty-eighth, fortieth, forty-first, forty-third, forty-fourth, forty-sixth, forty-seventh, forty-ninth and fiftieth pins of the first embedded display interface are unconnected pins. The tenth pin of the first embedded display interface is the first target pin; Pins 12, 16, 17, 20, 23, 26, 29, 32, 34, 36, 39, 42, 45, 48 and 51 of the first embedded display interface are ground pins; The eleventh pin of the first embedded display interface is the aging test pin; The thirteenth pin of the first embedded display interface is a data write pin, the fourteenth pin is a serial communication data signal transmission pin, and the fifteenth pin is a clock pin; Pins 18, 19, 21, 22, 24, 25, 27, and 28 of the first embedded display interface are the first data transmission pins; Pins 30 and 31 of the first embedded display interface are the first instruction transmission pins; The thirty-third pin of the first embedded display interface is a hot-plug detection pin; The first to eighth pins of the second embedded display interface are power supply pins; The ninth, thirty-fifth, thirty-seventh, thirty-eighth, fortieth, forty-first, forty-third, forty-fourth, forty-sixth, forty-seventh, forty-ninth and fiftieth pins of the second embedded display interface are unconnected pins; The tenth pin of the second embedded display interface is the second target pin; Pins 12, 16, 17, 20, 23, 26, 29, 32, 34, 36, 39, 42, 45, 48 and 51 of the second embedded display interface are ground pins; The eleventh pin of the second embedded display interface is the aging test pin; The thirteenth pin of the second embedded display interface is a data write pin, the fourteenth pin is a serial communication data signal transmission pin, and the fifteenth pin is a clock pin; Pins 18, 19, 21, 22, 24, 25, 27, and 28 of the second embedded display interface are second data transmission pins; Pins 30 and 31 of the second embedded display interface are second instruction transmission pins; The 33rd pin of the second embedded display interface is a hot-plug detection pin.

6. The display system according to claim 1, characterized in that, If the data transmission channel is established based on the second channel parameters, then the first to eighth pins of the first embedded display interface are power supply pins; The ninth pin of the first embedded display interface is an unconnected pin; The tenth pin of the first embedded display interface is the first target pin; Pins 12, 16, 17, 20, 23, 26, 29, 32, 34, 36, 39, 42, 45, 48 and 51 of the first embedded display interface are ground pins; The eleventh pin of the first embedded display interface is the aging test pin; The thirteenth pin of the first embedded display interface is a data write pin, the fourteenth pin is a serial communication data signal transmission pin, and the fifteenth pin is a clock pin; The eighteenth, nineteenth, twenty-first, twenty-second, twenty-fourth, twenty-fifth, twenty-seventh, twenty-eighth, thirty-seventh, thirty-eighth, fortieth, forty-first, forty-third, forty-fourth, forty-sixth, and forty-seventh pins of the first embedded display interface are the first data transmission pins; Pins 30, 31, 49, and 50 of the first embedded display interface are the first instruction transmission pins; The 33rd pin of the first embedded display interface is a hot-plug detection pin, and the 35th pin is a slave hot-plug detection pin. The first to eighth pins of the second embedded display interface are power supply pins; The ninth pin of the second embedded display interface is an unconnected pin; The tenth pin of the second embedded display interface is the second target pin; Pins 12, 16, 17, 20, 23, 26, 29, 32, 34, 36, 39, 42, 45, 48 and 51 of the second embedded display interface are ground pins; The eleventh pin of the second embedded display interface is the aging test pin; The thirteenth pin of the second embedded display interface is a data write pin, the fourteenth pin is a serial communication data signal transmission pin, and the fifteenth pin is a clock pin; Pins 18, 19, 21, 22, 24, 25, 27, 28, 37, 38, 40, 41, 43, 44, 46, and 47 of the second embedded display interface are second data transmission pins; Pins 30, 31, 49, and 50 of the second embedded display interface are second instruction transmission pins; The 33rd pin of the second embedded display interface is a hot-plug detection pin, and the 35th pin is a slave hot-plug detection pin.

7. The display system according to claim 1, characterized in that, The timing controller is used to receive display data transmitted by the control module based on the first data transmission pin in the first embedded display interface based on the second data transmission pin in the second embedded display interface, and transmit the display data to the display screen.

8. A method for establishing a channel, characterized in that, The method is applied to a timing controller in a display system. The display system further includes a control module, the control module having a first embedded display interface, and the timing controller having a second embedded display interface. The first embedded display interface and the second embedded display interface are connected via interface pins. The method includes: The control module acquires the voltage level transmitted by the first target pin of the first embedded display interface and controls the voltage level of the second target pin of the second embedded display interface, wherein the second target pin is any pin in the second embedded display interface; If the voltage level of the second target pin is high, then based on the first channel parameters corresponding to the high voltage, a data transmission channel for transmitting display data is established between the timing controller and the control module, or... If the voltage level of the second target pin is low, a data transmission channel for transmitting display data is established between the timing controller and the control module based on the second channel parameter corresponding to the low voltage. The number of channels indicated by the second channel parameter is greater than the number of channels indicated by the first channel parameter.

9. The method according to claim 8, characterized in that, The step of establishing a data transmission channel between the timing controller and the control module for transmitting display data based on the first channel parameters corresponding to the high-level voltage includes: Based on the first channel parameters corresponding to the high-level voltage, the pin definitions of each interface pin of the second embedded display interface are set; Based on the pin definitions of each of the interface pins of the second embedded display interface, a data transmission channel for transmitting display data is established between the timing controller and the control module.

10. The method according to claim 8, characterized in that, The step of establishing a data transmission channel between the timing controller and the control module for transmitting display data based on the second channel parameters corresponding to the low-level voltage includes: Based on the second channel parameters corresponding to the low-level voltage, the pin definitions of each interface pin of the second embedded display interface are set; Based on the pin definitions of each of the interface pins of the second embedded display interface, a data transmission channel for transmitting display data is established between the timing controller and the control module.

11. The method according to any one of claims 9 or 10, characterized in that, The interface pins of the second embedded display interface, based on the pin definitions, establish a data transmission channel between the timing controller and the control module for transmitting display data, including: Based on the second data transmission pin and the second instruction transmission pin in the second embedded display interface, the display parameters between the timing controller and the control module are matched to determine the link status data in the display parameters; If the link status data indicates that the link between the timing controller and the control module is in a stable state, then the establishment of the data transmission channel between the timing controller and the control module is completed.

12. The method according to claim 11, characterized in that, The display parameters also include performance data, identification data, and configuration data. The step of matching the display parameters between the timing controller and the control module based on the second data transmission pin and the second instruction transmission pin in the second embedded display interface to determine the link status data in the display parameters includes: Trigger information is transmitted to the control module via the second instruction transmission pin to trigger the control module to transmit a performance data read request via the first instruction transmission pin. In response to the performance data read request transmitted by the control module, the performance data is transmitted to the control module based on the second instruction transmission pin; In response to the identification data read request transmitted by the control module based on the first instruction transmission pin, the identification data is transmitted to the control module based on the second instruction transmission pin; The verification data transmitted by the control module based on the first data transmission pin is obtained based on the second data transmission pin, and the verification data is stored. In response to the verification data read request transmitted by the control module based on the first instruction transmission pin, the link status data is returned based on the second instruction transmission pin. The link status data indicates the stability of the link between the timing controller and the control module.

13. The method according to claim 8, characterized in that, The display system further includes a display screen, and after establishing a data transmission channel between the timing controller and the control module for transmitting display data, it further includes: The display data transmitted by the control module is obtained based on the data transmission channel, and the display data includes at least one frame of video data; The display timing of each video data in the display data is determined, and the display timing is used to control the display screen to output each video data in sequence.

14. The method according to claim 13, characterized in that, Before obtaining the display data transmitted by the control module based on the data transmission channel, the method further includes: In response to the data parameters transmitted by the control module, the clock parameters of the data output are adjusted.

15. The method according to claim 8, characterized in that, The method further includes: Based on the function of the pins, each interface pin in the second embedded display interface is clustered to obtain at least one pin group, and the pin group includes at least one interface pin with the same function. Empty pins are provided between each of the aforementioned pin groups.

16. A display device, characterized in that, The device includes a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to execute the steps of the method as described in any one of claims 8 to 15.

17. A computer storage medium storing a plurality of instructions adapted for loading by a processor and performing the steps of the method as claimed in any one of claims 8 to 15.

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