Led-chip-mounting board and display device

Abstract

This display device comprises: a first insulating layer that spreads in a region where a pixel is formed; a mounting pad that is provided on the first insulating layer and is disposed so as to correspond to the region where the pixel is formed; a second insulating layer that covers the first insulating layer and has an opening through which the upper surface of the mounting pad is exposed; a connection electrode that is disposed in a region inside of the opening and is in contact with the upper surface of the mounting pad; and an LED chip that is electrically connected to the connection electrode.

Description

Mounting Substrate for LED Chip and Display Device

[0001] One embodiment of the present invention relates to a mounting substrate for an LED (Light Emitting Diode) chip and a display device.

[0002] In recent years, as a next-generation display, the development of a so-called micro-LED display in which minute micro-LEDs are arranged within pixels has been underway. A micro-LED is a self-emitting element similar to an OLED (Organic Light Emitting Diode), but unlike an OLED, it is composed of a stable inorganic compound containing gallium (Ga) or indium (In) or the like. Therefore, compared with an OLED display, a micro-LED display is more likely to ensure high reliability. Further, a micro-LED has high luminous efficiency and can achieve high brightness. Therefore, a micro-LED display is expected as a next-generation display having high reliability, high brightness, and high contrast.

[0003] In a display equipped with an OLED, an OLED is directly formed on a substrate including a backplane on which a thin film transistor (TFT: Thin Film Transistor) is fabricated, whereas in a micro-LED display, individual LED chips are mounted via bumps on a substrate on which electrode pads are formed.

[0004] Japanese Unexamined Patent Application Publication No. 2021-015859

[0005] The bumps used for mounting an LED chip on a backplane substrate have a function of electrically connecting between the LED chip and the electrode pad and a function of adhering the LED chip onto the backplane substrate. Therefore, when mounting an LED chip on a backplane substrate, it is necessary to prevent the shape of the bumps from collapsing or spreading too much to the peripheral area of the electrode pad, and to enhance the shape reproducibility.

[0006] One embodiment of the present invention aims to provide an LED chip mounting substrate in which the bump shape is reproduced as designed. Another embodiment of the present invention aims to provide a display device in which the bump shape is reproduced as designed.

[0007] An LED chip mounting substrate according to one embodiment of the present invention includes a mounting pad disposed on a first insulating layer and electrically connected to the LED chip, a second insulating layer that covers the first insulating layer and has an opening that exposes the upper surface of the mounting pad, and a connecting electrode disposed in the region inside the opening and in contact with the upper surface of the mounting pad.

[0008] A display device according to one embodiment of the present invention includes a first insulating layer extending over a region where pixels are formed, a mounting pad arranged corresponding to the region where pixels are formed and provided on the first insulating layer, a second insulating layer covering the first insulating layer and having an opening that exposes the upper surface of the mounting pad, a connecting electrode arranged in a region inside the opening and in contact with the upper surface of the mounting pad, and an LED chip electrically connected to the connecting electrode.

[0009] This is a plan view showing the schematic configuration of a display device according to one embodiment of the present invention. This is a block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. This is an example of a circuit diagram showing the configuration of the pixel circuit of a display device according to one embodiment of the present invention. This is a plan view showing the configuration of the pixels of a display device according to one embodiment of the present invention. This is an end view showing the configuration of the pixels of a display device according to one embodiment of the present invention. This is an end view showing the configuration of the pixels of a display device according to one embodiment of the present invention. This is a plan view showing the configuration of the pixels of a display device according to one embodiment of the present invention. This is an end view showing the configuration of the pixels of a display device according to one embodiment of the present invention.

[0010] Embodiments of the present invention will be described below with reference to the drawings, etc. However, the present invention can be implemented in various forms without departing from its essence. The present invention is not to be interpreted as being limited to the embodiments described below. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the drawings are merely examples and do not limit the interpretation of the present invention.

[0011] When describing embodiments of the present invention, the direction from the substrate toward the LED chip is referred to as "up," and the opposite direction is referred to as "down." However, the expressions "up" or "down" merely describe the upper limit relationship of each element. For example, the expression that an LED chip is placed on a substrate includes cases where other components are interposed between the substrate and the LED chip. Furthermore, the expressions "up" or "down" include not only cases where each element overlaps in a plan view, but also cases where they do not overlap.

[0012] When describing embodiments of the present invention, elements having similar functions to those already described may be given the same reference numeral or the same reference numeral with an alphabet or other symbol attached, and their description may be omitted. Furthermore, if it is necessary to describe a certain element separately for each of the RGB colors, the symbol R, G, or B will be added after the reference numeral indicating that element to distinguish it. However, if it is not necessary to describe that element separately for each of the RGB colors, only the reference numeral indicating that element will be used for description.

[0013] When describing embodiments of the present invention, the term "LED chip mounting substrate" refers to a display device on which no LED chips are mounted, and the term "display device" refers to a display device on which LED chips are mounted on an LED chip mounting substrate and which is capable of emitting light from LEDs.

[0014] <First Embodiment> In this embodiment, a display device 10, which is one embodiment of the present invention, will be described.

[0015] (Configuration of the display device) Figure 1 is a plan view showing the schematic configuration of a display device according to one embodiment of the present invention. The display device 10 includes a substrate 100, a flexible printed circuit board 160 (FPC 160), and an LED chip mounting substrate 12 (see Figure 4) having an integrated circuit 170 (IC chip 170), and an LED chip 202. The display device 10 includes a display area 112, a peripheral area 114, and a terminal area 116.

[0016] The display area 112 is the area where pixels are formed. The display area 112 is an area in which a plurality of pixels 110, including LED chips 202, are arranged in the row direction (D1 direction) and the column direction (D2 direction). Specifically, in this embodiment, pixels 110R including a red LED chip 202R, pixels 110G including a green LED chip 202G, and pixels 110B including a blue LED chip 202B are arranged. Figure 1 shows an example in which pixels 110R, pixels 110G, and pixels 110B are used as sub-pixels and these constitute a single pixel 110. The display area 112 functions as an area for displaying an image corresponding to a video signal. A first insulating layer 118 is provided in the display area 112 so as to extend throughout the entire area.

[0017] The peripheral region 114 is the area surrounding the display region 112. The peripheral region 114 is an area where driver circuits (data driver circuit 130 and gate driver circuit 140 shown in Figure 2) for controlling the pixel circuits (pixel circuits 120 shown in Figure 2) provided for each pixel 110 are located.

[0018] The terminal area 116 is an area where multiple wires connected to the aforementioned driver circuit are concentrated. The flexible printed circuit board 160 is electrically connected to the multiple wires in the terminal area 116. Video signals (data signals) or control signals output from an external device (not shown) are input to the IC chip 170 via wiring (not shown) provided on the flexible printed circuit board 160. The IC chip 170 performs various signal processing on the video signals and generates control signals necessary for display control. The video signals and control signals output from the IC chip 170 are input to the display device 10 via the flexible printed circuit board 160.

[0019] (Circuit Configuration of Display Device) Figure 2 is a block diagram showing the circuit configuration of a display device 10 according to one embodiment of the present invention. As shown in Figure 2, it is possible to provide a pixel circuit 120 in the display area 112 corresponding to each pixel 110. In this embodiment, pixel circuits 120R, 120G, and 120B are provided corresponding to pixels 110R, 110G, and 110B, respectively. That is, a plurality of pixel circuits 120 are arranged in the row direction (D1 direction) and column direction (D2 direction) in the display area 112.

[0020] Figure 3 is a circuit diagram showing the configuration of a pixel circuit 120 of a display device 10 according to one embodiment of the present invention. The pixel circuit 120 can be arranged in a region surrounded by data lines 121, gate lines 122, anode power lines 123, and cathode power lines 124. The pixel circuit 120 of this embodiment may include a selection transistor 126, a drive transistor 127, a holding capacitor 128, and an LED 129. The LED 129 corresponds to the LED chip 202 shown in Figure 1. Of the pixel circuit 120, the circuit elements other than the LED 129 correspond to the drive circuit provided on the substrate 100. In other words, in Figure 3, the pixel circuit 120 is completed with the LED chip 202 mounted on the substrate 100.

[0021] As shown in Figure 3, the source electrode, gate electrode, and drain electrode of the selection transistor 126 are connected to the data line 121, gate line 122, and gate electrode of the drive transistor 127, respectively. The source electrode, gate electrode, and drain electrode of the drive transistor 127 are connected to the anode power line 123, the drain electrode of the selection transistor 126, and the LED 129, respectively. A retaining capacitor 128 is connected between the gate electrode and source electrode of the drive transistor 127. That is, the retaining capacitor 128 is connected to the drain electrode of the selection transistor 126. The anode and cathode of the LED 129 are connected to the drain electrode of the drive transistor 127 and the cathode power line 124, respectively.

[0022] Data line 121 is supplied with a gradation signal that determines the light intensity of LED 129. Gate line 122 is supplied with a gate signal to select the selection transistor 126 that writes the gradation signal. When the selection transistor 126 is turned ON, the gradation signal is stored in the holding capacitor 128. Then, when the drive transistor 127 is turned ON, a drive current corresponding to the gradation signal flows through the drive transistor 127. When the drive current output from the drive transistor 127 is input to LED 129, LED 129 lights up with a light intensity corresponding to the gradation signal.

[0023] Referring again to Figure 2, a data driver circuit 130 is positioned adjacent to the display area 112 in the column direction (D2 direction). A gate driver circuit 140 is positioned adjacent to the display area 112 in the row direction (D1 direction). In this embodiment, two gate driver circuits 140 are provided on both sides of the display area 112, but only one of them may be provided.

[0024] The data driver circuit 130 and the gate driver circuit 140 are both located in the peripheral region 114. However, the region in which the data driver circuit 130 is located is not limited to the peripheral region 114. For example, the data driver circuit 130 may be located on the flexible printed circuit board 160.

[0025] The data line 121 shown in Figure 3 extends from the data driver circuit 130 in the D2 direction and is connected to the source electrode of the selection transistor 126 in each pixel circuit 120. The gate line 122 extends from the gate driver circuit 140 in the D1 direction and is connected to the gate electrode of the selection transistor 126 in each pixel circuit 120.

[0026] A terminal section 150 is located in the terminal region 116. The terminal section 150 is connected to the data driver circuit 130 via connection wiring 151. Similarly, the terminal section 150 is connected to the gate driver circuit 140 via connection wiring 152. Furthermore, the terminal section 150 is connected to the flexible printed circuit board 160.

[0027] (Pixel Structure) Figure 4 is a plan view showing the pixel configuration of a display device according to one embodiment of the present invention. Specifically, it is an enlarged plan view of the pixel 110R shown in Figure 1. The pixel 110 includes an LED chip 202, a bump 204, an aperture 180, a connecting electrode 182, and a mounting pad 184. Note that in Figure 4, the upper configuration including the LED chip 202R is omitted, and the second insulating layer 119 is shown at the frontmost surface of the display device 10.

[0028] The second insulating layer 119, like the first insulating layer 118, is provided to extend over the display area 112. The second insulating layer 119 has an opening 180 in the pixel 110. The second insulating layer 119 may have multiple openings 180. As shown in Figure 4, the second insulating layer 119 has openings 180-1 and 180-2 in the pixel 110R.

[0029] The opening 180 is an opening for the electrical or direct connection between the mounting pad 184 and the connecting electrode 182. As described above, the opening 180 may include a plurality of openings 180. As shown in Figure 4, the pixel 110R is provided with openings 180-1 and 180-2. The openings 180 may be provided so as to overlap with the mounting pad 184. As shown in Figure 4, opening 180-1 overlaps with mounting pad 184-1, and opening 180-2 overlaps with mounting pad 184-2. The openings 180 may be surrounded by the outer peripheral edge 184E of the mounting pad 184. As shown in Figure 4, opening 180-1 is surrounded by the outer peripheral edge 184-1E of mounting pad 184-1. Opening 180-2 is surrounded by the outer peripheral edge 184-2E of mounting pad 184-2.

[0030] The opening 180 can be provided overlapping the connecting electrode 182. The opening end 180E of the opening 180 can surround the outer peripheral end 182E of the connecting electrode 182. As shown in Figure 4, the opening end 180-1E of the opening 180-1 surrounds the outer peripheral end 182-1E of the connecting electrode 182-1. The opening 180-1 exposes the connecting electrode 182-1. The opening end 180-2E of the opening 180-2 can be surrounded by the outer peripheral end 182-2E of the connecting electrode 182-2. However, as will be described in detail later, if a bump is provided between the connecting electrode 182-2 and the LED chip 202, the opening 180-2 should be formed to surround the outer peripheral end of the connecting electrode 182-2.

[0031] The mounting pads 184 are electrodes that electrically connect to the LED chip 202 and the anode power line 123 and cathode power line 124. The mounting pads 184 are arranged corresponding to the display area 112 and have a configuration that includes multiple mounting pads 184 connected to each power line. As shown in Figure 4, the mounting pads 184 include mounting pad 184-1 and mounting pad 184-2. Mounting pad 184-1 can be connected to the first wiring 186. As shown in Figure 4, the outer peripheral end 184-1E of mounting pad 184-1 surrounds the connecting electrode 182-1 and the bump 204. Mounting pad 184-2 can be electrically connected to the second wiring 188 through the opening 180-3 of the first insulating layer 118. Mounting pad 184-2 may be arranged to overlap the openings 180-2 and 180-3. The mounting pad 184-2 may be positioned to surround the outer peripheral end 182-2E of the connecting electrode 182-2.

[0032] The connecting electrode 182 is an electrode that electrically connects the LED chip 202 and the mounting pad 184. The connecting electrode 182 may be provided in proportion to the number of electrodes on the LED chip 202. As will be described in detail later, if the LED chip 202 is provided with multiple electrodes, the connecting electrode 182 may include multiple connecting electrodes 182. As shown in Figure 4, the connecting electrode 182 includes connecting electrode 182-1 and connecting electrode 182-2.

[0033] The connecting electrode 182 can be provided so as to overlap with the opening 180. As shown in Figure 4, the connecting electrode 182-1 is provided so as to overlap with the opening 180-1. The connecting electrode 182-2 is provided so as to overlap with the opening 180-2.

[0034] The connecting electrode 182-1 is positioned in the area inside the opening 180-1. The outer peripheral end 182-1E of the connecting electrode 182-1 can be positioned to surround the opening end 180-1E of the opening 180-1. The outer peripheral end 182-1E of the connecting electrode 182-1 can be positioned at a distance from the opening end 180-1E of the opening 180-1.

[0035] The outer peripheral end 182-2E of the connecting electrode 182-2 is positioned to surround the opening 180-2. The outer peripheral end 182-2E of the connecting electrode 182-2 may also be surrounded by the opening 180-2, as described above. When the outer peripheral end 182-2E of the connecting electrode 182-2 is positioned to surround the opening 180-2, the outer peripheral end 182-2E of the connecting electrode 182-2 can be separated from the opening end 180-2E of the opening 180-2.

[0036] The bumps 204 are electrodes for mounting the LED chip 202 onto the substrate 100. The bumps 204 can electrically connect the LED chip 202 to the connecting electrode 182 and the mounting pad 184. Multiple bumps 204 can be provided depending on the configuration of the LED chip 202. For example, in the case of a vertical LED chip where the n electrode and p electrode are arranged so as to sandwich the semiconductor layer, the bumps 204 are provided on one of the electrodes provided on the substrate 100 side, and in the case of a horizontal LED chip where both the n electrode and p electrode are located on the semiconductor layer side, the bumps 204 are provided on both the n electrode and the p electrode. Figure 4 shows the case of a vertical LED chip.

[0037] As shown in Figure 4, the bump 204 is provided so as to overlap with the opening 180-1. The bump 204 is provided in the inner region of the opening 180-1. The bump 204 is surrounded by the outer peripheral end 182-1E of the connecting electrode 182-1. The shape of the bump 204 in plan view is arbitrary and can be appropriately designed to suit the electrode shape and electrode arrangement of the LED chip 202.

[0038] Next, with reference to Figure 5, the cross-sectional structure of the pixel 110 will be described. Figure 5 is an end view showing the pixel configuration of a display device according to one embodiment of the present invention. Specifically, Figure 5 is an end view along the line A1-A2 in Figure 4. In Figure 5, the same components as those in the display device 10 shown in Figure 4 are given the same reference numerals, and redundant explanations are omitted.

[0039] Each pixel 110 has a drive transistor 127 (not shown) on a substrate 100 on which a base film 102 is provided.

[0040] The underlayer film 102 can be placed on the substrate 100. The underlayer film 102 can prevent contamination from the substrate 100 and can be formed using, for example, an inorganic insulating film. Examples of inorganic insulating films that can be used include silicon nitride films, silicon oxide films, and laminates thereof.

[0041] The drive transistor 127 only needs to be formed between the underlayer 102 and the first insulating layer 118, and a known transistor configuration can be used. For example, the drive transistor 127 includes a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer is electrically connected to a source electrode and a drain electrode. Here, the gate electrode is connected to the drain electrode of the selection transistor 126 shown in Figure 3. The source electrode is electrically connected to the anode power line 123 and the retaining capacitor 128 shown in Figure 3. The drain electrode is electrically connected to the LED chip 202 via a mounting pad 184.

[0042] The mounting pad 184 is disposed on the first insulating layer 118 provided on the base film 102. The LED chip 202 is mounted on the mounting pad 184-1. The mounting pad 184-2 can be connected to the second wiring 188 through the opening 180-3 provided in the first insulating layer 118.

[0043] The mounting pad 184 can be formed using a general metal material. As the metal material, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof can be used. The mounting pad 184 preferably includes a metal layer formed of a metal material selected from titanium (Ti), molybdenum (Mo), and molybdenum tungsten (MoW). The metal layer 184 formed of the above metal material can be exposed on its upper surface.

[0044] The mounting pad 184 may have a single-layer structure or a laminated structure. As shown in FIG. 5, the mounting pad 184 can be formed by laminating a conductive layer 184a-1, a conductive layer 184a-2, and a conductive layer -3. The upper surface of the mounting pad 184 can be the upper surface of the conductive layer 184a-1. The conductive layer 184a-1 can be exposed on its upper surface.

[0045] For the conductive layer 184a-1 and the conductive layer 184a-3, a metal material that is difficult to oxidize is used, and it is preferably a metal layer formed of a metal material selected from titanium (Ti), molybdenum (Mo), and molybdenum tungsten (MoW). The conductive layer 184a-1 and the conductive layer 184a-3 preferably sandwich the conductive layer 184a-2. The film thickness of the conductive layer 184a-2 can be made larger than the film thicknesses of the conductive layer 184a-1 and the conductive layer 184a-3. Further, the film thickness of the conductive layer 1​​The second wiring 188 can be formed between the base film 102 and the first insulating layer 118 so as to be connected to the mounting pad 184-2. The second wiring is disposed on the base film 102. The second wiring 188 can use the same configuration as the mounting pad 184. As shown in FIG. 5, the second wiring 188 can be formed by laminating a conductive layer 188a-1, a conductive layer 188a-2, and a conductive layer -3.

[0047] On the base film 102, a planarization layer 104 is provided so as to cover the second wiring 188. The planarization layer 104 is a transparent resin layer using a resin material such as polyimide, acrylic, or HRC. An opening is provided in the planarization layer 104. The first insulating layer 118 is formed on the planarization layer 104.

[0048] An opening 180-3 is provided in the first insulating layer 118. The opening 180-3 is disposed in the opening of the planarization layer 104. By providing openings in the planarization layer 104 and the first insulating layer 118, the second wiring 188 can be connected to the mounting pad 184-2. For the first insulating layer 118, for example, an inorganic insulating material can be used. The inorganic insulating material can use, for example, silicon nitride, silicon oxide, and a composite thereof.

[0049] On top of the first insulating layer, in addition to the mounting pad 184, a second insulating layer 119 is provided. The second insulating layer 119 covers the first insulating layer 118 and has an opening 180-1 that exposes the upper surface 184-1T of the mounting pad 184-1. The second insulating layer 119 can cover the upper surface and side surfaces of the mounting pad 184-2. The second insulating layer 119 can be formed using silicon nitride or the like. The second insulating layer 119 is preferably a silicon nitride layer.

[0050] Referring to FIG. 6, the opening 180-1 of the second insulating layer 119 will be described in detail. FIG. 6 is an enlarged view of the portion 400 shown in FIG. 5.

[0051] The mounting pad 184-1 may have an upper surface 1841T and a side surface 1841S. On the upper surface 1841T of the mounting pad 184-1, the upper surface 1841T-1 may overlap with the connecting electrode 182-1 and be exposed from the second insulating layer 119. The upper surface 1841T-2 may be exposed from the connecting electrode 182-1 and the second insulating layer 119. On the side surface 1841S of the mounting pad 184-1, the side surface 1841S-1 may be covered by the second insulating layer, and the side surface 1841S-2 may be exposed from the second insulating layer 119. The upper surface 1841T-2 may be continuous with the side surface 1841S-1. When the mounting pad 184-1 has a laminated structure of at least a conductive layer 184a-1 and a conductive layer 184a-2, the upper surface 1841T of the conductive layer 184a-1 is exposed from the second insulating layer 119 by the opening 180-1, and the side surface 1841S of the conductive layer 184a-2 is covered by the second insulating layer 119. A connecting electrode 182 is placed on the mounting pad 184. The upper surface 1841T of the mounting pad 184 is in contact with the connecting electrode 182. As shown in Figure 6, the upper surface 1841T-1 of the mounting pad 184-1 is in contact with the connecting electrode 182-1.

[0052] Refer to Figure 5 again. The connecting electrode 182-1 can be separated from the second insulating layer 119. The connecting electrode 182-2 can be in contact with the second insulating layer 119. The connecting electrode 182 can be formed of a conductive metal oxide. Preferably, the connecting electrode 182 is one selected from indium tin oxide (ITO), indium zinc oxide (IZO), and tin oxide.

[0053] The bump 204 is placed on the connecting electrode 182. As shown in Figure 5, the bump 204 is placed on the connecting electrode 182-1 which is separated from the second insulating layer 119. The bump 204 is separated from the second insulating layer 119. The bump 204 is separated from the mounting pad 184-1. The bump 204 can be formed using a conductive resin. For example, the bump 204 can be formed using a base resin such as EVA (Ethyl-Vinyl Acetate), polyolefin, rigid rubber, or adhesive polymer (polyester, nylon, etc.) in which conductive fine powder of carbon such as graphite is dispersed. The conductive resin has high adhesion not only to the material used for the connecting electrode 182 but also to the material used for the second insulating layer 119. In particular, the conductive resin has high adhesion to ITO and silicon nitride film. The conductive resin has low adhesion to the material used for the mounting pad 184. Specifically, conductive resins have poor adhesion to at least one of Ti and Al.

[0054] When the connecting electrode 182 and the second insulating layer 119, which is a passivation film, have high adhesion to the bump 204, the opening 180 of the passivation film is made larger than the pattern of the connecting electrode 182, as described above. This creates a region with low adhesion between the connecting electrode 182 and the passivation film. With this configuration that provides a region with low adhesion, even if the bump 204 is formed over the pattern of the connecting electrode 182, the portion of the bump 204 that has overridden the pattern will be more easily peeled off. In other words, by providing a region with low adhesion in the area where the shape of the bump 204 deviates from the design, the bump 204 is less likely to remain in the area that deviates from the design, and as a result, the bump 204 can be formed in the shape as designed.

[0055] The LED chip 202 can be placed on the bump 204. The LED chip 202 is electrically connected to the connecting electrode 182 via the bump 204. The LED chip 202 can also be electrically connected to the mounting pad 184 via the bump 204 and the connecting electrode 182.

[0056] The LED chip 202 corresponds to LED 129 in the circuit diagram shown in Figure 3. The LED chip 202 includes an anode 203a, a cathode 203b, and a layer 202a sandwiched between the anode 203a and the cathode 203b. The anode 203a of the LED chip 202 is electrically connected to the drain electrode of the drive transistor 127. The cathode 203b of the LED chip 202 is connected to the second wiring 188. The second wiring 188 is electrically connected to the cathode power line 124 shown in Figure 3. Note that the arrangement of the anode 203a and cathode 203b shown in Figure 5 is just an example, and the arrangement of the anode 203a and cathode 203b may be reversed.

[0057] The layer 202a of the LED chip 202 may include, for example, a p-type semiconductor layer, an active layer (light-emitting layer), and an n-type semiconductor layer, and these layers may be stacked to form a structure, with an anode 203a and a cathode 203b electrically connected to the p-type semiconductor layer and the n-type semiconductor layer, respectively.

[0058] The p-type semiconductor layer, the active layer, and the n-type semiconductor layer are formed from a compound semiconductor containing, for example, group 13 and group 15 elements. More specifically, the compound semiconductor contains at least one element selected from aluminum, gallium, and indium as the group 13 element, and at least one element selected from nitrogen, phosphorus, and arsenic as the group 15 element. For example, the p-type and n-type semiconductor layers may be formed from gallium nitride (GaN). Magnesium and beryllium can be used as dopants for the p-type semiconductor layer (p-type gallium nitride layer), and silicon, germanium, and oxygen can be used as dopants for the n-type semiconductor layer (n-type gallium nitride layer). The active layer may have a single-layer structure or a quantum well structure. A quantum well structure is a structure in which multiple thin films with different band gaps and thicknesses of approximately 1 to 5 nm are alternately stacked. Examples include alternating stacks of InGaN and GaN, alternating stacks of GaInAsP and InP, and alternating stacks of AlInAs and InGaAs.

[0059] The anode 203a is also called the p electrode, and the cathode 203b is also called the n electrode. The anode 203a and cathode 203b are formed using a metallic material and preferably have a metallic surface such as gold (Au) or silver (Ag).

[0060] The third insulating layer 106 is formed on the second insulating layer 119. The third insulating layer 106 is formed on the mounting pad 184 and the connecting electrode 182. The third insulating layer 106 can be provided in contact with the mounting pad 184, for example, as shown in Figure 5, the third insulating layer 106 can be provided in contact with the mounting pad 184-2. The LED chip 202 can be embedded in the third insulating layer 106. An opening 180-4 can be provided in the third insulating layer 106. The third insulating layer 106 can be formed using an insulating resin. For example, the third insulating layer 106 can be formed using polyimide, acrylic, etc.

[0061] The common electrode 190 is formed on the third insulating layer 106. The common electrode 190 is electrically connected to the LED chip 202. The common electrode 190 is connected to the cathode 203b. The common electrode 190 can be electrically connected to the mounting pad 184-2 via an opening 180-4 in the third insulating layer 106. As shown in Figure 5, the common electrode 190 can be electrically connected to the mounting pad 184-2 via a connecting electrode 182-2 between the common electrode 190 and the mounting pad 184-2. The connection between the common electrode 190 and the mounting pad 184-2 allows the LED chip 202 to be connected to the cathode power line 124.

[0062] The display device 10 of this embodiment includes a first insulating layer 118 that extends over a region 112 where pixels 110 are formed, a mounting pad 184 arranged in correspondence with the region 112 where pixels 110 are formed and provided on the first insulating layer 118, a second insulating layer 119 that covers the first insulating layer 118 and has an opening 180 that exposes the upper surface 1841T of the mounting pad 184, a connecting electrode 182 arranged in the region inside the opening 180 and in contact with the upper surface 1841T of the mounting pad 184, and an LED chip 202 electrically connected to the connecting electrode 182. As a result, the shape of the bumps 204 can be formed as designed. When the shape of the bumps 204 in the display region 112 is as designed, the electrical characteristics of the LEDs connected to each bump 204 become constant within the display region 112. Therefore, the brightness of the LEDs can be made constant within the display region 112, and the uniformity of brightness can be improved.

[0063] <Second Embodiment> In this embodiment, a display device 10 equipped with a horizontal LED chip will be described. Configurations that are the same as or similar to those described in the first embodiment may be omitted from the description.

[0064] Figure 7 is a plan view showing the pixel configuration of a display device according to one embodiment of the present invention. Specifically, Figure 7 is an enlarged plan view of pixel 110R shown in Figure 1. Figure 8 is an end view showing the pixel configuration of a display device according to one embodiment of the present invention. Specifically, Figure 8 is an end view along the line B1-B2 in Figure 7.

[0065] As shown in Figure 7, the open end 180-2E of the opening 180-2 can surround the outer peripheral end 182-2E of the connecting electrode 182-2. The opening 180-2 exposes the connecting electrode 182-2. The opening 2 exposes the mounting pad 184-2. The open end 180-2E of the opening 180-2 is positioned to surround the outer peripheral end 204-2E of the bump 204-2.

[0066] The connecting electrode 182-2 is positioned in the area inside the opening 180-2. The outer peripheral end 182-2E of the connecting electrode 182-2 can be separated from the opening end 180-2E of the opening 180-2. The outer peripheral end 182-2E of the connecting electrode 182-2 is formed to surround the outer peripheral end 204-2E of the bump 204-2. The connecting electrode 182-2 is provided to be separated from the second insulating layer 119.

[0067] The bump 204 may include multiple bumps 204. As shown in Figure 7, the bump 204 includes bump 204-1 and bump 204-2. Bump 204-1 is located in the inner region of the opening 180-1. Bump 204-2 is located in the inner region of the opening 180-2. Bump 204-1 is surrounded by the outer peripheral end 182-1E of the connecting electrode 182-1. Bump 204-2 is surrounded by the outer peripheral end 182-2E of the connecting electrode 182-2.

[0068] As shown in Figure 8, the opening 180-2 can expose the upper surface of the mounting pad 184-2. The mounting pad 184-2 can be electrically connected to the connecting electrode 182-2. The mounting pad 184-2 can make contact with the connecting electrode 182-2.

[0069] The bump 204-2 is positioned on the connecting electrode 182-2. The bump 204-2 can be electrically connected to the connecting electrode 182-2. The bump 204-2 can be in contact with the connecting electrode 182-2. The bump 204-2 can be separated from the second insulating layer 119. The bump 204-2 can be separated from the mounting pad 184-2. The LED chip 202 is positioned on the bump 204-2.

[0070] The cathode 203b of the LED chip 202 is positioned on the bump 204-2. The cathode 203b can be electrically connected to the bump 204-2. The cathode 203b can be in contact with the bump 204-2.

[0071] The display device 10 includes a first insulating layer 118 that extends over a region 112 where pixels 110 are formed, mounting pads 184-1 and 184-2 arranged in correspondence with the region 112 where pixels are formed and provided on the first insulating layer 118, a second insulating layer 119 that covers the first insulating layer 118 and has openings 180-1 and 180-2 that expose the upper surfaces 1842T of mounting pads 184-1 and 184-2 respectively, connecting electrodes 182-1 and 182-2 arranged in the regions inside the openings 180-1 and 180-2 respectively and in contact with the upper surfaces 1842T of mounting pads 184-1 and 184-2 respectively, and an LED chip 202 that is electrically connected to the connecting electrodes 182-1 and 182-2, thereby forming the shapes of bumps 204-1 and 204-2 as designed. If the shape of the bumps 204 within the display area 112 is as designed, the electrical characteristics of the LEDs connected to each bump 204 will be constant within the display area 112. As a result, the brightness of the LEDs will be constant within the display area 112.

[0072] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, devices based on the display devices of each embodiment, in which a person skilled in the art has added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0073] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention.

[0074] 10: Display device, 12: Mounting substrate, 100: Substrate, 102: Undercoat, 104: Planarization layer, 106: Third insulating layer, 110: Pixel, 110B: Pixel, 110G: Pixel, 110R: Pixel, 112: Display area, 114: Peripheral area, 116: Terminal area, 118: First insulating layer, 119: Second insulating layer, 120: Pixel circuit, 120B: Pixel circuit, 120G: Pixel circuit, 120R: Pixel circuit, 121: Data line, 122: Gate line, 123: Anode power line, 124: Cathode Power line, 126: Select transistor, 127: Drive transistor, 128: Holding capacitor, 130: Data driver circuit, 140: Gate driver circuit, 150: Terminal section, 151: Connection wiring, 152: Connection wiring, 160: Flexible printed circuit board, 170: Chip, 170: Integrated circuit, 180: Opening, 180-1: Opening, 180-1E: Opening end, 180-2: Opening, 180-2E: Opening end, 180-3: Opening, 180-4: Opening, 180E : Open end, 182: Connecting electrode, 182-1: Connecting electrode, 182-1E: Outer circumference end, 182-2: Connecting electrode, 182-2E: Outer circumference end, 182E: Outer circumference end, 184: Mounting pad, 184-1: Mounting pad, 184-1E: Outer circumference end, 184-1T: Top surface, 184-2: Mounting pad, 184-2E: Outer circumference end, 184a-1: Conductive layer, 184a-2: Conductive layer, 184a-3: Conductive layer, 184E: Outer circumference end, 186: First wiring, 188: Second wiring, 188a- 1: conductive layer, 188a-2: conductive layer, 190: common electrode, 202: tip, 202a: layer, 202B: tip, 202G: tip, 202R: tip, 203a: anode, 203b: cathode, 204: bump, 204-1: bump, 204-2: bump, 204-2E: outer edge, 400: portion, 1841S: side, 1841S-1: side, 1841S-2: side, 1841T: top, 1841T-1: top, 1841T-2: top, 1842T: top

Claims

1. An LED chip mounting substrate comprising: a mounting pad disposed on a first insulating layer and electrically connected to an LED chip; a second insulating layer covering the first insulating layer and having an opening that exposes the upper surface of the mounting pad; and a connecting electrode disposed in a region inside the opening and in contact with the upper surface of the mounting pad.

2. The mounting substrate for the LED chip according to claim 1, wherein the outer peripheral end of the connecting electrode is spaced apart from the opening end of the opening.

3. The mounting substrate for the LED chip according to claim 1, wherein the connecting electrode is formed of a conductive metal oxide.

4. The mounting pad for an LED chip according to claim 3, wherein the mounting pad includes a metal layer formed of one metallic material selected from Ti, Mo, and MoW, and the metal layer is exposed on the upper surface.

5. The LED chip mounting substrate according to claim 3, wherein the metal oxide is one selected from indium tin oxide, indium zinc oxide, and tin oxide.

6. The mounting substrate for an LED chip according to claim 3, wherein the second insulating layer is a silicon nitride layer.

7. A display device comprising: a first insulating layer extending over a region where pixels are formed; a mounting pad arranged corresponding to the region where pixels are formed and provided on the first insulating layer; a second insulating layer covering the first insulating layer and having an opening that exposes the upper surface of the mounting pad; a connecting electrode arranged in a region inside the opening and in contact with the upper surface of the mounting pad; and an LED chip electrically connected to the connecting electrode.

8. The display device according to claim 7, wherein the LED chip and the connecting electrode are electrically connected by a bump made of conductive resin.

9. The display device according to claim 7, wherein the outer peripheral end of the connecting electrode is spaced apart from the opening end of the opening.

10. The display device according to claim 7, wherein the connecting electrode is formed of a conductive metal oxide.

11. The display device according to claim 10, wherein the mounting pad includes a metal layer formed of one metallic material selected from Ti, Mo, and MoW, and the metal layer is exposed on the upper surface.

12. The display device according to claim 10, wherein the metal oxide is one selected from indium tin oxide, indium zinc oxide, and tin oxide.

13. The display device according to claim 10, wherein the second insulating layer is a silicon nitride layer.

14. The display device according to claim 7, comprising a third insulating layer in which the LED chip is embedded, and a common electrode on the third insulating layer, wherein the common electrode is electrically connected to the LED chip.

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