System and method for fail-safe generation of a rectangular wave signal

Abstract

Herein is disclosed a fail-safe circuit for generating a rectangular wave having a desired duty cycle, the circuit comprising: first and second duty cycle registers configured to output first and second parallel duty cycle signals each representing the desired duty cycle; a binary counter configured to generate a parallel counter signal; first and second comparators configured to generate first and second duty cycle rectangular waves; first and second supervisors configured to generate first and second supervisor signals; and a combining circuit configured to generate an output rectangular wave from the first and second duty cycle rectangular waves, and the first and second supervisor signals.

Description

SYSTEM AND METHOD FOR FAIL-SAFE GENERATION OF A RECTANGULAR WAVE SIGNALTechnical Field

[0001] The present disclosure is directed to systems and methods of generating a rectangular wave signal. More particularly, the present disclosure is directed to systems and methods of fail-safe generation of a rectangular wave signal having a duty cycle.Background

[0002] Many electric and electro-mechanic devices, for example, radio transmitters, heaters, lamps, motors, and the like, may use an electronic control signal. The control signal may be used to activate the device and maintain the device in an active state, and to deactivate the device and maintain the device in the deactivated state. Such signals typically have two states. A transition from the first state to the second state activates the device, and the device remains active so long as the signal is in the second state. A transition from the second state to the first state deactivates the device, and the device remains inactive so long as the signal is in the first state.

[0003] The two states of such a control signal are commonly referred to as “high” and “low”, “active” and “inactive”, “1” and “0”, and the like. The electrical properties of the two states of such a signal are commonly two different voltage levels, for example: 0 volts (V) for “low” and 5 V for “high”, or 0 V for “low” and 12 V for “high”, and the like.

[0004] Certain applications of control signals use a periodic control signal, wherein each period of the control signal comprises a first “high” portion, and a second “low” portion. Such periodic control signals can be used to achieve variable control of a binary device. For example, various types of electric lamps only operate at a single intensity of luminosity. As such, to facilitate variation in the intensity of the luminosity of such a lamp, the lamp may be controlled with a periodic control signal, and the luminosity of the lamp may be varied by controlling the portions of each period of the control signal that are “high” and “low”.

[0005] The waveform of such periodic control signals may be referred to as a rectangular wave, because the “high” and “low” states of the signal form respective plateaus and valleysin the signal’s waveform, and the combination of plateaus, valleys, and rising and falling edges therebetween, resemble rectangles. A rectangular wave may be described by a duty cycle, wherein the duty cycle of a rectangular wave is the percentage of each period for which the signal is “high”.

[0006] Periodic control signals may be used in a variety of applications, including certain safety critical applications, for example limiting the operation of devices that may be dangerous if operated above a certain percentage of a duty cycle. In such applications, there is a general desire for a system and method for fail-safe generation of a rectangular wave having a given duty cycle, where the rectangular wave can be used as a control signal.

[0007] The foregoing examples of the related art and limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.Summary

[0008] Further aspects and example embodiments are illustrated in the accompanying drawings and / or described in the following description.

[0009] One aspect of the invention provides a fail-safe circuit for generating a rectangular wave having a desired duty cycle, the circuit comprising: a first duty cycle register configured to receive a serial signal representing the desired duty cycle and output a first parallel duty cycle signal representing the desired duty cycle; a second duty cycle register configured to receive the serial signal and output a second parallel duty cycle signal representing the desired duty cycle; a binary counter configured to generate a parallel counter signal; a first comparator configured to generate a first duty cycle rectangular wave from the first parallel duty cycle signal and the parallel counter signal; a second comparator configured to generate a second duty cycle rectangular wave from the second parallel duty cycle signal and the parallel counter signal; a first supervisor configured to generate a first supervisor signal from the parallel counter signal; a second supervisor configured to generate a second supervisor signal from the parallel counter signal; and a combining circuit configured to generate an output rectangular wave from the first duty cyclerectangular wave, the second duty cycle rectangular wave, the first supervisor signal, and the second supervisor signal.

[0010] In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by reference to the drawings and by study of the following detailed descriptions.Brief Description of the Drawings

[0011] The accompanying drawings illustrate non-limiting example embodiments of the invention.

[0012] Fig. 1A is a schematic diagram of a circuit for fail-safe generation of an output rectangular wave, according to an example embodiment of the present invention.

[0013] Fig. 1 B is a schematic diagram of a circuit for fail-safe generation of an output rectangular wave, according to a further example embodiment of the present invention.

[0014] Fig. 2 is a schematic diagram of a method for fail-safe generation of an output rectangular wave, according to an example embodiment of the present invention.Description

[0015] Throughout the following description, specific details are set forth in order to provide a more thorough understanding of the invention. However, the invention may be practiced without these particulars. In other instances, well known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive sense.

[0016] The present disclosure is directed to systems and methods for fail-safe generation of a rectangular wave signal having a duty cycle. Rectangular waves may be used in a variety of applications as control signals to control the operation of a device, including to limit the operation of a device. Where rectangular waves are used as control signals to limit the operation of a device, one or more faults with the generation of the rectangular wave may result in operation of the device exceeding a desired operational limit. Exceeding the desired operational limit may result in unsafe operation of the device, for exampleoverheating of the device, or operation of the device which is unsafe for people or property in the vicinity of the device, for example overexposure to an output of the device.

[0017] For example, where a rectangular wave is intended to have a desired duty cycle, a fault with the circuit generating the rectangular wave may result in the circuit generating a rectangular wave with a higher duty cycle than the desired duty cycle. In extreme cases, a fault with the circuit may result in a signal being held at a “high” level, therefore with an effective 100% duty cycle.

[0018] The systems and methods disclosed herein generate a rectangular wave with a failsafe duty cycle. A rectangular wave with a fail-safe duty cycle is a rectangular wave with an output duty cycle equal to or less than a desired duty cycle, wherein the output duty cycle is less than the desired duty cycle if there are one or more faults in the generation of the rectangular wave.

[0019] Fig. 1A is a schematic diagram of circuit 100 for fail -safe generation of output rectangular wave 30 with output duty cycle 31 equal to or less than desired duty cycle 21 represented by serial signal 20, according to an example embodiment of the present invention. Circuit 100 comprises:• first duty cycle register 10A and second duty cycle register 10B (collectively, duty cycle registers 10);• binary counter 12;• first comparator 14A and second comparator 14B (collectively, comparators 14); • first supervisor 16A and second supervisor 16B (collectively, supervisors 16); and • combining circuit 18.

[0020] Each of duty cycle registers 10 are configured to receive serial signal 20 representing desired duty cycle 21 and output respective first and second parallel duty cycle signals 22A and 22B (collectively, parallel duty cycle signals 22) each representing desired duty cycle 21. Duty cycle registers 10 provide redundancy in generating parallel duty cycle signals 22 within circuit 100. The redundancy in duty cycle registers 10 provides fail-safe generation of parallel duty cycle signals 22.

[0021] Fail-safe generation of parallel duty cycle signals 22 results in output rectangular wave 30 having output duty cycle 31 equal to or less than desired duty cycle 21. For example:• if there are no faults with registers 10 and parallel duty cycle signals 22 both represent a duty signal equal to desired duty cycle 21 , then output duty cycle 31 will be equal to desired duty cycle 21 ;• if there is a fault with one of registers 10 causing the respective one of parallel duty cycle signals 22 to represent a duty cycle greater than desired duty cycle 21 , then output duty cycle 31 will be equal to desired duty cycle 21 ; and• if there is a fault with one of registers 10 causing the respective one of parallel duty cycle signals 22 to represent a duty cycle less than desired duty cycle 21 , then output duty cycle 31 will be equal to the lesser duty cycle, and therefore be less than desired duty cycle 21.

[0022] Because output duty cycle 31 is equal to the lesser of the duty cycles represented by parallel duty cycle signals 22, the generating of parallel duty cycle signals 22 is fail-safe, in that a fault with one of registers 10 may only result in output duty cycle 31 being less than or equal to desired duty cycle 21.

[0023] Binary counter 12 is configured to generate parallel counter signal 24. Parallel counter signal 24 comprises a parallel digital signal which increments by one each period, and resets to zero when the count overflows. In some embodiments, circuit 100 further comprises crystal oscillator 13, and crystal oscillator 13 controls the period at which binary counter 12 increments parallel counter signal 24. For example, binary counter 12 may increment parallel counter signal 24 with each oscillation of crystal oscillator 13.

[0024] First comparator 14A is configured to generate first duty cycle rectangular wave 26A from first parallel duty cycle signal 22A and parallel counter signal 24. Second comparator 14B is configured to generate second duty cycle rectangular wave 26B from second parallel duty cycle signal 22B and parallel counter signal 24. The redundancy in comparators 14 provides fail-safe generation of first duty cycle rectangular wave 26A and second duty cycle rectangular wave 26B (collectively, duty cycle rectangular waves 26).

[0025] Fail-safe generation of duty cycle rectangular waves 26 results in output rectangular wave 30 having output duty cycle 31 equal to desired duty cycle 21 if there are no faults with comparators 14, and output duty cycle 31 less than desired duty cycle 21 if there is a fault with one or both of comparators 14. For example, if a fault with one of comparators 14 causes one of duty cycle rectangular waves 26 to have a duty cycle other than desired dutycycle 21 , output duty cycle 31 will be equal to the one of duty cycle rectangular waves 26 with the lesser duty cycle. As such, if the fault causes one of duty cycle rectangular waves 26 to have a duty cycle greater than desired duty cycle 21 , then output duty cycle 31 will be equal to desired duty cycle 21. If the fault causes one of duty cycle rectangular waves 26 to have a duty cycle less than desired duty cycle 21 , then output duty cycle 31 will be less than desired duty cycle 21.

[0026] In some embodiments, comparators 14 generate respective duty cycle rectangular waves 14 by generating a high signal when the respective parallel duty cycle signal 22 is greater than parallel counter signal 24 and a low signal when the respective parallel duty cycle signal 22 is less than parallel counter signal 24.

[0027] Supervisors 16 are configured to generate respective first and second supervisor signals 28A and 28B (collectively, supervisor signals 28) indicating one or more errors with binary counter 12. In some embodiments, one of supervisors 16 is configured to generate a supervisor signal indicating a first error with binary counter 12, and a second one of supervisors 16 is configured to generate a supervisor signal indicating a second error with binary counter 12.

[0028] Supervisors 16 may generate respective first and second supervisor signals 28A and 28B from parallel counter signal 24. Each of supervisors 16 monitors binary counter 12, and either of supervisors 16 may reduce the duty cycle of output duty cycle 31 upon detection of an error with binary counter 12. As such, supervisors 16 provide fail-safe generation of output rectangular wave 30 having output duty cycle 31, wherein output duty cycle 31 is equal to or less than desired duty cycle 21.

[0029] In some embodiments, parallel counter signal 24 comprises a plurality of bits, and first supervisor 16A and second supervisor 16B generate respective first supervisor signal 28A and second supervisor signal 28B from the highest bit of the plurality of bits. One of supervisors 16, for example first supervisor 16A, may generate the respective supervisor signal 28 from a transition of the highest bit from high to low, and a second of supervisors 16, for example second supervisor 16B, may generate the respective supervisor signal 28 from a transition of the highest bit from low to high.

[0030] Supervisors 16 may be configured to generate respective supervisor signals 28 based on a transition of the highest bit of parallel counter signal 24 occurring within athreshold length of time. For example, first supervisor 16A may be configured to generate first supervisor signal 28A indicating the first error when the highest bit of binary counter 12 is high for a high threshold length of time. Second supervisor 16B may be configured to generate second supervisor signal 28B indicating the second error when the highest bit of binary counter 12 is low for a low threshold length of time. One or both of the high threshold length of time and the low threshold length of time may be 10 seconds, 45 seconds, 48 seconds, 50 seconds, and the like.

[0031] Combining circuit 18 generates output rectangular wave 30 from one or more of first duty cycle rectangular wave 26A, second duty cycle rectangular wave 26B, first supervisor signal 28A, and second supervisor signal 28B. In some embodiments, combining circuit 18 may be configured to generate output rectangular wave 30 based at least in part on a minimum of first duty cycle rectangular wave 26A and second duty cycle rectangular wave 26B. For example, combining circuit 30 may generate output rectangular wave 30 from a logical AND of first duty cycle rectangular wave 26A and second duty cycle rectangular wave 26B. As such, output rectangular wave 30 is generated in a fail-safe manner from first duty cycle rectangular wave 26A and second duty cycle rectangular wave 26B, in that if a fault causes one of duty cycle rectangular waves 26 to represent an erroneous duty cycle greater than desired duty cycle 21 , then output duty cycle 31 of output rectangular wave 30 will be equal to desired duty cycle 21 if the erroneous duty cycle is greater than desired duty cycle 21, and less than desired duty cycle 21 if the erroneous duty cycle is less than desired duty cycle 21. In either case, output duty cycle 31 is equal to or less than desired duty cycle 21, thereby providing a fail-safe against output duty cycle 31 exceeding desired duty cycle 21.

[0032] Combining circuit 18 may be configured to generate output rectangular wave 30 with output duty cycle 31 less than desired duty cycle 21 where one or both of supervisor signals 28 indicate an error. An output duty cycle 31 less than desired duty cycle 21 may be an output duty cycle equal to half of desired duty cycle 21 , a quarter of desired duty cycle 21 , or the like. In some embodiments, an output duty cycle 31 less than desired duty cycle 21 may be a 0% output duty cycle, meaning output rectangular wave 30 is a constant “low” signal, for example 0 V. Output rectangular wave 30 with output duty cycle 31 equal to 0% may also be referred to as a constant signal.

[0033] In some embodiments, combining circuit 18 comprises one or more transistors. Fig.1B is a schematic diagram of circuit 100, wherein combining circuit 18 comprises transistors 32A, 32B, 32C and 32D (collectively, transistors 32). Transistors 32 of combining circuit 18 may be configured to logically AND one or more of first duty cycle rectangular wave 26A, second duty cycle rectangular wave 26B, first supervisor signal 28A, and second supervisor signal 28B. Generating output rectangular wave 30 based on a logical AND of duty cycle rectangular waves 26 and supervisor signals 28 may provide a fail-safe generation of output rectangular wave 30, as all of duty cycle rectangular waves 26 and supervisor signals 28 must be logically “high” for output rectangular wave 30 to be logically “high”. As such, an error with any one of duty cycle rectangular waves 26 and supervisor signals 28 cannot increase output duty cycle 31 of output rectangular wave 30.

[0034] Where combining circuit 18 comprises transistors, combining circuit 18 may comprise:• first transistor 32A having a gate electrically connected to the output of first comparator 14A; and• second transistor 32B having a gate electrically connected to the output of second comparator 14B; and• wherein first transistor 32A and second transistor 32B are electrically connected in series between reference voltage 34 and output terminal 36, and first transistor 32A and second transistor 32B are configured to electrically isolate output terminal 36 from reference voltage 34 when one or both of duty cycle rectangular waves 26 are logically “low”.

[0035] Some embodiments of combining circuit 18 may further comprise:• third transistor 32C having a gate electrically connected to the output of first supervisor 16A; and• fourth transistor 32D having a gate electrically connected to the output of second supervisor 16B;• wherein third transistor 32C and fourth transistor 32D are electrically connected in series between second transistor 32B and reference voltage 34;• third transistor 32C is configured to electrically isolate output terminal 36 from reference voltage 34 based at least in part on first supervisor signal 28A; and• fourth transistor 32D is configured to electrically isolate output terminal 36 from reference voltage 34 based at least in part on second supervisor signal 28B.

[0036] In some embodiments, reference voltage 34 is an electrical ground at 0 V, or an electrical potential above 0V, for example 5V, 12V, and the like.

[0037] Fig. 2 is a schematic diagram of method 200 for fail-safe generation of output rectangular wave 60 having output duty cycle 61 equal to or less than desired duty cycle 51 represented by input signal 50. Method 200 comprises:• step 202, receiving input signal 50 representing desired duty cycle 51 ;• step 204, generating binary counter signal 52;• step 206, generating first duty cycle rectangular wave 54A from input signal 50 and binary counter signal 52;• step 208, generating second duty cycle rectangular wave 54B from input signal 50 and binary counter signal 52;• step 210, generating combined duty cycle rectangular wave 56, wherein combined duty cycle rectangular wave 56 is equal to a minimum of first duty cycle rectangular wave 54A and second duty cycle rectangular 54B;• step 212, generating first supervisor signal 58A from binary counter signal 52;• step 214, generating second supervisor signal 58B from binary counter signal 52;and• step 216, generating output rectangular wave 60 based on combined duty cycle rectangular wave 56, first supervisor signal 58A, and second supervisor signal 58B.

[0038] In some embodiments of method 200, input signal 50 comprises a serial duty cycle signal, and steps 206 and 208 comprise generating first and second duty cycle rectangular waves 54A and 54B by generating a parallel duty cycle signal from the serial duty cycle signal, and generating the first and second duty cycle rectangular waves 54A and 54B from the parallel duty cycle signal. Generating the parallel duty cycle signal may comprise generating a persistent parallel duty cycle signal, for example by using one or more nonvolatile memory registers.

[0039] Binary counter signal 52 may comprise a plurality of bits, and one or both of steps 212 and 214 may comprise generating one or both of first and second supervisor signals 58A and 58B from one bit of the plurality of bits, for example, a highest bit of the plurality ofbits. Generating one or both of first and second supervisor signals 58A and 58B may further comprise generating one or both of first and second supervisor signals 58A and 58B from a transition of the one bit of the plurality of bits. For example, step 212 may comprise generating first supervisor signal 58A from a transition of the highest bit from high to low, and step 214 may comprise generating second supervisor signal 58B from a transition of the highest bit from low to high.

[0040] One or both of steps 212 and 214 may further comprise generating one or both of first and second supervisor signals 58A and 58B to indicate an error, for example an error with binary counter signal 52. Generating first supervisor signal 58A may comprise generating first supervisor signal 58A indicating a first error when the highest bit of binary counter signal 52 is high for a high threshold length of time. Generating second supervisor signal 58B may comprise generating second supervisor signal 58B indicating a second error when the highest bit of binary counter signal 52 is low for a low threshold length of time.

[0041] Where one or both of first and second supervisor signals 58A and 58B indicate an error, step 216 may comprise generating output rectangular wave 60 with output duty cycle 61 less than desired duty cycle 51 , for example output duty cycle 61 equal to 5%, 0%, and the like.

[0042] While a number of exemplary aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions and sub-combinations thereof. It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions and sub-combinations as are consistent with the broadest interpretation of the specification as a whole.Some Embodiments

[0043] In one or more embodiments, one or both of the first duty cycle register 10A and second duty cycle register 10B comprise a non-volatile memory.

[0044] In some embodiments of the present invention, various voltages and / or signals may be inverted. For example, the signals generated by comparators 14 may be inverted, for example generating a low signal when the respective parallel duty cycle signal 22 is greaterthan parallel counter signal 24 and a high signal when the respective parallel duty cycle signal 22 is less than parallel counter signal 24. It is understood that such alternate embodiments are encompassed by the present invention.

[0045] One or more embodiments of the present invention may be used to generate a control signal having a duty cycle for operating a sanitization device, for example a sanitizing electric lamp. Examples of sanitizing electric lamps include ultraviolet lamps, wherein ultraviolet light emitted by the electric lamp may be used to sanitize one or more surfaces illuminated by the electric lamp. Such ultraviolet lamps may pose risks to individuals, animals, or property, if operated more than a threshold percentage of time. Furthermore, such ultraviolet lamps may degrade if operated more than a threshold percentage of time.

[0046] Ultraviolet sanitizers such as ultraviolet lamps may be controlled by a control signal comprising a rectangular wave having a duty cycle. It may be undesirable, for example unsafe, if the duty cycle of the control signal exceeds a desired duty cycle. Embodiments of the present invention may be used to provide a control signal for such ultraviolet sanitizers, and thereby provide fail-safe generation of a control signal having a desired duty cycle for such ultraviolet sanitizers. Generating a control signal having at most a desired duty cycle, wherein the desired duty cycle is determined based on safe operation of the ultraviolet sanitizer, may provide for fail-safe operation of such a device.Interpretation of Terms

[0047] Unless the context clearly requires otherwise, throughout the description and the claims:• “comprise”, “comprising”, and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to”;• “connected”, “coupled”, or any variant thereof, means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, or a combination thereof;• “herein”, “above”, “below”, and words of similar import, when used to describe this specification, shall refer to this specification as a whole, and not to any particular portions of this specification;• “or”, in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list;• the singular forms “a”, “an”, and “the” also include the meaning of any appropriate plural forms.

[0048] Words that indicate directions such as “vertical”, “transverse”, “horizontal”, “upward”, “downward”, “forward”, “backward”, “inward”, “outward”, “vertical”, “transverse”, “left”, “right”, “front”, “back”, “top”, “bottom”, “below”, “above”, “under”, and the like, used in this description and any accompanying claims (where present), depend on the specific orientation of the apparatus described and illustrated. The subject matter described herein may assume various alternative orientations. Accordingly, these directional terms are not strictly defined and should not be interpreted narrowly.

[0049] Embodiments of the invention may be implemented using specifically designed hardware, configurable hardware, programmable data processors configured by the provision of software (which may optionally comprise “firmware”) capable of executing on the data processors, special purpose computers or data processors that are specifically programmed, configured, or constructed to perform one or more steps in a method as explained in detail herein and / or combinations of two or more of these. Examples of specifically designed hardware are: logic circuits, application-specific integrated circuits (“ASICs”), large scale integrated circuits (“LSIs”), very large scale integrated circuits (“VLSIs”), and the like. Examples of configurable hardware are: one or more programmable logic devices such as programmable array logic (“PALs”), programmable logic arrays (“PLAs”), and field programmable gate arrays (“FPGAs”). Examples of programmable data processors are: microprocessors, digital signal processors (“DSPs”), embedded processors, graphics processors, math co-processors, general purpose computers, server computers, cloud computers, mainframe computers, computer workstations, and the like. For example, one or more data processors in a control circuit for a device may implement methods as described herein by executing software instructions in a program memory accessible to the processors.

[0050] For example, while processes or blocks are presented in a given order, alternative examples may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternative or subcombinations. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times.

[0051] In addition, while elements are at times shown as being performed sequentially, they may instead be performed simultaneously or in different sequences. It is therefore intended that the following claims are interpreted to include all such variations as are within their intended scope.

[0052] The invention may also be provided in the form of a program product. The program product may comprise any non-transitory medium which carries a set of computer-readable instructions which, when executed by a data processor, cause the data processor to execute a method of the invention. Program products according to the invention may be in any of a wide variety of forms. The program product may comprise, for example, non-transitory media such as magnetic data storage media including floppy diskettes, hard disk drives, optical data storage media including CD ROMs, DVDs, electronic data storage media including ROMs, flash RAM, EPROMs, hardwired or preprogrammed chips (e.g., EEPROM semiconductor chips), nanotechnology memory, or the like. The computer-readable signals on the program product may optionally be compressed or encrypted.

[0053] In some embodiments, the invention may be implemented in software. For greater clarity, “software” includes any instructions executed on a processor, and may include (but is not limited to) firmware, resident software, microcode, and the like. Both processing hardware and software may be centralized or distributed (or a combination thereof), in whole or in part, as known to those skilled in the art. For example, software and other modules may be accessible via local memory, via a network, via a browser or other application in a distributed computing context, or via other means suitable for the purposes described above.

[0054] Where a component (e.g. a register, comparator, transistor, assembly, device, circuit, etc.) is referred to above, unless otherwise indicated, reference to that component(including a reference to a “means”) should be interpreted as including as equivalents of that component any component which performs the function of the described component (i.e. , that is functionally equivalent), including components which are not structurally equivalent to the disclosed structure which performs the function in the illustrated exemplary embodiments of the invention.

[0055] Specific examples of systems, methods and apparatus have been described herein for purposes of illustration. These are only examples. The technology provided herein can be applied to systems other than the example systems described above. Many alterations, modifications, additions, omissions, and permutations are possible within the practice of this invention. This invention includes variations on described embodiments that would be apparent to the skilled addressee, including variations obtained by: replacing features, elements and / or acts with equivalent features, elements and / or acts; mixing and matching of features, elements and / or acts from different embodiments; combining features, elements and / or acts from embodiments as described herein with features, elements and / or acts of other technology; and / or omitting combining features, elements and / or acts from described embodiments.

[0056] Various features are described herein as being present in “some embodiments”. Such features are not mandatory and may not be present in all embodiments. Embodiments of the invention may include zero, any one or any combination of two or more of such features. This is limited only to the extent that certain ones of such features are incompatible with other ones of such features in the sense that it would be impossible for a person of ordinary skill in the art to construct a practical embodiment that combines such incompatible features. Consequently, the description that “some embodiments” possess feature A and “some embodiments” possess feature B should be interpreted as an express indication that the inventors also contemplate embodiments which combine features A and B (unless the description states otherwise or features A and B are fundamentally incompatible).

[0057] It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions, omissions, and sub-combinations as may reasonably be inferred. The scope of the claims should not be limited by the preferred embodiments set forth in the examples, but should be given the broadest interpretation consistent with the description as a whole.

Claims

CLAIMS1. A fail-safe circuit for generating a rectangular wave having a desired duty cycle, the circuit comprising:a first duty cycle register configured to receive a serial signal representing the desired duty cycle and output a first parallel duty cycle signal representing the desired duty cycle;a second duty cycle register configured to receive the serial signal and output a second parallel duty cycle signal representing the desired duty cycle;a binary counter configured to generate a parallel counter signal; a first comparator configured to generate a first duty cycle rectangular wave from the first parallel duty cycle signal and the parallel counter signal;a second comparator configured to generate a second duty cycle rectangular wave from the second parallel duty cycle signal and the parallel counter signal; a first supervisor configured to generate a first supervisor signal from the parallel counter signal;a second supervisor configured to generate a second supervisor signal from the parallel counter signal; anda combining circuit configured to generate an output rectangular wave from the first duty cycle rectangular wave, the second duty cycle rectangular wave, the first supervisor signal, and the second supervisor signal.

2. The fail-safe circuit according to claim 1 , wherein the parallel counter signal comprises a plurality of bits, and the first supervisor and the second supervisor generate the respective first supervisor signal and the second supervisor signal from a highest bit of the plurality of bits.

3. The fail-safe circuit according to claim 2, wherein the first supervisor generates the first supervisor signal from a transition of the highest bit from high to low, and the second supervisor generates the second supervisor signal from a transition of the highest bit from low to high.

4. The fail-safe circuit according to any one of claims 1 to 3, wherein the first comparator generates the first duty cycle rectangular wave by generating a high signal when the first parallel duty cycle signal is greater than the parallel counter signal and a low signal when the first parallel duty cycle signal is less than the parallel counter signal, and the second comparator generates the second duty cycle rectangular wave by generating a high signal when the second parallel duty cycle signal is greater than the parallel counter signal and a low signal when the second parallel duty cycle signal is less than the parallel counter signal.

5. The fail-safe circuit according to any one of claims 1 to 3, wherein the first comparator generates the first duty cycle rectangular wave by generating a low signal when the first parallel duty cycle signal is greater than the parallel counter signal and a high signal when the first parallel duty cycle signal is less than the parallel counter signal, and the second comparator generates the second duty cycle rectangular wave by generating a low signal when the second parallel duty cycle signal is greater than the parallel counter signal and a high signal when the second parallel duty cycle signal is less than the parallel counter signal.

6. The fail-safe circuit according to claim 2, wherein the first supervisor is configured to generate a first supervisor signal indicating a first error when the highest bit is high for a high threshold length of time, and the combining circuit is configured to generate an output rectangular wave with a disabling duty cycle when the first supervisor signal indicates the first error.

7. The fail-safe circuit according to claim 6, wherein the second supervisor is configured to generate a second supervisor signal indicating a second error when the highest bit is low for a low threshold length of time, and the combining circuit is configured to generate the output rectangular wave with the disabling duty cycle when the second supervisor signal indicates the second error.

8. The fail-safe circuit according to either of claims 6 and 7, wherein the disabling duty cycle is a 0% duty cycle.

9. The fail-safe circuit according to any one of claims 1 to 8, wherein the combining circuit is configured to generate the output rectangular wave based at least in part on a minimum of the first duty cycle rectangular wave and the second duty cycle rectangular wave.

10. The fail-safe circuit according to any one of claims 1 to 9, wherein the combining circuit comprises:a first transistor having a gate electrically connected to the output of the first comparator; anda second transistor having a gate electrically connected to the output of the second comparator;wherein the first transistor and the second transistor are electrically connected in series between a reference voltage and a duty cycle output, and the first transistor and the second transistor are configured to electrically isolate the duty cycle output from the reference voltage when one or both of the first duty cycle rectangular wave and the second duty cycle rectangular wave are low.

11. The fail-safe circuit according to claim 10, wherein the combining circuit further comprises:a third transistor having a gate electrically connected to the output of the first supervisor; anda fourth transistor having a gate electrically connected to the output of the second supervisor;wherein the third transistor and the fourth transistor are electrically connected in series between the second transistor and the reference voltage;the third transistor is configured to electrically isolate the duty cycle output from the reference voltage based at least in part on the first supervisor signal; and the fourth transistor is configured to electrically isolate the duty cycle output from the reference voltage based at least in part on the second supervisor signal.

12. The fail-safe circuit according to any one of claims 1 to 11 , wherein one or both of the first duty cycle register and the second duty cycle register comprise a nonvolatile memory.

13. A method for fail-safe generation of a rectangular wave having a desired duty cycle, the method comprising:receiving a signal representing the desired duty cycle;generating a first duty cycle rectangular wave from the duty cycle control signal and a binary counter signal;generating a second duty cycle rectangular wave from the duty cycle control signal and the binary counter signal;generating a combined duty cycle rectangular wave, wherein the combined duty cycle rectangular wave is equal to a minimum of the first duty cycle rectangular wave and the second duty cycle rectangular;generating a first supervisor signal from the binary counter signal; generating a second supervisor signal from the binary counter signal; and generating an output duty cycle based on the combined duty cycle rectangular wave, the first supervisor signal, and the second supervisor signal.

14. The method according to claim 13, wherein the signal representing the desired duty cycle comprises a serial duty cycle signal, and generating the first duty cycle rectangular wave comprises:generating a parallel duty cycle signal from the serial duty cycle signal; and generating the first duty cycle rectangular wave from the parallel duty cycle signal.

15. The method according to claim 14, wherein generating the parallel duty cycle signal comprises generating a persistent parallel duty cycle signal.

16. The method according to any one of claims 13 to 15, wherein the binary counter signal comprises a plurality of bits, and generating the first supervisor signal and the second supervisor signal comprises generating the respective first supervisor signal and the second supervisor signal from a highest bit of the plurality of bits.

17. The method according to claim 16, wherein generating the first supervisor signal comprises generating the first supervisor signal from a transition of the highest bitfrom high to low, and generating the second supervisor signal comprises generating the second supervisor signal from a transition of the highest bit from low to high.

18. The method according to claim 17, wherein generating the first supervisor signal comprises generating a first supervisor signal indicating a first error when the highest bit is high for a high threshold length of time, and generating the output duty cycle comprises generating an output duty cycle with a disabling duty cycle when the first supervisor signal indicates the first error.

19. The method according to claim 18, wherein generating the second supervisor signal comprises generating a second supervisor signal indicating a second error when the highest bit is low for a low threshold length of time, and generating the output duty cycle comprises generating the output duty cycle with the disabling duty cycle when the second supervisor signal indicates the second error.

20. The method circuit according to either of claims 18 and 19, wherein the disabling duty cycle is a 0% duty cycle.

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