Efficient Power Electronics Conversion TRIZ Cases

A microcontroller-controlled buck converter shapes startup inrush current to avoid unwanted GFCI trips while maintaining stable power delivery.

Pre-conduction lets an LLC resonant converter widen output voltage range while reducing quality factor, component stress, and efficiency loss.

A load-sensing PFC bypass disables correction at low output power to cut energy loss while maintaining harmonic compliance at higher loads.

Multiple discrete voltage levels and a selector unit enable soft switching, reducing high-frequency switching losses and power dissipation.

Variable power-transfer and energy-recycling intervals enable ZVS/ZCS switching to cut resonant converter losses across changing loads.

A sensing circuit briefly reactivates the active voltage path in standby to hold memory operating voltage with less area and standby current.

Voltage-threshold gate timing replaces fixed deadtime in a UPS IGBT drive circuit to prevent overcurrent without sacrificing conversion efficiency.

Zero-crossing detection of resonant current lets an LLC converter match switching and resonant frequency under light loads, improving efficiency and stability.

Overmolding a DC link capacitor into a power module shortens DC paths, cutting parasitic inductance, voltage overshoot, and switching losses.

A dedicated switch in the AC filter suppresses reactive power without frequent AC breaker operation, extending breaker life and maintaining grid stability.

Dynamic chopping period and duty-cycle adjustment in burst mode cuts output voltage ripple and improves power quality with lower software load.

A delayed secondary drive prevents primary and secondary switch overlap in synchronous flyback converters, improving efficiency and avoiding short circuits.

Real-time slew detection at the half-bridge node adjusts deadtime to maintain ZVS, improving LLC converter efficiency and EMI behavior.

Zero-crossing and reverse-current comparators shut off switches at zero current to keep USB-C buck-boost output stable during mode transitions.

Measures AC input voltage from DC bus and half-cycle sensing, enabling accurate converter input detection without extra sensing hardware.

Integrated current sensing lets power switches detect mode and delay turn-off for ZVS, cutting hard switching and controller load.

A switched-capacitor current feedback scheme minimizes harmonic bridge current, giving resonant converters load-invariant gain with lower losses.

A GaN and silicon driver split lets switched-capacitor converters survive startup voltage stress while lowering parasitic loss and silicon burden.

Phase-shifted parallel switching stages achieve ZVS, cut output ripple, and reduce output capacitor size in high-gain power converters.

A winding across two core legs integrates resonant and magnetizing inductance, cutting winding losses in high-current low-voltage LLC converters.

A two-leg secondary winding layout integrates resonant and magnetizing inductance to cut winding loss and fringing fields in LLC converters.

Voltage-derivative feedback adjusts auxiliary switch timing to achieve zero-voltage switching and cut RMS current, losses, and emissions.

Zero-sequence injection and phase-based switching keep Vienna rectifier input currents balanced while simplifying DC/DC regulation.

Impedance monitoring lets a switched-capacitor converter retune switching frequency as resonance drifts, avoiding hard switching and efficiency loss.

A vertically integrated GaN diode-transistor stack uses isolation layers and 2DEG depletion to cut leakage, save wafer area, and improve reliability.

A slope-based delay lets a second PFC phase turn on out of phase, avoiding sub-harmonic oscillation, lowering THD, and cutting switching loss.

Switch resistance modulation and staged load enablement limit start-up in-rush current in fixed-ratio bus converters.

A synchronous average harmonic controller lets a single-stage solid-state transformer cut series losses while maintaining isolated power factor correction and voltage regulation.

PWM pulse-width comparison identifies the least efficient power phase to shed, cutting losses and balancing wear in multiphase regulators.

Switching between phase shift and asymmetric PWM control widens duty ratio range and keeps DC output voltage stable under input fluctuation.

A single-core reactor with switchable interleave and in-phase driving cuts current ripple, losses, and reactor size in power conversion.

Switching between transformer and capacitor transmission paths widens DC-DC voltage conversion range while reducing loss and transformer size.

A voltage-selective skip threshold keeps a power converter from chattering between foldback and skip modes, cutting ripple and light-load losses.

A clamp circuit resets the inductor to stop startup current runaway in a bidirectional push-pull converter without high-voltage pre-biasing.

Threshold-based switching between non-complementary and Burst modes improves light-load efficiency while reducing no-load power, noise, and circulating current.

Input-voltage-based delay control separates primary and secondary switch timing in LLC converters to prevent shoot-through and improve efficiency.

A punch-through NPN triode and trench-gate layout cuts RC-IGBT reverse recovery loss while limiting leakage current and preserving IGBT cell reliability.

Adaptive switch timing redirects freewheeling current to balance inner and outer switch voltage and avoid higher-voltage components.

Electronic series-parallel switching replaces mechanical DC contacts to cover 200-800 V efficiently with soft switching and bidirectional flow.

Bridge-path bypass and middle voltage control improve DC-DC converter efficiency and power density while supporting buck, boost, and buck-boost modes.

Current-edge sensing detects DCM before drive-signal transitions, improving LLC synchronous rectifier timing accuracy with simpler layout.

Relay-based automatic transfer switching keeps power delivery stable during input faults without using two full redundant power supplies.