Electronic device, flash memory controller and access method thereof

Abstract

The present invention relates to an electronic device, a flash memory controller, and an access method thereof. The present invention discloses a flash memory controller comprising a read-only memory, a microprocessor, and a buffer memory, wherein the buffer memory comprises a data temporary storage area with continuous addresses. When the flash memory controller receives data from a host device, the microprocessor determines whether there is sufficient space between the last data entry and an end address in the data temporary storage area to store the entire content of the data. If there is insufficient space between the last data entry and the end address in the data temporary storage area to store the entire content of the data, the microprocessor directly writes the data starting from the start address in the data temporary storage area without writing any portion of the data to the area before the end address in the data temporary storage area.

Description

Technical Field

[0001] The present invention relates to a flash memory and a related control method. Background Art

[0002] With the rapid development of 3D flash memory, the number of stacked layers is increasing. The quality of data stored in flash memory has become unstable, and the method of writing data to flash memory can also affect its quality. Therefore, how to propose an efficient data writing method with better data quality and a good write amplification index (WAI) is an important issue. Summary of the Invention

[0003] Therefore, one of the objectives of the present invention is to provide a flash memory controller and a related control method so that data written to the flash memory has better quality and a better write amplification index, thereby solving the problems described in the prior art.

[0004] In one embodiment of the present invention, a flash memory controller is disclosed. The flash memory controller is used to access a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes multiple blocks, and each block includes multiple data pages. The flash memory controller includes a read-only memory, a microprocessor, and a buffer memory. The read-only memory is used to store a program code, and the microprocessor is used to execute the program code to control access to the flash memory module. The buffer memory includes a data temporary storage area with consecutive addresses, wherein the consecutive addresses include a start address and an end address. The data temporary storage area is used to temporarily store data from a host device. During operation of the flash memory controller, when the flash memory controller receives data from the host device, the microprocessor determines whether there is sufficient space between the last data entry and the end address of the data temporary storage area to store the entire content of the data. If there is space between the last data entry and the end address of the data temporary storage area to store a portion of the data content, but insufficient space to store the entire content of the data, the microprocessor directly writes the data starting from the start address of the data temporary storage area, and does not write any portion of the data to the area before the end address of the data temporary storage area.

[0005] In another embodiment of the present invention, an electronic device is disclosed, comprising a flash memory module and a flash memory controller, wherein the flash memory controller includes a buffer memory having a data temporary storage area with consecutive addresses, wherein the consecutive addresses include a start address and an end address, and the data temporary storage area is used to temporarily store data from a host device. During operation of the electronic device, when the flash memory controller receives data from the host device, the flash memory controller determines whether there is sufficient space between the last data entry and the end address in the data temporary storage area to store the entire data content. If there is space between the last data entry and the end address in the data temporary storage area to store a portion of the data content, but not enough space to store the entire data content, the flash memory controller directly writes the data starting from the start address in the data temporary storage area, and does not write any portion of the data into the area between the last data entry and the end address in the data temporary storage area.

[0006] In another embodiment of the present invention, a control method for a flash memory controller is disclosed, comprising the following steps: configuring a data temporary storage area with consecutive addresses in a buffer memory of the flash memory controller, wherein the consecutive addresses include a start address and an end address, and the data temporary storage area is used to temporarily store data from a master device; receiving data from the master device; determining whether there is sufficient space between the last data entry and the end address in the data temporary storage area to store the entire data content; and if there is space between the last data entry and the end address in the data temporary storage area to store a portion of the data content but insufficient space to store the entire data content, directly writing the data starting from the start address in the data temporary storage area without writing any portion of the data into the area between the last data entry and the end address in the data temporary storage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0008] Figure 2 FIG. 1 is a schematic diagram of a block in a flash memory module according to an embodiment of the present invention.

[0009] Figure 3 FIG. 1 is a schematic diagram showing a flash memory module including a plurality of first blocks and a second block according to an embodiment of the present invention.

[0010] Figure 4 FIG. 1 is a schematic diagram of planning a data temporary storage area in a buffer memory according to an embodiment of the present invention.

[0011] Figure 5FIG. 1 is a schematic diagram illustrating how to write the next piece of data when the remaining space after the last piece of data in the temporary data storage area is insufficient according to an embodiment of the present invention.

[0012] Figure 6 FIG. 4 is a flow chart of a control method of a flash memory controller according to an embodiment of the present invention.

[0013] Explanation of symbols

[0014] 100: Electronic devices

[0015] 110: Flash memory controller

[0016] 112: Microprocessor

[0017] 112C: Program code

[0018] 112M: Read-only memory

[0019] 114: Control Logic

[0020] 116: Buffer memory

[0021] 118: Interface Logic

[0022] 120: Flash memory module

[0023] 130: Main device

[0024] 132: Encoder

[0025] 134:Decoder

[0026] 142: Read retry table

[0027] 144: Read the success record table

[0028] 200: Block

[0029] 202: Floating Gate Transistor

[0030] 302,304:Super Block

[0031] 310,320: Storage surface

[0032] 312_1~312_N: first block

[0033] 322_1~322_N: first block

[0034] 314_1~314_M: Second block

[0035] 324_1~324_M: Second block

[0036] 313,315: Data page

[0037] 410: Data temporary storage area

[0038] 600~608: Steps

[0039] AD_S: starting address

[0040] AD_E: End address

[0041] BL1, BL2, BL3: bit lines

[0042] WL0~WL2,WL4~WL6: word lines DETAILED DESCRIPTION

[0043] Figure 1 FIG1 is a schematic diagram of an electronic device 100 according to an embodiment of the present invention. The electronic device 100 includes a flash memory module 120 and a flash memory controller 110. The flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120. The control logic 114 includes an encoder 132 and a decoder 134. The encoder 132 is used to encode data written into the flash memory module 120 to generate a corresponding check code (or error correction code, ECC), and the decoder 134 is used to decode data read from the flash memory module 120.

[0044] Typically, the flash memory module 120 includes multiple flash memory chips, each of which includes multiple blocks. The flash memory controller 110 erases data from the flash memory module 120 in blocks. Furthermore, a block can store a specific number of data pages, and the flash memory controller 110 writes data to the flash memory module 120 in pages. In this embodiment, the flash memory module 120 is a 3D NAND-type flash module.

[0045] In practice, the flash memory controller 110, which executes program code 112C via the microprocessor 112, can utilize its internal components to perform various control operations. For example, it utilizes control logic 114 to control access operations (particularly access operations to at least one block or at least one data page) of the flash memory module 120, utilizes buffer memory 116 to perform required buffering, and utilizes interface logic 118 to communicate with a host device 130. Buffer memory 116 is implemented as random access memory (RAM). For example, buffer memory 116 can be static random access memory (SRAM), but the present invention is not limited thereto.

[0046] In one embodiment, the electronic device 100 may be a portable memory device (e.g., a memory card compliant with SD / MMC, CF, MS, or XD standards), and the host device 130 may be another electronic device connectable to the electronic device 100, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the electronic device 100 may be a solid-state drive or an embedded storage device compliant with Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and may be installed in a mobile phone, a notebook computer, or a desktop computer. In this case, the host device 130 may be a processor of the mobile phone, the notebook computer, or the desktop computer.

[0047] Figure 2 FIG. 2 is a schematic diagram of a block 200 in a flash memory module 120 according to an embodiment of the present invention, wherein the flash memory module 120 is a three-dimensional NAND flash memory. Figure 2 As shown, block 200 includes a plurality of memory cells (such as the floating gate transistor 202 shown in the figure or other charge trap elements), which form a three-dimensional NAND flash memory architecture through a plurality of bit lines (only BL1 to BL3 are shown in the figure) and a plurality of word lines (such as WL0 to WL2, WL4 to WL6 shown in the figure). Figure 2In the example, taking the top plane as an example, all floating gate transistors on word line WL0 constitute at least one data page, all floating gate transistors on word line WL1 constitute at least another data page, and all floating gate transistors on word line WL2 constitute at least another data page... and so on. Furthermore, depending on the flash memory's write method, the definition of word line WL0 and data page (logical data page) may also vary. Specifically, when writing using a single-level cell (SLC) method, all floating gate transistors on word line WL0 correspond to only a single logical data page; when writing using a multi-level cell (MLC) method, all floating gate transistors on word line WL0 correspond to two logical data pages; when writing using a triple-level cell (TLC) method, all floating gate transistors on word line WL0 correspond to three logical data pages; and when writing using a quad-level cell (QLC) method, all floating gate transistors on word line WL0 correspond to four logical data pages. Since those skilled in the art should be familiar with the structure of a 3D NAND flash memory and the relationship between word lines and data pages, the relevant details are not detailed here.

[0048] Figure 3 FIG. 1 is a schematic diagram of a flash memory module 120 according to an embodiment of the present invention. Figure 3 As shown, the flash memory module 120 includes multiple storage planes (in this embodiment, two storage planes 310 and 320 are used for illustration), wherein the storage plane 310 includes at least a plurality of first blocks 312_1 to 312_N and a plurality of second blocks 314_1 to 314_M, and the storage plane 320 includes at least a plurality of first blocks 322_1 to 322_N and a plurality of second blocks 324_1 to 324_M, where N and M are any suitable positive integers. Each of the first blocks 322_1 to 322_N includes a plurality of data pages, for example Figure 3The first block 312_1 shown in FIG. 3 includes a data page 313; each of the second blocks 322_1 to 322_N includes multiple data pages, such as the data page 315 included in the second block 322_1 shown in FIG. In this embodiment, the blocks in the storage planes 310 and 320 constitute multiple super blocks. For example, the first block 312_1 in the storage plane 310 and the first block 322_1 in the storage plane 320 constitute a super block 302. The first blocks 312_1 and 322_1 in the super block 302 are accessed or erased simultaneously. For example, when the flash memory controller 110 writes data to the super block 302, the data can be written sequentially to the data page of the first block 312_1 and the data page of the first block 322_1 in the storage plane 320, or the data can be written to the data page of the first block 312_1 and the data page of the storage plane 320 in an interleaved manner. In another example, the second block 314_1 of the storage plane 310 and the second block 324_1 of the storage plane 320 constitute a super block 304, wherein the second blocks 314_1 and 324_1 in the super block 304 are accessed or erased simultaneously. For example, when the flash memory controller 110 writes data to the super block 304, the data can be written sequentially to the data page of the second block 314_1 and the data page of the second block 324_1 of the storage plane 320, or the data can be written to the data page of the second block 314_1 and the data page of the second block 324_1 of the storage plane 320 in an interleaved manner.

[0049] In this embodiment, the first blocks 312_1-312_N of the storage plane 310 and the first blocks 322_1-322_N of the storage plane 320 are both single-level storage blocks (SLC blocks), while the second blocks 314_1-314_M of the storage plane 310 and the second blocks 324_1-324_M of the storage plane 320 are both double-level storage blocks (MLC blocks), triple-level storage blocks (TLC blocks), or quad-level storage blocks (QLC blocks). For ease of explanation, the following embodiments assume that the second blocks 314_1-314_M and the second blocks 324_1-324_M are both double-level storage blocks, meaning that all memory cells on a single word line constitute two data pages. However, the present invention is not limited to this.

[0050] Figure 3The first blocks 312_1-312_N, 322_1-322_N and the second blocks 314_1-314_M, 322_4-324_M are used to directly store write data from the flash memory controller 110 and can be considered as temporary blocks. The flash memory module 120 can also include multiple data blocks for storing valid data from the temporary blocks in subsequent operations. To effectively utilize the flash memory module 120, when the data written by the flash memory controller 110 is small in size, such as multiple fragmented data of 4 KB in size, the data is written into the first blocks 312_1-312_N and 322_1-322_N. Furthermore, when the data written by the flash memory controller 110 is large in size (greater than 4 KB), the data is written into the second blocks 314_1-314_M and 324_1-324_M, thereby effectively utilizing the space of the flash memory module 120.

[0051] Because the flash memory module 120 is a three-dimensional flash memory module with a stacked architecture, experiments and measurements have shown that a one-shot programming method is preferred for data writing to double-level storage blocks, triple-level storage blocks (TLC blocks), and quad-level storage blocks, effectively reducing the number of error bits and improving write quality. Specifically, using a super block 304 in the flash memory module 120 comprising two double-level storage blocks as an example, assuming a data page size of 16 kilobytes (KB), since all memory cells on a single word line constitute two data pages, and second blocks 314_1 and 324_1 require data to be written simultaneously, the amount of data that can be written to the super block 304 at one time (the minimum amount of data) is 64KB (i.e., 16KB*2*2=64KB). Similarly, the amount of data written at one time to a super block 304 comprising a single-layer storage block is 32KB; if the super block comprises two three-layer storage blocks, the amount of data written at one time is 96KB (i.e., 16KB*3*2=96KB); and if the super block comprises two four-layer storage blocks, the amount of data written at one time is 128KB (i.e., 16KB*4*2=128KB).

[0052] As described above, since the amount of data written at one time to a super block 302 comprising single-layer storage blocks is 32KB, and the amount of data written at one time to a super block 304 comprising dual-layer storage blocks is 64KB, upon receiving data from the host device 130, the flash memory controller 110 temporarily stores the data in the buffer memory 116 and then moves the data stored in the buffer memory 116 to the flash memory module 120 at an appropriate time. However, since the amount of data from the host device 130 is not uniform, the storage space of the buffer memory 116 may not be allocated to ensure that each piece of data has a continuous address. This may cause data originally intended for writing to the super block 304 to be rewritten to the super block 302, thereby affecting the utilization of the flash memory module 120 and increasing the write amplification factor. Therefore, in the following embodiment, a method for accessing the buffer memory 116 is proposed to effectively solve this problem.

[0053] Specifically, the microprocessor 112 may configure the buffer memory 116 to have Figure 4 The data temporary storage area 410 is shown, wherein the data temporary storage area 410 has a continuous address, and the continuous address includes a start address AD_S and an end address AD_E. In one example, the size of the data temporary storage area 410 can be an integer multiple of the amount of data written to the super block 304 at one time, for example, it can be 8 times of 64KB, that is, 512KB. When the flash memory controller 110 receives data from the host device 130, the microprocessor 112 will write the data sequentially starting from the start address AD_S to Figure 4For example, the microprocessor 112 writes the first data from the master device 130 to a 32KB continuous address starting from the start address AD_S (note that the first data may be a combination of multiple data from the master device 130). The second data from the master device 130 is written to a 64KB continuous address immediately following the first data. The third data from the master device 130 is written to a 32KB continuous address immediately following the second data, and so on. Since the first data only has 32KB, the microprocessor 112 writes the first data to the super block 302 of the flash memory module 120 at an appropriate time. After the first data is written, the microprocessor 112 directly deletes the first data from the temporary data buffer 410 to make room for storing other data. Next, since the second data entry is 64KB in size, the microprocessor 112 writes the second data entry into the super block 304 of the flash memory module 120 at an appropriate time using a write-once method. After the second data entry is completely written, the microprocessor 112 directly deletes the second data entry from the temporary data buffer 410 to make room for storing other data. Next, since the third data entry is only 32KB in size, the microprocessor 112 writes the third data entry into the super block 302 of the flash memory module 120 at an appropriate time. After the third data entry is completely written, the microprocessor 112 directly deletes the third data entry from the temporary data buffer 410 to make room for storing other data.

[0054] As mentioned above, since the size of the data temporary storage area 410 can be an integer multiple of the amount of data written to the super block 304 at one time, but the data stored in the data temporary storage area 410 may be 32KB or 64KB, it is possible that only 32KB of storage space is left between the last data and the end address AD_E in the data temporary storage area 410. Figure 5For example, assume that the last data currently stored in the data temporary storage area 410 is the A-th data, and there is only 32KB of storage space left after the A-th data. At this time, if the (A+1)-th data is 64KB, the microprocessor 112 will directly abandon the 32KB storage space after the A-th data in the data temporary storage area 410 and directly write the (A+1)-th data to the 64KB continuous address starting from the starting address AD_S. Specifically, in conventional static random access memory operations, data is written to the end address AD_E and then continues writing at the start address AD_S. In other words, conventionally, the (A+1)th data is split into two parts (each 32KB), wherein the first part is written to the 32KB storage space between the Ath data and the end address AD_E, and the second part is written to the 32KB continuous address starting from the start address AD_S. However, this writing method causes the microprocessor 112 to treat the (A+1)th data as two different data and first write the first part of the (A+1)th data to the super block 302 including the single-layer storage block, and then write the second part of the (A+1)th data to the super block 302 including the single-layer storage block. In conventional memory operations, the (A+1)th data entry that could have been written to the super block 304 comprising double-layer storage blocks is instead written to the super block 302 comprising single-layer storage blocks, thereby affecting the write amplification index of the flash memory module 120. As described above, in this embodiment, when the remaining storage space between the last data entry, the Ath entry, and the end address AD_E in the data temporary storage area 410 is insufficient to store the entire contents of the next data entry (the (A+1)th data entry), the (A+1)th data entry is directly written starting from the start address AD_S of the data temporary storage area 410 without writing any portion of the (A+1)th data entry to the area between the last data entry and the end address AD_E in the data temporary storage area 410. This effectively avoids the aforementioned situation where data that could have been written to the super block 304 is instead written to the super block 302 due to discontinuous memory addresses.

[0055] In addition, the microprocessor 112 will sequentially write the data from the main device 130 to the address after the (A+1)th data. Figure 5 The 32KB storage space between the Ath data and the end address shown will remain a blank area until the Ath data is deleted and subsequent data can be written into it.

[0056] Figure 6 FIG. 1 is a flow chart of a control method of a flash memory controller according to an embodiment of the present invention. Referring to the contents described in the above embodiment, Figure 6 The process is as follows:

[0057] Step 600: The process starts.

[0058] Step 602: A buffer memory in the flash memory controller is configured with a data temporary storage area having continuous addresses, wherein the continuous addresses include a start address and an end address, and the data temporary storage area is used to temporarily store data from a master device.

[0059] Step 604: Receive data from the host device.

[0060] Step 606: Determine whether there is enough space between the last data in the data temporary storage area and the end address to store the entire content of the data.

[0061] Step 608: If there is space between the last data entry and the end address of the data temporary storage area to store part of the data content, but there is insufficient space to store all of the data content, the data is directly written starting from the start address of the data temporary storage area, and no part of the data is written to the area between the last data entry and the end address of the data temporary storage area.

[0062] To briefly summarize the present invention, in the flash memory controller of the present invention, through the planning and writing method of the internal buffer memory, it can be ensured that data that could originally be written to the double-layer storage block, triple-layer storage block, or quadruple-layer storage block will not be written to the single-layer storage block, thereby improving the utilization rate of the flash memory module.

[0063] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller comprises: A read-only memory for storing a program code; a microprocessor for executing the program code to control access to the flash memory module; and A buffer memory comprising a data temporary storage area having continuous addresses, wherein the continuous addresses include a start address and an end address, and the data temporary storage area is used to temporarily store data from a master device; When the flash memory controller receives data from the host device, the microprocessor determines whether there is sufficient space between the last data entry and the end address of the data temporary storage area to store the entire content of the data. If there is space between the last data entry and the end address of the data temporary storage area to store a portion of the data content, but insufficient space to store the entire content of the data, the microprocessor directly writes the data starting from the start address of the data temporary storage area, and does not write any part of the data into the area between the last data entry and the end address of the data temporary storage area.

2. The flash memory controller according to claim 1, wherein: Before the last piece of data in the data temporary storage area is deleted, the flash memory controller will not write any data into the area between the last piece of data and the end address in the data temporary storage area.

3. The flash memory controller according to claim 1, wherein: The flash memory module includes a plurality of first blocks and a plurality of second blocks, wherein each of the plurality of first blocks is a single-level cell (SLC) block, and each of the plurality of second blocks is a multi-level cell (MLC) block, a triple-level cell (TLC) block, or a quad-level cell (QLC) block; wherein the size of the data temporary area is an integer multiple of the amount of data that can be written at one time to the second block.

4. The flash memory controller according to claim 1, wherein: The flash memory module includes a plurality of first blocks and a plurality of second blocks, wherein each of the plurality of first blocks is a single-layer storage block, and each of the plurality of second blocks is a double-layer storage block, a triple-layer storage block, or a quadruple-layer storage block. The amount of data that can be written once to the first block is a first amount of data, and the amount of data that can be written once to the second block is a second amount of data. For any data with a continuous address stored in the data temporary area, if the amount of the data is the first amount of data, the microprocessor moves the data to one of the plurality of first blocks; and if the amount of the data is the second amount of data, the microprocessor moves the data to one of the plurality of second blocks.

5. The flash memory controller according to claim 1, wherein: The buffer memory is a static random access memory.

6. An electronic device comprising: a flash memory module; and A flash memory controller, wherein the flash memory controller includes a buffer memory, the buffer memory having a data temporary storage area with continuous addresses, wherein the continuous addresses include a start address and an end address, and the data temporary storage area is used to temporarily store data from a master device; When the flash memory controller receives data from the host device, the flash memory controller determines whether there is sufficient space between the last data entry and the end address of the data temporary storage area to store the entire data content. If there is space between the last data entry and the end address of the data temporary storage area to store a portion of the data content, but insufficient space to store the entire data content, the flash memory controller directly writes the data starting from the start address of the data temporary storage area, and does not write any portion of the data into the area between the last data entry and the end address of the data temporary storage area.

7. The electronic device according to claim 6, wherein: Before the last piece of data in the data temporary storage area is deleted, the flash memory controller will not write any data into the area between the last piece of data and the end address in the data temporary storage area.

8. The electronic device according to claim 6, wherein: The flash memory module includes a plurality of first blocks and a plurality of second blocks, wherein each of the plurality of first blocks is a single-level cell (SLC) block, and each of the plurality of second blocks is a multi-level cell (MLC) block, a triple-level cell (TLC) block, or a quad-level cell (QLC) block; wherein the size of the data temporary area is an integer multiple of the amount of data that can be written at one time to the second block.

9. The electronic device according to claim 6, wherein: The flash memory module includes a plurality of first blocks and a plurality of second blocks, wherein each of the plurality of first blocks is a single-layer storage block, and each of the plurality of second blocks is a double-layer storage block, a triple-layer storage block, or a quadruple-layer storage block. The amount of data that can be written once to the first block is a first amount of data, and the amount of data that can be written once to the second block is a second amount of data. For any data with a consecutive address stored in the data temporary area, if the amount of the data is the first amount of data, the flash memory controller moves the data to one of the plurality of first blocks; and if the amount of the data is the second amount of data, the flash memory controller moves the data to one of the plurality of second blocks.

10. A control method for a flash memory controller, comprising: A buffer memory in the flash memory controller is configured with a data temporary storage area having continuous addresses, wherein the continuous addresses include a start address and an end address, and the data temporary storage area is used to temporarily store data from a master device; receiving data from the master device; Determine whether there is enough space between the last data in the data temporary storage area and the end address to store all the contents of the data; and If there is space between the last data in the data temporary storage area and the end address to store part of the data, but there is not enough space to store the entire data, the data will be written directly from the starting address of the data temporary storage area, and no part of the data will be written to the area between the last data in the data temporary storage area and the end address.

11. The control method according to claim 10, wherein: The flash memory controller is used to access a flash memory module. The flash memory module includes a plurality of first blocks and a plurality of second blocks. Each of the plurality of first blocks is a single-level cell (SLC) block, and each of the plurality of second blocks is a multi-level cell (MLC) block, a triple-level cell (TLC) block, or a quad-level cell (QLC) block. The size of the data temporary buffer is an integer multiple of the amount of data that can be written to the second block at one time.

12. The control method according to claim 10, wherein: The flash memory controller is used to access a flash memory module, the flash memory module including a plurality of first blocks and a plurality of second blocks, each of the plurality of first blocks being a single-layer storage block, each of the plurality of second blocks being a double-layer storage block, a triple-layer storage block, or a quadruple-layer storage block, a first data amount that can be written at one time to the first block, and a second data amount that can be written at one time to the second block; and the control method further includes: For any data with a continuous address stored in the data temporary area, if the data size of the data is the first data size, move the data to one of the plurality of first blocks; and If the data size of any one piece of data is the second data size, the any one piece of data is moved to one of the plurality of second blocks.

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