A clock configuration system and method

Abstract

This application discloses a clock configuration system and method. It includes: a clock generation circuit and a communication module; the communication module includes a configuration unit, a clock management unit, and a communication circuit; the clock generation circuit is connected to the clock management unit in the communication module; the clock management unit is connected to the communication circuit; the communication circuit is connected to the configuration unit; the clock generation circuit provides a reference clock to the communication module; the configuration unit configures the line rate and data bit width of data transmission in the communication circuit, determines a clock division factor based on the line rate and the data bit width, and configures the clock division factor in the clock management unit; the clock management unit determines the operating clock frequency based on the reference clock and the clock division factor, and provides the operating clock frequency to the communication circuit. Determining the operating clock frequency by configuring the line rate and data bit width reduces the complexity of clock configuration in the communication module.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a clock configuration system and method. Background Technology

[0002] In increasingly complex communication systems, with the surge in data transmission volume, the rates supported by various communication protocols are becoming higher and higher, and the number of data transmission channels integrated within each communication module is increasing. Within a single channel, the line rates in the transmitting and receiving directions are completely independent; the line rates between each channel are independent; and the sampling frequencies in the transmitting and receiving directions are completely independent. While these characteristics bring advantages such as powerful data processing capabilities and flexible use, the increasing combination of AD / DA sampling frequencies and transmission channel line rates leads to increasingly larger design scales. Continuing to use traditional clock design and configuration methods will not only increase system complexity but also make clock configuration increasingly difficult. Summary of the Invention

[0003] This application provides a clock configuration system and method that can reduce the complexity of clock configuration in communication modules.

[0004] To achieve the above objectives, this application provides a clock configuration system, including: a clock generation circuit and a communication module; the communication module includes a configuration unit, a clock management unit, and a communication circuit.

[0005] The clock generation circuit is connected to the clock management unit in the communication module; the clock management unit is connected to the communication circuit; the communication circuit is connected to the configuration unit.

[0006] The clock generation circuit is used to provide a reference clock to the communication module; the configuration unit is used to configure the line rate and data bit width of data transmission in the communication circuit, and determine the clock division coefficient according to the line rate and the data bit width, and configure the clock division coefficient in the clock management unit; the clock management unit is used to determine the working clock frequency according to the reference clock and the clock division coefficient, and provide the working clock frequency to the communication circuit.

[0007] To achieve the above objectives, embodiments of this application provide a clock configuration method, executed by the clock configuration system described in embodiments of this application, comprising:

[0008] Receive the reference clock and obtain the configured data transmission line rate and data bit width;

[0009] The clock division factor is determined based on the line rate and the data bit width;

[0010] The operating clock frequency is determined based on the clock division factor and the reference clock.

[0011] The operating clock frequency is provided to the communication module.

[0012] This application proposes a clock configuration system and method, comprising: a clock generation circuit and a communication module; the communication module includes a configuration unit, a clock management unit, and a communication circuit; the clock generation circuit provides a reference clock to the communication module; the configuration unit configures the line rate and data bit width of data transmission in the communication circuit, determines a clock division factor based on the line rate and data bit width, and configures the clock division factor in the clock management unit; the clock management unit determines the operating clock frequency based on the reference clock and the clock division factor, and provides the operating clock frequency to the communication circuit. By determining the operating clock frequency based on the configured line rate and data bit width, multiple transmitting channels and multiple receiving channels in the communication circuit share a single operating clock frequency, avoiding an increase in the number of clocks due to an increase in the number of transmitting and receiving channels, thus simplifying the clock configuration process and reducing the complexity of clock configuration in the communication module. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the structure of a clock configuration system according to an embodiment of this application;

[0014] Figure 2 This is a schematic diagram of the structure of a clock configuration system according to an embodiment of this application;

[0015] Figure 3 This is a flowchart of a clock configuration method in an embodiment of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0017] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0018] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no inherent meaning. Therefore, "module," "part," or "unit" may be used interchangeably.

[0019] In one embodiment, Figure 1 This is a schematic diagram of a clock configuration system provided in an embodiment of this application. Figure 1As shown, the system includes: a clock generation circuit 10, a communication module 20, and an AD / DA circuit 30. The communication module 20 includes a configuration unit 21, a clock management unit 22, and a communication circuit 23.

[0020] The clock generation circuit 10 is connected to the clock management unit 22 in the communication module 20; the clock management unit 22 is connected to the communication circuit 23; and the communication circuit 23 is connected to the configuration unit 21.

[0021] The clock generation circuit 10 provides a reference clock to the communication module 20 and the AD / DA circuit 30. The configuration unit 21 configures the line rate and data bit width of data transmission in the communication circuit 23, and determines the clock division factor based on the line rate and data bit width, configuring the clock division factor in the clock management unit 22; the clock management unit 22 determines the operating clock frequency based on the reference clock and the clock division factor, and provides the operating clock frequency to the communication circuit 23.

[0022] The configuration unit can be understood as the system's central command center. It configures various units in a specific order according to different application scenarios to schedule system operation. Configurations for various scenarios can be pre-generated in lookup tables. Based on different scenarios, the corresponding configuration information in the table is selected for configuration. For example, assuming that when switching scenarios, scenario 1 selects the first configuration information in the table, and when switching to scenario 2, the second configuration information in the table is selected.

[0023] The clock configuration system in this embodiment can be applied to clock configuration for different rates in the JESD204B / C protocol.

[0024] In one embodiment, the clock management unit includes a phase-locked loop (PLL) circuit, a transmit frequency divider, and a data channel frequency divider; the communication circuit includes a transmit data processing unit, a transmit transmission layer unit, multiple transmit channels, and multiple parallel-to-serial conversion units; wherein, the transmit channels and parallel-to-serial conversion units correspond one-to-one. The PLL circuit is connected to the clock generation circuit, the transmit frequency divider, and the data channel frequency divider, respectively; the transmit frequency divider is connected to the transmit data processing unit and the transmit transmission layer unit, respectively; the data channel frequency divider is connected to multiple transmit channels; and each transmit channel is connected to its corresponding parallel-to-serial conversion unit. The configuration unit is used to configure the line rate and data bit width of each transmit channel, and to determine a first frequency division coefficient based on the total line rate and total data bit width of each transmit channel, and to configure the first frequency division coefficient in the transmit frequency divider; the configuration unit is also used to determine a second frequency division coefficient, and to configure the second frequency division coefficient in the data channel frequency divider. The PLL circuit is used to send a reference clock to the transmit frequency divider and the data channel frequency divider. The transmit frequency divider determines a first operating clock frequency based on a reference clock and a first division factor, and provides this first operating clock frequency to the transmit data processing unit and the transmit transmission layer unit. The data channel frequency divider determines a second operating clock frequency based on a reference clock and a second division factor, and provides this second operating clock frequency to multiple transmit channels. Multiple parallel-to-serial conversion units are connected to a clock generation circuit, used to receive a reference clock, and generate a third operating clock frequency required by the parallel-to-serial conversion units based on the reference clock.

[0025] The phase-locked loop (PLL) circuit is used to integrate the reference clock and send the integrated reference clock to the transmit divider, data channel divider, and receive divider. The integration process can be a process of frequency normalization of the reference clock, which can be understood as multiplying the reference clock by an integer multiple. For example, assuming the reference clock is 150Hz, normalizing it by three times results in 450Hz.

[0026] The parallel-to-serial conversion unit is also used to convert parallel transmitted data into serial transmitted data. If there are N parallel-to-serial conversion units, the clock generation circuit needs to provide N reference clocks.

[0027] In one embodiment, the method for determining the first frequency division coefficient based on the total line rate and total data bit width of each transmission channel may be: obtaining a first ratio of the total line rate to the total data bit width of each transmission channel; and determining the first frequency division coefficient based on the first ratio and the reference clock.

[0028] The first ratio is the first operating clock frequency. Assuming each transmission channel is configured with a line rate of R1(i) and a data bit width of W1(i), then the determined first operating clock frequency is: A first division factor is determined by the calculated first clock frequency and the integrated reference clock, and this first division factor is configured in the transmit divider so that the transmit divider generates a first operating clock frequency based on the first division factor and the integrated reference clock. The first division factor can be the ratio of the first clock frequency to the integrated reference clock.

[0029] In one embodiment, the system further includes: a plurality of first data conversion units and a plurality of second data conversion units; and each of the first and second data conversion units corresponds one-to-one with a transmission channel. The first data conversion units are connected between the transmission layer unit and the transmission channel; the second data conversion units are connected between the transmission channel and the parallel-to-serial conversion unit.

[0030] The write side of the first data transmission conversion unit is connected to the transmit frequency divider and is used to receive the first working clock frequency sent by the transmit frequency divider; the read side of the first data transmission conversion unit is connected to the data channel frequency divider and is used to receive the second working clock frequency sent by the data channel frequency divider; the first data transmission conversion unit is used to convert the working clock frequency of the transmitted data from the first working clock frequency to the second working clock frequency.

[0031] The write side of the second data transmission conversion unit is connected to the data channel frequency divider and is used to receive the second working clock frequency sent by the data channel frequency divider; the read side of the second data transmission conversion unit is connected to the parallel-to-serial conversion unit and is used to receive the third working clock frequency sent by the parallel-to-serial conversion unit; the second data transmission conversion unit is used to convert the bit width of the transmitted data and / or convert the working clock frequency of the transmitted data from the second working clock frequency to the third working clock frequency.

[0032] In one embodiment, the transmission channel includes a transmission link layer unit and a transmission data logic processing unit. The transmission link layer unit is connected between the first transmission data conversion unit and the transmission data logic processing unit; the transmission logic processing unit is connected between the transmission link layer unit and the second transmission data conversion unit; and a data channel frequency divider is used to provide a second operating clock frequency to the transmission link layer unit and the transmission data logic processing unit.

[0033] The transmit link layer unit is used to encode the transmitted data. The transmit data logic processing unit is used to perform framing and scrambling processing on the encoded transmitted data.

[0034] The encoding methods for transmitted data can include 8B / 10B encoding and 64b / 66b encoding. The scrambling process can involve performing a logical operation (e.g., XOR operation) between a pseudo-random sequence generated by a pseudo-random code generator and the transmitted data, altering the characteristics of the transmitted data and making it an unpredictable data stream. Framing can be achieved by adding a header and trailer to the beginning and end of a data segment, thus forming a frame.

[0035] In one embodiment, the clock management unit further includes a receive frequency divider; the communication circuit includes a receive data processing unit, a receive transmission layer unit, multiple receive channels, and multiple serial-to-parallel conversion units; wherein, the receive channels and serial-to-parallel conversion units correspond one-to-one. The receive frequency divider is connected to the phase-locked loop circuit, the receive data processing unit, and the receive transmission layer unit, respectively; the data channel frequency divider is connected to multiple receive channels; and the receive channels are connected to their corresponding serial-to-parallel conversion units.

[0036] The configuration unit is used to configure the line rate and data bit width of each receiving channel, determine the third division factor based on the total line rate and total data bit width of each receiving channel, and configure the third division factor in the receiving divider. The phase-locked loop circuit is used to send the reference clock to the receiving divider.

[0037] The receiver frequency divider is used to determine the fourth operating clock frequency based on the reference clock and the third frequency division coefficient, and provides the fourth operating clock frequency to the receiving data processing unit and the receiving transmission layer unit.

[0038] The data channel divider is also used to provide a second operating clock frequency to multiple transmit channels. Multiple serial-to-parallel conversion units are connected to a clock generation circuit to receive a reference clock and generate a fifth operating clock frequency required by the serial-to-parallel conversion units based on the reference clock.

[0039] One method for determining the third frequency division coefficient based on the total line rate and total data bit width of each receiving channel is to: obtain the second ratio of the total line rate to the total data bit width of each receiving channel; and determine the third frequency division coefficient based on the second ratio and the parameter clock.

[0040] The second ratio can be understood as the fourth operating clock frequency. Assuming the line rate configured for each receiving channel is R2(i) and the configured data bit width is W2(i), then the determined fourth operating clock frequency is: The third division factor is determined by the calculated fourth clock frequency and the integrated reference clock, and then configured in the receiver divider so that the receiver divider generates the fourth operating clock frequency based on the third division factor and the integrated reference clock. The third division factor can be the ratio of the fourth operating clock frequency to the integrated reference clock.

[0041] In one embodiment, the second frequency division factor can be determined by: obtaining the maximum value of the ratio of the line rate to the data bit width of each transmit channel and / or each receive channel; and determining the second frequency division factor based on the maximum value and the reference clock.

[0042] Specifically, the determined second operating clock frequency is: The second division factor is determined by the calculated second clock frequency and the integrated reference clock, and this second division factor is configured in the data channel divider so that the data channel divider generates the second operating clock frequency based on the second division factor and the integrated reference clock. This ensures that the line rate of data in the transmit link layer unit, transmit data logic processing unit, receive link layer unit, and receive data logic processing unit is greater than the line rate of all channels. The second division factor can be the ratio of the second clock frequency to the integrated reference clock.

[0043] In one embodiment, the system further includes: a plurality of first receiving data conversion units and a plurality of second receiving data conversion units; and each of the first receiving data conversion units and the second receiving data conversion units corresponds one-to-one with a receiving channel. The first receiving data conversion unit is connected between the receiving transmission layer unit and the receiving channel; the second receiving data conversion unit is connected between the receiving channel and the parallel-to-serial conversion unit.

[0044] The read side of the first receiving data conversion unit is connected to the receiving frequency divider and is used to receive the fourth working clock frequency sent by the receiving frequency divider; the write side of the first receiving data conversion unit is connected to the data channel frequency divider and is used to receive the second working clock frequency sent by the data channel frequency divider; the first receiving data conversion unit is used to convert the working clock frequency of the received data from the second working clock frequency to the fourth working clock frequency.

[0045] The read side of the second receiving data conversion unit is connected to the data channel frequency divider and is used to receive the second working clock frequency sent by the data channel frequency divider; the write side of the second receiving data conversion unit is connected to the serial-to-parallel conversion unit and is used to receive the fifth working clock frequency sent by the serial-to-parallel conversion unit; the second receiving data conversion unit is used to convert the bit width of the received data and / or convert the working clock frequency of the received data from the fifth working clock frequency to the second working clock frequency.

[0046] In one embodiment, the receiving channel includes a receive link layer unit and a receive data logic processing unit. The receive link layer unit is connected between the first receive data conversion unit and the receive data logic processing unit; the receive logic processing unit is connected between the receive link layer unit and the second receive data conversion unit. A data channel frequency divider is used to provide a second operating clock frequency to the receive link layer unit and the receive data logic processing unit.

[0047] The receiving link layer unit is used to decode the received data; the receiving data logic processing unit is used to deframe and descramble the received data.

[0048] Descrambling is the reverse process of scrambling. It can be performed using the same pseudo-random code as the transmitter, applying the same logical operations to the scrambled received data to restore the original data. Deframing is the reverse process of framing. After receiving the data stream, the start and end of a frame are identified based on the markers in the header and trailer of the received data.

[0049] In one embodiment, Figure 2 This is a schematic diagram of a clock configuration system according to an embodiment of this application. As a further explanation of the above embodiments, as... Figure 2 As shown, the clock management unit 22 includes a phase-locked loop (PLL) circuit, a transmit frequency divider, a data channel frequency divider, and a receive frequency divider. The communication circuit is divided into a communication circuit responsible for transmitting data and a communication circuit responsible for receiving data. The communication circuit responsible for transmitting data includes: a transmit data processing unit, a transmit transmission layer unit, multiple transmit channels, and multiple parallel-to-serial conversion units. Each transmit channel includes a transmit link layer unit and a transmit data logic processing unit. The communication circuit responsible for receiving data includes: a receive data processing unit, a receive transmission layer unit, multiple receive channels, and multiple serial-to-parallel conversion units. Each receive channel includes a receive link layer unit and a receive data logic processing unit.

[0050] The transmitting channels and parallel-to-serial conversion units are in a one-to-one correspondence. The receiving channels and serial-to-parallel conversion units are in a one-to-one correspondence.

[0051] In one embodiment, a transmit frequency divider is used to provide a first operating clock frequency to the transmit data processing unit and the transmit transport layer unit. A data channel frequency divider is used to provide a second operating clock frequency to the transmit link layer unit, the transmit data logic processing unit, the receive link layer unit, and the receive data logic processing unit. A receive frequency divider is used to provide a fourth operating clock frequency to the receive data processing unit and the receive transport layer unit.

[0052] In one embodiment, such as Figure 2 As shown, the phase-locked loop circuit is connected to the clock generation circuit, the transmit frequency divider, and the data channel frequency divider, respectively; the transmit frequency divider is connected to the transmit data processing unit and the transmit transmission layer unit, respectively; the data channel frequency divider is connected to multiple transmit channels; and the transmit channels are connected to their corresponding parallel-to-serial conversion units.

[0053] In one embodiment, the configuration unit 21 is configured to configure the line rate and data bit width of each transmission channel, determine a first frequency division coefficient based on the total line rate and total data bit width of each transmission channel, and configure the first frequency division coefficient in the transmission frequency divider; the configuration unit is further configured to determine a second frequency division coefficient based on the line rate and data bit width in each transmission channel and / or reception channel, and configure the second frequency division coefficient in the data channel frequency divider.

[0054] In one embodiment, the transmit frequency divider provides a first operating clock frequency to the transmit data processing unit and the transmit transport layer unit. The data channel frequency divider provides a second operating clock frequency to multiple transmit channels, namely, to the transmit link layer unit and the transmit data logic processing unit.

[0055] In one embodiment, multiple parallel-to-serial conversion units are connected to a clock generation circuit to receive a reference clock and generate a third operating clock frequency required by the parallel-to-serial conversion unit based on the reference clock.

[0056] In one embodiment, such as Figure 2 As shown, the system further includes: multiple first data conversion units and multiple second data conversion units; and each of the first and second data conversion units corresponds one-to-one with a transmission channel. The first data conversion unit is connected between the transmission layer unit and the transmission channel; the second data conversion unit is connected between the transmission channel and the parallel-to-serial conversion unit.

[0057] The first data conversion unit is used to convert the clock domain of the transmitted data. The second data conversion unit is used to convert the bit width and / or clock domain of the transmitted data. The clock domain conversion can be understood as converting the operating clock frequency of the transmitted data.

[0058] The write side of the first data transmission conversion unit is connected to the transmit frequency divider and is used to receive the first working clock frequency sent by the transmit frequency divider; the read side of the first data transmission conversion unit is connected to the data channel frequency divider and is used to receive the second working clock frequency sent by the data channel frequency divider; the first data transmission conversion unit is used to convert the working clock frequency of the transmitted data from the first working clock frequency to the second working clock frequency.

[0059] The write side of the first data conversion unit can be understood as the side on which the first data conversion unit inputs data, and the read side can be understood as the side on which the first data conversion unit outputs data.

[0060] The write side of the second data transmission conversion unit is connected to the data channel frequency divider and is used to receive the second working clock frequency sent by the data channel frequency divider; the read side of the second data transmission conversion unit is connected to the parallel-to-serial conversion unit and is used to receive the third working clock frequency sent by the parallel-to-serial conversion unit; the second data transmission conversion unit is used to convert the bit width of the transmitted data and / or convert the working clock frequency of the transmitted data from the second working clock frequency to the third working clock frequency.

[0061] The write side of the second data conversion unit can be understood as the side on which the second data conversion unit inputs data, and the read side can be understood as the side on which the second data conversion unit outputs data.

[0062] Both the first and second data conversion units are implemented using pingpong-RAM, where pingRAM and pongRAM can each store the data of one frame. The first data conversion unit writes data at a line rate of R1(i) on the write side and reads data at a line rate of f2*W1(i) on the read side. The second data conversion unit writes data at a line rate of f2*W1(i) on the write side and reads data at a line rate of R1(i) on the read side.

[0063] In one embodiment, such as Figure 2 As shown, the transmission channel includes a transmission link layer unit and a transmission data logic processing unit. The transmission link layer unit is connected between the first transmission data conversion unit and the transmission data logic processing unit; the transmission logic processing unit is connected between the transmission link layer unit and the second transmission data conversion unit. A data channel frequency divider is used to provide a second operating clock frequency to the transmission link layer unit and the transmission data logic processing unit.

[0064] The transmission link layer unit is used to encode the transmitted data; the transmission data logic processing unit is used to perform framing and scrambling processing on the encoded transmitted data. In this embodiment, the encoding method of the transmission link layer unit and the framing and scrambling methods of the transmission data logic processing unit are both configured by the configuration unit.

[0065] In one embodiment, such as Figure 2 As shown, the clock management unit also includes a receiver frequency divider; the communication circuit includes a receiver data processing unit, a receiver transmission layer unit, multiple receiver channels, and multiple serial-to-parallel conversion units; wherein, the receiver channels and serial-to-parallel conversion units correspond one-to-one.

[0066] In one embodiment, such as Figure 2 As shown, the receiving frequency divider is connected to the phase-locked loop circuit, the receiving data processing unit, and the receiving transmission layer unit, respectively; the data channel frequency divider is connected to multiple receiving channels; and the receiving channels are connected to their corresponding serial-to-parallel conversion units.

[0067] The configuration unit 21 is used to configure the line rate and data bit width of each receiving channel, determine the third frequency division coefficient based on the total line rate and total data bit width of each receiving channel, and configure the third frequency division coefficient in the receiving frequency divider.

[0068] The phase-locked loop circuit is used to send the integrated reference clock to the receiver divider. The receiver divider is used to provide the fourth operating clock frequency to the receive data processing unit and the receive transmission layer unit.

[0069] In this embodiment, the data channel divider is also used to provide the second operating clock frequency to multiple transmission channels.

[0070] In one embodiment, multiple serial-to-parallel conversion units are connected to a clock generation circuit to receive a reference clock and generate a fifth operating clock frequency required by the serial-to-parallel conversion unit based on the reference clock.

[0071] The serial-to-parallel conversion unit is also used to convert serial received data into parallel received data. If there are N serial-to-parallel conversion units, the clock generation circuit needs to provide N reference clocks.

[0072] In one embodiment, the system further includes: a plurality of first receiving data conversion units and a plurality of second receiving data conversion units; and each of the first receiving data conversion units and the second receiving data conversion units corresponds one-to-one with a receiving channel.

[0073] The first receiving data conversion unit is connected between the receiving transmission layer unit and the receiving channel; the second receiving data is connected between the receiving channel and the parallel-to-serial conversion unit.

[0074] In this embodiment, the first receive data conversion unit is used to convert the clock domain of the received data. The second receive data conversion unit is used to convert the bit width and / or clock domain of the received data. The clock domain conversion can be understood as converting the operating clock frequency of the received data.

[0075] In one embodiment, the read side of the first receiving data conversion unit is connected to the receiving frequency divider and is used to receive the fourth working clock frequency sent by the receiving frequency divider; the write side of the first receiving data conversion unit is connected to the data channel frequency divider and is used to receive the second working clock frequency sent by the data channel frequency divider; the first receiving data conversion unit is used to convert the working clock frequency of the received data from the second working clock frequency to the fourth working clock frequency.

[0076] Wherein, the write side of the first receiving data conversion unit can be understood as the side on which the first receiving data conversion unit inputs data, and the read side can be understood as the side on which the first receiving data conversion unit outputs data.

[0077] In one embodiment, the read side of the second receiving data conversion unit is connected to the data channel frequency divider and is used to receive the second operating clock frequency sent by the data channel frequency divider; the write side of the second receiving data conversion unit is connected to the serial-to-parallel conversion unit and is used to receive the fifth operating clock frequency sent by the serial-to-parallel conversion unit; the second receiving data conversion unit is used to convert the bit width of the received data and / or convert the operating clock frequency of the received data from the fifth operating clock frequency to the second operating clock frequency.

[0078] The write side of the second receiving data conversion unit can be understood as the side on which the second receiving data conversion unit inputs data, and the read side can be understood as the side on which the second receiving data conversion unit outputs data.

[0079] Both the first and second receive data conversion units are implemented using pingpong-RAM, and pingRAM and pongRAM can each store the data of one frame. The write side of the first transmit data conversion unit writes data at a line rate of f2*W2(i), and the read side reads data at a line rate of R2(i); the write side of the second transmit data conversion unit writes data at a line rate of R2(i), and the read side reads data at a line rate of f2*W2(i).

[0080] In one embodiment, the receiving channel includes a receive link layer unit and a receive data logic processing unit. The receive link layer unit is connected between the first receive data conversion unit and the receive data logic processing unit; the receive logic processing unit is connected between the receive link layer unit and the second receive data conversion unit. A data channel frequency divider is used to provide a second operating clock frequency to the receive link layer unit and the receive data logic processing unit.

[0081] The receiving link layer unit is used to decode the received data; the receiving data logic processing unit is used to deframe and descramble the received data. In this embodiment, the decoding method of the receiving link layer unit and the deframe and descrambling method of the receiving data logic processing unit are both configured by the configuration unit.

[0082] In this embodiment, the transmit link layer units and transmit data logic processing units in multiple transmit channels, and the receive link layer units and receive data logic processing units in multiple receive channels, share a single second operating clock frequency. This prevents an increase in the number of clocks due to an increase in the number of transmit and receive channels, thus simplifying the clock configuration process.

[0083] The technical solution of this embodiment includes: a clock generation circuit and a communication module; the communication module includes a configuration unit, a clock management unit, and a communication circuit; the clock generation circuit provides a reference clock to the communication module; the configuration unit configures the line rate and data bit width of data transmission in the communication circuit, determines the clock division factor based on the line rate and data bit width, and configures the clock division factor in the clock management unit; the clock management unit determines the operating clock frequency based on the reference clock and the clock division factor, and provides the operating clock frequency to the communication circuit. Determining the operating clock frequency by configuring the line rate and data bit width reduces the complexity of clock configuration in the communication module.

[0084] In one embodiment, Figure 3 This is a flowchart illustrating a clock configuration method provided in an embodiment of this application. Figure 3 As shown, the method includes the following steps:

[0085] S310 receives a reference clock and obtains the configured data transmission line rate and data bit width.

[0086] The S320 determines the clock division factor based on the line rate and data bit width.

[0087] S330 determines the operating clock frequency based on the clock division factor and the reference clock.

[0088] S340 provides the operating clock frequency to the communication module.

[0089] For the specific clock configuration process, please refer to the description in the above embodiments, which will not be repeated here.

[0090] The technical solution of this embodiment receives a reference clock and obtains the configured data transmission line rate and data bit width; determines the clock division factor based on the line rate and data bit width; determines the operating clock frequency based on the clock division factor and the reference clock; and provides the operating clock frequency to the communication module. Determining the operating clock frequency from the configured line rate and data bit width can reduce the complexity of clock configuration in the communication module.

[0091] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application.

[0092] Embodiments of this application can be implemented by executing computer program instructions through the data processor of a mobile device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0093] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of the invention. Therefore, the proper scope of the invention will be determined by the claims.

Claims

1. A clock configuration system, characterized by, The system comprises: a clock generation circuit and a communication module; the communication module comprises a configuration unit, a clock management unit and a communication circuit; the clock generation circuit is connected to the clock management unit in the communication module; the clock management unit is connected to the communication circuit; and the communication circuit is connected to the configuration unit; the clock generation circuit is configured to provide a reference clock to the communication module; the configuration unit is configured to configure a line rate and a data bit width of data transmission in the communication circuit, determine a clock division coefficient according to the line rate and the data bit width, and configure the clock division coefficient to the clock management unit; the clock management unit is configured to determine an operating clock frequency according to the reference clock and the clock division coefficient, and provide the operating clock frequency to the communication circuit; the clock management unit comprises a phase-locked loop circuit, a transmission frequency divider, a reception frequency divider and a data channel frequency divider; the communication circuit comprises a transmission data processing unit, a transmission transport layer unit, a reception data processing unit, a reception transport layer unit and a plurality of data channels, each data channel has independent transmission and reception channel processing; wherein the transmission channel comprises a first transmission data conversion unit, a transmission link layer unit, a transmission data logic processing unit, a second transmission data conversion unit and a parallel-serial conversion unit, and the reception channel comprises a first reception data conversion unit, a reception link layer unit, a reception data logic processing unit, a second reception data conversion unit and a serial-parallel conversion unit; the phase-locked loop circuit is connected to the reception frequency divider, the transmission frequency divider and the data channel frequency divider respectively; the transmission frequency divider outputs a first operating clock, and is connected to the transmission data processing unit, the transmission transport layer unit and the first transmission data conversion unit respectively; the reception frequency divider outputs a fourth operating clock, and is connected to the reception data processing unit, the reception transport layer unit and the first reception data conversion unit respectively; the data channel frequency divider outputs a second operating clock frequency, and is connected to core logic units of the plurality of data channels; wherein the core logic units comprise the first transmission data conversion unit, the transmission link layer unit, the transmission data logic processing unit, the second transmission data conversion unit, the first reception data conversion unit, the reception link layer unit, the reception data logic processing unit and the second reception data conversion unit; the first transmission data conversion unit in the data channel completes conversion from the first operating clock frequency to the second operating clock frequency; the second transmission data conversion unit completes conversion from the second operating clock frequency to a third operating clock frequency; the first reception data conversion unit completes conversion from the second operating clock frequency to the fourth operating clock frequency; and the second reception data conversion unit completes conversion from a fifth operating clock frequency to the second operating clock frequency.

2. The system according to claim 1, wherein The configuration unit is configured to configure the line rate and data bit width of each sending channel, determine a first frequency division coefficient according to the total line rate and total data bit width of each sending channel, and configure the first frequency division coefficient to the sending frequency divider; the configuration unit is further configured to determine a second frequency division coefficient and configure the second frequency division coefficient to the data channel frequency divider; The phase-locked loop circuit is configured to send a reference clock to the sending frequency divider and the data channel frequency divider; The sending frequency divider is configured to determine a first working clock frequency according to the reference clock and the first frequency division coefficient, and provide the first working clock frequency to the sending data processing unit and the sending transmission layer unit; The data channel frequency divider is configured to determine a second working clock frequency according to the reference clock and the second frequency division coefficient, and provide the second working clock frequency to the plurality of sending channels; The parallel-to-serial conversion unit and the serial-to-parallel conversion unit in each of the plurality of sending channels are provided with corresponding clock circuits, which are configured to receive the reference clock and generate a third working clock frequency and a fifth clock frequency required by the parallel-to-serial conversion unit and the serial-to-parallel conversion unit according to the reference clock.

3. The system of claim 2, wherein, Determining a first frequency division coefficient according to the total line rate and total data bit width of each sending channel comprises: Obtaining a first ratio of the total line rate to the total data bit width of each sending channel; Determining a first frequency division coefficient according to the first ratio and the reference clock.

4. The system of claim 2, wherein, The system further comprises a plurality of first sending data conversion units and a plurality of second sending data conversion units, and the first sending data conversion units and the second sending data conversion units are in one-to-one correspondence with the sending channels; The first sending data conversion unit is connected between the sending transmission layer unit and the sending channel, and the second sending data conversion unit is connected between the sending channel and the parallel-to-serial conversion unit; The write side of the first sending data conversion unit is connected to the sending frequency divider, configured to receive the first working clock frequency sent by the sending frequency divider; the read side of the first sending data conversion unit is connected to the data channel frequency divider, configured to receive the second working clock frequency sent by the data channel frequency divider; the first sending data conversion unit is configured to convert the working clock frequency of sending data from the first working clock frequency to the second working clock frequency; The write side of the second sending data conversion unit is connected to the data channel frequency divider, configured to receive the second working clock frequency sent by the data channel frequency divider; the read side of the second sending data conversion unit is connected to the parallel-to-serial conversion unit, configured to receive the third working clock frequency sent by the parallel-to-serial conversion unit; the second sending data conversion unit is configured to convert the bit width of sending data and / or convert the working clock frequency of sending data from the second working clock frequency to the third working clock frequency.

5. The system of claim 4, wherein, The sending channel comprises a sending link layer unit and a sending data logic processing unit; The sending link layer unit is connected between the first sending data conversion unit and the sending data logic processing unit; and the sending data logic processing unit is connected between the sending link layer unit and the second sending data conversion unit. The data channel frequency divider is configured to provide the second working clock frequency to the sending link layer unit and the sending data logic processing unit.

6. The system of claim 5, wherein, The sending link layer unit is configured to encode sending data; and the sending data logic processing unit is configured to perform framing and scrambling processing on the encoded sending data.

7. The system of claim 2, wherein, The clock management unit further comprises a receiving frequency divider; the communication circuit comprises a receiving data processing unit, a receiving transmission layer unit, a plurality of receiving channels and a plurality of serial-parallel conversion units; wherein the receiving channels and the serial-parallel conversion units correspond to each other one by one; The receiving frequency divider is connected with the phase-locked loop circuit, the receiving data processing unit and the receiving transmission layer unit respectively; the data channel frequency divider is connected with the plurality of receiving channels; and the receiving channels are connected with the corresponding serial-parallel conversion units; The configuration unit is configured to configure the line rate and the data bit width of each receiving channel, determine a third frequency division coefficient according to the total line rate and the total data bit width of each receiving channel, and configure the third frequency division coefficient to the receiving frequency divider; The phase-locked loop circuit is configured to send a reference clock to the receiving frequency divider; The receiving frequency divider is configured to determine a fourth working clock frequency according to the reference clock and the third frequency division coefficient, and provide the fourth working clock frequency to the receiving data processing unit and the receiving transmission layer unit; The data channel frequency divider is further configured to provide the second working clock frequency to the plurality of sending channels; The plurality of serial-parallel conversion units are connected with the clock generation circuit, configured to receive the reference clock, and generate a fifth working clock frequency required by the serial-parallel conversion unit according to the reference clock.

8. The system of claim 7, wherein, Determining the third frequency division coefficient according to the total line rate and the total data bit width of each receiving channel comprises: Obtaining a second ratio of the total line rate and the total data bit width of each receiving channel; Determining the third frequency division coefficient according to the second ratio and the reference clock.

9. The system of claim 7, wherein, Determining the second frequency division coefficient comprises: Obtaining a maximum value of the line rate and the data bit width ratio of each sending channel and / or each receiving channel; Determining the second frequency division coefficient according to the maximum value and the reference clock.

10. The system of claim 7, wherein, The system further comprises a plurality of first receiving data conversion units and a plurality of second receiving data conversion units; and the first receiving data conversion units and the second receiving data conversion units correspond to the receiving channels one by one; The first receiving data conversion unit is connected between the receiving transmission layer unit and the receiving channel; and the second receiving data conversion unit is connected between the receiving channel and the serial-parallel conversion unit. The first receiving data conversion unit is connected between the receiving transmission layer unit and the receiving channel; and the second receiving data conversion unit is connected between the receiving channel and the serial-parallel conversion unit. The read side of the first receiving data conversion unit is connected with the receiving frequency divider, for receiving the fourth working clock frequency sent by the receiving frequency divider; the write side of the first receiving data conversion unit is connected with the data channel frequency divider, for receiving the second working clock frequency sent by the data channel frequency divider; the first receiving data conversion unit is used for converting the working clock frequency of the receiving data from the second working clock frequency to the fourth working clock frequency; The read side of the second receiving data conversion unit is connected with the data channel frequency divider, for receiving the second working clock frequency sent by the data channel frequency divider; the write side of the second receiving data conversion unit is connected with the serial-parallel conversion unit, for receiving the fifth working clock frequency sent by the serial-parallel conversion unit; the second receiving data conversion unit is used for converting the bit width of the receiving data and / or converting the working clock frequency of the receiving data from the fifth working clock frequency to the second working clock frequency.

11. The system of claim 10, wherein, The receiving channel comprises a receiving link layer unit and a receiving data logic processing unit; The receiving link layer unit is connected between the first receiving data conversion unit and the receiving data logic processing unit; the receiving data logic processing unit is connected between the receiving link layer unit and the second receiving data conversion unit; The data channel frequency divider is used for providing the second working clock frequency to the receiving link layer unit and the receiving data logic processing unit.

12. The system of claim 11, wherein, The receiving link layer unit is used for decoding the receiving data; the receiving data logic processing unit is used for frame-decoding and descrambling the receiving data.

13. A clock configuration method, characterized by, The system of any one of claims 1-12 is executed, comprising: receiving a reference clock, and obtaining a line rate and a data bit width of a configured data transmission; determining a clock frequency division coefficient according to the line rate and the data bit width; determining a working clock frequency according to the clock frequency division coefficient and the reference clock; providing the working clock frequency to a communication module.

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