A data processing system, method and apparatus based on storage devices

Abstract

This application discloses a data processing system, method, and apparatus based on a storage device. The method includes: acquiring a data processing request; acquiring a preset enable relationship table, which includes enable relationships between chip select signal processing units; determining a first chip select signal logic unit corresponding to the target data, and determining a second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit based on the enable relationships; performing an enable operation on the second chip select signal logic unit, and performing a target processing operation on the target data in the first chip select signal logic unit. This application, by utilizing the enable relationships in the preset enable relationship list to determine the second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit corresponding to the target data, and then performing an enable operation on the second chip select signal logic unit before performing data processing operations, meets the high transmission rate requirements during data processing and improves the read / write performance of the storage device.

Description

Technical Field

[0001] This application relates to the field of data processing, and more particularly to a data processing system, method, and apparatus based on a storage device. Background Technology

[0002] With continuous technological advancements, NAND Flash supports increasingly higher speeds, from 200Mbps to 400Mbps, 533Mbps, 667Mbps, 800Mbps, and 1200Mbps. When applying flash memory devices to SSDs, the requirements for signal quality and data transfer rates are also becoming increasingly stringent in order to support these higher speeds. However, traditional, conventional topologies are finding it difficult to support the demands of high-speed flash memory devices. Summary of the Invention

[0003] In order to solve the above-mentioned technical problems, or at least partially solve the above-mentioned technical problems, this application provides a data processing system, method and apparatus based on storage devices.

[0004] According to one aspect of the embodiments of this application, a data processing system based on a storage device is provided, characterized in that the system includes: a controller and at least two flash memory devices, each of the flash memory devices including at least two sets of chip select signal groups;

[0005] The controller is connected to each of the flash memory devices through two sets of transmission channels. The controller is connected to a first set of chip select signal groups in each flash memory device through a first transmission channel and to a second set of chip select signal groups in each flash memory device through a second transmission channel, so that the controller and the flash memory devices form an H-shaped topology. The first set of chip select signal groups and the second set of chip select signal groups do not include the same chip select signal group.

[0006] Furthermore, the chip select signal group includes two different chip select signal logic units.

[0007] According to another aspect of the embodiments of this application, a data processing method based on a storage device is also provided, applied to a controller in a signal processing system, the method comprising:

[0008] Obtain a data processing request, wherein the data processing request carries target data and the target processing operation corresponding to the target data;

[0009] Obtain a preset enable relationship table, wherein the preset enable relationship table includes: enable relationships between chip select signal processing units;

[0010] Determine the first chip select signal logic unit corresponding to the target data, and determine the second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit based on the enable relationship;

[0011] An enable operation is performed on the second chip select signal logic unit, and the target data is processed in the first chip select signal logic unit.

[0012] Furthermore, determining the second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit based on the enable relationship includes:

[0013] Determine the first chip select signal group to which the first chip select signal logic unit belongs, and the first flash memory device to which the first chip select signal group belongs;

[0014] Based on the enabling relationship, a second flash memory device with an enabling relationship with the first flash memory device is determined, and a second chip select signal group that is in a different transmission channel from the second flash memory device is selected, wherein the transmission line is used to connect the chip select signal group and the controller;

[0015] Select the second chip select signal logic unit from the second chip select signal group.

[0016] Furthermore, the step of enabling the second chip select signal logic unit and performing the target processing operation on the target data in the first chip select signal logic unit includes:

[0017] When the target processing operation is data writing, an enable operation is performed on the second chip select signal logic unit;

[0018] After the terminal resistor of the second chip select signal logic unit performs an enable operation, the data content corresponding to the target data is written into the first chip select signal logic unit.

[0019] Furthermore, the step of enabling the second chip select signal logic unit and performing the target processing operation on the target data in the first chip select signal logic unit includes:

[0020] When the target processing operation is data writing, an enable operation is performed on the second chip select signal logic unit;

[0021] After the terminal resistor of the second chip select signal logic unit performs an enable operation, the data content corresponding to the target data is read from the first chip select signal logic unit.

[0022] Furthermore, after the terminating resistor of the second chip select signal logic unit performs an enable operation, the method further includes:

[0023] The terminal resistor of the controller is synchronously enabled.

[0024] According to another aspect of the embodiments of this application, a data processing apparatus based on a storage device is also provided, comprising:

[0025] The first acquisition module is used to acquire a data processing request, wherein the data processing request carries target data and the target processing operation corresponding to the target data;

[0026] The second acquisition module is used to acquire a preset enable relationship table, wherein the preset enable relationship table includes: enable relationships between chip select signal processing units;

[0027] The determining module is used to determine the first chip select signal logic unit corresponding to the target data, and to determine the second chip select signal logic unit that has an enabling relationship with the first chip select signal logic unit based on the enabling relationship;

[0028] The execution module is used to perform the target processing operation on the target data in the first chip select signal logic unit and to perform an enable operation on the second chip select signal logic unit.

[0029] According to another aspect of the embodiments of this application, a storage medium is also provided, the storage medium including a stored program that executes the above steps when the program is run.

[0030] According to another aspect of the embodiments of this application, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; wherein: the memory is used to store computer programs; and the processor is used to execute the steps in the above method by running the programs stored in the memory.

[0031] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the steps in the above-described method.

[0032] Compared with the prior art, the above-mentioned technical solutions provided in this application have the following advantages: In the process of data processing, the method provided in this application determines the second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit corresponding to the target data by using the enable relationship in the preset enable relationship list. Then, before performing data processing operations, the second chip select signal logic unit is enabled, thereby meeting the high transmission rate requirements in the data processing process and improving the read and write performance of the storage device. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A block diagram of a data processing system based on a storage device provided in an embodiment of this application;

[0036] Figure 2 A schematic diagram of a data processing system based on a storage device provided in another embodiment of this application.

[0037] Figure 3 A flowchart illustrating a data processing method based on a storage device, provided as an embodiment of this application;

[0038] Figure 4 A block diagram of a data processing apparatus based on a storage device provided in an embodiment of this application;

[0039] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another similar entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0042] This application provides a data processing system, method, and apparatus based on a storage device. The method provided by this invention can be applied to any electronic device as needed, such as a server, terminal, or other electronic device. For ease of description, it will be referred to as an electronic device below.

[0043] This application provides a data processing system based on a storage device, such as... Figure 1 As shown, the system includes: a controller and at least two flash memory devices, each of which includes at least two sets of chip select signals;

[0044] The controller is connected to each flash memory device through two sets of transmission channels. The controller is connected to the first set of chip select signal groups in each flash memory device through the first transmission channel and to the second set of chip select signal groups in each flash memory device through the second transmission channel, so that the controller and the flash memory devices form an H-type topology. The first set of chip select signal groups and the second set of chip select signal groups do not contain the same chip select signal group.

[0045] In the embodiments of this application, the chip select signal group includes two different chip select signal logic units.

[0046] As an example, such as Figure 2 As shown, the controller is connected to four flash memory devices: flash memory device A, flash memory device B, flash memory device C, and flash memory device D.

[0047] Flash memory devices A, B, C, and D each have four chip select signal groups. Each chip select signal group includes two chip select signal processing units, as follows: the first chip select signal group (which includes NAND-CE0_Lun0 and NAND-CE0_Lun1), the second chip select signal group (which includes NAND-CE1_Lun0 and NAND-CE1_Lun1), the third chip select signal group (which includes NAND-CE2_Lun0 and NAND-CE2_Lun1), and the fourth chip select signal group (which includes NAND-CE3_Lun0 and NAND-CE3_Lun1).

[0048] The controller is connected via the first transmission channel CH0 to NAND-CE1_Lun0, NAND-CE1_Lun1 in the second chip select signal group and NAND-CE3_Lun0, NAND-CE3_Lun1 in the fourth chip select signal group in flash memory device A. The controller is also connected via the first transmission channel CH0 to NAND-CE0_Lun0, NAND-CE0_Lun1 in the first chip select signal group and NAND-CE2_Lun0, NAND-CE2_Lun1 in the third chip select signal group in flash memory device B. Finally, the controller is connected via the first transmission channel CH0 to NAND-CE0_Lun0, NAND-CE0_Lun1 in the first chip select signal group and NAND-CE2_Lun0, NAND-CE2_Lun1 in the third chip select signal group in flash memory device C. The controller is connected to NAND-CE1_Lun0 and NAND-CE1_Lun1 in the second group of chip select signals and NAND-CE3_Lun0 and NAND-CE3_Lun1 in the fourth group of chip select signals in the flash memory device D via the first transmission channel CH0.

[0049] The controller is connected via the second transmission channel CH1 to NAND-CE0_Lun0, NAND-CE0_Lun1 in the first chip select signal group and NAND-CE2_Lun0, NAND-CE2_Lun1 in the third chip select signal group in flash memory device A. The controller is also connected via the second transmission channel CH1 to NAND-CE1_Lun0, NAND-CE1_Lun1 in the second chip select signal group and NAND-CE3_Lun0, NAND-CE3_Lun1 in the fourth chip select signal group in flash memory device B. Finally, the controller is connected via the first transmission channel CH1 to NAND-CE1_Lun0, NAND-CE1_Lun1 in the second chip select signal group and NAND-CE3_Lun0, NAND-CE3_Lun1 in the fourth chip select signal group in flash memory device C. The controller is connected to NAND-CE0_Lun0 and NAND-CE0_Lun1 in the first chip select signal group and NAND-CE2_Lun0 and NAND-CE2_Lun1 in the third chip select signal group in the flash memory device D via the second transmission channel CH1.

[0050] In this embodiment of the application, flash memory devices A, B, C, and D are simultaneously connected to the controller through two transmission channels in the storage device, forming an H-type topology. Compared with the traditional topology, the H-type topology can further improve the signal quality in data processing and transmission, and can enable the data transmission rate to reach 667bps.

[0051] According to one aspect of the embodiments of this application, a method embodiment of a data processing method based on a storage device is provided. Figure 3 A flowchart illustrating a data processing method based on a storage device provided in this application embodiment is shown below. Figure 3 As shown, the method includes:

[0052] Step S11: Obtain a data processing request, wherein the data processing request carries the target data and the target processing operation corresponding to the target data.

[0053] The method provided in this application embodiment is applied to a controller in a storage device, which may be a solid-state drive. The controller can receive a data processing request sent by a requesting device. The data processing request carries target data and the target processing operation corresponding to the target data. The target processing operation may be a data write operation and a data read / write operation.

[0054] It should be noted that when the requesting device has a data processing requirement, the requesting device determines the target data to be processed and the corresponding data processing operation based on the data processing requirement request. Then, it generates a data processing request based on the target data and the target data processing operation and sends the data processing request to the controller of the storage device.

[0055] Step S12: Obtain a preset enable relationship table, wherein the preset enable relationship table includes the enable relationship between chip select signal processing units.

[0056] In this embodiment, the preset enable relationship table can be designed by the operator based on the H-type topology formed by the chip select signal groups in the controller and storage device. The preset enable relationship table includes the enable relationships between chip select signal processing units.

[0057] As an example, the default enable relationship table is as follows:

[0058]

[0059]

[0060] Preset enable relationship table

[0061] Step S13: Determine the first chip select signal logic unit corresponding to the target data, and determine the second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit based on the enable relationship.

[0062] In this embodiment, determining the first chip select signal logic unit corresponding to the target data can be: determining the performance parameters of the current controller and each connected chip select signal logic unit, and determining the chip select signal logic unit with the optimal performance parameters as the first chip select signal logic unit. Alternatively, determining the state of the current controller and each connected chip select signal logic unit, and determining the chip select signal logic unit in an idle state as the first chip select signal logic unit.

[0063] In this embodiment of the application, determining the second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit based on the enable relationship includes the following steps A1-A3:

[0064] Step A1: Determine the first chip select signal group to which the first chip select signal logic unit belongs, and the first flash memory device to which the first chip select signal group belongs.

[0065] In this embodiment, since a flash memory device includes multiple chip select signal groups, and each chip select signal group includes two chip select signal logic units, pre-set configuration information of the flash memory device can be obtained. This configuration information includes the chip select signal groups in the flash memory device and the chip select signal logic units included in each chip select signal group. Then, the first flash memory device and the first chip select signal group to which the first chip select signal belongs can be directly determined.

[0066] Step A2: Based on the enable relationship, determine the second flash memory device that has an enable relationship with the first flash memory device, and select the second chip select signal group from the second flash memory device that is in a different transmission channel from the first chip select signal group, wherein the transmission line is used to connect the chip select signal group and the controller.

[0067] Step A3: Select the second chip select signal logic unit from the second chip select signal group.

[0068] In this embodiment, a second flash memory device with an enabling relationship to the first flash memory device can be determined based on the enabling relationships in a preset enabling relationship table. Then, a second chip select signal group that is in a different transmission channel from the second flash memory device is selected. A second chip select signal logic unit is then selected from the second chip select signal group.

[0069] It should be noted that the chip select signal groups in each flash memory device are connected to the controller through two different transmission channels, forming an H-type topology. Therefore, a second flash memory device with an enable relationship with the first flash memory device is identified. Then, a second chip select signal group located on a different transmission channel from the second flash memory device is identified. For example, the first chip select signal logic unit is Lun0 of the first chip select signal group CE0 in flash memory device A, and the first chip select signal logic unit is connected to the controller through the first transmission channel. At this time, based on the enable relationship, flash memory device B with an enable relationship with flash memory device A can be identified, and the second chip select signal group CE2 in flash memory device B can be identified. Then, the second chip select signal logic unit Lun1 is identified from the second chip select signal group CE2.

[0070] Step S14: Enable the second chip select signal logic unit and perform target processing operation on the target data in the first chip select signal logic unit.

[0071] In this embodiment, an enable operation is performed on the second chip select signal logic unit, and the target data is processed by the target data in the first chip select signal logic unit, including the following steps B1-B2:

[0072] Step B1: When the target processing operation is data writing, perform an enable operation on the second chip select signal logic unit.

[0073] Step B2: After the enable operation is performed on the terminating resistor of the second chip select signal logic unit, the data content corresponding to the target data is written into the first chip select signal logic unit.

[0074] As an example, when the controller writes data to a flash memory device: To write data to flash memory device A's CE0 lun0, the ODT (On-Demand Transmission) of flash memory device B's CE2 lun1 is first enabled, and then the target data is written to flash memory device A's CE0 lun0. To write data to flash memory device A's CE1 lun0, the ODT of flash memory device B's CE3 lun1 is first enabled, and then the target data is written to flash memory device A's CE1 lun0. It should be noted that ODT is the on-chip terminating resistor in the flash memory device, which allows the user to control the connection or disconnection of the internal terminating resistor in the flash memory device by reading and writing registers.

[0075] In this embodiment, step S14, which involves enabling the second chip select signal logic unit and performing target processing on the target data in the first chip select signal logic unit, includes the following steps C1-C2:

[0076] Step C1: When the target processing operation is data writing, perform an enable operation on the second chip select signal logic unit.

[0077] Step C2: After the enable operation is performed on the terminating resistor of the second chip select signal logic unit, the data content corresponding to the target data is read from the first chip select signal logic unit.

[0078] In this embodiment of the application, after the terminating resistor of the second chip select signal logic unit performs an enable operation, the method further includes: synchronously performing an enable operation on the terminating resistor of the controller.

[0079] As an example, when the controller reads data from a flash memory device, if it wants to read data from CE0 lun0 of flash memory device A, it enables the ODT of CE2 lun1 of flash memory device B, and simultaneously enables the controller's ODT. If it wants to read data from CE1 lun0 of flash memory device A, it enables the ODT of CE3 lun1 of flash memory device B, and simultaneously enables the controller's ODT.

[0080] The method provided in this application, during data processing, determines a second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit corresponding to the target data by utilizing the enable relationships in a preset enable relationship list. Then, before performing data processing operations, an enable operation is performed on the second chip select signal logic unit, thereby meeting the high transmission rate requirements during data processing and improving the read and write performance of the storage device.

[0081] Figure 4This is a block diagram of a data processing apparatus based on a storage device, provided as an embodiment of this application. This apparatus can be implemented as part or all of an electronic device through software, hardware, or a combination of both. Figure 4 As shown, the device includes:

[0082] The first acquisition module 41 is used to acquire a data processing request, wherein the data processing request carries target data and the target processing operation corresponding to the target data;

[0083] The second acquisition module 42 is used to acquire a preset enable relationship table, wherein the preset enable relationship table includes: the enable relationship between chip select signal processing units;

[0084] The determination module 43 is used to determine the first chip select signal logic unit corresponding to the target data, and to determine the second chip select signal logic unit that has an enable relationship with the first chip select signal logic unit based on the enable relationship;

[0085] The execution module 44 is used to perform target processing operations on the target data in the first chip select signal logic unit and to perform an enable operation on the second chip select signal logic unit.

[0086] In this embodiment, the determining module 43 is used to determine the first chip select signal group to which the first chip select signal logic unit belongs, and the first flash memory device to which the first chip select signal group belongs; based on the enabling relationship, determine the second flash memory device that has an enabling relationship with the first flash memory device, and select the second chip select signal group that is in a different transmission channel from the second flash memory device, wherein the transmission line is used to connect the chip select signal group and the controller; and select the second chip select signal logic unit from the second chip select signal group.

[0087] In this embodiment, the execution module 44 is used to enable the second chip select signal logic unit when the target processing operation is data writing; after enabling the second chip select signal logic unit, the data content corresponding to the target data is written into the first chip select signal logic unit.

[0088] In this embodiment, the execution module 44 is used to perform an enable operation on the second chip select signal logic unit when the target processing operation is data writing; after the enable operation is performed on the terminating resistor of the second chip select signal logic unit, the data content corresponding to the target data is read from the first chip select signal logic unit.

[0089] In this embodiment of the application, the execution module 44 is used to synchronously execute an enable operation on the controller's termination resistor after the second chip select signal logic unit's termination resistor performs an enable operation.

[0090] This application also provides an electronic device, such as... Figure 5 As shown, the electronic device may include: a processor 1501, a communication interface 1502, a memory 1503, and a communication bus 1504, wherein the processor 1501, the communication interface 1502, and the memory 1503 communicate with each other through the communication bus 1504.

[0091] Memory 1503 is used to store computer programs;

[0092] When the processor 1501 executes the computer program stored in the memory 1503, it implements the steps of the above embodiments.

[0093] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0094] The communication interface is used for communication between the aforementioned terminal and other devices.

[0095] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0096] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0097] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform any of the storage device-based data processing methods described in the above embodiments.

[0098] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the storage device-based data processing methods described in the above embodiments.

[0099] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state drive).

[0100] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

[0101] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A data processing method based on a storage device, applied to a controller in a signal processing system, characterized in that, The method comprises: acquiring a data processing request, wherein the data processing request carries target data and a target processing operation corresponding to the target data; acquiring a preset enablement relationship table, wherein the preset enablement relationship table comprises an enablement relationship between chip select signal processing units; determining a first chip select signal logic unit corresponding to the target data, and determining a second chip select signal logic unit having an enablement relationship with the first chip select signal logic unit according to the enablement relationship; performing an enablement operation on the second chip select signal logic unit, and performing the target processing operation on the target data in the first chip select signal logic unit; the determining of the second chip select signal logic unit having the enablement relationship with the first chip select signal logic unit according to the enablement relationship comprises: determining a first chip select signal group to which the first chip select signal logic unit belongs, and a first flash memory device to which the first chip select signal group belongs; determining a second flash memory device having an enablement relationship with the first flash memory device based on the enablement relationship, and selecting a second chip select signal group different from the first chip select signal group in a transmission channel from the second flash memory device, wherein the transmission line is used for connecting the chip select signal group and the controller; and selecting the second chip select signal logic unit from the second chip select signal group.

2. The method of claim 1, wherein, the performing of the enablement operation on the second chip select signal logic unit and the performing of the target processing operation on the target data in the first chip select signal logic unit comprises: in a case where the target processing operation is data writing, performing the enablement operation on the second chip select signal logic unit; after the terminal resistor of the second chip select signal logic unit performs the enablement operation, writing data content corresponding to the target data into the first chip select signal logic unit.

3. The method of claim 1, wherein, the performing of the enablement operation on the second chip select signal logic unit and the performing of the target processing operation on the target data in the first chip select signal logic unit comprises: in a case where the target processing operation is data writing, performing the enablement operation on the second chip select signal logic unit; after the terminal resistor of the second chip select signal logic unit performs the enablement operation, reading data content corresponding to the target data from the first chip select signal logic unit.

4. The method of claim 3, wherein, after the terminal resistor of the second chip select signal logic unit performs the enablement operation, the method further comprises: synchronously performing the enablement operation on the terminal resistor of the controller.

5. A data processing apparatus based on a storage device, characterized by comprises: a first acquisition module, configured to acquire a data processing request, wherein the data processing request carries target data and a target processing operation corresponding to the target data; a second acquisition module, configured to acquire a preset enablement relationship table, wherein the preset enablement relationship table comprises an enablement relationship between chip select signal processing units; a determination module, configured to determine a first chip select signal logic unit corresponding to the target data, and determine a second chip select signal logic unit having an enablement relationship with the first chip select signal logic unit according to the enablement relationship; The execution module is configured to execute the target processing operation on the target data in the first chip select signal logic unit and perform an enabling operation on the second chip select signal logic unit. The determination module is configured to determine a first chip select signal group to which the first chip select signal logic unit belongs and a first flash memory device to which the first chip select signal group belongs; determine, based on the enabling relationship, a second flash memory device having an enabling relationship with the first flash memory device, and select, from the second flash memory device, a second chip select signal group different from the first chip select signal group in a transmission channel, wherein the transmission line is configured to connect the chip select signal group and the controller; and select the second chip select signal logic unit from the second chip select signal group.

6. A data processing system based on storage devices, characterized in that The system comprises a controller and at least two flash memory devices, each of the flash memory devices comprising at least two chip select signal groups; and the controller is configured to perform the method of any one of claims 1-4. The controller is connected to each of the flash memory devices through two transmission channels, wherein the controller is connected to a first chip select signal group in each of the flash memory devices through a first transmission channel and connected to a second chip select signal group in each of the flash memory devices through a second transmission channel, so that an H-shaped topology is formed between the controller and the flash memory devices, and the first chip select signal group and the second chip select signal group do not comprise the same chip select signal group.

7. The system of claim 6, wherein, The chip select signal group comprises two different chip select signal logic units.

8. A storage medium, characterized by The storage medium comprises a stored program, wherein the program performs the method of any one of claims 1-4 when executed.

9. An electronic device, comprising: The system comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are in communication with each other through the communication bus; and wherein: The memory is configured to store a computer program. The processor is configured to perform the method of any one of claims 1-4 by running the program stored in the memory.

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