Display panel and display device

Abstract

The present invention provides a display panel and a display device, in which a data signal is written into a driving transistor in a sub-pixel through a first signal line during a data writing phase; the first signal line is reused during at least a part of a non-data writing phase, and a power signal is transmitted through the first signal line and a second signal line, thereby indirectly reducing a voltage drop problem when the second signal line transmits a power signal alone, ensuring that the power signals received by each sub-pixel are infinitely consistent, thereby improving the display uniformity of the display panel, and ultimately improving the display effect of the display panel.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment, and more specifically, to a display panel and a display device. Background Art

[0002] With the development of science and technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today. The main component of electronic devices to realize the display function is the display panel.

[0003] In existing display panels, the power signal lines that provide power signals to sub-pixels are located on the same metal layer. In order to ensure the transmittance of the display panel, the wiring space of the longitudinal power signal lines is extremely limited, resulting in a smaller width of the power signal lines. Then, under high current driving conditions, the voltage drop on the power signal lines is obvious, which ultimately leads to inconsistent power signals received by each sub-pixel, resulting in differentiated display, affecting the display effect of the display panel. Summary of the invention

[0004] In view of this, in order to solve the above problems, the present invention provides a display panel and a display device, and the technical solutions are as follows:

[0005] A display panel, comprising: a plurality of sub-pixels arranged in an array;

[0006] The sub-pixel comprises: a pixel circuit and a light-emitting element, the pixel circuit comprises a driving transistor and a data writing transistor, the driving transistor is used to provide a driving current for the light-emitting element, and the data writing transistor is used to provide a data signal for the driving transistor;

[0007] The display panel further comprises: a first signal line for transmitting the data signal, a second signal line for transmitting a power signal, a first gating module and a second gating module;

[0008] The first end of the first gating module is used to receive the data signal, the second end is electrically connected to the first signal line, and the third end is electrically connected to the second signal line; the first end of the second gating module is electrically connected to the second signal line, and the second end is electrically connected to the first signal line; the first electrode of the data writing transistor is electrically connected to the first signal line; the first electrode of the driving transistor is coupled to the second signal line;

[0009] The pixel circuit includes a data writing phase and a non-data writing phase;

[0010] In the data writing stage, the first end of the first gating module is in an open state, the third end of the first gating module and the second gating module are in a closed state, and the data signal is transmitted to the gate of the driving transistor through the first signal line and the data writing transistor;

[0011] During at least part of the time period of the non-data writing phase, the first end of the first gating module is in a closed state, the third end of the first gating module and the second gating module are in an open state, and the first signal line and the second signal line are both used to transmit the power signal.

[0012] A display device comprises the display panel mentioned above.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] The display panel provided by the present invention is provided with a first selection module and a second selection module, so that the first end of the first selection module is used to receive a data signal, the second end is electrically connected to the first signal line, and the third end is electrically connected to the second signal line; the first end of the second selection module is electrically connected to the second signal line, and the second end is electrically connected to the first signal line; the first electrode of the data writing transistor is electrically connected to the first signal line; the first electrode of the driving transistor is coupled to the second signal line, in the data writing stage, the first end of the first selection module is in an open state, the third end of the first selection module and the second selection module are in a closed state, and the data signal is transmitted to the gate of the driving transistor through the first signal line and the data writing transistor; in at least part of the time period of the non-data writing stage, the first end of the first selection module is in a closed state, the third end of the first selection module and the second selection module are in an open state, and the first signal line and the second signal line are both used to transmit the power signal.

[0015] That is to say, in the data writing stage, the data signal is written into the driving transistor in the sub-pixel through the first signal line; the first signal line is reused during at least part of the time period of the non-data writing stage, and the power signal is transmitted through the first signal line and the second signal line, thereby indirectly reducing the voltage drop problem when the second signal line transmits the power signal alone, ensuring that the power signals received by each sub-pixel tend to be infinitely consistent, thereby improving the display uniformity of the display panel, and ultimately improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0017] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0018] Figure 2 A schematic diagram of a sub-pixel provided by an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0020] Figure 4 A schematic diagram of the structure of another sub-pixel provided by an embodiment of the present invention;

[0021] Figure 5 A timing control schematic diagram provided by an embodiment of the present invention;

[0022] Figure 6 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0023] Figure 7 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0024] Figure 8 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0025] Fig. 9 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0026] Fig.10 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0027] Fig.11 Another timing control schematic diagram provided by an embodiment of the present invention;

[0028] Fig.12 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0029] Fig.13 for Fig.12 A partial cross-sectional schematic diagram of a display panel is shown;

[0030] Fig.14 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0031] Fig.15 A schematic structural diagram of a display device provided by the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] refer to Figure 1 , Figure 1 A structural schematic diagram of a display panel provided in an embodiment of the present invention, the display panel includes: a plurality of sub-pixels arranged in an array; in order to achieve full-color display of the display panel, the plurality of sub-pixels 11 may optionally include sub-pixels for emitting green light, sub-pixels for emitting blue light, and sub-pixels for emitting red light.

[0035] refer to Figure 2 , Figure 2 A schematic diagram of a sub-pixel provided in an embodiment of the present invention, the sub-pixel 11 includes: a pixel circuit 12 and a light-emitting element Q, the pixel circuit 12 includes a driving transistor M1 and a data writing transistor M2, the driving transistor M1 is used to provide a driving current for the light-emitting element Q, and the data writing transistor M2 is used to provide a data signal Vdata for the driving transistor M1.

[0036] The driving transistor M1 is coupled to the light emitting element Q. The driving transistor M1 generates a corresponding driving current based on the data signal Vdata and transmits the driving current to the light emitting element Q. The light emitting element Q emits light based on the driving current.

[0037] refer to Figure 3 , Figure 3 The structure diagram of another display panel provided by an embodiment of the present invention, the display panel further includes: a first signal line L1 for transmitting the data signal Vdata, a second signal line L2 for transmitting the power signal PVDD, a first gating module 13 and a second gating module 14.

[0038] The first end of the first selection module 13 is used to receive the data signal Vdata, the second end is electrically connected to the first signal line L1, and the third end is electrically connected to the second signal line L2; the first end of the second selection module 14 is electrically connected to the second signal line L2, and the second end is electrically connected to the first signal line L1; the first electrode of the data writing transistor M2 is electrically connected to the first signal line L1; the first electrode of the driving transistor M1 is coupled to the second signal line L2, and is used to receive the power signal PVDD.

[0039] The pixel circuit 12 includes a data writing phase and a data non-writing phase.

[0040] In the data writing stage, the first end of the first gating module 13 is in an open state, the third end of the first gating module 13 and the second gating module are in a closed state, and the data signal Vdata is transmitted to the gate of the driving transistor M1 through the first signal line L1 and the data writing transistor M2.

[0041] During at least part of the time period of the non-data writing phase, the first end of the first gating module 13 is in a closed state, the third end of the first gating module 13 and the second gating module 14 are in an open state, and the first signal line L1 and the second signal line L2 are both used to transmit the power signal PVDD.

[0042] Specifically, Figure 3 As shown, taking two sub-pixels in two adjacent rows as an example, the first electrode of the data write transistor M2 in the sub-pixel in the nth row is electrically connected to the first signal line L1, and the first electrode of the data write transistor M2 in the sub-pixel in the n+1th row is electrically connected to the first signal line L1.

[0043] like Figure 3 The connection method between the first selection module 13, the second selection module 14, the first signal line L1, the second signal line L2 and the two sub-pixels in two adjacent rows shown is that the data signal Vdata is written into the driving transistor M1 in the sub-pixel through the first signal line L1 during the data writing stage; the first signal line L1 is reused during at least part of the time period of the non-data writing stage, and the power signal PVDD is transmitted through the first signal line L1 and the second signal line L2, thereby indirectly reducing the voltage drop problem when the second signal line L2 transmits the power signal PVDD alone, ensuring that the power signal PVDD received by each sub-pixel is infinitely consistent, thereby improving the display uniformity of the display panel, and ultimately improving the display effect of the display panel.

[0044] It should be noted that one of the first gating modules 13 and one of the second gating modules 14 correspond to N columns of the sub-pixels 11, where N≥1 and N is a positive integer. In the embodiment of the present invention, N=1 is taken as an example for description.

[0045] Optionally, in another embodiment of the present invention, refer to Figure 4 , Figure 4 A schematic diagram of the structure of another sub-pixel provided in an embodiment of the present invention.

[0046] The pixel circuit 12 further includes: a compensation transistor M3, which is used to compensate for the threshold voltage of the driving transistor M1; the first electrode of the compensation transistor M3 is connected to the gate of the driving transistor M1, the second electrode of the compensation transistor M3 is connected to the second electrode of the driving transistor M1, and the gate of the compensation transistor M3 is used to receive the control signal S1. The control signal S1 received by the compensation transistor M3 is a pulse signal, and the effective pulse of the control signal S1 controls the compensation transistor M3 to be in the on state to compensate for the threshold voltage of the driving transistor M1; the invalid pulse of the control signal S1 controls the compensation transistor M3 to be in the off state. Therefore, under the control of the control signal S1, the compensation transistor M3 selectively compensates for the threshold voltage of the driving transistor M1.

[0047] Optional, such as Figure 4 As shown, the pixel circuit 12 also includes a first light-emitting control transistor M4 and a second light-emitting control transistor M5; the first light-emitting control transistor M4 is connected between the second signal line L2 and the first electrode of the driving transistor M1, and the second light-emitting control transistor M5 is connected between the second electrode of the driving transistor M1 and the light-emitting element Q, and is used to control whether the pixel circuit 12 is in the light-emitting stage or the non-light-emitting stage.

[0048] The gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 simultaneously receive the light-emitting control signal EM. Under the control of the light-emitting control signal EM, the second light-emitting control transistor M5 is in an on state or an off state. The light-emitting control signal EM received by the gate of the second light-emitting control transistor M5 is a pulse signal. In the light-emitting stage, the light-emitting control signal EM outputs a valid pulse to control the second light-emitting control transistor M5 to be in an on state, and the driving current provided by the driving transistor M1 flows into the light-emitting element Q to make it emit light. In the non-light-emitting stage, the light-emitting control signal EM outputs an invalid pulse to control the second light-emitting control transistor M5 to be in an off state, and the light-emitting element Q does not emit light.

[0049] Optional, such as Figure 4 As shown, the pixel circuit 12 further includes a first reset transistor M6; a first electrode of the first reset transistor M6 receives a reset signal V REF1, the second electrode of the first reset transistor M6 is connected to the gate of the driving transistor M1, and the gate of the first reset transistor M6 is used to receive the control signal S2. The control signal S2 received by the first reset transistor M6 is a pulse signal, and the effective pulse of the control signal S2 controls the first reset transistor M6 to be in the on state to reset the gate of the driving transistor M1; the invalid pulse of the control signal S2 controls the first reset transistor M6 to be in the off state.

[0050] Optional, such as Figure 4 As shown, the pixel circuit 12 further includes a second reset transistor M7; the first electrode of the second reset transistor M7 is used to receive the initialization signal V REF2 The second electrode of the second reset transistor M7 is connected to the anode of the light emitting element Q, and the gate of the second reset transistor M7 is used to receive the scanning signal S3. The control signal S3 received by the second reset transistor M7 is a pulse signal. The effective pulse of the control signal S3 controls the second reset transistor M7 to be in the on state. The initialization signal V REF2 The anode of the light emitting element Q is written into through the second reset transistor M7 to initialize the light emitting element Q; the invalid pulse of the control signal S3 controls the second reset transistor M7 to be in the off state.

[0051] The cathode of the light emitting element Q is connected to the power signal terminal PVEE.

[0052] Optional, such as Figure 4 As shown, the pixel circuit 12 further includes a storage capacitor C1, a first plate of the storage capacitor C1 is connected to the second signal line L2, and a second plate of the storage capacitor C1 is connected to the gate of the driving transistor M1.

[0053] Optionally, in another embodiment of the present invention, refer to Figure 5 , Figure 5 A timing control schematic diagram provided for an embodiment of the present invention.

[0054] The non-data writing phase includes a light emitting phase.

[0055] In the light-emitting stage, the first end of the first gating module 13 is in a closed state, the third end of the first gating module 13 and the second gating module 14 are in an open state, and the first signal line L1 and the second signal line L2 are both used to transmit the power signal PVDD.

[0056] Specifically, in this embodiment, the non-data writing phase at least includes a light emitting phase. Figure 5In it, EM represents the timing of the light-emitting control signal EM simultaneously received by the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 in the pixel circuit 12, Data represents the timing of the data writing stage, S_n represents the timing of the control signal received by the gate of the data writing transistor M2 in the sub-pixel in the nth row, and S_n+1 represents the timing of the control signal received by the gate of the data writing transistor M2 in the sub-pixel in the n+1th row.

[0057] pass Figure 5 It can be seen from the timing control schematic diagram that after the data signals of all rows are written, the light-emitting control signal EM uniformly controls the light-emitting states of the light-emitting elements in all rows.

[0058] That is to say, in the data writing stage, the data signal Vdata is written into the driving transistor M1 in the sub-pixel through the first signal line L1; in the light-emitting stage, the first signal line L1 is reused, and the power signal PVDD is transmitted through the first signal line L1 and the second signal line L2, so as to indirectly reduce the voltage drop problem when the second signal line L2 transmits the power signal PVDD alone, and ensure that the power signal PVDD received by each sub-pixel is infinitely consistent, thereby improving the display uniformity of the display panel and ultimately improving the display effect of the display panel.

[0059] Optionally, in another embodiment of the present invention, refer to Figure 6 , Figure 6 A schematic structural diagram of another display panel provided by an embodiment of the present invention.

[0060] The first gating module includes a first transistor T1 and a second transistor T2.

[0061] The first electrode of the first transistor T1 is used to receive the data signal Vdata, the first electrode of the second transistor T2 is electrically connected to the second signal line L2, and the second electrodes of the first transistor T1 and the second transistor T2 are both electrically connected to the first signal line L1.

[0062] The gate of the first transistor T1 is used to receive a first control signal K1 , and the gate of the second transistor T2 is used to receive a second control signal K2 .

[0063] Specifically, the first selection module 13 is composed of two transistors, the first electrode of the first transistor T1 serves as the first end of the first selection module 13, the connecting end of the second electrode of the first transistor T1 and the second electrode of the second transistor T2 serves as the second end of the first selection module 13, and the first electrode of the second transistor T2 serves as the third end of the first selection module 13.

[0064] The first control signal K1 received by the first transistor T1 is a pulse signal. The effective pulse of the first control signal K1 controls the first transistor T1 to be in the on state; the ineffective pulse of the first control signal K1 controls the first transistor T1 to be in the off state.

[0065] Similarly, the second control signal K2 received by the second transistor T2 is a pulse signal, and the effective pulse of the second control signal K2 controls the second transistor T2 to be in the on state; the ineffective pulse of the second control signal K2 controls the second transistor T2 to be in the off state.

[0066] Optionally, in another embodiment of the present invention, Figure 6 As shown, the first transistor T1 and the second transistor T2 are of different transistor types.

[0067] The first control signal K1 and the second control signal K2 are the same.

[0068] Specifically, the first transistor T1 and the second transistor T2 are of different transistor types, for example, one of the transistors is an N-type transistor and the other is a P-type transistor, to ensure that the first transistor T1 is in an on state during the data writing phase, and the second transistor T2 is in an off state during the data writing phase, the first transistor T1 is in an off state during the light emitting phase, and the second transistor T2 is in an on state during the light emitting phase.

[0069] Furthermore, the first control signal K1 and the second control signal K2 are identical and can be transmitted through the same signal line, which can also simplify wiring difficulty.

[0070] Optionally, in another embodiment of the present invention, refer to Figure 7 , Figure 7 A schematic structural diagram of another display panel provided by an embodiment of the present invention.

[0071] The first transistor T1 and the second transistor T2 are of the same transistor type.

[0072] The first control signal K1 and the second control signal K2 are different.

[0073] Specifically, the first transistor T1 and the second transistor T2 are of the same transistor type. For example, the first transistor T1 and the second transistor T2 are both P-type transistors. At this time, two different control signals are used to respectively control the first transistor T1 and the second transistor T2 to ensure that the first transistor T1 is in an on state during the data writing stage, and the second transistor T2 is in an off state during the data writing stage, the first transistor T1 is in an off state during the light emitting stage, and the second transistor T2 is in an on state during the light emitting stage.

[0074] Furthermore, by respectively controlling the states of the first transistor T1 and the second transistor T2 through two different control signals, the problem of signal crosstalk can be avoided.

[0075] Optionally, in another embodiment of the present invention, refer to Figure 8 , Figure 8 A schematic structural diagram of another display panel provided by an embodiment of the present invention.

[0076] The second gating module 14 includes: a third transistor T3.

[0077] A first electrode of the third transistor T3 is electrically connected to the second signal line L2 , and a second electrode of the third transistor T3 is electrically connected to the first signal line L1 .

[0078] The gate of the third transistor T3 is used to receive a third control signal K3.

[0079] Specifically, the first electrode of the third transistor T3 serves as the first end of the second gating module 14 , and the second electrode of the third transistor T3 serves as the second end of the second gating module 14 .

[0080] The third control signal K3 received by the third transistor T3 is a pulse signal, and the valid pulse of the third control signal K3 controls the third transistor T3 to be in the on state; the invalid pulse of the third control signal K3 controls the third transistor T3 to be in the off state.

[0081] Optionally, in another embodiment of the present invention, refer to Fig. 9 , Fig. 9 A schematic structural diagram of another display panel provided by an embodiment of the present invention.

[0082] The second transistor T2 and the third transistor T3 are of the same transistor type.

[0083] The second control signal K2 is the same as the third control signal K3.

[0084] Specifically, during at least part of the time period of the non-data writing stage, for example, during the light-emitting stage, the first end of the first enabling module 13 is in a closed state, and the third end of the first enabling module 13 and the second enabling module 14 are in an open state, that is, the second transistor T2 and the third transistor T3 need to be in an on state at the same time, so that the first signal line L1 and the second signal line L2 are both used to transmit the power signal PVDD. Obviously, the second transistor T2 and the third transistor T3 of the same transistor type can be used, for example, the second transistor T2 and the third transistor T3 are both P-type transistors.

[0085] At this time, the second control signal K2 and the third control signal K3 are the same and can be transmitted through the same signal line, which can also simplify the wiring difficulty.

[0086] Furthermore, in another embodiment of the present invention, it can be seen from the above description that the pixel circuit also includes: a first light-emitting control transistor M4 located between the second signal line L2 and the first electrode of the driving transistor M1, and a second light-emitting control transistor M5 located between the second electrode of the driving transistor M1 and the anode of the light-emitting element Q.

[0087] The gate of the first light emission control transistor M4 and the gate of the second light emission control transistor M5 both receive a light emission control signal EM.

[0088] The second control signal K2, the third control signal K3 and the light emitting control signal EM are the same.

[0089] Specifically, since the first end of the first enabling module 13 is in a closed state, the third end of the first enabling module 13 and the second enabling module 14 are in an open state during the light-emitting stage, that is, the second transistor T2 and the third transistor T3 need to be in an on state at the same time, and the second light-emitting control transistor M5 is also in an on state at this time, the same control signal can be used to control the states of the second transistor T2, the third transistor T3 and the second light-emitting control transistor M5 to further simplify the wiring difficulty.

[0090] It should be noted that the reference Fig.10 , Fig.10 This is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. In the embodiment of the present invention, the state in which the light emitting control signal EM simultaneously controls the second transistor T2, the third transistor T3 and the second light emitting control transistor M5 is used as an example for explanation.

[0091] Optionally, in another embodiment of the present invention, refer to Fig.11 , Fig.11 Another timing control schematic diagram provided for an embodiment of the present invention.

[0092] The gate of the data writing transistor M2 is configured to receive a fourth control signal S4 .

[0093] The start time of the fourth control signal S4 is equal to or later than the end time of the data signal transmission.

[0094] Specifically, Fig.11In which EM represents the timing of the light-emitting control signal EM, the second control signal K2 and the third control signal K3 simultaneously received by the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 in the pixel circuit, Data represents the timing of the data writing stage, S_n represents the timing of the fourth control signal S4 received by the gate of the data writing transistor M2 in the sub-pixel in the nth row, S_n+1 represents the timing of the fourth control signal S4 received by the gate of the data writing transistor M2 in the sub-pixel in the n+1th row, and K1 represents the timing of the first control signal K1 received by the gate of the first transistor T1.

[0095] In order to avoid the problem that the data signal Vdata cannot be written into the driving transistor M1, before the fourth control signal S4 received by the gate of the data writing transistor M2 in each row of sub-pixels is turned on, the data signal Vdata can be transmitted to the data signal line first, and after the fourth control signal S4 is turned on, the data signal Vdata can be immediately written into the gate of the driving transistor M1 in the sub-pixel.

[0096] Furthermore, the end time of the first control signal K1 is earlier than the start time of the light-emitting stage to avoid signal interference in the light-emitting stage. That is to say, before the start of the light-emitting stage, the first transistor T1 is in the off state, and the second transistor T2 and the third transistor T3 are in the on state at the same time, so that the first signal line L1 and the second signal line L2 are both used to transmit the power signal PVDD.

[0097] Optionally, in another embodiment of the present invention, refer to Fig.12 , Fig.12 A schematic structural diagram of another display panel provided by an embodiment of the present invention.

[0098] The first signal line L1 extends along a first direction X, and the first direction X is a column direction of the array arrangement.

[0099] The first signal line L1 includes a first line end L1a and a second line end L1b opposite to each other in the first direction X, and the first line end L1a and the second line end L1b are short-circuited with the second signal line L2 respectively.

[0100] Specifically, in the embodiment of the present invention, the first direction X is explained by taking the extension direction of the long side of the display panel as an example. By short-circuiting the first signal line L1 and the second signal line L2, the data signal line and the power signal line are connected in parallel. The power signal PVDD is transmitted through the parallel first signal line L1 and the second signal line L2, and its resistance is reduced. Obviously, the voltage drop problem when the second signal line L2 transmits the power signal PVDD alone can be indirectly reduced, ensuring that the power signal PVDD received by each sub-pixel is infinitely consistent, thereby improving the display uniformity of the display panel, and finally improving the display effect of the display panel.

[0101] Optionally, in another embodiment of the present invention, refer to Fig.13 , Fig.13 for Fig.12 A partial cross-sectional schematic diagram of a display panel is shown.

[0102] The first signal line L1 and the second signal line L2 are located in different metal layers.

[0103] Specifically, the first signal line L1 and the second signal line L2 are short-circuited by the first transistor T1, and can also be short-circuited by the second transistor T2 and / or the third transistor T3. In the embodiment of the present invention, only the first signal line L1 and the second signal line L2 are short-circuited by the first transistor T1 as an example.

[0104] Optionally, in another embodiment of the present invention, refer to Fig.14 , Fig.14 A schematic structural diagram of another display panel provided by an embodiment of the present invention.

[0105] The display panel includes a display area AA and a frame area BB at least partially surrounding the display area AA.

[0106] The first gating module 13 and the second gating module 14 are located in the border area BB and on two opposite sides of the display area AA in the second direction Y.

[0107] The second direction Y is the column direction of the array arrangement.

[0108] Specifically, in the embodiment of the present invention, the border area BB fully surrounds the display area AA as an example. For example, the first selection module 13 can be placed in the lower border area, and the second selection module 14 can be placed in the upper border area, so as to realize the control of the sub-pixels in N columns, where N≥1 and N is a positive integer.

[0109] Optionally, based on all the above embodiments of the present invention, another embodiment of the present invention further provides a display device, referring to Fig.15 , Fig.15 A schematic structural diagram of a display device provided by the present invention.

[0110] The display device 100 includes the display panel described in the above embodiment of the present application.

[0111] The display device 100 includes but is not limited to display devices such as mobile phones and tablets. The display device at least has the same technical effect as a display panel.

[0112] The display panel and display device provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0113] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0114] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0115] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The display panel comprises: a plurality of sub-pixels arranged in an array; The sub-pixel comprises: a pixel circuit and a light-emitting element, the pixel circuit comprises a driving transistor and a data writing transistor, the driving transistor is used to provide a driving current for the light-emitting element, and the data writing transistor is used to provide a data signal for the driving transistor; The display panel further comprises: a first signal line for transmitting the data signal, a second signal line for transmitting a power signal, a first gating module and a second gating module; The first end of the first gating module is used to receive the data signal, the second end is electrically connected to the first signal line, and the third end is electrically connected to the second signal line; the first end of the second gating module is electrically connected to the second signal line, and the second end is electrically connected to the first signal line; the first electrode of the data writing transistor is electrically connected to the first signal line; the first electrode of the driving transistor is coupled to the second signal line; The pixel circuit includes a data writing phase and a non-data writing phase; In the data writing stage, the first end of the first gating module is in an open state, the third end of the first gating module and the second gating module are in a closed state, and the data signal is transmitted to the gate of the driving transistor through the first signal line and the data writing transistor; During at least part of the time period of the non-data writing phase, the first end of the first gating module is in a closed state, the third end of the first gating module and the second gating module are in an open state, and the first signal line and the second signal line are both used to transmit the power signal.

2. The display panel according to claim 1, characterized in that: The non-data writing phase includes a light emitting phase; In the light-emitting stage, the first end of the first gating module is in a closed state, the third end of the first gating module and the second gating module are in an open state, and the first signal line and the second signal line are both used to transmit the power signal.

3. The display panel according to claim 1, characterized in that: The first gating module includes a first transistor and a second transistor; The first electrode of the first transistor is used to receive the data signal, the first electrode of the second transistor is electrically connected to the second signal line, and the second electrode of the first transistor and the second electrode of the second transistor are both electrically connected to the first signal line; The gate of the first transistor is used to receive a first control signal, and the gate of the second transistor is used to receive a second control signal.

4. The display panel according to claim 3, characterized in that: The first transistor and the second transistor are of different transistor types; The first control signal and the second control signal are the same.

5. The display panel according to claim 3, characterized in that: The first transistor and the second transistor are of the same transistor type; The first control signal and the second control signal are different.

6. The display panel according to claim 3, characterized in that: The second gating module includes: a third transistor; A first electrode of the third transistor is electrically connected to the second signal line, and a second electrode of the third transistor is electrically connected to the first signal line; The gate of the third transistor is used to receive a third control signal.

7. The display panel according to claim 6, characterized in that: The second transistor and the third transistor are of the same transistor type; The second control signal is the same as the third control signal.

8. The display panel according to claim 7, characterized in that: The pixel circuit further includes: a first light emission control transistor located between the second signal line and the first electrode of the driving transistor, and a second light emission control transistor located between the second electrode of the driving transistor and the anode of the light emitting element; The gate of the first light emission control transistor and the gate of the second light emission control transistor both receive a light emission control signal; The second control signal, the third control signal and the light emitting control signal are the same.

9. The display panel according to claim 1, characterized in that: One of the first gating modules and one of the second gating modules correspond to N columns of sub-pixels, where N≥1, and N is a positive integer.

10. The display panel according to claim 1, characterized in that: The first signal line extends along a first direction, which is a column direction of the array arrangement; The first signal line includes a first line end and a second line end opposite to each other in the first direction, and the first line end and the second line end are short-circuited with the second signal line respectively.

11. The display panel according to claim 1, characterized in that: The first signal line and the second signal line are located in different metal layers.

12. The display panel according to claim 1, characterized in that: The display panel comprises a display area and a frame area at least partially surrounding the display area; The first gating module and the second gating module are located in the border area and on two opposite sides of the display area in the second direction; The second direction is the column direction of the array arrangement.

13. The display panel according to claim 3, characterized in that: The gate of the data writing transistor is used to receive a fourth control signal; Wherein, the start time of the fourth control signal is equal to or later than the end time of the data signal transmission.

14. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 13.

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