A method and system for tracking a hard loop of a Beidou navigation

Abstract

The application discloses a Beidou navigation hard loop tracking processing method and system, which comprises a DLL code tracking loop and a PLL carrier tracking loop; a channel correlation value output by a channel correlator is read, a loop state stored in a RAM is read, and a current loop state is acquired; the hard loop is configured according to the loop state and different signal system characteristics, a code frequency control word is obtained, the calculated carrier frequency control word and the code frequency control word are set to a tracking channel, and then the loop state is switched according to a current loop completion condition. Therefore, the high-frequency loop tracking software processing bottleneck problem is solved, the low-frequency loop tracking processing is compatible, and the efficiency of loop processing is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a hard loop tracking processing method and system for Beidou navigation spread spectrum signal and baseband signal processing of a navigation receiver. BACKGROUND

[0002] At present, the Beidou-3 system has been formally put into operation, supports multi-frequency point and multi-system signals, provides RNSS positioning and navigation services and RDSS short message communication services for ground users, and terminal users receive different signals of the Beidou-3 system.

[0003] Taking the Beidou-3 RDSS frequency point as an example, the symbol inner integration time of the civilian frequency pilot branch is 1ms, the data branch integration time is 0.03125ms, and the symbol inner integration time of the authorized frequency is 0.03125ms. When the satellite navigation baseband signal tracking processing is performed by a traditional receiver, the signal is generally tracked based on a DSP or ARM platform. The tracking method based on software is affected by the speed of the platform device. When the symbol inner integration time of the tracked signal is 0.03125ms and the tracking refresh frequency of the loop is 32k, the processing capacity bottleneck of the software form tracking method will appear, thereby affecting the normal use of the equipment.

[0004] Among the numerous signal systems of the Beidou-3, the text symbol time is from 0.03125ms to 10ms. The software cannot be compatible with high symbol rate and low symbol rate signal tracking, especially the high frequency loop tracking processing is limited.

[0005] To further improve the tracking processing capacity of the Beidou-3 navigation signal, the Beidou navigation tracking hard loop design method and system of the present application are proposed. SUMMARY

[0006] The main purpose of the present application is to provide a Beidou navigation hard loop tracking processing method and system which is easy to understand, easy to implement, high in reliability, and can adapt to high symbol rate and low symbol rate, to solve the above-mentioned high frequency loop software processing bottleneck problem of Beidou navigation.

[0007] To achieve the above-mentioned purpose, the Beidou navigation hard loop system provided by the present application comprises a DLL code tracking loop and a PLL carrier tracking loop. The DLL code tracking loop is a second-order loop supporting first-order loop parameter configuration, and in the first-order loop state, a carrier-assisted pseudo code is used. The PLL carrier tracking loop is designed as a third-order loop supporting second-order loop parameter configuration.

[0008] Further, the PLL carrier tracking loop uses FFT frequency discrimination for lock-in, and the FFT point number can be configured.

[0009] Further, the DLL code tracking loop and the PLL carrier tracking loop are decomposed into 125 steps. The decomposition of the DLL and PLL calculation steps is decomposed into 125 steps, and all calculations are completed when processing to the 125th step, so that multi-channel simultaneous tracking can be completed using a lower clock.

[0010] Further, the loop state jump switching of the DLL code tracking loop and the PLL carrier tracking loop is achieved by opening a RAM to temporarily store data between states.

[0011] The application also provides a Beidou navigation hard loop tracking processing method based on any of the above methods, comprising the steps of:

[0012] Step S1, reading the channel correlation value output by the channel correlator, reading the loop state stored in the RAM, and obtaining the current loop state;

[0013] Step S21, when the loop state is in the confirmation stage, calculating the maximum peak value branch of the signal envelope by the channel correlation value, and obtaining the code frequency control word according to the adjustment amount setting;

[0014] Step S22, when the loop state is in the FFT frequency offset discrimination traction stage, sending the read channel correlation value to the FFT unit for frequency discrimination to obtain the carrier frequency control word, and then performing corresponding single millisecond or multi-millisecond code ring DLL phase discrimination on the lead and lag correlation value envelopes to obtain the code frequency control word;

[0015] Step S23, when the loop state is in the PLL tracking stage, performing single millisecond or multi-millisecond phase discrimination on the on-time branch correlation value, obtaining the loop quality indicator through energy statistics to obtain the carrier frequency control word, and then performing corresponding single millisecond or multi-millisecond code ring DLL phase discrimination on the lead and lag correlation value envelopes to obtain the code frequency control word;

[0016] Step S3, setting the calculated carrier frequency control word and code frequency control word to the tracking channel, and then switching the loop state according to the current loop completion condition.

[0017] Further, the step S1 further comprises a step of judging whether the current loop state is between confirmation and lock loss; if yes, then entering step S1; if no, then entering the loop state jump processing.

[0018] Further, the step S3 further comprises setting the calculated carrier frequency control word and code frequency control word to the tracking channel and saving them to the RAM.

[0019] Further, the step S21 comprises adjusting the correlation peak position to the on-time branch, and configuring it as multi-millisecond, and obtaining the code frequency control word according to the adjustment amount.

[0020] Furthermore, the FFT unit in step S22 supports configurable number of points when performing frequency discrimination.

[0021] Furthermore, in step S23, when performing corresponding single-millisecond or multi-millisecond code ring DLL phase detection calculations on the time-bound branch correlation values, the arctangent operation is implemented using a lookup table, wherein the multi-millisecond related channel correlation values ​​are stored in RAM.

[0022] The BeiDou navigation hard loop tracking processing method and the flexible hard loop implementation in the technical solution of this invention are designed using FPGA to address the characteristics of different signal systems at multiple frequency points in the navigation signal system. The software configures the hard loop according to the characteristics of the signal system, which solves the bottleneck problem of high-frequency loop tracking software processing, while being compatible with low-frequency loop tracking processing and improving the efficiency of loop processing. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the modules of the Beidou navigation hard loop system in one embodiment of the present invention;

[0024] Figure 2 This is a flowchart illustrating the BeiDou navigation hard loop tracking processing method in one embodiment of the present invention;

[0025] Figure 3 for Figure 2 A flowchart illustrating the sub-steps of the BeiDou navigation hard loop tracking processing method.

[0026] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0027] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0028] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0029] Please see Figure 1 To achieve the above objectives, a BeiDou navigation hard loop system in one embodiment of the present invention includes a DLL code tracking loop 10 and a PLL carrier tracking loop 20; wherein, the DLL code tracking loop 10 is a second-order loop that supports first-order loop parameter configuration, and in the first-order loop state, a carrier-assisted pseudocode is used; the PLL carrier tracking loop 20 is designed as a third-order loop that supports second-order loop parameter configuration.

[0030] Further, the PLL carrier tracking loop adopts FFT frequency discrimination, and the FFT point number is configured.

[0031] Further, the decomposition calculation steps of the DLL code tracking loop and the PLL carrier tracking loop are 125 taps.

[0032] Further, the loop state jump switching of the DLL code tracking loop and the PLL carrier tracking loop is realized by opening RAM to realize data storage between states.

[0033] Specifically, the channel correlation value ready flag is monitored in real time, compatible with 0.03125ms to 10ms integration time, covering all signal systems of Beidou frequency points, and can adapt to the use demand of each system. Support loop state jump switching, realize the switching from lock confirmation to stable tracking state, realize the data storage between states by opening RAM. The non-linear operations such as arctangent operation and division operation use approximation algorithm and lookup table scheme, which takes into account speed and area.

[0034] In a specific example, a parameter configuration and software interaction module is used to issue configuration information such as loop coefficient, multi-millisecond configuration, NCO setting, etc. to the hard loop by software. The correlation value reading module reads the correlation value according to the correlation value ready flag given by the channel, and the frequency is controlled by the channel according to the signal integration time. The coherent and incoherent operation module processes and calculates the correlation value to obtain the multi-millisecond correlation value, the multi-millisecond envelope value, etc. The FFT frequency discrimination locking unit, the DLL code loop unit, the PLL carrier loop unit and the NCO setting unit jointly complete the traction tracking of the signal. The switching of the second-order DLL and the first-order DLL can be set by the parameters issued by the software, and the switching of the third-order PLL and the second-order PLL is also configured by the parameters issued by the software. After the frequency control word setting is completed, the switching is performed according to the loop condition, and the state is saved to the RAM to complete the loop calculation of a tracking channel.

[0035] The application also provides a Beidou navigation hard loop tracking processing method based on any one of the above-mentioned methods, comprising the steps of:

[0036] Step S1, reading the channel correlation value output by the channel correlator, reading the loop state stored in the RAM, and obtaining the current loop state;

[0037] Step S21, when the loop state is in the confirmation stage, the channel correlation value is used to calculate the signal envelope to find the branch where the maximum peak value is located, and the code frequency control word is obtained according to the adjustment amount setting;

[0038] Step S22, when the loop state is in the FFT frequency offset discrimination traction phase, the read channel correlation value is sent to the FFT unit for frequency discrimination to obtain the carrier frequency control word, and the lead and lag correlation value envelopes are subjected to corresponding single millisecond or multi-millisecond code loop DLL phase discrimination to obtain the code frequency control word.

[0039] Step S23, when the loop state is in the PLL tracking phase, the single millisecond or multi-millisecond phase discrimination is performed on the on-time branch correlation value, and the loop quality indicator is obtained through energy statistics to obtain the carrier frequency control word, and the lead and lag correlation value envelopes are subjected to corresponding single millisecond or multi-millisecond code loop DLL phase discrimination to obtain the code frequency control word.

[0040] Step S3, the calculated carrier frequency control word and code frequency control word are set to the tracking channel, and the loop state switching is performed according to the current loop completion condition.

[0041] Further, the step S3 further includes setting the calculated carrier frequency control word and code frequency control word to the tracking channel to the RAM.

[0042] Further, the step S21 includes adjusting the correlation peak position to the on-time branch, and being configured as multi-millisecond, and obtaining the code frequency control word according to the adjustment amount.

[0043] Further, the FFT unit in the step S22 supports point number configuration when performing frequency discrimination.

[0044] Further, in the step S23, when the on-time branch correlation value is subjected to corresponding single millisecond or multi-millisecond code loop DLL phase discrimination calculation, the arctangent operation is realized by using a lookup table, and the multi-millisecond correlation channel correlation value is stored in the RAM.

[0045] Please combine Figure 3 , the step S1 further includes a step of judging whether the current loop state is between confirmation and loss of lock; if yes, the step S1 is entered; if no, the loop state jump processing is entered, and the empty processing is entered.

[0046] When the loop state is in the confirmation phase, the step S21 is entered, the DLL code tracking loop is independently operated, the maximum peak branch is found after the signal envelope is calculated through the channel correlation value, the code frequency control word is obtained according to the adjustment amount setting, and then the NCO setting is entered.

[0047] When the loop state is in the FFT frequency offset discrimination traction phase, step S22 is entered, the channel correlation value read is sent to the FFT unit for frequency discrimination to obtain the carrier frequency control word; then code loop DLL phase discrimination is entered, i.e., the leading and lagging correlation value envelopes are subjected to corresponding single millisecond or multi-millisecond code loop DLL phase discrimination to obtain the code frequency control word, and then NCO setting is entered.

[0048] When the loop state is in the PLL tracking phase, step S23 is entered, the on-time branch correlation value is subjected to single millisecond or multi-millisecond phase discrimination to determine whether the on-time branch satisfies multi-millisecond tracking or single millisecond tracking; then energy statistics are performed by corresponding modes to obtain the loop quality indication, thereby obtaining the carrier frequency control word; then code loop DLL phase discrimination is entered, i.e., the leading and lagging correlation value envelopes are subjected to corresponding single millisecond or multi-millisecond code loop DLL phase discrimination to obtain the code frequency control word, and then NCO setting is entered.

[0049] The NCO setting includes saving the carrier frequency control word or the code frequency control word into the RAM and setting into the digital oscillator of the tracking channel to complete the copying of the local carrier and the local pseudo-random code. The digital oscillator is not within the scope of the present text, and the principle will not be described again.

[0050] The state switching jump processing refers to state switching according to the completion after all loop operations are completed in the current loop state. The specific switching logic is as follows:

[0051] If the current loop is the confirmation state, if the confirmation is successful, the state jumps to the traction state, if the confirmation fails, the state jumps to the loss of lock state, and the state is saved to the RAM;

[0052] If the current loop is the traction state, if the traction is successful, the state jumps to the bit synchronization state, if the traction fails, the state jumps to the loss of lock state, and the state is saved to the RAM;

[0053] If the current loop is the bit synchronization state, if the bit synchronization is successful, the state jumps to the frame synchronization state, if the bit synchronization fails, the state jumps to the loss of lock state, and the state is saved to the RAM;

[0054] If the current loop is the frame synchronization state, if the frame synchronization is successful, the state jumps to the electric text receiving state, if the frame synchronization fails, the state jumps to the loss of lock state, and the state is saved to the RAM;

[0055] If the current loop is the electric text receiving state, if the electric text receiving is successful, the state jumps to the working state, if the electric text receiving fails, the state jumps to the loss of lock state, and the state is saved to the RAM;

[0056] In a specific application example, in step S3, after setting the frequency control word, the loop state is updated to the RAM, and the loop processing of one tracking channel is completed. 125 clock cycles are required for each channel, and the working clock of the FPGA hard loop is calculated at 62MHz. Therefore, 496 channels of tracking calculation can be completed within 1ms, and 15 channels of tracking calculation can be completed within 0.03125ms. In the current Beidou-III signal system, the symbol time of the S2CD is 0.03125ms, and the hard loop mode can meet the tracking requirements of high symbol rate.

[0057] In the description of the present specification, the description of the terms "one embodiment", "another embodiment", "other embodiments", or "first embodiment to Xth embodiment" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, method steps or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0058] The above embodiment numbers of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0059] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A method for tracking and processing a Beidou navigation hard loop based on a Beidou navigation hard loop system, characterized in that, The Beidou navigation hard loop system comprises a DLL code tracking loop and a PLL carrier tracking loop; wherein the DLL code tracking loop is a second-order loop supporting first-order loop parameter configuration, and in the first-order loop state, carrier-assisted pseudo code is used; the PLL carrier tracking loop is designed as a third-order loop supporting second-order loop parameter configuration; The PLL carrier tracking loop adopts FFT frequency discrimination, and the FFT point number is configured; the decomposition calculation steps of the DLL code tracking loop and the PLL carrier tracking loop are 125 beats; the loop state jump switching of the DLL code tracking loop and the PLL carrier tracking loop is realized by opening RAM to temporarily store data between states. The Beidou navigation hard loop tracking processing method comprises the following steps: Step S1, reading the channel correlation value output by the channel correlator, reading the loop state stored in the RAM, and obtaining the current loop state; Step S21, when the loop state is in the confirmation stage, finding the branch where the maximum peak value is located by calculating the signal envelope according to the channel correlation value, and obtaining the code frequency control word according to the adjustment amount setting; Step S22, when the loop state is in the FFT frequency offset discrimination traction stage, sending the read channel correlation value into the FFT unit for frequency discrimination to obtain the carrier frequency control word, and then performing corresponding single-millisecond or multi-millisecond code ring DLL phase discrimination on the lead and lag correlation value envelopes to obtain the code frequency control word; Step S23, when the loop state is in the PLL tracking stage, performing single-millisecond or multi-millisecond phase discrimination on the on-time branch correlation value, obtaining the loop quality indicator through energy statistics to obtain the carrier frequency control word, and then performing corresponding single-millisecond or multi-millisecond code ring DLL phase discrimination on the lead and lag correlation value envelopes to obtain the code frequency control word; Step S3, setting the calculated carrier frequency control word and code frequency control word to the tracking channel, and then switching the loop state according to the current loop completion condition.

2. The Beidou navigation hard loop tracking processing method according to claim 1, characterized in that, The step S1 further comprises a step of judging whether the current loop state is between confirmation and lock loss; if yes, step S1 is entered; if no, loop state jump processing is entered.

3. The Beidou navigation hard loop tracking processing method according to claim 1, characterized in that, The step S21 comprises adjusting the correlation peak position to the on-time branch, and configuring it as multi-millisecond, and obtaining the code frequency control word according to the adjustment amount.

4. The Beidou navigation hard loop tracking processing method according to claim 1, characterized in that, The FFT unit in step S22 supports point number configuration when performing frequency discrimination.

5. The Beidou navigation hard loop tracking processing method according to claim 1, characterized in that, In step S23, when performing phase discrimination calculation on the on-time branch correlation value, the arctangent operation is realized by using a lookup table, wherein the channel correlation value of multi-millisecond correlation is stored in the RAM.

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