Via resistance test structure and method for testing via resistance

Abstract

The application provides a via resistance test structure and a method for testing via resistance. The test structure comprises N vias, N+1 layers of metal lines connected by the vias between adjacent two layers of the metal lines, and N+3 test pads, wherein two test pads are respectively connected to the first ends of two layers of the metal lines in the length direction, and the rest of the test pads are respectively connected to the second ends of the metal lines in the length direction, or the first ends of the metal lines in the width direction, or the second ends of the metal lines in the width direction. N is an integer greater than or equal to 2. The N+3 test pads are used to measure the resistance of the N vias, thereby saving the number of test pads, further saving the wafer area and reducing the cost.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to a via resistance test structure, a method for testing via resistance, a method for fabricating the test structure, and a semiconductor structure and test system. Background Technology

[0002] As large-scale integrated circuit manufacturing progresses towards higher integration levels, smaller critical dimensions, and increasingly complex device structures, the requirements for the precision and repeatability of integrated circuit manufacturing processes are becoming increasingly stringent. To meet the overall electrical performance requirements of integrated circuits, circuits with different structures are often stacked layer by layer during chip manufacturing. Specifically, the front-end stacking in integrated circuit manufacturing mainly involves gates and contact holes, while the back-end stacking mainly involves vias and metal lines.

[0003] When performing stress migration testing on semiconductor devices, a large number of test pads are required to test the resistance of vias between metal lines. This excessive use of test pads wastes resources and wafer area, resulting in higher device production costs.

[0004] Stress migration effect is a common reliability problem in integrated circuits, and its risk is primarily assessed through the design of test structures. When testing the resistance of structures for stress migration effect, a four-terminal method is often required to accurately obtain the resistance change of the tested structure. However, a test structure requires four test pads. On wafers in normal mass production, test structures can only be placed in the dicing lines between DIEs, and the area of ​​these dicing lines is very limited. Therefore, it is necessary to optimize the design of the test structure to reduce the use of test pads while still meeting the requirements for assessable reliability. Summary of the Invention

[0005] The main objective of this application is to provide a via resistance test structure, a method for testing via resistance, and a method for preparing the test structure, so as to solve the problem of wasting test pads and wafer area when performing via resistance testing in some schemes.

[0006] To achieve the above objectives, according to one aspect of this application, a through-hole resistance test structure is provided, comprising: N through holes; N+1 layers of stacked metal wires, with adjacent layers of metal wires connected by the through holes, and one through hole connecting adjacent layers of metal wires; N+3 test pads, wherein two test pads are respectively connected to the first end of the length direction of two layers of metal wires, and the remaining test pads are correspondingly connected to the second end of the length direction of each metal wire, or the first end of the width direction of each metal wire, or the second end of the width direction of each metal wire, wherein N is an integer greater than or equal to 2.

[0007] Optionally, the N+1 stacked metal lines include a first layer of metal lines and an N+1th layer of metal lines located on the outer side. The first end of the first layer of metal lines and the first end of the N+1th layer of metal lines in the length direction are respectively connected to the corresponding test pads. The two test pads are respectively used to be electrically connected to a current tester, and the remaining test pads are used to be electrically connected to a potential tester.

[0008] Optionally, the width of the metal wire is greater than or equal to 0.5 micrometers.

[0009] Optionally, the length of the metal wire is greater than or equal to 20 micrometers.

[0010] Optionally, the N+1 layers of stacked metal wires are arranged in parallel.

[0011] Optionally, all the metal wires and all the through holes are made of copper.

[0012] According to another aspect of this application, a method for testing via resistance using any of the test structures is provided, comprising: measuring the current flowing through each of the vias using two test pads connected to a first end in the length direction of a metal line; testing a first potential on the Mth layer metal line using test pads connected to a second end in the length direction of the Mth layer metal line, or a first end in the width direction of the Mth layer metal line, or a second end in the width direction of the Mth layer metal line; testing a second potential on the M+1th layer metal line using test pads connected to a second end in the length direction of the M+1th layer metal line, or a first end in the width direction of the M+1th layer metal line, or a second end in the width direction of the M+1th layer metal line; and obtaining the resistance of the Mth via based on the first potential, the second potential, and the current, wherein 1 ≤ M ≤ N.

[0013] According to another aspect of this application, a method for fabricating a test structure is provided, comprising: forming a semiconductor structure including N vias and N+1 layers of metal lines, wherein adjacent metal lines are connected through the vias, and N is an integer greater than or equal to 2; forming N+3 test pads in a non-device region of the semiconductor structure, wherein two test pads are respectively connected to the first end of each of the two metal lines in the length direction, and the remaining test pads are connected one-to-one to the second end of each metal line in the length direction, or the first end of each metal line in the width direction, or the second end of each metal line in the width direction.

[0014] According to another aspect of this application, a semiconductor structure is provided, comprising: a device region and a non-device region, wherein the via and metal line in the via resistance test structure are located in the device region, and the test pad is located in the non-device region.

[0015] According to another aspect of this application, a testing system is provided, comprising: any one of the via resistance testing structures, a current tester, and a potential tester, wherein the via resistance testing structure is used to test the resistance of the via, the current tester is used to test the current flowing through each of the vias, and the potential tester is used to test the potential of each layer of metal wires.

[0016] Using the technical solution of this application, the via resistance test structure includes N vias, N+1 layers of stacked metal lines, and N+3 test pads. Adjacent metal lines are connected through the vias. The resistance of N vias is measured using N+3 test pads. That is, the via resistance is measured using fewer test pads, saving the number of test pads and further saving wafer area. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 This illustrates one through-hole resistance test structure among several schemes;

[0019] Figure 2 Another through-hole resistance test structure is shown in some of the schemes;

[0020] Figure 3 A via resistance test structure according to an embodiment of this application is shown;

[0021] Figure 4 Another via resistance test structure according to an embodiment of this application is shown;

[0022] Figure 5 A flowchart of a method for testing via resistance according to an embodiment of this application is shown;

[0023] Figure 6 A flowchart illustrating a method for preparing a test structure according to an embodiment of this application is shown.

[0024] The above figures include the following reference numerals:

[0025] 10. First layer of metal wire; 20. Second layer of metal wire; 30. Third layer of metal wire; 40. Fourth layer of metal wire; 50. First through hole; 60. Second through hole; 70. Third through hole; 80. Test pad. Detailed Implementation

[0026] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0027] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0028] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0029] For ease of description, the following explains some of the nouns or terms used in the embodiments of this application:

[0030] Stress migration (SM): When an integrated circuit chip is stored at a certain temperature for a certain period of time without applying current, voids or even complete breaks may appear on some metal lines (aluminum or copper process metal lines). This phenomenon is generally considered to be a result of stress release within the integrated circuit chip itself.

[0031] Some solutions waste test pads and wafer area when performing through-hole resistance testing, such as... Figure 1 As shown, to test the resistance of a via between the first and second metal layers, the four-terminal method requires four test pads. Similarly, as... Figure 2 As shown, to test the resistance of three vias, even with shared test pads, eight test pads are still required. If the test pads are not shared, 3 × 4 = 12 test pads are needed. To address the problem of wasted test pads and wafer area during via resistance testing, embodiments of this application provide a via resistance testing structure, a method for testing via resistance, and a method for fabricating the testing structure.

[0032] A typical embodiment of this application provides a through-hole resistance testing structure, comprising:

[0033] N through holes;

[0034] The N+1 layers of stacked metal wires are connected by the aforementioned through holes between adjacent layers of the aforementioned metal wires, and there is one aforementioned through hole between adjacent layers of the aforementioned metal wires.

[0035] There are N+3 test pads, wherein two of the test pads are respectively connected to the first end of the length direction of each of the two metal lines, and the remaining test pads are connected one-to-one to the second end of the length direction of each metal line, or the first end of the width direction of each metal line, or the second end of the width direction of each metal line, wherein N is an integer greater than or equal to 2.

[0036] Specifically, the N+1 layers of stacked metal wires are arranged in parallel.

[0037] Specifically, when N equals 3, six test pads are used to test the resistance of the three vias, which is better than... Figure 2 The test structure shown saves two test pads; when N equals 4, resistance testing of four vias can be achieved using only seven test pads, compared to using... Figure 2 The test structure shown saves 3 test pads.

[0038] Specifically, N can be set to an integer such as 2, 3, 4, 5, or 6. The number of metal lines is determined according to the chip design requirements.

[0039] Specifically, such as Figure 2 As shown, the metal wire width W is the maximum width value to be detected in the stress migration test. The length L of the metal wire is much greater than the metal wire width W. Generally speaking, the length L of the metal wire is greater than or equal to 20 times the metal wire width W.

[0040] Figure 3 The diagram illustrates a test structure for testing the resistance of three vias, comprising three vias, four layers of stacked metal wires, and six test pads 80. The three vias are identified as the first via 50, the second via 60, and the third via 70. The four layers of stacked metal wires are identified as the first layer metal wire 10, the second layer metal wire 20, the third layer metal wire 30, and the fourth layer metal wire 40. One test pad is connected to the first end of the first layer metal wire 10 along its length, another test pad is connected to the first end of the fourth layer metal wire 40 along its length, and the remaining test pads are connected to the first end of the width direction of each of the aforementioned metal wires.

[0041] It should be noted that the first end of the first layer of metal wire along its length and the first end of the fourth layer of metal wire along its length can be either of the two ends, and the first end of each of the aforementioned metal wires along its width can also be either of the two ends along its width. Figure 3 This is merely illustrating one scenario.

[0042] Figure 4 The diagram illustrates a test structure for testing the resistance of three vias, comprising three vias, four layers of stacked metal wires, and six test pads 80. The three vias are identified as the first via 50, the second via 60, and the third via 70. The four layers of stacked metal wires are identified as the first layer metal wire 10, the second layer metal wire 20, the third layer metal wire 30, and the fourth layer metal wire 40. One test pad is connected to the first end of the first layer metal wire 10 along its length, another test pad is connected to the first end of the fourth layer metal wire 40 along its length, and the remaining test pads are connected to the second end of each of the aforementioned metal wires along their respective lengths.

[0043] It should be noted that the first end of the first layer of metal wire along its length and the first end of the fourth layer of metal wire along its length can be either of the two ends, and the second end of each of the aforementioned metal wires along its length can be either of the two ends. Figure 4 This is merely illustrating one scenario.

[0044] exist Figure 4 A power supply voltage is applied to the test pad connected to the second end of the fourth layer metal line 40 along its length, and a ground voltage is applied to the test pad connected to the second end of the first layer metal line 10 along its length, thus forming a test circuit.

[0045] Specifically, the aforementioned N+1 layers of stacked metal wires include the first layer of metal wires and the N+1th layer of metal wires located on the outer side (e.g., Figure 2 The first layer of metal wire 10 and the fourth layer of metal wire 40 in Figure 3 The first layer of metal wire 10 and the fourth layer of metal wire 40 in Figure 4 The first metal line 10 and the fourth metal line 40 are used in this circuit. The first end of the first metal line and the first end of the (N+1)th metal line are respectively connected to the corresponding test pads. These two test pads are electrically connected to a current meter, and the remaining test pads are used to connect to a potential meter. That is, the test pads connected to the first end of the first metal line and the first end of the (N+1)th metal line are used to test current, and the remaining test pads are used to test voltage. The resistance measurement principle in this scheme is based on the four-terminal method.

[0046] The via resistance test structure of this application includes N vias, N+1 layers of stacked metal lines, and N+3 test pads. Adjacent metal lines are connected through the vias. The resistance of N vias is measured using N+3 test pads. That is, the via resistance is measured using fewer test pads, saving the number of test pads and further saving wafer area.

[0047] Preferably, the width of the metal wire is greater than or equal to 0.5 micrometers.

[0048] Preferably, the length of the metal wire is greater than or equal to 20 micrometers. The length of the metal wire is much greater than its width.

[0049] Specifically, the materials of all the aforementioned metal wires and all the aforementioned through holes are copper.

[0050] Another typical embodiment of this application provides a method for testing the resistance of a through-hole, such as... Figure 5 As shown, it includes:

[0051] Step S101: Measure the current flowing through each of the above-mentioned through holes by using two test pads connected to the first end of the metal wire along its length.

[0052] Specifically, since the multilayer metal wires form a series structure through vias, the current flowing through multiple vias is equal. Therefore, the current measured on the test pad connected to the first end in the length direction of the first layer metal wire, or on the test pad connected to the first end in the length direction of the N+1th layer metal wire, can be equivalent to the current flowing through all the vias.

[0053] Step S102: Test the first potential on the M-th metal line by connecting the test pad to the second end in the length direction of the M-th metal line, or the first end in the width direction of the M-th metal line, or the second end in the width direction of the M-th metal line.

[0054] Step S103: Test the second potential on the M+1 layer metal line by connecting the test pad to the second end in the length direction of the M+1 layer metal line, or the first end in the width direction of the M+1 layer metal line, or the second end in the width direction of the M+1 layer metal line.

[0055] Step S104: Based on the first potential, the second potential, and the current, obtain the resistance of the Mth via, where 1≤M≤N.

[0056] Specifically, (Second Potential - First Potential) / Current = Resistance of the (M-1)th via. That is, a potential meter is used to measure the first potential and the aforementioned second potential, a current meter is used to measure the current, and the difference between the second and first potentials is divided by the current to obtain the resistance of the Mth via. Furthermore, the four-terminal method for resistance measurement does not affect the measurement of solder pads, the metal wires connected to the vias are wide, and their resistance is relatively small compared to the metal via resistance. In addition, the stress migration effect occurs at the interface between the metal via and the metal wires, which can eliminate the influence of solder pad resistance, contact resistance, etc. This solution is based on the four-terminal method for testing via resistance, thus enabling accurate measurement of via resistance.

[0057] This solution enables the testing of via resistance between any two adjacent metal lines in a multilayer metal line, and requires fewer test pads, thus reducing the use of test pads and saving wafer area.

[0058] use Figure 4 The specific method for testing the resistance of the through-hole in the structure shown is as follows:

[0059] A power supply voltage is applied to the test pad 80 connected to the second end of the fourth layer metal line 40 along its length, and a ground voltage, i.e., grounding, is applied to the test pad 80 connected to the second end of the first layer metal line 10 along its length.

[0060] The current is measured on the test pad 80 connected to the first end of the fourth layer metal line 40 in the length direction, or at the test pad 80 connected to the first end of the first layer metal line 10 in the length direction.

[0061] The voltage at the remaining solder pads was measured.

[0062] Therefore, the resistance value of the second via 60 is equal to the quotient of the difference between the voltage measured at the test pad 80 at the second end of the third metal line 30 along its length and the voltage measured at the test pad 80 at the second end of the second metal line 20 along its length, and the current. The resistance testing principle for the remaining vias is the same as that for the second via 60. This allows for the testing of the resistance values ​​of the first via 50, the second via 60, and the third via 70.

[0063] Another typical embodiment of this application provides a method for preparing a test structure, such as... Figure 6 As shown, it includes:

[0064] Step S201: Form a semiconductor structure including N vias and N+1 layers of metal lines, wherein adjacent metal lines are connected through the vias, and N is an integer greater than or equal to 2;

[0065] Step S202: N+3 test pads are formed in the non-device region of the above semiconductor structure, wherein two of the above test pads are respectively connected to the first end of the length direction of each of the two metal lines, and the remaining test pads are connected one-to-one to the second end of the length direction of each metal line, or the first end of the width direction of each metal line, or the second end of the width direction of each metal line.

[0066] In this scheme, the test structure is fabricated by forming a semiconductor structure including N vias and N+1 layers of metal lines, forming N+3 test pads in the non-device area of ​​the semiconductor structure, and setting the positions of the test pads.

[0067] Another typical embodiment of this application provides a semiconductor structure including a device region and a non-device region. The vias and metal lines in the aforementioned via resistance testing structure are located in the device region, and the test pads are located in the non-device region. Since the via resistance testing structure includes N vias, N+1 layers of stacked metal lines, and N+3 test pads, with adjacent metal lines connected by the vias, the resistance of N vias can be measured using N+3 test pads. This means that the via resistance is measured using fewer test pads, saving the number of test pads and further saving wafer area.

[0068] Another typical embodiment of this application provides a testing system including the aforementioned via resistance testing structure, a current meter, and a potential meter. The via resistance testing structure is used to test the resistance of vias, the current meter is used to test the current flowing through each via, and the potential meter is used to test the potential of each metal line layer. Since the via resistance testing structure includes N vias, N+1 layers of stacked metal lines, and N+3 test pads, with adjacent metal lines connected through the vias, the resistance of N vias can be measured using N+3 test pads. This means that the via resistance is measured using fewer test pads, saving the number of test pads and further saving wafer area.

[0069] Specifically, in the fabrication of semiconductor devices, during the formation of metal lines and vias, a low-k dielectric material is etched to form trenches and via openings. The etching of the low-k dielectric material may include forming a metal hard mask over the low-k dielectric material, and using a patterned metal hard mask as an etching mask to form the trenches. The via openings are also formed and are self-aligned with the trenches. The trenches and via openings are then filled with a metal material, including copper. Chemical mechanical polishing is then performed to remove excess metal material over the low-k dielectric material. The remaining metal material forms the metal lines and vias.

[0070] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0071] 1) The via resistance test structure of this application includes N vias, N+1 layers of stacked metal lines and N+3 test pads. The adjacent two layers of the above-mentioned metal lines are connected through the above-mentioned vias. The resistance of N vias is measured by using N+3 test pads. That is, the via resistance is measured by using fewer test pads, which saves the number of test pads and further saves wafer area.

[0072] 2) The method for testing via resistance in this application can test the via resistance between any two adjacent metal lines in a multilayer metal line, and requires fewer test pads, thus reducing the use of test pads and saving wafer area.

[0073] 3) The method for fabricating the test structure of this application is to fabricate the test structure by forming a semiconductor structure including N through holes and N+1 layers of metal lines, forming N+3 test pads in the non-device area of ​​the semiconductor structure, and setting the positions of the test pads.

[0074] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A through-hole resistance testing structure, characterized in that, include: N through holes; N+1 layers of stacked metal wires, with adjacent layers of metal wires connected by the through hole, and one through hole connecting adjacent layers of metal wires; There are N+3 test pads, wherein two of the test pads are respectively connected to the first end of the length direction of each of the two metal wires and are respectively used to electrically connect to a current tester, and the remaining test pads are connected one-to-one to the second end of the length direction of each metal wire, or the first end of the width direction of each metal wire, or the second end of the width direction of each metal wire, and the remaining test pads are used to electrically connect to a potential tester, wherein N is an integer greater than or equal to 2.

2. The through-hole resistance testing structure according to claim 1, characterized in that, The N+1 layers of stacked metal wires include a first layer of metal wires and an N+1th layer of metal wires located on the outer side. The first end of the first layer of metal wires and the first end of the N+1th layer of metal wires in the length direction are respectively connected to the corresponding test pads, and the two test pads are respectively used for electrical connection with the current tester.

3. The through-hole resistance testing structure according to claim 1, characterized in that, The width of the metal wire is greater than or equal to 0.5 micrometers.

4. The through-hole resistance testing structure according to claim 3, characterized in that, The length of the metal wire is greater than or equal to 20 micrometers.

5. The through-hole resistance testing structure according to any one of claims 1 to 4, characterized in that, The N+1 layers of stacked metal wires are arranged in parallel.

6. The through-hole resistance testing structure according to any one of claims 1 to 4, characterized in that, All of the metal wires and all of the through holes are made of copper.

7. A method for testing the resistance of a via using the test structure described in any one of claims 1 to 6, characterized in that, include: The current flowing through each of the vias is measured by two test pads connected to the first end of the metal wire along its length. The first potential on the M-th metal line is tested by connecting a test pad to the second end in the length direction of the M-th metal line, or the first end in the width direction of the M-th metal line, or the second end in the width direction of the M-th metal line. The second potential on the M+1 layer metal line is tested by connecting a test pad to the second end in the length direction of the M+1 layer metal line, or the first end in the width direction of the M+1 layer metal line, or the second end in the width direction of the M+1 layer metal line. The resistance of the Mth through-hole is obtained based on the first potential, the second potential, and the current, where 1 ≤ M ≤ N.

8. A method for preparing a test structure, characterized in that, include: A semiconductor structure comprising N vias and N+1 layers of metal lines is formed, wherein adjacent layers of metal lines are connected through the vias, and N is an integer greater than or equal to 2; N+3 test pads are formed in the non-device region of the semiconductor structure. Two of the test pads are respectively connected to the first end of the length direction of each of the two metal lines and are respectively used to be electrically connected to a current tester. The remaining test pads are connected one-to-one to the second end of the length direction of each metal line, or the first end of the width direction of each metal line, or the second end of the width direction of each metal line, and are used to be electrically connected to a potential tester.

9. A semiconductor structure, characterized in that, include: The device area and the non-device area, wherein the via and metal line in the via resistance test structure of any one of claims 1 to 6 are located in the device area, and the test pads of any one of claims 1 to 6 are located in the non-device area.

10. A testing system, characterized in that, include: The via resistance test structure, current tester, and potential tester according to any one of claims 1 to 6, wherein the current tester is used to test the current flowing through each of the vias, the potential tester is used to test the potential of each metal wire layer, and the via resistance test structure is used to determine the resistance of the via based on the current and the potential.

Images