Detection substrate, method for manufacturing the same, and flat panel detector

Abstract

The application provides a kind of detecting substrate, its manufacturing method and flat panel detector, belong to photoelectric detection technical field, it can at least partially solve the problem of poor stability of transistor in existing detecting substrate.The application provides a kind of detecting substrate, comprising: substrate, transistor, reading electrode and photoelectric conversion structure are sequentially arranged along the direction away from substrate;The detecting substrate further comprises: oxide layer between the layer where the transistor is located and the layer where the reading electrode is located;Wherein, the orthographic projection of the oxide layer on the substrate at least covers the orthographic projection of the transistor on the substrate;The reading electrode is electrically connected with the transistor, and the orthographic projection of the connecting position on the substrate does not overlap with the orthographic projection of the transistor on the substrate.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of photoelectric detection, and particularly relates to a detection substrate, a manufacturing method thereof and a flat panel detector. BACKGROUND

[0002] X-ray detection technology is widely used in industrial non-destructive testing, container scanning, circuit board inspection, medical treatment, security and the like, and has a broad application prospect. Traditional X-ray imaging technology belongs to analog signal imaging, and has low resolution and poor image quality. X-ray digital imaging technology (Digital Radio Graphy, DR) appeared in the late 1990s, which directly converts X images into digital images by using an X-ray flat panel detector. Since the converted digital images are clear, have high resolution, and are easy to save and transmit, the X-ray digital imaging technology has become a research hotspot at present.

[0003] According to different structures, the X-ray flat panel detector can be divided into a direct conversion type (Direct DR) and an indirect conversion type (Indirect DR). Among them, the indirect conversion type X-ray flat panel detector technology is relatively mature, has relatively low cost, high detective quantum efficiency (DQE), good reliability and the like, and has been widely developed and applied.

[0004] The X-ray flat panel detector mainly includes a thin film transistor (TFT) and a PIN. Under X-ray irradiation, the scintillator layer or the fluorescent layer of the indirect conversion type X-ray flat panel detector converts X-ray photons into visible light, and then the visible light is converted into an electric signal under the action of the PIN. Finally, the electric signal is read by the TFT and output to obtain a display image.

[0005] In the prior art, the TFT contained in the flat panel detector can be an amorphous silicon (a-Si) TFT. However, the a-Si TFT has the disadvantages of low mobility and large inherent size, which leads to low frame rate and low pixel fill rate of the flat panel detector. The oxide TFT represented by amorphous indium gallium zinc oxide (a-IGZO) TFT has the superior performances of high mobility, high transparency, small size, low preparation temperature and low cost, so that the frame rate and the pixel fill rate of the flat panel detector containing the a-IGZO TFT are both high. In the process of manufacturing the flat panel detector containing the a-IGZO TFT, a PIN film layer is generally deposited on the a-IGZO TFT. However, during the deposition of the PIN film layer, hydrogen atoms (H Plasma) diffuse to the channel region of the a-IGZO TFT, which causes poor stability of the a-IGZO TFT, and further affects the performance of the flat panel detector. SUMMARY

[0006] The present application at least partly solves the problem of poor stability of the existing detection substrate transistor, and provides a detection substrate with high transistor stability and high product reliability.

[0007] The technical scheme adopted to solve the technical problem of the present application is a detection substrate, comprising: a substrate, a transistor, a reading electrode and a photoelectric conversion structure arranged in sequence in the direction away from the substrate; the detection substrate further comprises: a first insulating layer, an electrical connection layer and an oxide layer arranged in sequence in the direction away from the substrate between the layer where the transistor is located and the layer where the reading electrode is located; wherein,

[0008] The orthogonal projection of the oxide layer on the substrate covers at least the orthogonal projection of the transistor on the substrate.

[0009] The reading electrode is electrically connected to the transistor, and the connection position has no overlap with the orthogonal projection of the transistor on the substrate.

[0010] Optionally, the detection substrate further comprises: a first insulating layer and an electrical connection layer arranged in sequence in the direction away from the substrate between the layer where the transistor is located and the oxide layer.

[0011] The first insulating layer is provided with a first via hole, and the electrical connection layer is connected to the first electrode of the transistor through the first via hole.

[0012] Optionally, the area where the orthogonal projection of the oxide layer on the substrate is located covers the orthogonal projection of the reading electrode on the substrate.

[0013] The oxide layer has a second via hole, and the reading electrode is connected to the electrical connection layer through the second via hole.

[0014] Further optionally, the number of transistors, reading electrodes and photoelectric conversion structures is multiple.

[0015] The first electrode of each transistor is electrically connected to each photoelectric conversion structure through each reading electrode in a one-to-one correspondence.

[0016] Further optionally, the multiple transistors are uniformly arranged on the detection substrate.

[0017] The distance between the second via hole and the adjacent transistor in each direction is equal.

[0018] Further optionally, the area where each electrically connected transistor and photoelectric conversion structure is located is a pixel area.

[0019] The oxide layers corresponding to the pixel regions are independent of each other.

[0020] Optionally, the photoelectric conversion structure comprises an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer.

[0021] Optionally, the material of the oxide layer comprises an oxide.

[0022] Optionally, the material of the active layer of the transistor comprises indium gallium zinc oxide.

[0023] Another technical solution for solving the technical problem of the present application is a flat panel detector comprising any one of the above detection substrates.

[0024] Another technical solution for solving the technical problem of the present application is a preparation method of a detection substrate, comprising:

[0025] forming a transistor on a substrate

[0026] forming an oxide layer on the substrate on which the transistor is formed, wherein the orthographic projection of the oxide layer on the substrate covers at least the orthographic projection of the transistor on the substrate.

[0027] forming a reading electrode and a photoelectric conversion structure on the substrate; the reading electrode is electrically connected to the transistor, and the orthographic projection of the connection position on the substrate does not overlap with the orthographic projection of the transistor on the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings are used to provide a further understanding of the present application, and constitute a part of the specification, and are used to explain the present application together with the following specific embodiments, but do not constitute a limitation to the present application. In the drawings:

[0029] Figure 1 is an I-V curve of a transistor of an existing detection substrate;

[0030] Figure 2 is an I-V curve of a transistor of a detection substrate of an embodiment of the present application;

[0031] Figure 3 is a schematic diagram of a planar structure of a detection substrate of an embodiment of the present application;

[0032] Figure 4 is a schematic diagram of a cross-sectional structure of a detection substrate of Figure 3 along the line a-a';

[0033] Figure 5 is a schematic diagram of a cross-sectional structure of a detection substrate of Figure 3 along the line b-b';

[0034] Figure 6 A schematic view of forming a transistor in the manufacturing method of the detecting substrate according to an embodiment of the present application;

[0035] Figure 7 A schematic view of forming a first insulating layer in the manufacturing method of the detecting substrate according to an embodiment of the present application;

[0036] Figure 8 A schematic view of forming an electrically connecting layer in the manufacturing method of the detecting substrate according to an embodiment of the present application;

[0037] Figure 9 A schematic view of forming an oxide layer in the manufacturing method of the detecting substrate according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the skilled in the art better understand the technical solutions of the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments. In each of the drawings, the same elements are denoted by similar reference numerals. For the sake of clarity, each part in the drawings is not drawn in proportion. In addition, some well-known parts can not be shown in the drawings. The thickness and shape of each film layer in the drawings do not reflect the true proportion, and the purpose is only to illustrate the content of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0039] Unless otherwise defined, technical terms or scientific terms used herein should be understood as having the common meaning in the field of the present application to which they belong. The use of "first", "second" and similar words in the specification and claims of the present application does not indicate any order, number or importance, but is only used to distinguish different components. "Include" or "contain" and similar words mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "In", "out", "up", "down" and the like are only used to indicate relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] In the present application, two structures "arranged in the same layer" means that the two structures are formed by the same material layer, so they are in the same layer in the stacking relationship, but it does not mean that the distance between them and the substrate is equal, nor does it mean that other layer structures between them and the substrate are completely the same.

[0041] In the present application, the "patterning process" refers to a step of forming a structure with a specific pattern, which can be a photolithography process including one or more steps of forming a material layer, coating photoresist, exposure, development, etching, photoresist stripping, etc. Of course, the "patterning process" can also be an imprinting process, an inkjet printing process, or other processes.

[0042] Many specific details of the present application are described below, such as the structure, material, size, processing process and technology of components, so that the present application can be more clearly understood. However, as those skilled in the art can understand, the present application can be implemented without these specific details.

[0043] Embodiment 1:

[0044] As shown in Figures 1 to 5 The present embodiment provides a detection substrate, comprising: a substrate substrate 1, a transistor 2, a read electrode 4, a photoelectric conversion structure 3 arranged in turn in the direction away from the substrate substrate 1, and an oxide layer 5 between the layer where the transistor 2 is located and the layer where the read electrode 4 is located. Wherein, the orthographic projection of the oxide layer 5 on the substrate substrate 1 at least covers the orthographic projection of the transistor 2 on the substrate substrate 1; the read electrode 4 is connected with the transistor 2, and the orthographic projection of the connection position of the two on the substrate substrate 1 does not overlap with the orthographic projection of the transistor 2 on the substrate substrate 1.

[0045] The orthographic projection of the oxide layer 5 on the substrate substrate 1 at least covers the orthographic projection of the transistor 2 on the substrate substrate 1. Wherein, "cover" means that the upper structure completely blocks the lower structure. That is, in the present embodiment, from the direction of the oxide layer 5 away from the substrate substrate 1, the oxide layer 5 at least completely blocks the transistor 2. The material of the oxide layer 5 is preferably a relatively dense metal oxide material to reduce the downward penetration of hydrogen atoms (H Plasma). Specifically, the metal oxide material can include any material that is easy to combine with hydrogen atoms, such as indium tin oxide, indium zinc oxide, indium gallium zinc oxide, etc., which are not limited here.

[0046] In the detection substrate provided by the present embodiment, by setting the oxide layer covering at least the channel region of the transistor 2 between the layer where the transistor 2 is located and the layer where the read electrode 4 is located, the hydrogen atoms generated in the subsequent deposition process of the photoelectric conversion structure 3 react with the material of the oxide layer 5, so that the hydrogen atoms are consumed by the oxide layer 5, avoiding the hydrogen atoms reaching the channel region of the transistor 2, thereby improving the stability of the transistor 2 and improving the performance of the flat panel detector.

[0047] The photoelectric conversion structure 3 needs to be connected to the transistor 2, and the oxide layer 5 is placed between the photoelectric converter and the transistor 2 to protect the transistor 2. Because the oxide layer 5 has a relatively high resistance, conventionally, a through-hole can be formed in the oxide layer 5 to allow the photoelectric converter to connect directly to the transistor 2 via the read electrode 4. However, in this case, if... Figure 1 As shown, the curve of transistor 2 shows that within the gate 24 (Gate) turn-off region, as the Vgs voltage continues to decrease, the leakage current (I) increases. off The charge will gradually increase, making it impossible to effectively lock in the charge of the PIN photodiode. In this embodiment, the oxide layer 5 completely covers the transistor 2, and no vias are placed in the area of ​​the oxide layer 5 corresponding to the transistor 2. This ensures the protective effect of the oxide layer 5 on the transistor 2 and avoids the hydrogen atoms generated during the deposition of the photoelectric conversion structure 3 from affecting the transistor. Experimental data shows that, as Figure 2 As shown, in the test substrate provided in this embodiment, the curve of transistor 2 is within the gate 24 (Gate) turn-off interval, and with V... gs As the voltage continues to decrease, the leakage current (I) increases. off The flow will be relatively smooth, which can effectively improve the turn-off characteristics of transistor 2 and ensure the product characteristics and reliability of the probe substrate.

[0048] Optionally, this embodiment also includes a first insulating layer 7, an electrical connection layer 6, and an oxide layer 5 disposed between the layer containing the transistor 2 and the oxide layer 5, and sequentially disposed in a direction away from the substrate 1.

[0049] Among them, such as Figure 3 As shown and Figure 7 As shown, a first via 2a is provided on the first insulating layer 7, and the electrical connection layer 6 is connected to the first electrode 21 of the transistor 2 through the first via 2a; the orthographic projection of the oxide layer 5 on the substrate 1 at least covers the orthographic projection of the transistor 2 on the substrate 1; the read electrode 4 is connected to the transistor 2 through the electrical connection layer 6; the orthographic projection of the read electrode 4 at the connection position with the electrical connection layer 6 on the substrate 1 does not overlap with the orthographic projection of the transistor 2 on the substrate 1.

[0050] In other words, in this embodiment, the first electrode 21 of transistor 2 is electrically connected to the photoelectric conversion structure 3 through the electrical connection layer 6 and the readout electrode 4. The active layer 22 of transistor 2 is made of oxide, specifically indium gallium zinc oxide (IGZO). The IGZO active layer 22 has excellent carrier mobility, which can improve the readout rate of the detection data of the probe substrate and realize dynamic real-time detection. The active layer 22 includes a channel region, and contact regions of the first electrode 21 and the second electrode 25 located on both sides of the channel region.

[0051] The first insulating layer 7 can be formed by a single layer of silicon oxide, or a stack of silicon oxide and resin, or a stack of silicon oxide / silicon nitride / silicon oxynitride with resin, so as to effectively avoid the problem of channel region conductorization of the active layer 22 made of IGZO material caused by using a single layer of silicon nitride to form the first insulating layer 7 in the related art.

[0052] The read electrode 4 can be formed of molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, tantalum, tantalum nitride, alloys thereof, combinations thereof, or other suitable materials.

[0053] The photoelectric conversion structure 3 includes an N-type semiconductor layer with N-type impurities, an intrinsic semiconductor layer without impurities, and a P-type semiconductor layer with P-type impurities, which are sequentially stacked on the read electrode 4. Alternatively, the photoelectric conversion structure 3 includes a P-type semiconductor layer with P-type impurities, an intrinsic semiconductor layer without impurities, and an N-type semiconductor layer with N-type impurities, which are sequentially stacked on the read electrode 4. The thickness of the intrinsic semiconductor layer can be greater than the thicknesses of the P-type semiconductor layer and the N-type semiconductor layer. The photoelectric conversion structure 3 can convert a light signal into an electrical signal, and transmit the electrical signal to the transistor 2 through the read electrode 4, and then be converted into an image signal through a data line.

[0054] Preferably, to better avoid the influence of hydrogen atoms on the channel region, the orthographic projection of the oxide layer 5 on the substrate 1 covers the orthographic projection of the read electrode 4 on the substrate 1. The oxide layer 5 has a second via 5a, and the read electrode 4 is connected to the electrical connection layer 6 through the second via 5a. That is, the oxide layer can be arranged to cover the area of the pixel unit where the transistor 2 is located, so as to avoid the hydrogen atoms from reaching the channel region of the transistor 2 through lateral diffusion to the greatest extent. At the same time, by forming the second via 5a on the oxide layer 5, the read electrode can be connected to the electrical connection layer 6 located below the oxide layer 5. In order to enable the oxide layer 5 to cover the area where the transistor 2 is located, the orthographic projection of the second via 5a on the substrate 1 should not overlap with the orthographic projection of the transistor 2 on the substrate 1, so as to ensure the basic protection effect of the oxide layer 5 on the transistor 2.

[0055] Optionally, in the detection substrate provided in this embodiment, there are multiple transistors 2, readout electrodes 4, and photoelectric conversion structures 3; the first electrode 21 of each transistor 2 is electrically connected to each photoelectric conversion structure 3 in a one-to-one correspondence through each readout electrode 4. The correspondingly connected transistors 2, readout electrodes 4, photoelectric conversion structures 3, and the electrical connection layer 6 and oxide layer 5 located between the layer containing transistors 2 and the layer containing readout electrodes 4 constitute a pixel unit. In this embodiment, the detection substrate may also include a source driver, a gate driver 24, a bias voltage generator, data lines, gate lines, bias lines, etc., located on the substrate 1. Among them, the source driver provides a switching signal for the data lines. The gate driver 24 provides a scanning signal for the gate lines; the bias voltage generator provides a bias voltage signal for the bias lines.

[0056] Optionally, in this embodiment, the region where each electrically connected transistor 2 and photoelectric conversion structure 3 are located is a pixel region: the oxide layers corresponding to each pixel region are independent of each other, thereby avoiding crosstalk between pixel signals.

[0057] Further optionally, multiple transistors 2 are uniformly arranged on the probe substrate; the second via 5a is equidistant from adjacent transistors 2 in each direction. Specifically, for example... Figures 4 to 6 As shown, the second via 5a is formed on the oxide layer 5. This means that there is no oxide layer 5 material at the location of the second via 5a, allowing hydrogen atoms to continue penetrating downwards. If the second via is close to the transistor 2, after a brief period of lateral diffusion, it will affect the active layer 22, thus affecting the operating characteristics of the transistor 2. Therefore, the farther the second via 5a is from the transistor 2, the better the protective effect of the oxide layer 5 on the transistor 2. In the probe substrate, there are multiple pixel regions, each with a transistor 2. Besides the transistor 2 of the same pixel unit, there are transistors 2 of other pixel units surrounding the second via 5a. In this embodiment, the second via 5a is located at the center of the region formed by the multiple transistors 2, ensuring that the distance between the second via 5a and the adjacent transistors 2 is equal, thereby maximizing the uniformity of the characteristics of different transistors 2 on the probe substrate. Of course, in practice, the position of the second via 5a may have some deviation, and the distance from each transistor 2 may differ, but the orthogonal projection of the second via 5a on the substrate 1 must not overlap with the orthogonal projection of the transistor 2 on the substrate.

[0058] Optionally, in the embodiment, the detection substrate further comprises a bias voltage electrode 8 (not shown in the figure) above the photoelectric conversion structure 3, the projection of the bias voltage electrode 8 on the substrate 1 and the projection of the reading electrode 4 on the substrate 1 overlap, a storage capacitor can be formed between the bias voltage electrode 8 and the reading electrode 4, and the electrical signal converted by the photoelectric conversion structure 3 can be stored in the storage capacitor. Specifically, the bias voltage electrode 8 can be formed of a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO) to improve light transmission efficiency.

[0059] In addition, the orthographic projection of the bias voltage electrode 8 on the substrate 1 is located within the orthographic projection of the photoelectric conversion structure 3 on the substrate 1, that is, the area of the bias voltage electrode 8 is slightly smaller than the area of the photoelectric conversion structure 3. Optionally, the distance between the edge of the bias voltage electrode 8 and the edge of the photoelectric conversion structure 3 is 0.5 μm to 5 μm, such as 1.0 μm, 1.5 μm, 1.8 μm, 2.0 μm, 2.5 μm, 3.0 μm, etc. By the above arrangement, the non-uniformity of the PIN edge electric field can be reduced.

[0060] Optionally, in the embodiment, the substrate 1 can be a flexible substrate 1, such as a plastic substrate with excellent heat resistance and durability, for example, polyvinyl ether phthalate, polyethylene glycol naphthalate, polycarbonate, polyarylate, polyetherimide, polyether sulfone, or polyimide, etc. It can also be a rigid substrate 1, such as a glass substrate, which is not limited in the embodiment.

[0061] Optionally, in the embodiment, the detection substrate further comprises a bias voltage electrode 8 (not shown in the figure) above the photoelectric conversion structure 3, the projection of the bias voltage electrode 8 on the substrate 1 and the projection of the reading electrode 4 on the substrate 1 overlap, a storage capacitor can be formed between the bias voltage electrode 8 and the reading electrode 4, and the electrical signal converted by the photoelectric conversion structure 3 can be stored in the storage capacitor. Specifically, the bias voltage electrode 8 can be formed of a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO) to improve light transmission efficiency.

[0062] The bias voltage line is located on the side of the layer where the bias voltage electrode 8 is located away from the substrate 1, and has a protective layer 10 (not shown in the figure) on the side of the bias voltage line away from the substrate 1. The bias voltage line runs through the detection area along the data line direction. Optionally, the bias voltage line is located at the center of the two data lines, thereby minimizing the coupling capacitance with the data lines, and also being as far away as possible from the gate 24 of the transistor 2, thereby reducing the coupling capacitance with the gate 24 of the transistor 2. The bias voltage line can be a transparent material such as ITO or IZO, or a metal material such as molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, tantalum, tantalum nitride, an alloy thereof, a combination thereof, or other suitable materials. When a transparent material is used, the bias voltage line located above the photoelectric conversion structure 3 does not block the light, and the fill factor can be effectively improved. At the same time, the bias voltage line can be made by a one-time patterning process together with the ITO of the bonding area, thereby saving the process flow. When a metal material is used, the resistance of the bias voltage line can be effectively reduced, thereby ensuring higher bias voltage consistency in the entire detection area. In order to ensure a high fill factor, the orthogonal projection of the bias voltage line on the substrate 1 and the orthogonal projection of the active layer 22 on the substrate 1 do not overlap. Of course, the orthogonal projection of the bias voltage line on the substrate 1 and the orthogonal projection of the active layer 22 on the substrate 1 can also not overlap, thereby ensuring a high fill factor and saving production costs.

[0063] Optionally, a scintillator layer can also be included on the side of the protective layer 10 away from the substrate 1. The material of the scintillator layer is a material capable of converting X-rays into visible light, such as CsI:Tl, Gd202S:Tb, and the like, and other possible materials such as CsI:Na, CaWO4, CdWO4, CeF3, and the like. The wavelength peak of the visible light converted from X-rays on the scintillator layer is 530nm-580nm, and the spectral range can reach 350nm-700nm. The light has a very short delay effect, and can decay to less than 1% of the X-ray illumination brightness within 1ms after the X-rays disappear.

[0064] Embodiment 2

[0065] The embodiment provides a flat panel detector including any one of the detection substrates provided in Embodiment 1. Since the principle of solving the problem of the flat panel detector is similar to the principle of solving the problem of the above-mentioned detection substrate, the implementation of the flat panel detector provided in the embodiment of the present application can be referred to the implementation of the above-mentioned detection substrate provided in the embodiment of the present application, and the repeated parts will not be described herein.

[0066] Embodiment 3

[0067] As Figures 6 to 9As shown, the embodiment provides a preparation method of a detection substrate, which can be used to prepare any one of the detection substrates provided in Embodiment 1. The preparation method can include the following steps:

[0068] S1, forming a transistor 2 on a substrate substrate 1 in sequence.

[0069] This step specifically includes a patterning process to sequentially prepare a gate metal layer, a gate insulating layer 23, an active layer 22 and a source-drain metal layer on the substrate substrate 1: the gate metal layer includes a gate 24 and a gate line, and the source second electrode 25 metal layer includes a first electrode 21, a second electrode 25 and a data line. Among them, the first electrode 21, the second electrode 25, the gate 24 and the active layer 22 constitute the transistor 2.

[0070] Optionally, after forming the transistor 2, a first insulating layer 7 can also be formed. The first insulating layer 7 has a first via hole 2a in the region where the first electrode 21 is located. The first passivation layer can be a single-layer structure composed of silicon oxide, or a laminated structure composed of silicon oxide / silicon nitride / silicon oxynitride.

[0071] S2, forming an oxide layer 5 on the substrate substrate 1 with the electrically connected layer 6, and the orthogonal projection of the oxide layer 5 on the substrate substrate 1 covers at least the orthogonal projection of the transistor 2 on the substrate substrate 1.

[0072] The oxide layer 5 fully protects the channel region from the left, top and right directions, can combine with hydrogen atoms (H Plasma) in the subsequent process of photoelectric conversion structure 3, and avoids the diffusion of hydrogen atoms to the channel region, which causes the channel region to be conductive and affects the performance stability of the transistor 2.

[0073] Optionally, the oxide layer can cover the entire pixel unit area to better protect the transistor 2. When the oxide layer covers the entire pixel unit area, the oxide layer has a hollow structure (second via hole 5a) in other regions outside the region where the transistor 2 is located, so that the subsequent reading electrode 4 can be connected with the electrically connected layer 6 through the second via hole 5a.

[0074] Optionally, before forming the oxide layer 5, it also includes S3, forming an electrically connected layer 6 on the substrate substrate 1 with the first insulating layer 7, and the electrically connected layer 6 is connected with the first electrode 21 of the transistor 2 through the first via hole 2a.

[0075] The electrically connected layer 6 is electrically connected with the first electrode 21 of the transistor 2 through the first via hole 2a. The material of the electrically connected layer 6 can include molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, tantalum, tantalum nitride, its alloy and combination thereof, or other suitable materials.

[0076] S4, forming the read electrode 4 and the photoelectric conversion structure 3 on the substrate 1; the read electrode 4 is connected with the transistor 2 through the electric connection layer 6; the orthographic projection of the read electrode 4 on the substrate 1 at the connection position with the electric connection layer 6 does not overlap with the orthographic projection of the transistor 2 on the substrate 1.

[0077] Specifically, the photoelectric conversion structure 3 comprises an N-type semiconductor layer with N-type impurities, an intrinsic semiconductor layer without impurities, and a P-type semiconductor layer with P-type impurities, which are sequentially stacked on the read electrode 4; the method for forming the photoelectric conversion structure 3 can refer to the prior art, which is not described here again.

[0078] S5, sequentially forming the second passivation layer, the bias electrode layer and the resin layer 9 on the substrate 1. Specifically, the method for forming the second passivation layer, the bias electrode layer and the resin layer 9 can refer to the related prior art, which is not described here again in this embodiment.

[0079] It should be noted that, in this document, the terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0080] According to the embodiments of the present application as described above, these embodiments do not describe all the details, nor limit the present application to only the specific embodiments described. Obviously, according to the above description, many modifications and changes can be made. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A detection substrate, comprising: A substrate, comprising a transistor, a readout electrode, and a photoelectric conversion structure sequentially disposed along a direction opposite to the substrate; characterized in that the detector substrate further comprises: an oxide layer located between the transistor layer and the readout electrode layer; wherein... The orthogonal projection of the oxide layer on the substrate at least covers the orthogonal projection of the transistor on the substrate; The read electrode is electrically connected to the transistor, and the orthographic projection of the connection position on the substrate does not overlap with the orthographic projection of the transistor on the substrate. The detection substrate further includes: a first insulating layer and an electrical connection layer disposed between the transistor layer and the oxide layer, and sequentially disposed along a direction away from the substrate. A first via is provided on the first insulating layer, and the electrical connection layer is connected to the first electrode of the transistor through the first via; The region where the oxide layer is projected onto the substrate covers the region where the read electrode is projected onto the substrate; The oxide layer has a second via, and the read electrode is connected to the electrical connection layer through the second via.

2. The detection substrate according to claim 1, characterized in that, The number of transistors, readout electrodes, and photoelectric conversion structures are all multiple; The first electrode of each transistor is electrically connected to each photoelectric conversion structure in a one-to-one correspondence through each readout electrode.

3. The detection substrate according to claim 2, characterized in that, The transistors are evenly arranged on the probe substrate; The second via is equidistant from the transistors adjacent to it in each direction.

4. The detection substrate according to claim 2, characterized in that, Each electrically connected transistor and the area where the photoelectric conversion structure is located constitutes a pixel area: The oxide layers corresponding to each pixel region are independent of each other.

5. The detection substrate according to any one of claims 1 to 4, characterized in that, The photoelectric conversion structure includes: an N-type semiconductor layer, an intrinsic semiconductor layer, and a P-type semiconductor layer.

6. The detection substrate according to any one of claims 1 to 4, characterized in that, The oxide layer is made of metal oxides.

7. The detection substrate according to claim 1, characterized in that, The active layer of the transistor is made of indium gallium zinc oxide.

8. A flat panel detector, characterized in that, Includes the probe substrate as described in any one of claims 1 to 7.

9. A method for preparing a probe substrate, wherein the probe substrate is as described in any one of claims 1 to 7, characterized in that, The preparation method includes: Transistors are sequentially formed on a substrate. An oxide layer is formed on a substrate on which the transistor is formed, wherein the orthogonal projection of the oxide layer on the substrate at least covers the orthogonal projection of the transistor on the substrate; A readout electrode and a photoelectric conversion structure are formed on the substrate; the readout electrode is electrically connected to the transistor, and the orthographic projection of the connection position on the substrate does not overlap with the orthographic projection of the transistor on the substrate; Before forming the oxide layer, the process also includes: On the side of the transistor layer facing away from the substrate, a first insulating layer and an electrical connection layer are formed sequentially; and a first via is formed on the first insulating layer so that the electrical connection layer is connected to the first electrode of the transistor through the first via. The region where the oxide layer is projected onto the substrate covers the region where the read electrode is projected onto the substrate; After forming the oxide layer, the process further includes: A second via is formed in the oxide layer, through which the read electrode is connected to the electrical connection layer.

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