Methods, devices, equipment, media, and flat panel detectors for adjusting data port phase deviation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- IRAY TECHNOLOGY CO LTD
- Filing Date
- 2025-12-19
- Publication Date
- 2026-05-26
Smart Images
Figure CN122086196A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technology, and in particular to a method, apparatus, device, medium, and flat panel detector for adjusting the phase deviation of a data port. Background Technology
[0002] Data port phase deviation refers to the misalignment or asynchrony between the data signal and the corresponding clock reference signal in the transmission timing. Due to factors such as hardware design, manufacturing precision, or temperature and voltage fluctuations, the edges of the data signal may not remain stable precisely within the effective sampling window of the clock; this timing deviation is called phase deviation. Excessive deviation can directly cause the system to violate the setup or hold time timing requirements during sampling, resulting in data reading errors, and consequently leading to serious consequences such as degraded system performance, increased communication error rate, or even functional failure.
[0003] Therefore, it is necessary to adjust the phase deviation of the data port to ensure precise alignment between the data signal and the clock sampling edge, thereby ensuring stable and reliable data acquisition even under harsh operating conditions and guaranteeing the robust operation of the entire system. Thus, how to adjust the phase deviation of the data port is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] This application provides a method, apparatus, device, medium, and flat panel detector for adjusting the phase deviation of a data port, to solve the technical problem of how to adjust the phase deviation of a data port.
[0005] The first aspect of this application provides a method for adjusting the phase deviation of a data port, the method comprising:
[0006] Identify the target device and configure multiple adjustment parameters for the target device;
[0007] The multiple adjustment parameters are traversed to obtain the collected data output by the target device based on each adjustment parameter;
[0008] Obtain the channel signal value and / or channel bit error rate of all readout channels in each of the acquired data under each of the adjustment parameters, so as to determine the corresponding timing alignment candidate parameter for the readout channel based on the channel signal value and / or the channel bit error rate among all the adjustment parameters;
[0009] Timing alignment parameters are obtained based on the candidate timing alignment parameters, and the timing alignment parameters are configured to the corresponding readout channels to adjust the data port phase deviation of the target device.
[0010] In some embodiments of the first aspect of this application, determining the corresponding timing alignment candidate parameter for the readout channel based on the channel signal value among all the adjustment parameters includes:
[0011] Determine whether the channel signal value of each readout channel is normal under each adjustment parameter, and determine the adjustment parameter corresponding to the normal channel signal value as the timing alignment candidate parameter of the corresponding readout channel; wherein, when the channel signal value is within a preset signal range, the channel signal value is determined to be normal.
[0012] In some embodiments of the first aspect of this application, determining the corresponding timing alignment candidate parameter for the readout channel based on the channel bit error rate among all the adjustment parameters includes:
[0013] The standard channel bit error rate is determined based on the channel bit error rate of each readout channel under each adjustment parameter.
[0014] The adjustment parameter corresponding to the standard channel bit error rate is determined as the timing alignment candidate parameter of the corresponding readout channel; wherein, the channel bit error rate within the standard bit error rate range is the standard channel bit error rate.
[0015] In some embodiments of the first aspect of this application, obtaining timing alignment parameters based on the timing alignment candidate parameters includes:
[0016] The maximum allowable delay time is obtained based on the step time of the aforementioned timing alignment candidate parameters;
[0017] The median value of the maximum allowable delay time is taken as the optimal time margin;
[0018] The timing alignment parameters are obtained based on the step time of the candidate timing alignment parameters and the optimal time margin.
[0019] In some embodiments of the first aspect of this application, the method further includes: storing the timing alignment parameters configured for the readout channel to generate historical data of the timing alignment parameters of the readout channel.
[0020] In some embodiments of the first aspect of this application, the target device includes an X-ray flat panel detector.
[0021] A second aspect of this application provides a data port phase deviation adjustment device, the device comprising:
[0022] The parameter module is configured to determine a target device and configure multiple adjustment parameters for the target device.
[0023] The traversal module is configured to traverse multiple of the adjustment parameters to obtain the acquisition data output by the target device based on each of the adjustment parameters;
[0024] The candidate parameter module is configured to acquire the channel signal value and / or channel bit error rate of all readout channels in each of the acquired data under each of the adjustment parameters, so as to determine the timing alignment candidate parameters for the readout channels based on the channel signal value and / or the channel bit error rate among all the adjustment parameters;
[0025] The adjustment module is configured to obtain timing alignment parameters based on the timing alignment candidate parameters, and configure the timing alignment parameters to the corresponding readout channel to adjust the data port phase deviation of the target device.
[0026] A third aspect of this application provides a flat panel detector, including a field-programmable gate array (FPGA); the FPGA is configured to:
[0027] Configure multiple adjustment parameters;
[0028] Iterate through multiple adjustment parameters to obtain the collected data output based on each adjustment parameter;
[0029] Obtain the channel signal value and / or channel bit error rate of all readout channels in each of the acquired data under each of the adjustment parameters, so as to determine the corresponding timing alignment candidate parameter for the readout channel based on the channel signal value and / or the channel bit error rate among all the adjustment parameters;
[0030] Timing alignment parameters are obtained based on the candidate timing alignment parameters, and the timing alignment parameters are configured to the corresponding readout channels to adjust the data port phase deviation.
[0031] A fourth aspect of this application provides an electronic device, the electronic device comprising: a memory and a processor;
[0032] The memory is configured to store computer programs;
[0033] The processor is configured to execute a computer program stored in the memory to cause the electronic device to perform the method as described in any one of the first aspects.
[0034] The fifth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described in any one of the first aspects.
[0035] As described above, this application provides a method, apparatus, device, medium, and flat panel detector for adjusting the phase deviation of a data port, which has the following beneficial effects:
[0036] First, this application effectively adjusts the data port phase deviation, ensuring data and clock timing alignment, thus enabling accurate data acquisition and providing technical and cost guarantees for the effective application of various devices. Second, this application supports the effective configuration of timing alignment parameters for each readout channel of the acquired data, catering to different user groups and usage scenarios. This ensures the normal operation of each channel while maximizing time margin, thereby improving adaptability to various environments. Third, this application provides historical data storage functionality, enabling effective adaptive configuration, supporting multiple application scenarios, and offering simple operation. Finally, based on these features, this application provides a flat panel detector that adaptively configures timing alignment parameters, especially automatically during detector power-on or self-test processes, effectively avoiding image channel anomalies caused by data port phase deviation due to temperature and other abnormalities. Attached Figure Description
[0037] Figure 1 The diagram shown illustrates the data port phase deviation provided in an embodiment of this application.
[0038] Figure 2 The diagram shown is a flowchart illustrating the method for adjusting the phase deviation of a data port provided in an embodiment of this application.
[0039] Figure 3 The diagram shown is a data flow chart of an X-ray flat panel detector provided in an embodiment of this application.
[0040] Figure 4 The diagram shows a flowchart of obtaining timing alignment parameters based on candidate timing alignment parameters, as provided in an embodiment of this application.
[0041] Figure 5 The diagram shown is a structural schematic of a data port phase deviation adjustment device provided in an embodiment of this application.
[0042] Figure 6 The diagram shown is an application schematic of the data port phase deviation adjustment device provided in the embodiments of this application.
[0043] Figure 7 shows a schematic diagram comparing the effects of adjusting the data port phase deviation of the flat panel detector provided in the embodiment of this application.
[0044] Figures 8a to 8c The diagrams show the effects of the flat panel detector provided in this application after adjustment in low temperature, high temperature, and power-on / off scenarios.
[0045] Figure 9 The diagram shown is a structural schematic of the electronic device provided in an embodiment of this application. Detailed Implementation
[0046] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.
[0047] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0048] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.
[0049] Before providing a further detailed description of this application, the nouns and terms used in the embodiments of this application are explained, and the nouns and terms used in the embodiments of this application shall be interpreted as follows:
[0050] X-ray flat panel detector: a solid-state electronic device that directly converts X-ray energy into digital images.
[0051] CMOS image sensor: A chip that uses complementary metal-oxide-semiconductor technology to convert optical images into electronic signals.
[0052] IO Delay: An automated process in digital chip design (especially FPGA and high-speed interface design) used to find and set the optimal timing window for data sampling of input / output pins to ensure that data is read stably and reliably.
[0053] Wafer: A silicon wafer used to fabricate silicon semiconductor circuits. It can integrate multiple ADCs to process weak analog signals representing image information generated by the sensing units of a flat panel detector (such as a photodiode array), and convert these signals in parallel and at high speed into digital signals that can be processed later.
[0054] ADC: Analog-to-Digital Converter, which can be used as a readout channel to convert analog signals into digital signals for output.
[0055] FPGA: Field Programmable Gate Array, is a semi-custom integrated circuit whose hardware logic functions can still be redefined by the user through programming after manufacturing.
[0056] PCBA: Printed Circuit Board Assembly, refers to the entire process and final product of mounting and soldering various electronic components (chips, resistors, capacitors, connectors, etc.) onto an empty PCB.
[0057] Due to factors such as hardware design, manufacturing precision, or temperature and voltage fluctuations, the edges of data signals may not remain precisely stable within the effective sampling window of the clock, resulting in phase deviations at the data port, such as... Figure 1 As shown. For example, for large-size, multi-panel flat panel detectors, due to hardware design, manufacturing process, individual differences, or different temperatures and application scenarios, the clock and data at the detector's data port may experience relative delays, leading to abnormal data acquisition. This manifests as channel anomalies in the image, causing the detector to malfunction and resulting in numerous losses.
[0058] To at least solve the above-mentioned technical problems, this application provides a method, apparatus, device, medium, and flat panel detector for adjusting the phase deviation of the data port, which can effectively adjust the phase deviation of the data port, ensure data and clock timing alignment, and enable the device to collect data accurately, providing technical and cost guarantees for the effective application of various devices.
[0059] Figure 2 The diagram shows a flowchart illustrating the method for adjusting the phase deviation of a data port provided in an embodiment of this application. Figure 2 As shown, the data port phase deviation adjustment method provided in this application embodiment includes steps S1 to S4.
[0060] S1. Identify the target device and configure multiple adjustment parameters for it.
[0061] In some embodiments, the target device may be identified as an X-ray flat panel detector, and multiple adjustment parameters may be configured for the X-ray flat panel detector. Figure 3 The diagram shown is a data flow chart of an X-ray flat panel detector provided in an embodiment of this application. Figure 3As shown, an X-ray flat panel detector uses X-rays to irradiate the object being inspected, forming an X-ray image. An X-ray conversion layer (e.g., cesium iodide) inside the detector converts the invisible X-ray photons into visible light, which then illuminates the underlying sensing unit (e.g., a photodiode array). This converts the optical signal of each pixel into an electrical signal, which is an analog signal for each pixel. Finally, multiple ADCs integrated on the wafer convert these analog signals in parallel and at high speed into digital signals suitable for subsequent processing.
[0062] Furthermore, the raw digital signal output by the ADC enters the Read PCBA. It typically integrates signal conditioning circuitry and a multiplexer, responsible for receiving data from multiple ADCs, synchronizing and integrating them to form a digital image, and possibly performing basic noise reduction processing. Subsequently, the data is sent to the Core PCBA. The FPGA on the Core PCBA executes high-speed image correction algorithms, such as offset correction, gain correction, and bad pixel repair, and compresses or reformats the image data before transmitting it to the computer via a high-speed interface.
[0063] Therefore, in some embodiments, multiple different adjustment parameters are configured for all wafers and FPGAs in the X-ray flat panel detector to adjust the data deviations that may be generated by the data ports of the wafers and FPGAs respectively, so as to ensure that there are no channel anomalies in the digital image.
[0064] Furthermore, the step time for multiple adjustment parameters can be customized to effectively reduce the number of searches and calculations, thereby improving adjustment efficiency.
[0065] S2. Iterate through multiple adjustment parameters to obtain the collected data output by the target device based on each adjustment parameter.
[0066] In some embodiments, multiple adjustment parameters are traversed to acquire the collected data output by the target device under the corresponding adjustment parameter settings. Taking the X-ray flat panel detector mentioned above as an example, 32 adjustment parameters (values 0-31) are configured for the FPGA, and 8 adjustment parameters (values 32-39) are configured for the Wafer. The delay of the corresponding data signal relative to the clock signal is then configured sequentially according to the values of the adjustment parameters. After each configuration, a reset is performed, and then the corresponding image data is acquired, resulting in 40 images, each corresponding to one of the 40 adjustment parameters.
[0067] S3. Obtain the channel signal value and / or channel bit error rate of all readout channels in each acquired data under each adjustment parameter, and determine the corresponding timing alignment candidate parameter for the readout channel based on the channel signal value and / or channel bit error rate among all adjustment parameters.
[0068] In some embodiments, determining the corresponding timing alignment candidate parameter for the readout channel based on the channel signal value among all adjustment parameters includes: determining whether the channel signal value of each readout channel is normal under each adjustment parameter, and determining the adjustment parameter corresponding to the normal channel signal value as the timing alignment candidate parameter for the corresponding readout channel. Wherein, when the channel signal value is within a preset signal range, the channel signal value is determined to be normal.
[0069] Taking a large-size, multi-layered CMOS detector as an example, assuming the CMOS detector is composed of M wafers, and each wafer has N ADCs (i.e., N readout channels), the image data acquired by the CMOS detector should have a total of Q (Q = N*M) readout channels. It is necessary to configure optimal timing alignment parameters for each of the Q readout channels to ensure normal channel operation and form a final high-quality digital image. In the above embodiment with 40 images, the channel signal values of the Q readout channels in each image are obtained under 40 adjustment parameters, that is, the channel signal values corresponding to the Qth readout channel under the adjustment of the 40 parameters are obtained. Then, it is determined whether the channel signal value of the Qth readout channel under the Kth adjustment parameter is normal. If so, the Kth adjustment parameter is determined as a candidate timing alignment parameter for the Qth readout channel.
[0070] Furthermore, the channel signal value of the Qth channel in the image can be determined by methods such as variance and grayscale value. This application does not impose any restrictions on this.
[0071] Taking the Qth readout channel as an example, with the adjustment parameter set to IO delay, the normal channel signal value of the Qth readout channel is shown in Table 1.
[0072] Table 1 shows the normal conditions of the channel signal values for the Qth readout channel.
[0073]
[0074] Where 0-31 represent the FPGA's IO delay values, and 32-39 represent the Wafer's IO delay values. When the channel signal value of the Qth read channel is normal at a certain IO delay value, it indicates that the Qth read channel is normal, meaning that this IO delay value is a candidate parameter for timing alignment of the Qth read channel. For example, as shown in Table 1, if the Qth read channel is normal at IO delay values 1-8, 15-16, and 29-33, then these IO delay values are candidate parameters for timing alignment of the Qth read channel. In other embodiments, determining the corresponding timing alignment candidate parameter for the readout channel based on the channel bit error rate among all adjustment parameters includes: determining the standard channel bit error rate based on the channel bit error rate of each readout channel under each adjustment parameter; determining the adjustment parameter corresponding to the standard channel bit error rate as the timing alignment candidate parameter for the corresponding readout channel; wherein, the channel bit error rate within the range of the standard bit error rate is the standard channel bit error rate.
[0075] In the above embodiment of 40 images, the channel bit error rate (BER) of Q readout channels in each image under 40 adjustment parameters is obtained using known alignment codes. That is, the BER of the Qth readout channel under each of the 40 adjustment parameters is obtained. When the BER of the Qth readout channel under the Kth adjustment parameter is within the standard BER range, it is considered that the BER of the Qth readout channel under the Kth adjustment parameter is the standard channel BER. In this case, the Kth adjustment parameter is used as a candidate timing alignment parameter for the Qth readout channel.
[0076] The standard bit error rate range can be customized, and this application does not impose any restrictions.
[0077] S4. Obtain timing alignment parameters based on timing alignment candidate parameters, and configure the timing alignment parameters to the corresponding readout channels to adjust the phase deviation of the data port of the target device.
[0078] Figure 4 The diagram shows a flowchart illustrating the process of obtaining timing alignment parameters based on candidate timing alignment parameters, as provided in an embodiment of this application. Figure 4 As shown, obtaining the timing alignment parameters based on the timing alignment candidate parameters includes steps S41 to S43.
[0079] S41. Obtain the maximum allowable delay time based on the step time of the timing alignment candidate parameters.
[0080] S42. Use the median of the maximum allowable delay time as the optimal time margin.
[0081] S43. Obtain timing alignment parameters based on the step time and optimal time margin of the timing alignment candidate parameters.
[0082] It should be noted that this application sets a threshold for the allowable delay time. Only when the delay time corresponding to the timing alignment candidate parameter of a continuously normal read channel meets the threshold, or when the delay time corresponding to the timing alignment candidate parameter of a certain normal read channel meets the threshold, can it be used as the allowable delay time, and the optimal time margin can be obtained based on this. If no delay time meets the threshold, an error will be reported, prompting the need to replace the core board or wafer, etc.
[0083] Taking Table 1 above as an example, when the timing alignment candidate parameter is the parameter configured by the FPGA, the step time is n1 (50ps); when the timing alignment candidate parameter is the parameter configured by the Wafer, the step time is n2 (150ps), and the threshold for the allowed delay time is 150ps. In this case, the delay time corresponding to the 1st-8th IO delay values is n1*7 = 350ps. Similarly, the delay time corresponding to the 15th-16th IO delay values is n1*2 = 100ps; the delay time corresponding to the 29th-33rd IO delay values is n1*2 + n2*2 = 400ps. Therefore, the delay time corresponding to the 15th-16th IO delay values does not meet the 150ps requirement and cannot be used as the allowed delay time in subsequent calculations.
[0084] Furthermore, the allowable delay time is 350ps corresponding to the 1st to 8th IO delay values, and 400ps corresponding to the 29th to 33rd IO delay values. Therefore, the maximum allowable time should be 400ps.
[0085] Furthermore, by using the median of the maximum allowable time as the optimal time margin, the Qth channel remains in a normal state within this optimal time margin. That is, the optimal time margin is 200ps. Based on the step time of the 29th-33rd IO delay values and the optimal time margin, the 200ps following the 29th IO delay value is determined to be closest to the 32nd IO delay value. Therefore, the 32nd IO delay value is the timing alignment parameter. In other words, this application uses the median of the configuration values of the normal channel under the maximum allowable delay time as the optimal time margin to obtain the timing alignment parameter, thereby increasing adaptability.
[0086] In some embodiments, the timing alignment parameters configured for the read channel can also be stored to generate historical data of the timing alignment parameters of the read channel, so as to quickly configure the timing alignment parameters in the application.
[0087] It should be noted that the protection scope of the data port phase deviation adjustment method provided in this application embodiment is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting or replacing steps in the prior art based on the principle of this application is included in the protection scope of this application.
[0088] Figure 5 The diagram shown is a structural schematic of a data port phase deviation adjustment device provided in an embodiment of this application. Figure 5 As shown, the data port phase deviation adjustment device 1 of this application includes a parameter module 10, a traversal module 20, a candidate parameter module 30, and an adjustment module 40.
[0089] Parameter module 10 is configured to determine the target device and configure multiple adjustment parameters for the target device;
[0090] Traversal module 20 is configured to traverse multiple adjustment parameters to obtain the acquisition data output by the target device based on each adjustment parameter;
[0091] The candidate parameter module 30 is configured to acquire the channel signal value and / or channel bit error rate of all readout channels in each acquired data under each adjustment parameter, so as to determine the timing alignment candidate parameters for the readout channels based on the channel signal value and / or channel bit error rate among all adjustment parameters;
[0092] The adjustment module 40 is configured to obtain timing alignment parameters based on the timing alignment candidate parameters and configure the timing alignment parameters to the corresponding readout channel in order to adjust the phase deviation of the data port of the target device.
[0093] It should be noted that the principles of the parameter module 10, traversal module 20, candidate parameter module 30 and adjustment module 40 provided in the embodiments of this application correspond one-to-one with the steps in the above method, so they will not be repeated here.
[0094] In some embodiments, the data port phase deviation adjustment device can be implemented in hardware and interact with the flat panel detector via a hardware protocol interface. For example... Figure 6 As shown, the data port phase deviation adjustment device 1 is connected to the flat panel detector 2 and is configured with multiple adjustment parameters to obtain the corresponding image output by the flat panel detector 2 under each adjustment parameter, i.e., the acquired data. Then, the data port phase deviation adjustment device 1 can obtain the channel signal values and / or channel bit error rates of all readout channels in each acquired data under each adjustment parameter, use this to determine candidate timing alignment parameters for the readout channels, and then obtain the timing alignment parameters based on these parameters and write them into the flat panel detector 2 to adjust the data port phase deviation of the flat panel detector 2.
[0095] This application also provides a flat panel detector, which includes a field-programmable gate array (FPGA); the FPGA is configured to:
[0096] Configure multiple adjustment parameters;
[0097] Iterate through multiple adjustment parameters to obtain the collected data output based on each adjustment parameter;
[0098] Obtain the channel signal value and / or channel bit error rate of all readout channels in each acquired data under each adjustment parameter, so as to determine the corresponding timing alignment candidate parameter for the readout channel based on the channel signal value and / or channel bit error rate among all adjustment parameters;
[0099] Timing alignment parameters are obtained based on candidate timing alignment parameters, and then configured to the corresponding readout channels to adjust the phase deviation of the data port.
[0100] In some embodiments, please refer to Figure 3 The X-ray flat panel detector shown controls the FPGA and wafer via a Core PCBA. The FPGA firmware allows for the configuration of different adjustment parameters for the FPGA and wafer, as well as initial image acquisition. Subsequently, the flat panel detector transmits the acquired output images to the PC via the detector network interface. The PC calculates the channel signal values and / or channel bit error rates for all readout channels in each image under various adjustment parameters and returns this information to the FPGA in the Core PCBA within the flat panel detector. The FPGA then determines the corresponding timing alignment candidate parameters for each readout channel based on the channel signal values and / or channel bit error rates among all adjustment parameters, and obtains the timing alignment parameters based on these candidate parameters to adjust the data port phase deviation.
[0101] Furthermore, the above adjustment process can be completed automatically during detector power-on or self-test, which can effectively avoid image channel abnormalities caused by data port phase deviation due to temperature and other anomalies. It can also minimize image abnormalities and cost losses caused by environmental changes, detector temperature changes, firmware upgrades and downgrades, detector power-on and power-off, and other factors.
[0102] Figure 7 shows a schematic diagram comparing the effects of adjusting the data port phase deviation of the flat panel detector provided in the embodiment of this application. Figures 8a to 8c The diagrams show the effects of the flat panel detector provided in this application after adjustment in low temperature, high temperature, and power-on / off scenarios.
[0103] Therefore, this application can effectively adjust the data port phase deviation, ensuring data and clock timing alignment, thus enabling accurate data acquisition and providing technical and cost guarantees for the effective application of various devices. Secondly, this application supports the effective configuration of timing alignment parameters for each readout channel of the acquired data, catering to different user groups and usage scenarios. While ensuring the normal operation of each channel, it also provides maximum time margin, improving adaptability to various environments. Thirdly, this application provides historical data storage functionality, effectively achieving adaptive configuration, supporting multiple application scenarios, and offering simple operation. Finally, based on these features, this application provides a flat panel detector that can adaptively complete the configuration of timing alignment parameters, especially automatically during detector power-on or self-test processes, effectively avoiding image channel abnormalities caused by data port phase deviation due to temperature and other anomalies.
[0104] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.
[0105] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this application, depending on actual needs. For example, the functional modules / units in the various embodiments of this application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit. Those skilled in the art should further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0106] Figure 9The diagram shown is a structural schematic of the electronic device of this application in one embodiment. For example... Figure 9 As shown, the chip 90 of this application includes one or more memories 901 and one or more processors 902. The memory 901 is configured to store data associated with an image; the processing unit 902 is electrically coupled to the memory 901 and configured to perform the methods described above. In some embodiments, the memory 901 includes various media capable of storing data, such as RAM, memory cards, or optical discs. The processing unit 902 may be a graphics processing unit (GPU), a neural processing unit (NPU), a display processing unit (DPU), a video processing unit (VPU), a digital signal processor (DSP), an image signal processor (ISP), etc.; it may also be an application-specific integrated circuit (ASIC) or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0107] This application also provides a computer-readable storage medium. Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing a processor. The program can be stored in a computer-readable storage medium, which is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disk, and any combination thereof. The storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid-state drive (SSD)).
[0108] This application embodiment may also provide a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in this application embodiment are generated. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.
[0109] When the computer program product is executed by a computer, the computer performs the method described in the foregoing method embodiments. The computer program product can be a software installation package; when the foregoing method is required, the computer program product can be downloaded and executed on the computer.
[0110] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.
[0111] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0112] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.
Claims
1. A method for adjusting the phase deviation of a data port, characterized in that, The method includes: Identify the target device and configure multiple adjustment parameters for the target device; The multiple adjustment parameters are traversed to obtain the collected data output by the target device based on each adjustment parameter; Obtain the channel signal value and / or channel bit error rate of all readout channels in each of the acquired data under each of the adjustment parameters, so as to determine the corresponding timing alignment candidate parameter for the readout channel based on the channel signal value and / or the channel bit error rate among all the adjustment parameters; Timing alignment parameters are obtained based on the candidate timing alignment parameters, and the timing alignment parameters are configured to the corresponding readout channels to adjust the data port phase deviation of the target device.
2. The method for adjusting the phase deviation of the data port according to claim 1, characterized in that, Based on the channel signal value, the corresponding timing alignment candidate parameters for the readout channel among all the adjustment parameters include: Determine whether the channel signal value of each readout channel is normal under each adjustment parameter, and determine the adjustment parameter corresponding to the normal channel signal value as the timing alignment candidate parameter of the corresponding readout channel; wherein, when the channel signal value is within a preset signal range, the channel signal value is determined to be normal.
3. The method for adjusting the phase deviation of the data port according to claim 1, characterized in that, Based on the channel bit error rate, the corresponding timing alignment candidate parameters for the readout channel among all the adjustment parameters include: The standard channel bit error rate is determined based on the channel bit error rate of each readout channel under each adjustment parameter. The adjustment parameter corresponding to the standard channel bit error rate is determined as the timing alignment candidate parameter of the corresponding readout channel; wherein, the channel bit error rate within the standard bit error rate range is the standard channel bit error rate.
4. The method for adjusting the phase deviation of the data port according to claim 1, characterized in that, Obtaining timing alignment parameters based on the candidate timing alignment parameters includes: The maximum allowable delay time is obtained based on the step time of the aforementioned timing alignment candidate parameters; The median value of the maximum allowable delay time is taken as the optimal time margin; The timing alignment parameters are obtained based on the step time of the candidate timing alignment parameters and the optimal time margin.
5. The method for adjusting the phase deviation of the data port according to claim 1, characterized in that, The method further includes: storing the timing alignment parameters configured for the readout channel to generate historical data of the timing alignment parameters of the readout channel.
6. The method for adjusting the phase deviation of the data port according to claim 1, characterized in that, The target device includes an X-ray flat panel detector.
7. A data port phase deviation adjustment device, characterized in that, The device includes: The parameter module is configured to determine a target device and configure multiple adjustment parameters for the target device. The traversal module is configured to traverse multiple of the adjustment parameters to obtain the acquisition data output by the target device based on each of the adjustment parameters; The candidate parameter module is configured to acquire the channel signal value and / or channel bit error rate of all readout channels in each of the acquired data under each of the adjustment parameters, so as to determine the timing alignment candidate parameters for the readout channels based on the channel signal value and / or the channel bit error rate among all the adjustment parameters; The adjustment module is configured to obtain timing alignment parameters based on the timing alignment candidate parameters, and configure the timing alignment parameters to the corresponding readout channel to adjust the data port phase deviation of the target device.
8. A flat panel detector, characterized in that, Includes a field-programmable gate array; the field-programmable gate array is configured to: Configure multiple adjustment parameters; Iterate through multiple adjustment parameters to obtain the collected data output based on each adjustment parameter; Obtain the channel signal value and / or channel bit error rate of all readout channels in each of the acquired data under each of the adjustment parameters, so as to determine the corresponding timing alignment candidate parameter for the readout channel based on the channel signal value and / or the channel bit error rate among all the adjustment parameters; Timing alignment parameters are obtained based on the candidate timing alignment parameters, and the timing alignment parameters are configured to the corresponding readout channels to adjust the data port phase deviation.
9. An electronic device, characterized in that, The electronic device includes: a memory and a processor; The memory is configured to store computer programs; The processor is configured to execute a computer program stored in the memory to cause the electronic device to perform the method of any one of claims 1 to 6.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by an electronic device, it implements the method of any one of claims 1 to 6.