Double-balanced mixer

Abstract

The present invention discloses a double-balanced mixer, comprising: a coupling transformer, first and second diode string circuits, and a first coil assembly. The coupling transformer receives a first input signal and generates at least one set of signals with opposite voltage phases. The first diode string circuit is coupled to the coupling transformer and generates a first node voltage based on a first set of bias voltages. The second diode string circuit is coupled to the coupling transformer and generates a second node voltage based on a second set of bias voltages. The first coil assembly is coupled to the first and second diode string circuits, receives the first and second node voltages and the second input signal, and generates an output signal. The first node voltage is equal to the second node voltage.

Description

Technical Field

[0001] The present invention relates to a communication technology, and in particular to a double-balanced mixer. Background Art

[0002] In fields such as wireless communications and radar, signals need to be up-converted or down-converted to facilitate transmission and processing. Therefore, mixers have become essential components in communication systems.

[0003] A double-balanced mixer (DBM) is a type of mixer. Conventional DBMs typically use Schottky diodes with low forward voltage. However, due to the high cost of Schottky diodes, lower-cost silicon diodes are often used in the communications field. However, current DBMs using silicon diodes require multiple capacitors at the output circuit to block voltage, which increases the size of the DBM and makes it suitable only for certain circuit architectures. Summary of the Invention

[0004] A double-balanced mixer according to the present invention includes a coupling transformer, a first diode string circuit, a second diode string circuit, and a first coil assembly. The coupling transformer receives a first input signal and generates at least one set of signals with opposite voltage phases. The first diode string circuit is coupled to the coupling transformer and receives a first voltage signal and a second voltage signal associated with the at least one set of signals with opposite voltage phases, and a first coil-end signal associated with the second input signal, to generate a first output signal. Furthermore, the first node voltage is generated based on a first set of bias voltages. The second diode string circuit is coupled to the coupling transformer and receives a third voltage signal and a fourth voltage signal associated with the at least one set of signals with opposite voltage phases, and a second coil-end signal associated with the second input signal, to generate a second output signal. Furthermore, the second node voltage is generated based on a second set of bias voltages. The first coil assembly is coupled to the first diode string circuit to receive the first node voltage and to the second diode string circuit to receive the second node voltage. The first coil assembly generates the first and second coil-end signals based on the second input signal and generates an output signal based on the first and second output signals. The first node voltage is equal to the second node voltage.

[0005] In order to make the above features of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 1 is a block diagram of a double-balanced mixer according to an embodiment of the present invention.

[0007] Figure 2FIG. 1 is a circuit diagram of a double-balanced mixer according to a first embodiment of the present invention.

[0008] Figure 3 FIG. 1 is a circuit diagram of a double-balanced mixer according to a second embodiment of the present invention.

[0009] Figure 4 FIG. 1 is a circuit diagram of a double-balanced mixer according to a third embodiment of the present invention.

[0010] Figure 5 A circuit diagram of a double-balanced mixer according to a fourth embodiment of the present invention is shown.

[0011] Figure 6 FIG. 1 is a circuit diagram of a double-balanced mixer according to a fifth embodiment of the present invention.

[0012] Figure 7 A circuit diagram of a double-balanced mixer according to a sixth embodiment of the present invention is shown.

[0013] Figure 8 FIG. 1 is a circuit diagram of a mixer circuit with noise suppression function according to a first embodiment of the present invention.

[0014] Figure 9 FIG. 1 is a circuit diagram of a mixer circuit with noise suppression function according to a second embodiment of the present invention.

[0015] Figure 10 FIG. 1 is a circuit diagram of a mixer circuit with noise suppression function according to a third embodiment of the present invention.

[0016] Main diagrams

[0017] 100:Double balanced mixer

[0018] CT: Coupling transformer

[0019] DC1, DC2: diode string circuit

[0020] IF: output signal

[0021] IF1, IF2: output signal

[0022] LO, RF: input signal

[0023] RF+, RF-: coil end signal

[0024] SS: a group of signals with opposite voltage phases

[0025] TS1: Coil assembly

[0026] V1, V2, V3, V4: voltage signals

[0027] VN1, VN2: node voltage DETAILED DESCRIPTION

[0028] The present invention provides a double-balanced mixer using low-cost diodes. By utilizing dual-path biasing diodes, the sensitivity of the double-balanced mixer can be improved, even when using diodes with higher forward voltages. Furthermore, the double-balanced mixer of the present invention can eliminate capacitors in the output circuit, thereby reducing the area of the double-balanced mixer and making the double-balanced mixer adaptable to various circuit architectures, such as heterodyne and homodyne architectures (also known as zero intermediate frequency (IF) architectures).

[0029] Figure 1 FIG. 1 is a block diagram of a double-balanced mixer according to an embodiment of the present invention. Figure 1 The double-balanced mixer 100 includes a coupling transformer CT, a diode string circuit DC1, a diode string circuit DC2, and a coil assembly TS1. The diode string circuits DC1 and DC2 are coupled to the coupling transformer CT, and the coil assembly TS1 is coupled to the diode string circuits DC1 and DC2.

[0030] In an embodiment of the present invention, a coupling transformer CT receives an input signal LO and generates at least one set of signals SS with opposite voltage phases. A diode string circuit DC1 receives voltage signals V1 and V2 associated with the at least one set of signals SS with opposite voltage phases, and a coil-end signal RF+ associated with the input signal RF, to generate an output signal IF1. The diode string circuit DC2 receives voltage signals V3 and V4 associated with the at least one set of signals SS with opposite voltage phases, and a coil-end signal RF- associated with the input signal RF, to generate an output signal IF2. The diode string circuit DC2 also generates a node voltage VN2 based on a second set of bias voltages. A coil assembly TS1 is coupled to the diode string circuit DC1 to receive the node voltage VN1 and to the diode string circuit DC2 to receive the node voltage VN2. The coil assembly TS1 generates coil-end signals RF+ and RF- based on the input signal RF, and generates an output signal IF based on the output signals IF1 and IF2. The coil-end signals RF+ and RF- have opposite voltage phases. In one embodiment, the input signal LO, the output signal IF, the signal SS, the voltage signals V1, V2, V3, and V4, the input signal RF, and the coil end signals RF+ and RF may be AC signals; the first set of bias voltages, the second set of bias voltages, and the node voltages VN1 and VN2 may be DC voltages. The first set of bias voltages and the second set of bias voltages may be the same or different.

[0031] It is worth noting that, in one embodiment, the node voltage VN1 is equal to the node voltage VN2. Therefore, the double-balanced mixer 100 can omit the need for additional capacitors in the output circuit (e.g., the coil assembly TS1) to block voltage. This reduces the area of the double-balanced mixer 100 and makes the double-balanced mixer 100 applicable to various circuit architectures, particularly a homodyne architecture (also known as a zero-IF architecture).

[0032] In one embodiment, the frequency of the output signal IF is related to the frequency of the input signal LO and the frequency of the input signal RF. For example, the frequency of the output signal IF is equal to the difference or sum of the frequencies of the input signal LO and the input signal RF.

[0033] In one embodiment, the double-balanced mixer 100 may further optionally include a DC blocking circuit CC ( Figure 1 (Not shown in the figure), a DC blocking circuit CC is coupled between the coupling transformer CT and the diode string circuits DC1 and DC2 to block direct current while allowing alternating current to pass, thereby ensuring that the diode string circuits DC1 and DC2 operate in an appropriate bias state. Specifically, the DC blocking circuit CC receives at least one set of signals SS with opposite voltage phases and generates voltage signals V1, V2, V3, and V4.

[0034] Figure 2 FIG1 is a circuit diagram of a double-balanced mixer according to a first embodiment of the present invention. Figure 2 , Figure 2 The double-balanced mixer 200 can be implemented as Figure 1 The detailed circuit structures of the components (coupling transformer CT, diode string circuit DC1, diode string circuit DC2, coil assembly TS1, and DC blocking circuit CC) in the double-balanced mixer 100 and the double-balanced mixer 200 are further discussed herein.

[0035] In an embodiment of the present invention, the coupling transformer CT includes a coil set TS2. The coil set TS2 receives an input signal LO and generates a set of signals SS with opposite voltage phases. Specifically, the set of signals SS with opposite voltage phases includes a positive signal LO+ and a negative signal LO-.

[0036] Specifically, in one embodiment, coil assembly TS2 includes a primary coil H1 and a secondary coil H2. One terminal of primary coil H1 receives an input signal LO, and the other terminal is coupled to a reference voltage. A center tap of secondary coil H2 is coupled to a reference voltage. Coil assembly TS2 generates a positive signal LO+ and a negative signal LO- based on the turns ratio between primary coil H1 and secondary coil H2 (i.e., positive signal LO+ is generated at one terminal of secondary coil H2, and negative signal LO- is generated at the other terminal). In one embodiment, the reference voltage is, for example, a ground potential, although this is not a limitation of the present invention.

[0037] In an embodiment of the present invention, a diode string circuit DC1 includes a terminal T1, a terminal T2, and a node N1. Specifically, terminal T1 receives a high bias voltage VBH1 and a voltage signal V1 associated with a reverse signal LO-, while terminal T2 receives a low bias voltage VBL1 and a voltage signal V2 associated with a forward signal LO+. Node N1 generates a node voltage VN1 based on the high bias voltage VBH1 and the low bias voltage VBL1. Specifically, the diode string circuit DC1 generates a node voltage VN1 based on a first set of bias voltages (high bias voltage VBH1 and low bias voltage VBL1). The node voltage VN1 is equal to half the sum of the low bias voltage VBL1 and the high bias voltage VBH1.

[0038] In one embodiment, diode string circuit DC1 further includes a diode D1 and a diode D2. Diode D1 is coupled between terminal T1 and node N1, with the anode of diode D1 coupled to terminal T1 and the cathode of diode D1 coupled to node N1. Diode D2 is coupled between terminal T2 and node N1, with the cathode of diode D2 coupled to terminal T2 and the anode of diode D2 coupled to node N1. In other words, the first set of bias voltages is used to provide a forward bias to turn on diodes D1 and D2. In one embodiment, diodes D1 and D2 may be silicon diodes or polysilicon diodes, but the present invention is not limited thereto.

[0039] In an embodiment of the present invention, the diode string circuit DC2 includes a terminal T3, a terminal T4, and a node N2. Specifically, the terminal T3 receives a high bias voltage VBH2 and a voltage signal V3 associated with the forward signal LO+, while the terminal T4 receives a low bias voltage VBL2 and a voltage signal V4 associated with the reverse signal LO-. Node N2 generates a node voltage VN2 based on the high bias voltage VBH2 and the low bias voltage VBL2. Specifically, the diode string circuit DC2 generates a node voltage VN2 based on the second set of bias voltages (the high bias voltage VBH2 and the low bias voltage VBL2). The node voltage VN2 is equal to half the sum of the low bias voltage VBL2 and the high bias voltage VBH2.

[0040] In one embodiment, diode string circuit DC2 further includes a diode D3 and a diode D4. Diode D3 is coupled between terminal T3 and node N2, with its anode coupled to terminal T3 and its cathode coupled to node N2. Diode D4 is coupled between terminal T4 and node N2, with its cathode coupled to terminal T4 and its anode coupled to node N2. In other words, the second set of bias voltages is used to provide a forward bias to turn on diodes D3 and D4. In one embodiment, diodes D3 and D4 may be silicon diodes or polysilicon diodes, but the present invention is not limited thereto.

[0041] This section further describes how voltage signals V1 and V4 related to the reverse signal LO-, and voltage signals V2 and V3 related to the forward signal LO+, are generated. In an embodiment of the present invention, a DC block circuit CC includes capacitors C1, C2, C3, and C4. Capacitor C1 receives the forward signal LO+ and generates voltage signal V3, capacitor C2 receives the forward signal LO+ and generates voltage signal V2, capacitor C3 receives the reverse signal LO- and generates voltage signal V1, and capacitor C4 receives the reverse signal LO- and generates voltage signal V4. Specifically, capacitors C1, C2, C3, and C4 block direct current (DC) while allowing alternating current (AC) to pass through.

[0042] In an embodiment of the present invention, coil assembly TS1 includes a primary coil H3 and a secondary coil H4. One terminal of primary coil H3 receives an input signal RF, and the other terminal receives a reference voltage. One terminal of secondary coil H4 receives a node voltage VN1, and the other terminal receives a node voltage VN2. Based on the input signal RF input to primary coil H3, coil assembly TS1 generates a coil-end signal RF+ at one terminal of secondary coil H4 and a coil-end signal RF- at the other terminal of secondary coil H4. Coil assembly TS1 also generates an output signal IF at the center tap of secondary coil H4 based on output signals IF1 and IF2. Diode string circuit DC1 receives voltage signal V1 at terminal T1, voltage signal V2 at terminal T2, and coil-end signal RF+ at node N1 to generate output signal IF1. Diode string circuit DC2 receives voltage signal V3 at terminal T3, voltage signal V4 at terminal T4, and coil-end signal RF- at node N2 to generate output signal IF2. In one embodiment, the reference voltage is, for example, a ground level, but the invention is not limited thereto.

[0043] It is important to note that in one embodiment, high bias voltage VBH1 and low bias voltage VBL1 are input to diode string circuit DC1 via inductor L1 and inductor L2, respectively. In another embodiment, high bias voltage VBH2 and low bias voltage VBL2 are input to diode string circuit DC2 via inductor L3 and inductor L4, respectively. Inductors L1, L2, L3, and L4 are used to block alternating current (AC) while allowing DC to pass. In one embodiment, low bias voltages VBL1 and VBL2 are, for example, ground potential, though this is not a limitation of the present invention.

[0044] In one embodiment, low bias voltage VBL1 is equal to low bias voltage VBL2, and high bias voltage VBH1 is equal to high bias voltage VBH2. In one embodiment, the sum of low bias voltage VBL1 and high bias voltage VBH1 is equal to the sum of low bias voltage VBL2 and high bias voltage VBH2. Therefore, node voltage VN1 is equal to node voltage VN2, allowing diode string circuits DC1 and DC2 to operate in appropriate states (e.g., to prevent leakage current or to operate at symmetrical on-state voltages to reduce noise). This allows the double-balanced mixer 200 to omit the need for voltage blocking capacitors at the output circuit, reducing the area of the double-balanced mixer 200 and making it adaptable to various circuit architectures.

[0045] Figure 3 FIG2 is a circuit diagram of a double-balanced mixer according to a second embodiment of the present invention. Figure 3 , Figure 3 The double-balanced mixer 300 can be implemented as Figure 1 The detailed circuit structures of the components (coupling transformer CT, diode string circuit DC1, diode string circuit DC2, coil assembly TS1, and DC blocking circuit CC) in the double-balanced mixer 100 and the double-balanced mixer 300 are further discussed herein.

[0046] However, it is worth noting that Figure 3 The diode string circuit DC2 and coil group TS1 are the same as Figure 2 Therefore, the following description will focus on the differences (coupling transformer CT, diode string circuit DC1, and DC blocking circuit CC).

[0047] In an embodiment of the present invention, the coupling transformer CT includes a coil set TS2. The coil set TS2 receives an input signal LO and generates a set of signals SS with opposite voltage phases. Specifically, the set of signals SS with opposite voltage phases includes a positive signal LO+ and a negative signal LO-.

[0048] Specifically, in one embodiment, coil assembly TS2 includes a primary coil H1 and a secondary coil H2. One terminal of primary coil H1 receives an input signal LO, and the other terminal is coupled to a reference voltage. The center tap of secondary coil H2 is coupled to a low bias voltage VBL1. Coil assembly TS2 generates a positive signal LO+ and a negative signal LO- based on the turns ratio between primary coil H1 and secondary coil H2 (i.e., positive signal LO+ is generated at one terminal of secondary coil H2, and negative signal LO- is generated at the other terminal). In one embodiment, the reference voltage is, for example, a ground potential, although the present invention is not limited thereto.

[0049] In an embodiment of the present invention, a diode string circuit DC1 includes a terminal T1, a terminal T2, and a node N1. Terminal T1 receives a high bias voltage VBH1 and a voltage signal V1 associated with a reverse signal LO-. Terminal T2 receives a voltage signal V2 associated with a forward signal LO+. Node N1 generates a node voltage VN1 based on the high bias voltage VBH1 and a low bias voltage VBL1. Specifically, voltage signal V2 represents the forward signal LO+. The diode string circuit DC1 generates a node voltage VN1 based on a first set of bias voltages (high bias voltage VBH1 and low bias voltage VBL1). Node voltage VN1 is equal to half the sum of low bias voltage VBL1 and high bias voltage VBH1.

[0050] In one embodiment, diode string circuit DC1 further includes a diode D1 and a diode D2. Diode D1 is coupled between terminal T1 and node N1, with its anode coupled to terminal T1 and its cathode coupled to node N1. Diode D2 is coupled between terminal T2 and node N1, with its cathode coupled to terminal T2 and its anode coupled to node N1. In other words, the first set of bias voltages is used to provide a forward bias to turn on diodes D1 and D2.

[0051] This section further describes how voltage signals V1 and V4 related to the reverse signal LO-, and voltage signal V3 related to the forward signal LO+, are generated. In an embodiment of the present invention, a DC block circuit CC includes capacitors C1, C3, and C4. Capacitor C1 receives the forward signal LO+ and generates voltage signal V3, capacitor C3 receives the reverse signal LO- and generates voltage signal V1, and capacitor C4 receives the reverse signal LO- and generates voltage signal V4. Specifically, capacitors C1, C3, and C4 block direct current (DC) while allowing AC current to pass.

[0052] It should be noted that, in one embodiment, the high bias voltage VBH1 is input to the diode string circuit DC1 via the inductor L1 . The inductor L1 is used to block alternating current and allow direct current to pass.

[0053] In one embodiment, low bias voltage VBL1 is equal to low bias voltage VBL2, and high bias voltage VBH1 is equal to high bias voltage VBH2. In one embodiment, the sum of low bias voltage VBL1 and high bias voltage VBH1 is equal to the sum of low bias voltage VBL2 and high bias voltage VBH2. Consequently, node voltage VN1 is equal to node voltage VN2. This allows the double-balanced mixer 300 to omit the need for voltage blocking capacitors at the output circuit. This reduces the area of the double-balanced mixer 300 and makes the double-balanced mixer 300 adaptable to a variety of circuit architectures.

[0054] Figure 4 FIG. 1 is a circuit diagram of a double-balanced mixer according to a third embodiment of the present invention. Figure 4 , Figure 4 The double-balanced mixer 400 can be implemented as Figure 1 The detailed circuit structures of the components (coupling transformer CT, diode string circuit DC1, diode string circuit DC2, coil assembly TS1, and DC blocking circuit CC) in the double-balanced mixer 100 and the double-balanced mixer 400 are further discussed herein.

[0055] However, it is worth noting that Figure 4 The diode string circuit DC1 is the same as Figure 3 The diode string circuit DC1, Figure 4 The coil set TS1 is the same as Figure 2 Therefore, the following description will focus on the differences (coupling transformer CT, diode string circuit DC2, and DC blocking circuit CC).

[0056] In an embodiment of the present invention, the coupling transformer CT includes a coil set TS2. The coil set TS2 receives an input signal LO and generates a set of signals SS with opposite voltage phases. Specifically, the set of signals SS with opposite voltage phases includes a positive signal LO+ and a negative signal LO-.

[0057] Specifically, in one embodiment, coil assembly TS2 includes a primary coil H1 and a secondary coil H2. One terminal of primary coil H1 receives an input signal LO, and the other terminal is coupled to a reference voltage. Secondary coil H2 includes a first coil and a second coil. One terminal of the first coil receives a low bias voltage VBL1, and one terminal of the second coil receives a low bias voltage VBL2. Coil assembly TS2 generates a positive signal LO+ and a negative signal LO- based on the turns ratio between primary coil H1 and the first and second coils of secondary coil H2 (i.e., the positive signal LO+ is generated at the other terminal of the first coil of secondary coil H2, and the negative signal LO- is generated at the other terminal of the second coil of secondary coil H2).

[0058] In an embodiment of the present invention, the diode string circuit DC2 includes a terminal T3, a terminal T4, and a node N2. Terminal T3 receives a high bias voltage VBH2 and a voltage signal V3 associated with a forward signal LO+. Terminal T4 receives a voltage signal V4 associated with a reverse signal LO-. Node N2 generates a node voltage VN2 based on the high bias voltage VBH2 and the low bias voltage VBL2. Specifically, the voltage signal V4 represents the reverse signal LO-. The diode string circuit DC2 generates a node voltage VN2 based on a second set of bias voltages (the high bias voltage VBH2 and the low bias voltage VBL2). The node voltage VN2 is equal to half the sum of the low bias voltage VBL2 and the high bias voltage VBH2.

[0059] In one embodiment, diode string circuit DC2 further includes diode D3 and diode D4. Diode D3 is coupled between terminal T3 and node N2, with its anode coupled to terminal T3 and its cathode coupled to node N2. Diode D4 is coupled between terminal T4 and node N2, with its cathode coupled to terminal T4 and its anode coupled to node N2. In other words, the second set of bias voltages is used to provide a forward bias to turn on diodes D3 and D4.

[0060] This section further describes how to generate a voltage signal V1 related to the reverse signal LO- and a voltage signal V3 related to the forward signal LO+. In one embodiment of the present invention, a DC block circuit CC includes capacitors C1 and C3. Capacitor C1 receives the forward signal LO+ and generates a voltage signal V3, while capacitor C3 receives the reverse signal LO- and generates a voltage signal V1. Specifically, capacitors C1 and C3 block direct current (DC) while allowing AC current to pass.

[0061] It should be noted that, in one embodiment, the high bias voltage VBH2 is input to the diode string circuit DC2 via the inductor L3 . The inductor L3 is used to block the alternating current and allow the direct current to pass.

[0062] In one embodiment, low bias voltage VBL1 is equal to low bias voltage VBL2, and high bias voltage VBH1 is equal to high bias voltage VBH2. In one embodiment, the sum of low bias voltage VBL1 and high bias voltage VBH1 is equal to the sum of low bias voltage VBL2 and high bias voltage VBH2. Consequently, node voltage VN1 is equal to node voltage VN2. This allows the double-balanced mixer 400 to omit the need for voltage blocking capacitors at the output circuit. This reduces the area of the double-balanced mixer 400 and makes the double-balanced mixer 400 adaptable to a variety of circuit architectures.

[0063] Figure 5 FIG. 4 is a circuit diagram of a double-balanced mixer according to a fourth embodiment of the present invention. Figure 5 , Figure 5 The double-balanced mixer 500 can be implemented as Figure 1 The detailed circuit structures of the components (coupling transformer CT, diode string circuit DC1, diode string circuit DC2, coil assembly TS1, and DC blocking circuit CC) in the double-balanced mixer 100 and the double-balanced mixer 500 are further discussed herein.

[0064] However, it is worth noting that Figure 5 The coil set TS1 is the same as Figure 2 Therefore, the following description will focus on the differences (coupling transformer CT, diode string circuit DC1, diode string circuit DC2, and DC blocking circuit CC).

[0065] In an embodiment of the present invention, the coupling transformer CT includes a coil assembly TS2 and a coil assembly TS3. Coil assembly TS2 receives an input signal LO and generates a set of signals SS with opposite voltage phases, comprising a positive signal LO+ and a negative signal LO-. Coil assembly TS3 receives an input signal LO and generates another set of signals SS with opposite voltage phases, comprising a positive signal LO1+ and a negative signal LO1-.

[0066] Specifically, in one embodiment, coil assembly TS2 includes a primary coil H1 and a secondary coil H2. One terminal of primary coil H1 receives an input signal LO, and the other terminal is coupled to a reference voltage. The center tap of secondary coil H2 is coupled to a high bias voltage VBH1. Coil assembly TS2 generates a positive signal LO+ and a negative signal LO- based on the turns ratio between primary coil H1 and secondary coil H2 (i.e., positive signal LO+ is generated at one terminal of secondary coil H2, and negative signal LO- is generated at the other terminal). In one embodiment, the reference voltage is, for example, a ground potential, although the present invention is not limited thereto.

[0067] Furthermore, in one embodiment, coil assembly TS3 includes a primary coil H5 and a secondary coil H6. One terminal of primary coil H5 receives an input signal LO, and the other terminal is coupled to a reference voltage. A center tap of secondary coil H6 is coupled to a low bias voltage VBL1. Coil assembly TS3 generates a positive signal LO1+ and a negative signal LO1- based on the turns ratio of primary coil H5 to secondary coil H6 (i.e., a positive signal LO1+ is generated at the other terminal of secondary coil H6, and a negative signal LO1- is generated at the other terminal). In one embodiment, the reference voltage is, for example, a ground potential, although the present invention is not limited thereto.

[0068] In an embodiment of the present invention, a diode string circuit DC1 includes a terminal T1, a terminal T2, and a node N1. Terminal T1 receives a voltage signal V1 related to a reverse signal LO-, and terminal T2 receives a voltage signal V2 related to a forward signal LO1+. Node N1 generates a node voltage VN1 based on a high bias voltage VBH1 and a low bias voltage VBL1. Specifically, voltage signal V1 represents the reverse signal LO-, and voltage signal V2 represents the forward signal LO1+. Diode string circuit DC1 generates node voltage VN1 based on a first set of bias voltages (high bias voltage VBH1 and low bias voltage VBL1). Node voltage VN1 is equal to half the sum of low bias voltage VBL1 and high bias voltage VBH1.

[0069] In one embodiment, diode string circuit DC1 further includes a diode D1 and a diode D2. Diode D1 is coupled between terminal T1 and node N1, with its anode coupled to terminal T1 and its cathode coupled to node N1. Diode D2 is coupled between terminal T2 and node N1, with its cathode coupled to terminal T2 and its anode coupled to node N1. In other words, the first set of bias voltages is used to provide a forward bias to turn on diodes D1 and D2.

[0070] In one embodiment of the present invention, diode string circuit DC2 includes terminals T3, T4, and node N2. Terminal T3 receives a high bias voltage VBH2 and a voltage signal V3 associated with a forward signal LO+. Terminal T4 receives a low bias voltage VBL2 and a voltage signal V4 associated with a reverse signal LO1-. Node N2 generates a node voltage VN2 based on the high bias voltage VBH2 and the low bias voltage VBL2. Specifically, diode string circuit DC2 generates a node voltage VN2 based on a second set of bias voltages (high bias voltage VBH2 and low bias voltage VBL2). Node voltage VN2 is equal to half the sum of the low bias voltage VBL2 and the high bias voltage VBH2.

[0071] In one embodiment, diode string circuit DC2 further includes diode D3 and diode D4. Diode D3 is coupled between terminal T3 and node N2, with its anode coupled to terminal T3 and its cathode coupled to node N2. Diode D4 is coupled between terminal T4 and node N2, with its cathode coupled to terminal T4 and its anode coupled to node N2. In other words, the second set of bias voltages is used to provide a forward bias to turn on diodes D3 and D4.

[0072] This section further describes how to generate voltage signal V3 related to the positive signal LO+ and voltage signal V4 related to the negative signal LO1-. In one embodiment of the present invention, DC block circuit CC includes capacitors C1 and C4. Capacitor C1 receives the positive signal LO+ and generates voltage signal V3, while capacitor C4 receives the negative signal LO1- and generates voltage signal V4. Specifically, capacitors C1 and C4 block direct current (DC) while allowing AC current to pass.

[0073] It is important to note that in one embodiment, the high bias voltage VBH2 and the low bias voltage VBL2 are input to the diode string circuit DC2 via inductors L3 and L4, respectively. Inductors L3 and L4 are used to block alternating current (AC) while allowing DC current to pass. In one embodiment, the low bias voltages VBL1 and VBL2 are, for example, ground potentials, although this is not a limitation of the present invention.

[0074] In one embodiment, low bias voltage VBL1 is equal to low bias voltage VBL2, and high bias voltage VBH1 is equal to high bias voltage VBH2. In one embodiment, the sum of low bias voltage VBL1 and high bias voltage VBH1 is equal to the sum of low bias voltage VBL2 and high bias voltage VBH2. Consequently, node voltage VN1 is equal to node voltage VN2. This allows the double-balanced mixer 500 to omit the need for voltage blocking capacitors at the output circuit. This reduces the area of the double-balanced mixer 500 and makes the double-balanced mixer 500 adaptable to a variety of circuit architectures.

[0075] Figure 6 FIG. 5 is a circuit diagram of a double-balanced mixer according to a fifth embodiment of the present invention. Figure 6 , Figure 6 The double-balanced mixer 600 can be implemented as Figure 1 The detailed circuit structures of the components (coupling transformer CT, diode string circuit DC1, diode string circuit DC2, and coil assembly TS1) in the double-balanced mixer 100 and the double-balanced mixer 600 are further discussed herein.

[0076] However, it is worth noting that Figure 6 The coil set TS1 is the same as Figure 2 Therefore, the following description will focus on the differences (coupling transformer CT, diode string circuit DC1, and diode string circuit DC2).

[0077] In an embodiment of the present invention, the coupling transformer CT includes a coil assembly TS2 and a coil assembly TS3. Coil assembly TS2 receives an input signal LO and generates a set of signals SS with opposite voltage phases, comprising a positive signal LO+ and a negative signal LO-. Coil assembly TS3 receives an input signal LO and generates another set of signals SS with opposite voltage phases, comprising a positive signal LO1+ and a negative signal LO1-.

[0078] Specifically, in one embodiment, coil assembly TS2 includes a primary coil H1 and a secondary coil H2. One terminal of primary coil H1 receives an input signal LO, and the other terminal is coupled to a reference voltage. The center tap of secondary coil H2 is coupled to a high bias voltage VBH. Coil assembly TS2 generates a positive signal LO+ and a negative signal LO- based on the turns ratio between primary coil H1 and secondary coil H2 (i.e., positive signal LO+ is generated at one terminal of secondary coil H2, and negative signal LO- is generated at the other terminal). In one embodiment, the reference voltage is, for example, a ground potential, although the present invention is not limited thereto.

[0079] Furthermore, in one embodiment, coil assembly TS3 includes a primary coil H5 and a secondary coil H6. One terminal of primary coil H5 receives an input signal LO, and the other terminal is coupled to a reference voltage. A center tap of secondary coil H6 is coupled to a low bias voltage VBL. Coil assembly TS3 generates a positive signal LO1+ and a negative signal LO1- based on the turns ratio of primary coil H5 to secondary coil H6 (i.e., positive signal LO1+ is generated at one terminal of secondary coil H6, and negative signal LO1- is generated at the other terminal). In one embodiment, the reference voltage is, for example, a ground potential, although the present invention is not limited thereto.

[0080] In an embodiment of the present invention, a diode string circuit DC1 includes a terminal T1, a terminal T2, and a node N1. Terminal T1 receives a voltage signal V1 related to a reverse signal LO-, and terminal T2 receives a voltage signal V2 related to a forward signal LO1+. Node N1 generates a node voltage VN1 based on a high bias voltage VBH and a low bias voltage VBL. Specifically, voltage signal V1 represents the reverse signal LO-, and voltage signal V2 represents the forward signal LO1+. Diode string circuit DC1 generates node voltage VN1 based on a first set of bias voltages (high bias voltage VBH and low bias voltage VBL). Node voltage VN1 is equal to half the sum of low bias voltage VBL and high bias voltage VBH.

[0081] In one embodiment, diode string circuit DC1 further includes a diode D1 and a diode D2. Diode D1 is coupled between terminal T1 and node N1, with its anode coupled to terminal T1 and its cathode coupled to node N1. Diode D2 is coupled between terminal T2 and node N1, with its cathode coupled to terminal T2 and its anode coupled to node N1. In other words, the first set of bias voltages is used to provide a forward bias to turn on diodes D1 and D2.

[0082] In an embodiment of the present invention, diode string circuit DC2 includes a terminal T3, a terminal T4, and a node N2. Terminal T3 receives a voltage signal V3 associated with a forward signal LO+, and terminal T4 receives a voltage signal V4 associated with a reverse signal LO1-. Node N2 generates a node voltage VN2 based on a high bias voltage VBH and a low bias voltage VBL. Specifically, voltage signal V3 represents the forward signal LO+, and voltage signal V4 represents the reverse signal LO1-. Diode string circuit DC2 generates a node voltage VN2 based on a second set of bias voltages (high bias voltage VBH and low bias voltage VBL). Node voltage VN2 is equal to half the sum of low bias voltage VBL and high bias voltage VBH.

[0083] In one embodiment, diode string circuit DC2 further includes diode D3 and diode D4. Diode D3 is coupled between terminal T3 and node N2, with its anode coupled to terminal T3 and its cathode coupled to node N2. Diode D4 is coupled between terminal T4 and node N2, with its cathode coupled to terminal T4 and its anode coupled to node N2. In other words, the second set of bias voltages is used to provide a forward bias to turn on diodes D3 and D4.

[0084] based on Figure 6 In the circuit architecture of the double-balanced mixer 600, since the node voltage VN1 is equal to the node voltage VN2, the double-balanced mixer 600 can omit the capacitor at the output end circuit to block the voltage, thereby reducing the area of the double-balanced mixer 600 and making the double-balanced mixer 600 applicable to various circuit architectures.

[0085] Figure 7 FIG. 5 is a circuit diagram of a double-balanced mixer according to a sixth embodiment of the present invention. Figure 7 , the double-balanced mixer 700 of FIG. can be implemented as Figure 1 The detailed circuit structures of the components (coupling transformer CT, diode string circuit DC1, diode string circuit DC2, and coil assembly TS1) in the double-balanced mixer 100 and the double-balanced mixer 700 are further discussed herein.

[0086] However, it is worth noting that Figure 7The diode string circuit DC1 and the diode string circuit DC2 are the same as Figure 6 The diode string circuit DC1 and the diode string circuit DC2, and Figure 7 The coil set TS1 is the same as Figure 2 Therefore, the following description will focus on the differences (coupling transformer CT).

[0087] In an embodiment of the present invention, a coupling transformer CT includes a coil assembly TS2. The coil assembly TS2 receives an input signal LO and generates a set of signals SS with opposite voltage phases and another set of signals SS with opposite voltage phases. Specifically, the set of signals SS with opposite voltage phases includes a positive signal LO+ and a negative signal LO-, while the other set of signals SS with opposite voltage phases includes a positive signal LO1+ and a negative signal LO1-.

[0088] Specifically, in one embodiment, coil assembly TS2 includes a primary coil H1, a secondary coil H2, and a secondary coil H7. One terminal of primary coil H1 receives an input signal LO, and the other terminal is coupled to a reference voltage. A center tap of secondary coil H2 is coupled to a high bias voltage VBH, and a center tap of secondary coil H7 is coupled to a low bias voltage VBL. Coil assembly TS2 generates a positive signal LO+, a negative signal LO-, a positive signal LO1+, and a negative signal LO1- based on the turns ratio of primary coil H1, secondary coil H2, and secondary coil H7 (i.e., a positive signal LO+ is generated at one terminal of secondary coil H2, and a negative signal LO- is generated at the other terminal; a positive signal LO1+ is generated at one terminal of secondary coil H7, and a negative signal LO1- is generated at the other terminal). In one embodiment, the reference voltage is, for example, a ground potential, but the present invention is not limited thereto.

[0089] based on Figure 7 In the circuit architecture of the double-balanced mixer 700, since the node voltage VN1 is equal to the node voltage VN2, the double-balanced mixer 700 can omit the capacitor at the output end circuit to block the voltage, thereby reducing the area of the double-balanced mixer 700 and making the double-balanced mixer 700 applicable to various circuit architectures.

[0090] It's worth noting that, in some cases, the output signal IF of a double-balanced mixer may include not only the frequency-dependent output voltage Vif, but also other unwanted DC and AC interference. For example, this includes the DC common-mode voltage Vcm generated by multiple bias voltages and the AC noise voltage Vnoise generated by multiple bias voltages. This presents a significant design challenge for biased double-balanced mixers. Therefore, the following further proposes solutions to address these issues.

[0091] Figure 8FIG1 is a circuit diagram of a mixer circuit with noise suppression function according to a first embodiment of the present invention. Figure 8 , Figure 8 The circuit 800 includes a mixer, in particular a diode mixer (eg a double-balanced mixer DBM), a voltage divider circuit DC and an amplifier Amp. In one embodiment, the double-balanced mixer DBM including a plurality of diodes may include Figure 2 and Figure 7 Any of the double-balanced mixers 200 to 700, or any other double-balanced mixer using at least one set of bias voltages. The at least one set of bias voltages is used to forward conduct a plurality of diodes. In an embodiment of the present invention, any of the double-balanced mixers 200 to 700 and the voltage divider circuit are DC-coupled to an amplifier Amp.

[0092] In an embodiment of the present invention, any of the double-balanced mixers 200 to 700 receives at least one set of bias voltages, such as a high bias voltage VBH and a low bias voltage VBL. Specifically, in one embodiment, the high bias voltage VBH and the low bias voltage VBL provide a first conduction bias voltage to the diode string circuit DC1 and a second conduction bias voltage to the diode string circuit DC2. In embodiments where the double-balanced mixer receives a first set of bias voltages and a second set of bias voltages, the first and second sets of bias voltages may be identical, that is, the high bias voltage VBH is equal to the high bias voltages VBH1 and VBH2, and the low bias voltage VBL is equal to the low bias voltages VBL1 and VBL2. In other words, the high bias voltages VBH1 and VBH2 received by the double-balanced mixer may be provided by the high bias voltage VBH, and the low bias voltages VBL1 and VBL2 received by the double-balanced mixer may be provided by the low bias voltage VBL.

[0093] In an embodiment of the present invention, the voltage divider circuit DC receives the aforementioned at least one bias voltage, such as the high bias voltage VBH and the low bias voltage VBL, and generates a common-mode signal CS at an output terminal. Specifically, the common-mode signal CS includes a common-mode voltage Vcm and a noise voltage Vnoise, thereby suppressing the common-mode voltage Vcm and the noise voltage Vnoise in the output signal IF.

[0094] Specifically, in one embodiment, the voltage divider circuit DC includes a resistor R1 and a resistor R2. Resistor R2 is coupled in series to resistor R1. One terminal of resistor R1 receives a high bias voltage VBH, and one terminal of resistor R2 receives a low bias voltage VBL. The other terminals of resistor R1 and resistor R2 are coupled to an output terminal of the voltage divider circuit DC to generate a common-mode signal CS at the output terminal of the voltage divider circuit DC.

[0095] In an embodiment of the present invention, the amplifier Amp has an input terminal IN+ and an input terminal IN−. The input terminal IN+ is coupled to the output terminal of the coil assembly TS1 to receive the output signal IF. The input terminal IN− is coupled to the output terminal of the voltage divider circuit DC to receive the common-mode signal CS. The amplifier Amp generates a final output signal FS at the output terminal OUT.

[0096] Specifically, in one embodiment, amplifier Amp multiplies the voltage difference (Vif) between output signal IF received at input terminal IN+ and common-mode signal CS received at input terminal IN- by Av to amplify the noise-suppressed output signal IF (i.e., the final output signal FS). In one embodiment, amplifier Amp is, for example, an intermediate frequency amplifier, although the present invention is not limited thereto.

[0097] Figure 9 FIG2 is a circuit diagram of a mixer circuit with noise suppression function according to a second embodiment of the present invention. Figure 9 , Figure 9 The circuit 900 is similar to Figure 8 The circuit 800 differs from the double-balanced mixers 200 to 700 in the amount of bias voltages received by any one of the double-balanced mixers 200 to 700 or other double-balanced mixers using at least one set of bias voltages and the circuit structure of the voltage divider circuit DC. Therefore, only the above differences will be described below.

[0098] In an embodiment of the present invention, any of the double-balanced mixers 200 through 700 receives at least one set of bias voltages, for example, two sets of bias voltages, including a high bias voltage VBH1, a high bias voltage VBH2, a low bias voltage VBL1, and a low bias voltage VBL2. Specifically, in one embodiment, the high bias voltage VBH1 and the low bias voltage VBL1 provide a first conduction bias voltage to the diode string circuit DC1, while the high bias voltage VBH2 and the low bias voltage VBL2 provide a second conduction bias voltage to the diode string circuit DC2.

[0099] In an embodiment of the present invention, a voltage divider circuit DC receives high bias voltages VBH1 and VBH2, low bias voltages VBL1 and VBL2, and generates a common-mode signal CS at an output terminal. Specifically, the common-mode signal CS includes a common-mode voltage Vcm and a noise voltage Vnoise, thereby suppressing the common-mode voltage Vcm and the noise voltage Vnoise in the output signal IF.

[0100] Specifically, in one embodiment, the voltage divider circuit DC includes resistors R1, R2, R3, and R4. Resistor R2 is coupled in series to resistor R1, and resistor R4 is coupled in series to resistor R3. One terminal of resistor R1 receives a high bias voltage VBH1, one terminal of resistor R2 receives a low bias voltage VBL1, one terminal of resistor R3 receives a high bias voltage VBH2, and one terminal of resistor R4 receives a low bias voltage VBL2. The other terminals of resistors R1, R2, R3, and R4 are coupled to an output terminal of the voltage divider circuit DC to generate a common-mode signal CS at the output terminal of the voltage divider circuit DC.

[0101] Furthermore, it's important to note that in some cases, the output signal IF of a mixer, particularly a diode mixer (e.g., a double-balanced mixer), may include not only the aforementioned output voltage Vif, common-mode voltage Vcm, and noise voltage Vnoise, but also a DC offset voltage Vos generated by feedthrough from the input signal LO port to the input signal RF port (limited RF / LO isolation). Amplification of the DC offset voltage Vos by amplifier Amp can reduce the dynamic range. Therefore, the following proposes solutions to address this issue.

[0102] Figure 10 FIG3 is a circuit diagram of a mixer circuit with noise suppression function according to a third embodiment of the present invention. Figure 10 , Figure 10 The circuit 1000 is similar to Figure 8 The circuit 800 differs from the circuit 1000 in that the circuit 1000 further includes an AC impedance element (resistor R) and a DC impedance element (capacitor C). Therefore, the following description focuses solely on these differences. In particular, in one embodiment, the AC impedance element may also be an inductor, which is not a limitation of the present invention.

[0103] In an embodiment of the present invention, one end of the resistor R is coupled to the output terminal of any one of the double-balanced mixers 200 to 700 to receive the output signal IF. One end of the capacitor C is coupled to the output terminal of the voltage divider circuit DC to receive the common-mode signal CS. The other end of the capacitor C and the other end of the resistor R are commonly coupled to the input terminal IN- of the amplifier Amp to generate the common-mode signal CS′ at the input terminal IN- of the amplifier Amp.

[0104] Specifically, in one embodiment, resistor R filters out the DC offset voltage Vos from the output signal IF and inputs the DC offset voltage Vos to the input terminal IN- of amplifier Amp to cancel the DC offset voltage Vos from the output signal IF. In one embodiment, capacitor C inputs the common-mode signal CS (common-mode voltage Vcm and noise voltage Vnoise) to the input terminal IN- of amplifier Amp to cancel the common-mode voltage Vcm and noise voltage Vnoise from the output signal IF.

[0105] In summary, the double-balanced mixer provided by embodiments of the present invention utilizes dual-path bias diodes to improve the sensitivity of the double-balanced mixer, even when using diodes with relatively high conduction voltages. Furthermore, capacitors can be omitted from the output circuit, thereby reducing the area of the double-balanced mixer and making the double-balanced mixer adaptable to a variety of circuit architectures. Furthermore, in the mixing circuit provided by embodiments of the present invention, the mixer (e.g., the aforementioned double-balanced mixer) is further coupled to a voltage divider circuit and an amplifier. The amplifier utilizes the common-mode signal of the voltage divider circuit to suppress noise in the mixer's output signal.

[0106] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims of this patent.

Claims

1. A double-balanced mixer, characterized in that include: a coupling transformer for receiving a first input signal and generating at least one set of signals with opposite voltage phases; a first diode string circuit coupled to the coupling transformer, configured to receive a first voltage signal and a second voltage signal associated with the at least one set of voltage signals having opposite phases, and a first coil end signal associated with a second input signal to generate a first output end signal, and to generate a first node voltage according to a first set of bias voltages; a second diode string circuit coupled to the coupling transformer, configured to receive a third voltage signal and a fourth voltage signal associated with the at least one set of voltage signals having opposite phases, and a second coil-end signal associated with the second input signal to generate a second output-end signal, and to generate a second node voltage according to a second set of bias voltages; as well as a first coil assembly coupled to the first diode string circuit to receive the first node voltage and coupled to the second diode string circuit to receive the second node voltage, for generating the first coil end signal and the second coil end signal according to the second input signal, and generating an output signal according to the first output end signal and the second output end signal; The first node voltage is equal to the second node voltage.

2. The double-balanced mixer according to claim 1, wherein Also includes: The DC blocking circuit is coupled between the coupling transformer and the first diode string circuit and the second diode string circuit, and is used to receive the at least one set of signals with opposite voltage phases and generate the first voltage signal, the second voltage signal, the third voltage signal, and the fourth voltage signal.

3. The double-balanced mixer according to claim 2, wherein: The coupling transformer comprises: A second coil group is used to receive the first input signal and generate the at least one group of signals with opposite voltage phases. The at least one group of signals with opposite voltage phases includes a first forward signal and a first reverse signal.

4. The double-balanced mixer according to claim 3, wherein The first diode string circuit includes: a first terminal for receiving a first high bias voltage and the first voltage signal related to the first reverse signal; a second terminal for receiving a first low bias voltage and the second voltage signal related to the first forward signal; and a first node for receiving the first coil end signal and generating the first output end signal, and generating the first node voltage according to the first high bias voltage and the first low bias voltage, and The first diode string circuit further comprises: a first diode coupled between the first end point and the first node, wherein an anode of the first diode is coupled to the first end point, and a cathode of the first diode is coupled to the first node; and A second diode is coupled between the second end point and the first node, wherein a cathode of the second diode is coupled to the second end point, and an anode of the second diode is coupled to the first node.

5. The double-balanced mixer according to claim 3, wherein: The second diode string circuit includes: a third terminal for receiving a second high bias voltage and the third voltage signal related to the first forward signal; a fourth terminal for receiving a second low bias voltage and the fourth voltage signal related to the first reverse signal; and a second node for receiving the second coil end signal and generating the second output end signal, and generating the second node voltage according to the second high bias voltage and the second low bias voltage, and The second diode string circuit further comprises: a third diode coupled between the third terminal and the second node, wherein an anode of the third diode is coupled to the third terminal, and a cathode of the third diode is coupled to the second node; and A fourth diode is coupled between the fourth end point and the second node, wherein a cathode of the fourth diode is coupled to the fourth end point, and an anode of the fourth diode is coupled to the second node.

6. The double-balanced mixer according to claim 3, wherein The second coil assembly includes: a first primary coil, one end of which receives the first input signal and the other end of which is coupled to a reference voltage; and a first secondary coil, a center tap of which is coupled to the reference voltage or a first low bias voltage, The second coil assembly generates the first forward signal and the first reverse signal according to the first primary coil and the first secondary coil.

7. The double-balanced mixer according to claim 3, wherein: The first diode string circuit includes: a first terminal for receiving a first high bias voltage and the first voltage signal related to the first reverse signal; a second terminal for receiving the second voltage signal related to the first forward signal, wherein the second voltage signal is the first forward signal; and A first node is used to receive the first coil end signal and generate the first output end signal, and to generate the first node voltage according to the first high bias voltage and a first low bias voltage.

8. The double-balanced mixer according to claim 3, wherein: The second diode string circuit includes: a third terminal for receiving a second high bias voltage and the third voltage signal related to the first forward signal; a fourth terminal for receiving the fourth voltage signal related to the first reverse signal, wherein the fourth voltage signal is the first reverse signal; and A second node is used to receive the second coil end signal and generate the second output end signal, and to generate the second node voltage according to the second high bias voltage and a second low bias voltage.

9. The double-balanced mixer according to claim 3, wherein: The second coil assembly includes: a first primary coil, one end of which receives the first input signal and the other end of which is coupled to a reference voltage; and A first secondary coil includes a first coil and a second coil, wherein one end of the first coil receives a first low bias voltage, and one end of the second coil receives a second low bias voltage. The second coil assembly generates the first forward signal and the first reverse signal according to the first primary coil and the first coil and the second coil of the first secondary coil.

10. The double-balanced mixer according to claim 2, wherein: The coupling transformer comprises: a second coil assembly for receiving the first input signal and generating a first set of signals with opposite voltage phases, the first set of signals with opposite voltage phases comprising a first forward signal and a first reverse signal; and A third coil group is used to receive the first input signal and generate a second set of signals with opposite voltage phases. The second set of signals with opposite voltage phases includes a second positive signal and a second negative signal.

11. The double-balanced mixer according to claim 10, wherein: The first diode string circuit includes: a first terminal for receiving the first voltage signal related to the first reverse signal, wherein the first voltage signal is the first reverse signal; a second terminal for receiving the second voltage signal related to the second forward signal, wherein the second voltage signal is the second forward signal; and a first node for receiving the first coil end signal and generating the first output end signal, and generating the first node voltage according to a first high bias voltage and a first low bias voltage, and The second diode string circuit includes: a third terminal for receiving a second high bias voltage and the third voltage signal related to the first forward signal; a fourth terminal for receiving a second low bias voltage and the fourth voltage signal related to the second reverse signal; and A second node is used to receive the second coil end signal and generate the second output end signal, and to generate the second node voltage according to the second high bias voltage and the second low bias voltage.

12. The double-balanced mixer according to claim 10, wherein: in The second coil assembly includes: a first primary coil, one end of which receives the first input signal and the other end of which is coupled to a reference voltage; and a first secondary coil, a center tap of which is coupled to a first high bias voltage, The second coil assembly generates the first forward signal and the first reverse signal according to the first primary coil and the first secondary coil. The third coil assembly includes: a second primary coil, one end of which receives the first input signal and the other end of which is coupled to the reference voltage; and a second secondary winding having a center tap coupled to a first low bias voltage, The third coil assembly generates the second forward signal and the second reverse signal according to the second primary coil and the second secondary coil.

13. The double-balanced mixer according to claim 1, wherein The coupling transformer comprises: a second coil assembly for receiving the first input signal and generating a first set of signals with opposite voltage phases, the first set of signals with opposite voltage phases comprising a first forward signal and a first reverse signal; and A third coil group is used to receive the first input signal and generate a second set of signals with opposite voltage phases. The second set of signals with opposite voltage phases includes a second positive signal and a second negative signal.

14. The double-balanced mixer according to claim 13, wherein The first diode string circuit includes: a first terminal for receiving the first voltage signal related to the first reverse signal, wherein the first voltage signal is the first reverse signal; a second terminal for receiving the second voltage signal related to the second forward signal, wherein the second voltage signal is the second forward signal; and a first node for receiving the first coil end signal and generating the first output end signal, and generating the first node voltage according to a high bias voltage and a low bias voltage, and The second diode string circuit includes: a third terminal for receiving the third voltage signal related to the first positive signal, wherein the third voltage signal is the first positive signal; a fourth terminal for receiving the fourth voltage signal related to the second reverse signal, wherein the fourth voltage signal is the second reverse signal; and A second node is used to receive the second coil end signal and generate the second output end signal, and to generate the second node voltage according to the high bias voltage and the low bias voltage.

15. The double-balanced mixer according to claim 13, wherein in The second coil assembly includes: a first primary coil, one end of which receives the first input signal and the other end of which is coupled to a reference voltage; and a first secondary coil having a center tap coupled to a high bias voltage, The second coil assembly generates the first forward signal and the first reverse signal according to the first primary coil and the first secondary coil. The third coil assembly includes: a second primary coil, one end of which receives the first input signal and the other end of which is coupled to the reference voltage; and a second secondary winding having a center tap coupled to a low bias voltage, The third coil assembly generates the second forward signal and the second reverse signal according to the second primary coil and the second secondary coil.

16. The double-balanced mixer according to claim 1, wherein The coupling transformer comprises: A second coil group is used to receive the first input signal and generate a first set of signals with opposite voltage phases and a second set of signals with opposite voltage phases, wherein the first set of signals with opposite voltage phases includes a first positive signal and a first negative signal, and the second set of signals with opposite voltage phases includes a second positive signal and a second negative signal.

17. The double-balanced mixer according to claim 1, wherein The first coil assembly includes: a first primary coil, one terminal of which receives the second input signal, and the other terminal of which receives a reference voltage; and a first secondary coil, one end of which receives the first node voltage, and the other end of which receives the second node voltage; The first coil assembly generates the output signal at a center tap of the first secondary coil according to the first primary coil and the first secondary coil.

18. The double-balanced mixer according to claim 1, wherein The frequency of the output signal is related to the frequency of the first input signal and the frequency of the second input signal.

19. The double-balanced mixer according to claim 1, wherein It is further coupled to a voltage divider circuit and an amplifier, wherein: The voltage divider circuit is used to generate a common mode signal at an output terminal according to at least one of the first bias voltage group and the second bias voltage group, and The amplifier has a first input terminal coupled to the first coil assembly to receive the output signal, and a second input terminal coupled to the output terminal of the voltage divider circuit to suppress noise in the output signal and generate a final output signal at an output terminal.

20. The double-balanced mixer according to claim 1, wherein The first set of bias voltages is the same as the second set of bias voltages.

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